9.

Design and Implementation of FIFO using FPGA

AIM: To design and implementation of FIFO using FPGA

Tools used:
1. Vivado 2018.1 tool
2. Vivado Simulator
3. EDGEA7

Diagram:

Program:

module fifo ( Clk, dataIn, RD,WR, EN, dataOut, Rst, EMPTY, FULL);
input Clk, RD, WR, EN, Rst;
output EMPTY, FULL;
input [7:0] dataIn;
output reg [7:0] dataOut; // internal registers
reg [2:0] Count = 0;
reg [7:0] FIFO [0:7];
reg [2:0] readCounter = 0,
writeCounter = 0;
assign EMPTY = (Count==0)? 1'b1:1'b0;
assign FULL = (Count==8)? 1'b1:1'b0;
always @ (posedge Clk)
begin
if (EN==0);
else begin
if (Rst) begin
readCounter = 0;
 writeCounter = 0;
end
else if (RD ==1'b1 && Count!=0) begin
dataOut = FIFO[readCounter];
readCounter = readCounter+1;
end
else if (WR==1'b1 && Count<8) begin
FIFO[write Counter] = dataIn;
writeCounter = writeCounter+1;
end
else;
end
if (write Counter==8)
writeCounter=0;
else if (readCounter==8)
readCounter=0;
else;
if (readCounter > writeCounter) begin
Count=readCounter-writeCounter;
end
else if (writeCounter > readCounter)
Count=writeCounter-readCounter;
else;
end
endmodule

Test bench:
module fifo_tb;
reg Clk;
reg [7:0] dataIn;
reg RD;
reg WR;
reg EN;
reg Rst;

// Outputs

wire [7:0] dataOut;

wire EMPTY;
wire FULL;

// Instantiate the Unit Under Test (UUT)

fifo uut (.Clk(Clk), .dataIn(dataIn), .RD(RD), .WR(WR), .EN(EN), .dataOut(dataOut),.Rst(Rst),

.EMPTY(EMPTY), .FULL(FULL) );

initial begin
// Initialize Inputs
Clk = 1'b0;
dataIn = 7'h0;
 RD = 1'b0;
WR = 1'b0;
EN = 1'b0;
Rst = 1'b1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
EN = 1'b1;
Rst = 1'b1;
#20;
Rst = 1'b0;
WR = 1'b1;
dataIn = 7'h0;
#20;
dataIn = 7'h1;
#20;
dataIn = 7'h2;
#20;
dataIn = 7'h3;
#20;
dataIn = 7'h4;
#20;
WR = 1'b0;
RD = 1'b1;
end
always #10 Clk = ~Clk;
endmodule

Constraints:
set_property PACKAGE_PIN N11 [get_ports Clk_0]
set_property IOSTANDARD LVCMOS33 [get_ports Clk_0]
set_property PACKAGE_PIN P1 [get_ports Rst_0]
set_property IOSTANDARD LVCMOS33 [get_ports Rst_0]
set_property PACKAGE_PIN N1 [get_ports {dataIn_0[7]}]
set_property PACKAGE_PIN N2 [get_ports {dataIn_0[6]}]
set_property PACKAGE_PIN N3 [get_ports {dataIn_0[5]}]
set_property PACKAGE_PIN M1 [get_ports {dataIn_0[4]}]
set_property PACKAGE_PIN M2 [get_ports {dataIn_0[3]}]
set_property PACKAGE_PIN M4 [get_ports {dataIn_0[2]}]
set_property PACKAGE_PIN L4 [get_ports {dataIn_0[1]}]
set_property PACKAGE_PIN L5 [get_ports {dataIn_0[0]}]
set_property PACKAGE_PIN K2 [get_ports {dataOut_0[7]}]
set_property PACKAGE_PIN K3 [get_ports {dataOut_0[6]}]
set_property PACKAGE_PIN L2 [get_ports {dataOut_0[5]}]
set_property PACKAGE_PIN L3 [get_ports {dataOut_0[4]}]
set_property PACKAGE_PIN K1 [get_ports {dataOut_0[3]}]
set_property PACKAGE_PIN J1 [get_ports {dataOut_0[2]}]
set_property PACKAGE_PIN H3 [get_ports {dataOut_0[1]}]
set_property PACKAGE_PIN J3 [get_ports {dataOut_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataIn_0[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataIn_0[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataIn_0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataIn_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataIn_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataIn_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataIn_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataIn_0[0]}]
set_property PACKAGE_PIN P4 [get_ports RD_0]
set_property PACKAGE_PIN T8 [get_ports WR_0]
set_property IOSTANDARD LVCMOS33 [get_ports RD_0]
set_property IOSTANDARD LVCMOS33 [get_ports WR_0]
set_property PACKAGE_PIN R8 [get_ports EN_0]
set_property IOSTANDARD LVCMOS33 [get_ports EN_0]
set_property PACKAGE_PIN P6 [get_ports EMPTY_0]
set_property PACKAGE_PIN K5 [get_ports FULL_0]
set_property IOSTANDARD LVCMOS33 [get_ports EMPTY_0]
set_property IOSTANDARD LVCMOS33 [get_ports FULL_0]
set_property IOSTANDARD LVCMOS33 [get_ports {dataOut_0[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataOut_0[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataOut_0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataOut_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataOut_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataOut_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataOut_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dataOut_0[0]}]

Simulation Results:

Result:

The FIFO using FPGA is designed using Verilog HDL. Simulation and synthesis is performed
using Vivado tool. Functional verification of the design is performed using a Verilog HDL test bench.
 10. Design a 4-bit up down counter using Xilinx IPs and
verified it on FPGA using VIO IP

AIM: To design a 4-bit up down counter using Xilinx IPs and verified it on FPGA using
VIO IP.
Tools used:

1. Vivado 2018.1 tool

2. Vivado Simulator

Diagram:

Program:
//clock_division
module clk_div(reset, clk_in, clk_out);
input reset, clk_in;
output reg clk_out;

//Use a 29 bit register for counter values

reg [28:0] ctr;

//Whenever the clock rises, increment counter

//When ctr hits the desired value, the clk_out will toggle.
always@(posedge clk_in)
begin
if(reset)
begin
ctr = 29'd0;
clk_out<= 0;
end
else if(ctr >= 29'h2FAF080 )
begin
ctr = 29'd0;
clk_out = ~clk_out;
end
else
ctr = ctr + 29'd1;
end

endmodule

// design_1_wrapper
module design_1_wrapper
(clk_0);
input clk_0;

wire clk_0;

design_1 design_1_i
(.clk_0(clk_0));
endmodule

//Constraints:
set_property PACKAGE_PIN E3 [get_ports clk_0]
set_property IOSTANDARD LVCMOS33 [get_ports clk_0]

VIO Results:

Result:

The 4-bit up down counter is designed using Verilog HDL verified it on FPGA using VIO IP. Simulation
and synthesis is performed using Vivado tool. Functional verification of the design is performed
using a Verilog HDL test bench.