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Module 4 Model Question

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11 views3 pages

Module 4 Model Question

Uploaded by

yadavabhi4268
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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1. Explain the principle of set-associative mapping of cache memory.

(Module 4/CO2/Understand-IOCQ) 7

2. Explain how a virtual address can be mapped to a physical address with the help of
memory map table. (Module 4/CO2/Understand-IOCQ) 6

3.Draw and explain memory hierarchy pyramid. (Module 4/CO2/Remember-LOCQ) 5

4. Describe different types of cache misses. (Module 4/CO2/Remember-LOCQ)


5

5. Describe different types of Page replacement algorithm.


(Module 4/CO2/Remember-LOCQ) 5

6. Describe different types of Cache writing methods.


(Module 4/CO2/Remember-LOCQ) 5

7. a. Define hit ratio. (Module 4/CO2/Remember-LOCQ)

b. Calculate the average access time and efficiency of a memory system having the
following specification:
• Cache memory access time is 60 ns
• Main memory access time is 160 ns
• hit ratio of the cache memory is 0.9
(Module 4/CO2/Understand-IOCQ) 2+3

8. Explain the principle of associative mapping of cache memory.


(Module 4/CO2/Understand-IOCQ) 5
9. Write a short note on associative memory. (Module 4/CO2/Understand-IOCQ)
5

10. Give a comparison between SRAM and DRAM. (Module 4/CO2/Remember-LOCQ)


11. Construct a 1k X 4 memory using 512 X 2 memory.
(Module 4/CO2/Apply-HOCQ)
5
12. Explain the inclusion property and locality of reference in connection with cache
memory.
(Module 4/CO2/Understand-IOCQ)
5
13. a. Define cache mapping. Explain direct cache mapping technique.
(Module 4/CO2/Understand-IOCQ)
b. According to the following information, determine the size of the subfields (in bits) in
the address for direct mapping, associative mapping and set associative mapping cache
schemes:
• Main memory size is 256 MB, Cache memory size is 1 MB
• The address space of the processor is 256 MB
• The block size is 128 bytes
• No of blocks in a cache set is 8
(Module 4/CO2/Apply-HOCQ)
2+7+6
14. a. Give a comparison between RAM and ROM.
(Module 4/CO2/Remember-LOCQ)
b. Show the bus connection with a CPU to connect four RAM chips of size 128 X 8 bits each
and one ROM chip of 512 X 8 bit size. Assume that the CPU has 8 bit data bus and 16 bit
address bus. Explain the bus connection. Show the memory address map table.
(Module 4/CO2/Apply-HOCQ)
3+12
15. Construct a 1k X 8 RAM using 256 X 2 RAM.
(Module 4/CO2/Apply-HOCQ) 7
16. a. Illustrate Virtual memory. Show how address mapping is done using Paging
technique. Give an example.
(Module 4/CO2/Understand-IOCQ)
b. Write in brief about Associative Memory Page Table.
(Module 4/CO2/Understand-IOCQ)
2+8+5
17. a. Write down the Advantages of Segmentation. Explain segmented page mapping
technique with proper diagram.
(Module 4/CO2/Understand-IOCQ)
b. A system has 64 bit virtual address and 43 bit physical address. If the page size is 8kB,
calculate the number of pages and number of frames.
(Module 4/CO2/Understand-IOCQ)
3+9+3
18. Write short note on Cache writing methods
(Module 4/CO2/Remember-LOCQ) 5
19. Write short note on Page replacement algorithm
(Module 4/CO2/Remember-LOCQ) 5
20. Write short note on Translation look-aside buffer
(Module 4/CO2/Remember-LOCQ) 5
21. Write short note on Associative memory
(Module 4/CO2/Remember-LOCQ) 5
22. Write short note on Memory Interleaving
(Module 4/CO2/Remember-LOCQ) 5

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