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20 views

Lecture #13

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Teshome Girma
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Chapter 4: Sequential Logic

1. Definitions and Basic Concepts


 A sequential circuit consists of a combinational circuit to which
storage elements are connected
to form a feedback path.

Multivibrators:
 Multivibrators fall into three categories: astable, monostable, and bistable.

 Astable Multivibrators: The output is unstable in either state. That is, the output
continually changes from 0 to 1 to 0, etc. Astable multivibrators are used as the time base
for automatic and / or sequential devices.

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Monostable Multivibrators:

 The output is stable in one state and unstable in the other. The specific
behavior is that the “input” is a “trigger” which causes the output to make a
transition from the stable to the unstable state, where it remains for a
length of time (τ), and then reverts to the stable state.

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Bistable Multivibrators:

 The output is stable in both states although the input can “trigger” a
transition from one state to the other.

 The two categories of bistable devices are the latch and the flip-flop. The
basic difference between latches and flip-flops is the way in which they are
changed from one state to the other.

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2. Memory Elements: Latches and flip-flops
The basic SR latch
 Its inputs, Set(S) and Reset (R), provide the means for changing the state, Q, of the
circuit.

 When both inputs, R and S, are equal to 0 the latch maintains its existing state.
 When R = 0 and S = 1, the latch is set into a state where Qa = 1 and Qb = 0.
 When R = 1 and S = 0, the latch is reset into a state where Qa = 0 and Qb = 1.
 When R = S = 1, both Qa and Qb will be 0. (In normal operation, this condition is avoided)
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Gated SR Latch
 It includes two extra AND gates.
 When the clock signal Clk is equal to 0, the S’ and R’ inputs to the
latch will be 0, regardless of the values of signals S and R.
Hence the latch will maintain its existing state as long as Clk = 0.
 When Clk changes to 1, the S’ and R’ signals will be the same as the S and R signals,
respectively.
Therefore, in this mode it will behave as the basic latch.

 we will often say that the latch is set when Q = 1, and it is reset when Q = 0.
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Gated SR Latch with NAND Gates
 We can also construct the latch with NAND gates.

 We will use the circuit in preference to the previous gated latch.

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Gated D Latch
 Has a single data input, called D, and it stores the value on this input, under the
control of a clock signal.

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Master-Slave and Edge-Triggered D Flip-Flops
 flip-flop denotes a storage element that changes its output state at the edge of a controlling clock
signal.
Master-Slave D Flip-Flop
 Consider the circuit given below, which consists of two gated D latches.
 The first, called master, changes its state while Clock = 1.
 The second, called slave, changes its state while Clock = 0.

 Regardless of the number of changes in the D input to the


master stage during one clock cycle, the observer of the Qs
signal will see only the change that corresponds to the D input
at the negative edge of the clock.
 The > mark to denote that the flip-flop responds to the
“active edge” of the clock.
 A bubble on the clock input to indicate that the active edge for this particular circuit is the
negative edge (where the clock signal changes from 1 to 0).
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Edge-Triggered D Flip-Flop
 When clock=0, the output of gate 2 and 3 are high. Thus
p1=p2=1, which maintains the output latch. Besides, the
signal p3 is equal to D, and p4 is equal to its complement.
 When clock changes to 1, the value of p3 and p4 are
transmitted through gates 2 and 3 to cause p1= D and p2=D,
which sets Q=D and Q = D .

 After clock changes to 1, any further change in D will not affect the output latch as long as
clock=1.
 Suppose first that D = 0 at the positive edge of the clock. Then P2 = 0, which will keep the output
of gate 4 equal to 1 as long as Clock = 1, regardless of the value of the D input.
 The second case is if D = 1 at the positive edge of the clock. Then P1 = 0, which forces the
outputs of gates 1 and 3 to be equal to 1, regardless of the D input.
 The circuit responds to the positive clock edge.
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 D Flip-Flops with Clear and Preset
 The figure below shows a positive edge triggered D- flip-flop with Clear and Preset
capability.

 Placing a 0 on the Clear input will force the flip-


flop into the state Q = 0. If Clear = 1, then this
input will have no effect on the NAND gates.
Similarly, Preset = 0 forces the flip-flop into the
state Q = 1,while Preset = 1 has no effect.
 Note that both Clear and Preset can not be 0 at the same time.
 Exercise: Make Clear and Preset capability for the master-slave D flip-flop.
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Synchronous reset for a D flip-flop
 In the above circuit, if Clear = 0 then the flip-flop goes into the state Q = 0
immediately, regardless of the value of the clock signal. In such a circuit, where the
Clear signal is used to clear a flip-flop without regard to the clock signal, we say that
the flip-flop has an asynchronous clear.
 In practice, it is often preferable to clear the flip-flops on the active edge of the
clock. Such synchronous clear can be accomplished as shown in figure below.

 The flip-flop operates normally when the Clear input is equal to 1. But if Clear goes
to 0, then on the next positive edge of the clock the flip-flop will be cleared to 0.

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T Flip-Flop
 By including some simple logic circuitry to drive its input, the D flip-flop may be
modified to a different storage element, T-flip-flop.

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JK Flip-Flop
 Another circuit can be derived from the T-flip-flop above.
 Instead of using a single control input, T, we can use two inputs, J and K.

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