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Lecture #9

The document discusses combinational logic circuits including arithmetic comparators and adders/subtractors. It describes how to design comparators to compare two n-bit numbers and produce outputs indicating equality, greater than, and less than. It also covers binary addition using half adders and full adders in ripple carry adders as well as carry lookahead adders for faster addition.

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Teshome Girma
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0% found this document useful (0 votes)
20 views15 pages

Lecture #9

The document discusses combinational logic circuits including arithmetic comparators and adders/subtractors. It describes how to design comparators to compare two n-bit numbers and produce outputs indicating equality, greater than, and less than. It also covers binary addition using half adders and full adders in ripple carry adders as well as carry lookahead adders for faster addition.

Uploaded by

Teshome Girma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Chapter 3: Combinational Logic

Arithmetic Comparison Circuits


 Considers the design of a comparator that has two n-bit inputs, A and B, which represent
unsigned binary numbers.
 The comparator produces three outputs, called AeqB, AgtB, and AltB.
AeqB output is set to 1 if A and B are equal.
AgtB output is 1 if A is greater than B.
AltB output is 1 if A is less than B.
 It is not feasible to design using truth table, for it requires large sized table
Let A = a3a2a1a0 and B = b3b2b1b0.
Define a set of intermediate signals called i3, i2, i1, and i0. Each signal, ik , is 1 if the bits of
A and B with the same index are equal.
That is,
Where the ⊕ symbol represents the XOR operation.

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 The complement of the XOR operation, denoted as . This operation is called
XNOR and has the symbol . Hence,

 The comparator’s AeqB output is then given by

 An expression for the AgtB output can be derived by considering the bits of A and B
in the order from the most-significant bit to the least-significant bit. The first bit-
position, k, at which ak and bk differ determines whether A is less than or greater
than B. If ak = 0 and bk = 1, then A < B. But if ak = 1 and bk = 0, then A > B. The
AgtB output is defined by

 The AltB output can be derived by using the other two outputs as

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 A logic circuit that implements the four-bit comparator circuit is shown in figure
below.

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 This approach can be extended to design comparator for any value of n.
 Binary Adder/Subtractor:
 The addition of 2 one-bit numbers entails four possible combinations
• Two bits are needed to represent the result of the addition
 The right-most bit is called the sum, s.
 The left-most bit , is called the carry, c
• Produced as a carry-out when both bits being added are equal to 1.

• The addition operation is defined in the form of a truth table:

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 The sum bit s is the XOR function
 Where the sum-of-products form

 The carry c is the AND function of inputs x and y.


 A circuit realization of these functions is shown below. This circuit, which implements
the addition of only two bits, is called a half-adder.

 How do we implement an adder?


 When larger numbers that have multiple bits are involved.

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Full adder
 How to add X = (01111)2 and Y = (01010)2
 Add each pair of bits
 For each bit position i, the addition operation may include a carry-in from bit
position i − 1.
 For bit position 0, there is no carry-in.
 For each other bit position i, the addition involves bits xi and yi , and a carry-in ci .
 The carry-out, ci+1, is equal to 1 if the sum of xi , yi , and ci is equal to either 2 or 3.

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 The truth table that specify the sum and carry-out functions of variables xi , yi , and ci
and the Karnaugh maps for these functions is given below.

 For the carry-out function the optimal sum-of-products realization is

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 For the si function a sum-of-products realization is

 The si function can be implemented using the XOR gates.

• Therefore, a single three-input XOR gate can be used to realize si .

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 The logic circuit, full adder, implementing the operation mentioned becomes

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 A full-adder can be constructed from two half-adders. The circuit is given below.

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 Ripple-Carry Adder
 To perform addition by hand:
 Start from the least-significant digit and add pairs of digits
 If a carry is produced in position i, then this carry is added to the operands in
position i+1.
 The same arrangement can be used in a logic circuit that performs addition,
using a full-adder circuit, connected as shown below, for each bit position.

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 Each full-adder introduces a certain delay before its Si and Ci+1 outputs are valid. Let

this delay be denoted as Δt. Thus, the delay in the n full adders will be nΔt. which
means that the complete sum is available after a delay of nΔt.

 Adder and Subtractor Unit


 The only difference between performing addition and subtraction is that for
subtraction it is necessary to use the 2’s complement of one operand.
 Let X and Y be the two operands, such that Y serves as the subtrahend in
subtraction.
 The 2’s complement of Y can be found by complementing each bits of Y and then
adding 1, which is done by making the carry-in bit Co=1.
 Two-input XOR gates can be used to choose between true and complemented
versions of the subtrahend Y.

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 This idea can be applied in the design of the adder/subtractor unit shown below.

 is a control signal that chooses whether addition or subtraction is to be


performed. It is 0 for addition and 1 for subtraction.
 c0 = 1 when subtraction is to be performed.
 When the addition operation is performed, we will have ci = 0.
 The n-bit adder can be implemented using the ripple-carry structure

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 Carry-Lookahead Adder
 Fast adder
 From the previous discussion, the carry-out function for stage i can be realized as

 If we factor this expression as

then it can be written as


….. Eq(1)
where

Expanding eq (1) in terms of stage i-1 gives

Generally, for any stage i, the expression for Ci+1 ending with stage 0 becomes

….. Eq(2)

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 Two bit carry-lookahead adder
From eq (2)

The circuit implementing the adder becomes

 Carry-out signal is
produced after a total of
three gate delays

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