Lecture #9
Lecture #9
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The complement of the XOR operation, denoted as . This operation is called
XNOR and has the symbol . Hence,
An expression for the AgtB output can be derived by considering the bits of A and B
in the order from the most-significant bit to the least-significant bit. The first bit-
position, k, at which ak and bk differ determines whether A is less than or greater
than B. If ak = 0 and bk = 1, then A < B. But if ak = 1 and bk = 0, then A > B. The
AgtB output is defined by
The AltB output can be derived by using the other two outputs as
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A logic circuit that implements the four-bit comparator circuit is shown in figure
below.
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This approach can be extended to design comparator for any value of n.
Binary Adder/Subtractor:
The addition of 2 one-bit numbers entails four possible combinations
• Two bits are needed to represent the result of the addition
The right-most bit is called the sum, s.
The left-most bit , is called the carry, c
• Produced as a carry-out when both bits being added are equal to 1.
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The sum bit s is the XOR function
Where the sum-of-products form
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Full adder
How to add X = (01111)2 and Y = (01010)2
Add each pair of bits
For each bit position i, the addition operation may include a carry-in from bit
position i − 1.
For bit position 0, there is no carry-in.
For each other bit position i, the addition involves bits xi and yi , and a carry-in ci .
The carry-out, ci+1, is equal to 1 if the sum of xi , yi , and ci is equal to either 2 or 3.
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The truth table that specify the sum and carry-out functions of variables xi , yi , and ci
and the Karnaugh maps for these functions is given below.
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For the si function a sum-of-products realization is
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The logic circuit, full adder, implementing the operation mentioned becomes
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A full-adder can be constructed from two half-adders. The circuit is given below.
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Ripple-Carry Adder
To perform addition by hand:
Start from the least-significant digit and add pairs of digits
If a carry is produced in position i, then this carry is added to the operands in
position i+1.
The same arrangement can be used in a logic circuit that performs addition,
using a full-adder circuit, connected as shown below, for each bit position.
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Each full-adder introduces a certain delay before its Si and Ci+1 outputs are valid. Let
this delay be denoted as Δt. Thus, the delay in the n full adders will be nΔt. which
means that the complete sum is available after a delay of nΔt.
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This idea can be applied in the design of the adder/subtractor unit shown below.
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Carry-Lookahead Adder
Fast adder
From the previous discussion, the carry-out function for stage i can be realized as
Generally, for any stage i, the expression for Ci+1 ending with stage 0 becomes
….. Eq(2)
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Two bit carry-lookahead adder
From eq (2)
Carry-out signal is
produced after a total of
three gate delays
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