Bipolar Logic

 Bipolar logic families use semiconductor diodes and bipolar junction transistors as the basic
building blocks of logic circuits.
Diode Logic
 Use diodes and resistors to perform logic operations.
 Logic levels in a simple diode logic system:

o Diode AND gate

 Suppose that both inputs are connected to HIGH voltage.
 Say VA =VB =4 V
 Both diodes are forward biased and Truth table
Vout is one diode drop above 4v.
A B out
Vout=4+0.7=4.7V (High)
0 0 0
 If one of the inputs is LOW- say 1V, then the
output Vout will be one diode drop above the 0 1 0
lower input. The same will be the output if both 1 0 0
the inputs are LOW. 1 1 1
Vout=1+0.7=1.7V (LOW)
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 o Diode OR gate
 If one of the inputs is HIGH, the output will be one diode drop below the
higher input. (i.e. 4-0.7=3.3V: HIGH)
 If both of the inputs are LOW, then the output LOW. (i.e. one diode drop
below the low value, 1-0.7=0.3V)
Truth table
A B out
0 0 0
0 1 1
1 0 1
1 1 1

Transistor Logic Inverter

 The common-emitter configuration of an npn transistor is shown below as a logic inverter.

 When VIN is HIGH, the transistor switch is closed, and the

output terminal is connected to ground, definitely a
LOW voltage. When VIN is LOW, the transistor switch is
open and the output terminal is pulled to +5 V through
a resistor; the output voltage is HIGH.

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 Transistor-Transistor Logic
 The most commonly used bipolar logic family is transistor-transistor logic.
 Before the emergence of CMOS, the dominant technology was transistor-transistor
logic, commonly referred to as TTL.
 All series of TTL logic gates operate from 5V dc supply.
 The series within the TTL family are designated by the prefix 74 (commercial) or 54
(military) followed by a letter or letters that indicate the series and a number that
indicates the type of logic device within the series.
 A TTL IC can be distinguished from CMOS by the letters that follow the 74 or 54
prefix.
 The basic TTL series and their designations are as follows:
 74 – Standard TTL (no letter)
 74S – Schottky TTL
 74AS – Advanced Schottky TTL
 74LS – Low-power Schottky TTL
 74ALS – Advanced low-power Schottky TTL
 74F – Fast TTL
 For example, 74LS00 is Low-Power Schottky Quad 2-input NAND.

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  Input and output logic level (TTL)

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 The operation of the TTL NAND gate is given in the following table.

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 Emitter Coupled Logic (ECL)
 The fastest bipolar circuit architecture with much more power consumption.

ECL OR/NOR Gate

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  Voltage Levels in Logic Gates
 Consider the NMOS inverter:

 When Vx = 0 V, the NMOS transistor is turned off. No

current flows; hence Vf = 5 V.
 When Vx = VDD, the NMOS transistor is turned on. To
calculate the value of Vf , let us represent the NMOS
transistor by a resistor with the value RDS=
 Assuming
and

Vf becomes:

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 The CMOS Inverter
 The meaning of the symbol VOH is the voltage produced when the output is high and
VOL refers to the voltage produced when the output is low.
 For the previous NMOS inverter, and
 Consider the CMOS inverter
 The voltage transfer characteristic

 Due to leakage current, the

value of VOH and VOL will be
affected. Thus, typical value of
VOL is 0.1mV rather than 0V.

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  From the voltage transfer characteristic:
 The voltage VIL is defined as the maximum input voltage level that the inverter will
interpret as low, hence producing a high output.
 The voltage VIH is the minimum input voltage level that the inverter will interpret as
high, hence producing a low output.

 Noise Margin: is the maximum external noise voltage added to an input signal
that does not cause an undesirable change in the circuit output.
 Electronic circuits are constantly subjected to random perturbations, called
noise, which can alter the output voltage levels.
 Consider the two NOT gates shown below,

 The ability to tolerate noise without affecting the correct operation of the
circuit is known as noise margin.
 For the low output voltage, we define the low noise margin as
NML =VIL −VOL
 The high noise margin is defined as
NMH =VOH −VIH
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  Dynamic Operation of Logic Gates
 Consider the connection of two NOT gates with the stray capacitance.

 The existence of stray

capacitance has a negative
effect on the speed of
operation of logic circuits

 Voltage across a capacitor cannot change instantaneously. In this circuit, when the
PMOS transistor in N1 is turned on, the capacitor is charged to VDD; it is discharged
when the NMOS transistor is turned on.

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 In real circuits, waveforms do not have perfectly vertical edges in
transition from one logic level to the other.
 For the previous circuit with stray capacitance:

 Where:
tr: Rise time
tf: fall time

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 The propagation delay is given by the equation

Where K’n: A constant (For NMOS)

W: Channel width
L: Channel Length

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  Power Dissipation in Logic Gates
 Define two types of power:
 Static power: Dissipated by the current that flows in the steady state.
 Dynamic power: Consumed when the current flows because of changes in signal
levels.
 NMOS circuits consume static power as well as dynamic power, while
CMOS circuits consume only dynamic power.
 Consider the CMOS inverter:
 Due to the stray capacitance, current flows through the transistors during
charging and discharging.

 From the voltage transfer

characteristics also, there
is a range of input voltage
Vx during which both
transistors are turned on
and current flows from
VDD to Gnd.
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 Power Dissipation in Logic Gates

 The amount of energy stored in the capacitor is equal to CVDD2 /2.

 When the capacitor is discharged to 0 V, this stored energy is
dissipated in the NMOS transistor.

 Similarly, for the situation in Figure (b), the energy CVDD 2/2 is
dissipated in the PMOS transistor when C is charged up to VDD.

 Thus for each cycle in which the inverter charges and discharges C,
the amount of energy dissipated is equal to CVDD2.
 Since power is defined as energy used per unit time, the power
dissipated in the inverter is the product of the energy used in one
discharge/charge cycle times the number of such cycles per second,
f.
 Hence the dynamic power consumed is
PD = fCVDD2
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 Generally power dissipation can be calculated as

Where:
• VCC Supply Voltage.
• ICC Current drawn from supply voltage.
• ICCH Current drawn when output is High.
• ICCL Current drawn when output is Low.

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  Fan-in and Fan-out in Logic Gates
 Fan-in
 The fan-in of a logic gate is defined as the number of inputs to the gate.
 In some logic gate configuration, it may be impractical to increase the
number of inputs beyond a small number. However; in others, is practical
to build high fan-in.
- propagation delay
- Noise margin
 High fan-in CMOS logic gates always require either k NMOS or k PMOS
transistors in series and are therefore never practical.
 Fan-out
 The number of other gates that a specific gate drives is called its fan-out.
 The driven gates contributes to the capacitive load, and could affect the
propagation delay.

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  The effect of fan-out on propagation delay

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 Data sheets: A typical data sheet consists of an information page that shows, among other things,
the logic diagram and packages, the recommended operating conditions, the electrical
characteristics, and the switching characteristics. Partial data sheet for 74LS00 is shown here.

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  Summary of logic family

 TTL is a logic family that has been in use for 50 years and is
considered to be standard.
 ECL has an advantage in systems requiring high‐speed operation.
 MOS is suitable for circuits that need high component density, and
CMOS is preferable in systems requiring low power consumption,
such as digital cameras, personal media players, and other handheld
portable devices.
 CMOS has become the dominant logic family, while TTL and ECL
continue to decline in use.

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 References
 Thomas L. Floyed, Digital Fundamentals
 Wakerly, Digital Design Principles and Practices.
 Vranesic, Fundamentals of Digital Logic With Verilog Design.
 M. Morris Mano, Digital Design

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