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Lecture #11

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5 views9 pages

Lecture #11

Uploaded by

Teshome Girma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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 Decoders

 logic circuit with n inputs and 2n outputs.


 Decoder circuits are used to decode encoded information.
 Only one output is asserted at a time, and each output corresponds to one valuation of
the inputs.
 The decoder also has an enable input, En, that is used to disable the outputs; if En = 0,
then none of the decoder outputs is asserted. If En = 1, the valuation of wn−1 · · ·w1w0
determines which of the outputs is asserted.

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 2-to-4 decoder
 The two data inputs, w1 and w0 represent a two-bit number that causes the decoder
to assert one of the outputs y0, . . . , y3.
 Setting the inputs w1w0 to 00, 01, 10, or 11 causes the output y0, y1, y2, or y3 to be
set to 1, respectively.

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 Larger decoders can be built using the sum-of-products structure or else they can be
constructed from smaller decoders.
 Building a 3-to-8 decoder using 2-to-4 decoders.
 The w2 input drives the enable inputs of the two decoders. The top decoder is
enabled if w2 = 0, and the bottom decoder is enabled if w2 = 1. This concept can
be applied for decoders of any size.

 Exercise: Construct a 4-to-16 decoder using 2-to-4 decoders.


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 Example #1: Building Multiplexers from Decoder
 The sum-of- products implementation of the 4-to-1 multiplexer requires AND
gates to distinguish the four different valuations of the select inputs s1 and s0.
 Hence, the 4-to-1 multiplexer becomes.

 The enable input of the decoder is not needed in this case, and it is set to 1.

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 Example #2: Building demultiplexers from Decoder
 The demultiplexer can be implemented using a decoder circuit. For example, the 2-
to-4 decoder shown below can be used as a 1-to-4 demultiplexer. In this case the En
input serves as the data input for the demultiplexer, and the y0 to y3 outputs are the
data outputs. The valuation of w1w0 determines which of the outputs is set to the
value of En.

 In practice decoder circuits are used much more often as decoders rather than as
demultiplexers.

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 Encoders
 An encoder performs the opposite function of a decoder. It encodes given information
into a more compact form.
 Encoders are used to reduce the number of bits needed to represent given
information.
- Transmission: fewer wires.
- Storage: small data size.

Binary Encoders
 Encodes information from 2n inputs into an n-bit code as shown below.

 Exactly one of the input signals should have a value of 1, and the outputs present
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the binary number that identifies which input is equal to 1.
 4-to-2 encoder

 Observe that the output y0 is 1 when either input w1


or w3 is 1, and output y1 is 1 when input w2 or w3 is
1. Hence these outputs can be generated by the
circuit shown below.

 All input patterns that have multiple inputs set to 1 are not shown in the truth table, and
they can be treated as don’t-care conditions.

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 Priority Encoders
 In a priority encoder each input has a priority level associated with it.
 The encoder outputs indicate the active input that has the highest priority. When an
input with a high priority is asserted, the other inputs with lower priority are
ignored.
 4-to-2 priority encoder
 w0 has the lowest priority and w3 the highest.
 The outputs y1 and y0 represent the binary
number that identifies the highest priority
input set to 1.

 An output, z, is provided to indicate the condition of all inputs are 0.


 z=1 when at least one of the inputs is equal to 1.
 z=0 when all inputs are equal to 0. (The outputs y1 and y0 are not meaningful in this
case, and hence the first row of the truth table can be treated as a don’t-care condition
for y1 and y0.)
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 Let’s define a set of intermediate signals, i0, . . . , i3:
 Each signal, ik , is equal to 1 only if the input with the same index, wk , represents the
highest-priority input that is set to 1.
 The logic expressions for i0, . . . , i3 are -In terms of the intermediate signals, the
truth table becomes
i3 i2 i1 i0 y1 y0 z
0 0 0 0 x x 0
0 0 0 1 0 0 1
0 0 1 0 0 1 1
0 1 0 0 1 0 1
1 0 0 0 1 1 1

 Observing the truth tables, the circuit for the priority encoder has the same structure as
the 4-to-2 binary encoder.
 Encoder output
-What will be the circuit for the 4-to-1 priority encoder?

 Output z:
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