Scribd
Upload
22 views4 pages

Final

The document configures clock settings for various modules on a microcontroller by selecting clock sources and divisors. It sets the clock source and divisor for modules like the CPU, watchdog timer, timer units, ADC, CAN, and I2C through a series of clock control register writes with synchronization to ensure changes take effect.

Uploaded by

Siva Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
22 views4 pages

Final

The document configures clock settings for various modules on a microcontroller by selecting clock sources and divisors. It sets the clock source and divisor for modules like the CPU, watchdog timer, timer units, ADC, CAN, and I2C through a series of clock control register writes with synchronization to ensure changes take effect.

Uploaded by

Siva Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
You are on page 1/ 4

/* HS IntOSC setting */

CLKCTL.ROSCSTPM = _CGC_ROSCSTPM_DEFAULT_VALUE | _CGC_HSOSC_REQUEST_STOP;


/* PPLLCLK setting */
WPROTR.PROTCMD1 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_PPLLCLKS_CTL = _CGC_PPLLCLK_SOURCE_EMCLK;
CLKCTL.CKSC_PPLLCLKS_CTL = (uint32_t) ~_CGC_PPLLCLK_SOURCE_EMCLK;
CLKCTL.CKSC_PPLLCLKS_CTL = _CGC_PPLLCLK_SOURCE_EMCLK;
while ((CLKCTL.CKSC_PPLLCLKS_ACT & _CGC_PPLLCLK_SOURCE_ACTIVE) !=
_CGC_PPLLCLK_SOURCE_EMCLK)
{
NOP();
}
/* CPU clock setting */
WPROTR.PROTCMD1 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_CPUCLKS_CTL = _CGC_CPU_CLK_SOURCE_EMCLK;
CLKCTL.CKSC_CPUCLKS_CTL = (uint32_t) ~_CGC_CPU_CLK_SOURCE_EMCLK;
CLKCTL.CKSC_CPUCLKS_CTL = _CGC_CPU_CLK_SOURCE_EMCLK;
while (CLKCTL.CKSC_CPUCLKS_ACT != _CGC_CPU_CLK_SOURCE_EMCLK)
{
NOP();
}
WPROTR.PROTCMD1 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_CPUCLKD_CTL = _CGC_CPU_CLK_DIVIDER_1;
CLKCTL.CKSC_CPUCLKD_CTL = (uint32_t) ~(_CGC_CPU_CLK_DIVIDER_1);
CLKCTL.CKSC_CPUCLKD_CTL = _CGC_CPU_CLK_DIVIDER_1;
while (CLKCTL.CKSC_CPUCLKD_ACT != (_CGC_CPU_CLK_DIVIDER_1))
{
NOP();
}
/* WDTA0 clock domain setting */
WPROTR.PROTCMD0 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_AWDTAD_CTL = _CGC_WDTA_CLK_SOURCE_LSOSC_128;
CLKCTL.CKSC_AWDTAD_CTL = (uint32_t) ~_CGC_WDTA_CLK_SOURCE_LSOSC_128;
CLKCTL.CKSC_AWDTAD_CTL = _CGC_WDTA_CLK_SOURCE_LSOSC_128;
while (CLKCTL.CKSC_AWDTAD_ACT != _CGC_WDTA_CLK_SOURCE_LSOSC_128)
{
NOP();
}
CLKCTL.CKSC_AWDTAD_STPM = _CGC_CKSC_AWDTAD_STPM_DEFAULT_VALUE |
_CGC_WDTA_CLK_REQUEST_STOP;
/* TAUJ0 clock domain setting */
WPROTR.PROTCMD0 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_ATAUJS_CTL = _CGC_TAUJ_CLK_SOURCE_HSOSC;
CLKCTL.CKSC_ATAUJS_CTL = (uint32_t) ~_CGC_TAUJ_CLK_SOURCE_HSOSC;
CLKCTL.CKSC_ATAUJS_CTL = _CGC_TAUJ_CLK_SOURCE_HSOSC;
while (CLKCTL.CKSC_ATAUJS_ACT != _CGC_TAUJ_CLK_SOURCE_HSOSC)
{
NOP();
}
WPROTR.PROTCMD0 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_ATAUJD_CTL = _CGC_TAUJ_CLK_DIVIDER_1;
CLKCTL.CKSC_ATAUJD_CTL = (uint32_t) ~_CGC_TAUJ_CLK_DIVIDER_1;
CLKCTL.CKSC_ATAUJD_CTL = _CGC_TAUJ_CLK_DIVIDER_1;
while (CLKCTL.CKSC_ATAUJD_ACT != _CGC_TAUJ_CLK_DIVIDER_1)
{
NOP();
}
CLKCTL.CKSC_ATAUJD_STPM = _CGC_CKSC_ATAUJD_STPM_DEFAULT_VALUE |
_CGC_TAUJ_CLK_REQUEST_STOP;
/* RTCA0 clock domain setting */
WPROTR.PROTCMD0 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_ARTCAS_CTL = _CGC_RTCA_CLK_SOURCE_DISABLE;
CLKCTL.CKSC_ARTCAS_CTL = (uint32_t) ~_CGC_RTCA_CLK_SOURCE_DISABLE;
CLKCTL.CKSC_ARTCAS_CTL = _CGC_RTCA_CLK_SOURCE_DISABLE;
while (CLKCTL.CKSC_ARTCAS_ACT != _CGC_RTCA_CLK_SOURCE_DISABLE)
{
NOP();
}
WPROTR.PROTCMD0 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_ARTCAD_CTL = _CGC_RTCA_CLK_DIVIDER_DISABLE;
CLKCTL.CKSC_ARTCAD_CTL = (uint32_t) ~_CGC_RTCA_CLK_DIVIDER_DISABLE;
CLKCTL.CKSC_ARTCAD_CTL = _CGC_RTCA_CLK_DIVIDER_DISABLE;
while (CLKCTL.CKSC_ARTCAD_ACT != _CGC_RTCA_CLK_DIVIDER_DISABLE)
{
NOP();
}
/* ADCA0 clock domain setting */
WPROTR.PROTCMD0 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_AADCAS_CTL = _CGC_ADCA0_CLK_SOURCE_HSOSC;
CLKCTL.CKSC_AADCAS_CTL = (uint32_t) ~_CGC_ADCA0_CLK_SOURCE_HSOSC;
CLKCTL.CKSC_AADCAS_CTL = _CGC_ADCA0_CLK_SOURCE_HSOSC;
while (CLKCTL.CKSC_AADCAS_ACT != _CGC_ADCA0_CLK_SOURCE_HSOSC)
{
NOP();
}
WPROTR.PROTCMD0 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_AADCAD_CTL = _CGC_ADCA0_CLK_DIVIDER_1;
CLKCTL.CKSC_AADCAD_CTL = (uint32_t) ~_CGC_ADCA0_CLK_DIVIDER_1;
CLKCTL.CKSC_AADCAD_CTL = _CGC_ADCA0_CLK_DIVIDER_1;
while (CLKCTL.CKSC_AADCAD_ACT != _CGC_ADCA0_CLK_DIVIDER_1)
{
NOP();
}
CLKCTL.CKSC_AADCAD_STPM = _CGC_CKSC_AADCAD_STPM_DEFAULT_VALUE |
_CGC_ADCA0_CLK_REQUEST_STOP;
/* RLIN clock domain setting */
WPROTR.PROTCMD1 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_ILINS_CTL = _CGC_RLIN_CLK_SOURCE_PPLLCLK2;
CLKCTL.CKSC_ILINS_CTL = (uint32_t) ~_CGC_RLIN_CLK_SOURCE_PPLLCLK2;
CLKCTL.CKSC_ILINS_CTL = _CGC_RLIN_CLK_SOURCE_PPLLCLK2;
while (CLKCTL.CKSC_ILINS_ACT != _CGC_RLIN_CLK_SOURCE_PPLLCLK2)
{
NOP();
}
WPROTR.PROTCMD1 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_ILIND_CTL = _CGC_RLIN_CLK_DIVIDER_1;
CLKCTL.CKSC_ILIND_CTL = (uint32_t) ~_CGC_RLIN_CLK_DIVIDER_1;
CLKCTL.CKSC_ILIND_CTL = _CGC_RLIN_CLK_DIVIDER_1;
while (CLKCTL.CKSC_ILIND_ACT != _CGC_RLIN_CLK_DIVIDER_1)
{
NOP();
}
CLKCTL.CKSC_ILIND_STPM = _CGC_CKSC_ILIND_STPM_DEFAULT_VALUE |
_CGC_RLIN_CLK_REQUEST_STOP;
/* Peripheral clock domain setting */
WPROTR.PROTCMD1 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_IPERI1S_CTL = _CGC_PERI1_CLK_SOURCE_PPLLCLK;
CLKCTL.CKSC_IPERI1S_CTL = (uint32_t) ~_CGC_PERI1_CLK_SOURCE_PPLLCLK;
CLKCTL.CKSC_IPERI1S_CTL = _CGC_PERI1_CLK_SOURCE_PPLLCLK;
while (CLKCTL.CKSC_IPERI1S_ACT != _CGC_PERI1_CLK_SOURCE_PPLLCLK)
{
NOP();
}
WPROTR.PROTCMD1 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_IPERI2S_CTL = _CGC_PERI2_CLK_SOURCE_PPLLCLK2;
CLKCTL.CKSC_IPERI2S_CTL = (uint32_t) ~_CGC_PERI2_CLK_SOURCE_PPLLCLK2;
CLKCTL.CKSC_IPERI2S_CTL = _CGC_PERI2_CLK_SOURCE_PPLLCLK2;
while (CLKCTL.CKSC_IPERI2S_ACT != _CGC_PERI2_CLK_SOURCE_PPLLCLK2)
{
NOP();
}
/* ADCA1 clock domain setting */
WPROTR.PROTCMD1 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_IADCAS_CTL = _CGC_ADCA1_CLK_SOURCE_DISABLE;
CLKCTL.CKSC_IADCAS_CTL = (uint32_t) ~_CGC_ADCA1_CLK_SOURCE_DISABLE;
CLKCTL.CKSC_IADCAS_CTL = _CGC_ADCA1_CLK_SOURCE_DISABLE;
while (CLKCTL.CKSC_IADCAS_ACT != _CGC_ADCA1_CLK_SOURCE_DISABLE)
{
NOP();
}
/* RS-CANn clock domains setting */
WPROTR.PROTCMD1 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_ICANS_CTL = _CGC_RSCAN_CLK_SOURCE_PPLLCLK;
CLKCTL.CKSC_ICANS_CTL = (uint32_t) ~_CGC_RSCAN_CLK_SOURCE_PPLLCLK;
CLKCTL.CKSC_ICANS_CTL = _CGC_RSCAN_CLK_SOURCE_PPLLCLK;
while (CLKCTL.CKSC_ICANS_ACT != _CGC_RSCAN_CLK_SOURCE_PPLLCLK)
{
NOP();
}
CLKCTL.CKSC_ICANS_STPM = _CGC_CKSC_ICANS_STPM_DEFAULT_VALUE |
_CGC_RSCAN_CLK_REQUEST_STOP;
WPROTR.PROTCMD1 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_ICANOSCD_CTL = _CGC_RSCANOSC_CLK_SOURCE_DISABLE;
CLKCTL.CKSC_ICANOSCD_CTL = (uint32_t) ~_CGC_RSCANOSC_CLK_SOURCE_DISABLE;
CLKCTL.CKSC_ICANOSCD_CTL = _CGC_RSCANOSC_CLK_SOURCE_DISABLE;
while (CLKCTL.CKSC_ICANOSCD_ACT != _CGC_RSCANOSC_CLK_SOURCE_DISABLE)
{
NOP();
}
/* CSI clock domain setting */
WPROTR.PROTCMD1 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_ICSIS_CTL = _CGC_CSI_CLK_SOURCE_PPLLCLK;
CLKCTL.CKSC_ICSIS_CTL = (uint32_t) ~_CGC_CSI_CLK_SOURCE_PPLLCLK;
CLKCTL.CKSC_ICSIS_CTL = _CGC_CSI_CLK_SOURCE_PPLLCLK;
while (CLKCTL.CKSC_ICSIS_ACT != _CGC_CSI_CLK_SOURCE_PPLLCLK)
{
NOP();
}
/* IIC clock domain setting */
WPROTR.PROTCMD1 = _WRITE_PROTECT_COMMAND;
CLKCTL.CKSC_IIICS_CTL = _CGC_IIC_CLK_SOURCE_PPLLCLK2;
CLKCTL.CKSC_IIICS_CTL = (uint32_t) ~_CGC_IIC_CLK_SOURCE_PPLLCLK2;
CLKCTL.CKSC_IIICS_CTL = _CGC_IIC_CLK_SOURCE_PPLLCLK2;
while (CLKCTL.CKSC_IIICS_ACT != _CGC_IIC_CLK_SOURCE_PPLLCLK2)
{
NOP();
}
/* Synchronization processing */
g_cg_sync_read = CLKCTL.CKSC_CPUCLKS_CTL;
__syncp();

You might also like