CMOS Design

BTech ( E & Tc) Sem-VI

Prepared By
Prof. (Dr.) Shruti Oza-Rahurkar

Prepared by Prof (Dr) Shruti Oza-Rahurkar

 PREFACE

CMOS VLSI Design and Technology have gained significant popularity due to rapid
advances in IC design and technology. With the help of CMOS VLSI design, it became
possible to miniaturize circuits along with improved performance in terms of power
and speed. CMOS VLSI design is a vast subject hence it is very complex to find
complete design process details. This material focuses on introduction to CMOS VLSI
Design. The material gives students a solid foundation and understanding of CMOS
VLSI Design and Technology.

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 1
MOS Transistor

Content

1.1 Basic MOS structure

1.2 MOS system under external bias
1.3 Operation of MOS transistor
1.4 MOSFET C-V characteristics
1.5 MOSFET scaling and small geometry effects
1.6 MOSFET capacitance

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1.1 Introduction
The MOS Field Effect Transistor(MOSFET) is the fundamental device used in CMOS
digital, analog and mixed integrated circuits. Compared to the bipolar junction
transistor (BJT), following are the benefits of using MOS devices.
• It occupies smaller area on silicon.
• Its fabrication (manufacturing process) is very simple compared to BJT.
• Its operation is Simple.
• It is basically a trans-conductance device.
• It is voltage operated device.

1.2 Basic MOS structure and flat-band voltage

A simple two-.terminal MOS structure is shown in Fig. 1.1. The structure consists of
three layers.
• Metal gate electrode,
• Insulating oxide (SiO2) layer,
• P-type bulk semiconductor (Si), called the substrate.
The MOS structure inherently forms a parallel plate capacitor (the metal gate and the
substrate acting as the two terminals (plates) and the oxide layer as the dielectric). The
thickness of the SiO2 layer is usually between 10-50 nm. The effect of different bias
conditions on MOS structure is useful to understand the behavior of MOSFET.

Fig.1.1 Two terminal MOS structure

The energy band diagram of the p-type substrate is shown in Fig. 1.2.Now in p type
silicon (doped with boron using doing concentration NA) the equilibrium hole
concentration is given as NA and electron concentrations is given as ni2/NA. The band-
gap between the conduction band and the valence band for silicon is approximately 1.1

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eV. The location of the Fermi level EFpwithin the band-gap is determined by the doping
type and the doping concentration in the silicon substrate. The Fermi potential
ΦFp(defined as amount by which intrinsic Fermi level(EI) shift due to doping of boron
atoms in p type si, The Fermi potential is a function of temperature and doping
concentration and can be expressed as equation below.

--------(1.1)

Fig.1.2 Energy band diagram of P type silicon.

For a p-type semiconductor, the Fermi potential can also be expressed as,

---------(1.2)
Whereas for an n-type semiconductor (doped with a donor concentration ND), the
Fermi potential is written as,

-------------(1.3)
Here, k denotes the Boltzmann constant; q denotes the unit (electron) charge.

The Fermi potential is positive voltage in case of n-type material and negative voltage
for p-type material. To understand the energy band diagram of MOS system following
two important terms is defined as follows.
• The electron affinity (qΧ)of silicon is defined as the energy required for an
electron to move from the conduction band into free space.
• The work function (Фs), is defined as the energy required for an electron to
move from the Fermi level into free space is called the work function Фs, and
is given by,

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 ----------(1.4)
The energy band diagram of MOS system is denoted in Fig. 1.3.
• The silicon dioxide layer between the p type silicon substrate and the metal gate
has a large band-gap of about 8 eV. and an electron affinity of 0.95 eV.
• The work function qΦMof metal gate is about 4.1 eV.
• The work function of p type silicon is energy required to move the electron from
EFp =(electron affinity of si +1/2 band gap energy + energy difference (EFp-EI))

Fig.1.3 Energy band diagram of MOS structure before fabrication.

Now when MOS structure is fabricated (in a fabrication lab) as shown in Fig.1.1
following physical phenomena, occur due to the work-function difference between
metal and semiconductor layers.
• The Fermi levels of all three materials line-up.
• The line-up process results in a built in voltage drop across MOS system
(material layer lying at higher energy level gives out its energy results in a
voltage drop).
• Part of this built-in voltage drop occurs across the insulating oxide layer and the
rest of the voltage drop (potential difference) occurs at the silicon surface next
to the silicon-oxide interface.
• This forces the energy bands of silicon to bend downward near the surface while
the bulk Fermi levels are unaffected.
If a voltage corresponding to work function difference between metal and p type silicon
is applied externally between the gate and the substrate, the bending of the energy bands
near the surface can be compensated. The amount of corrective voltage needs to be
applied to flatten the bands is called flat-band voltage.

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The resulting combined energy band diagram of the MOS system is shown in Fig. 1.4
.Following are the observations regarding the energy band diagrams.
• The equilibrium Fermi levels of the semiconductor (Si) substrate and the metal
gate are at the same potential.
• The Fermi potential at the surface, also called surface potential Φs, is smaller in
magnitude than the bulk Fermi potential ΦF.
• The bulk Fermi level is not affected by the band bending, whereas the surface
Fermi level moves closer to the intrinsic Fermi (mid-gap) level.

Fig.1.4 energy band diagram of combined MOS system

1.3 MOS structure under external bias

The electrical behaviour of MOS structure under external bias condition must be
understood first to understand the operation of MOSFET. Now, assume the substrate
voltage VB is set to zero. Depending on the polarity and the magnitude of VG, three
different operating regions can be observed for the system.
• Accumulation,
• Depletion and
• Inversion.

1. VG : Very small negative corresponds to accumulation.

If a negative voltage VG is applied to the gate electrode, the holes in the p-type substrate
are attracted to the semiconductor-oxide interface. The hole concentration at surface of
p type substrate (near the oxide interface) becomes larger than the equilibrium hole
concentration inside the p type si substrate. This is called carrier accumulation on the
surface of p type silicon substrate (Fig. 1.5).The direction of oxide electric field is
towards the gate electrode. (Electric field is always drawn from positive field to
negative field) The negative surface potential also causes the energy bands to bend
upward near the surface. While the hole density near the surface increases as a result of

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the applied negative gate bias, the electron (minority carrier) concentration decreases
as the negatively charged electrons are pushed deeper into the substrate.

Fig.1.5A cross section view of MOS structure and energy band diagram in accumulation region

2. VG: Very small positive corresponds to depletion.

Now consider the next case in which a small positive gate bias VG is applied to the gate
electrode. The positive gate voltage tends to induce equal amount of negative charge
on opposite side due to parallel plate capacitor arrangements (near Si-SiO2
interface).Due to positive voltage on gate, the holes lying in the p type substrate, will
be repelled back into the substrate and these holes will leave negatively charged fixed
acceptor ions behind. Thus, a depletion region is created near the surface. Note that
under this bias condition, the region near the semiconductor-oxide interface is nearly
devoid of all mobile carriers Since the substrate bias is set to zero, the oxide electric
field will be directed towards the substrate in this case. The positive surface potential
causes the energy bands to bend downward near the surface, as shown in Fig. 1.6.

Fig.1.6 A cross section view of MOs structure and energy band diagram in depletion region

The majority carriers, i.e., the holes in the substrate, will be repelled back into the
substrate as a result of the positive gate bias, and these holes will leave negatively
charged fixed acceptor ions behind. Thus, a depletion region is created near the surface.
Note that under this bias condition, the region near the semiconductor-oxide interface
is nearly devoid of all mobile carriers.

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The thickness Xd of this depletion region on the surface can easily be found as a function
of the surface potentials. Thus, the depth of the depletion region is proportional to
square root of surface potential and inversely proportional to doping concentration
expressed by poisons equation as below.

----------(1.5)
3. VG: large positive corresponds to inversion.
To complete our discussion of different gate bias conditions and their effects upon the
MOS system, next case is further increase in the positive gate bias. As a result of the
increasing surface potential VG in positive direction, the minority carriers (electrons)
in the p type silicon substrate tend together at si-sio2 interface.

Fig.1.7 A cross section view of MOs structure and energy band diagram in strong
inversion region
When the electron concentration is greater than hole concentration at si-sio2 interface,
the surface of p type silicon is converted in to n-type. This tends to increase the
downward bending further at the surface. The n-type region created at si-sio2 surface
by the positive gate bias is called the surface inversion layer, and this condition is
called surface inversion. It will be seen that the thin inversion layer on the surface with
a large mobile electron concentration can be utilized for conducting current between
two terminals of the MOS transistor
1.5 MOSFET structure and operation of MOS transistor
The basic structure of an n-channel MOSFET is shown in Fig. 1.8. This four-terminal
device consists of a p-type substrate, in which two n+ diffusion regions, the drain and
the source formed. The surface of the substrate region between the drain and the source
is converted with a thin oxide layer, and the metal (or poly silicon) gate is deposited on
top of this gate dielectric. The midsection of the device can easily be recognized as the

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basic MOS structure which was examined in the previous sections. The two n+ regions
will be the current conducting terminals of this device. The device structure
iscompletely symmetrical with respect to the drain and source regions. The device can
be operated in cut-off, linear and saturation mode.

Fig.1.8 A basic structure of n channel enhancement MOSFET.

A conducting channel is formed through applied gate voltage in the section of the
device between the drain and the source diffusion regions. The distance between the
drain and source diffusion regions is the channel length L, and the lateral extent of the
channel (perpendicular to the length dimension) is the channel width W. Both the
charnel length and the channel width are important parameters which can be used to
control some of the electrical properties of the MOSFET. The thickness of the oxide
layer covering the channel region, tox, is also an important parameter.
• A MOS transistor which has no conducting channels at zero gate bias an
enhancement-type MOSFET.
• If a conducting channel already exists at zero gate bias the device is called a
depletion-type MOSFET.
In a MOSFET with p-type substrate and with n+ source and drain regions, the channel
region to be formed on the surface is n-type. Thus, such a device with p-type substrate
is called an n-channel MOSFET. In a MOSFET with n-type substrate and with p+
source and drain regions, on the other hand, the channel is p-type and the device is
called a p-channel MOSFET.

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 Fig.1.9 A circuit symbol of n and p channel transistor

• The abbreviations used for the device terminals are: G for the gate, D for the
drain s for the source, and B for the substrate (or body).
• In an n-channel MOSFET, the source is defined as n region which has a lower
potential than the other n region namely drain. By convention, all terminal
voltages of the device are defined with respect to the source potential.
• The gate-to-source voltage is denoted by VGS, the drain-to-source voltage is
denoted by VDS, and the substrate-to-source voltage is denoted by VBS. Circuit
symbols for both n-channel and p-channel enhancement-type MOSFETs are
shown in Fig. 1.9.
.
The n-channel enhancement-type MOSFET is biased in depletion, linear and saturation
mode as shown in Fig: 1.10(a),(b),(c). Here we require two batteries VGS and VDS. The
source, the drain, and the substrate terminals are all connected to ground. A positive
gate-to-source voltage VGSis then applied to the gate in order to create the conducting
channel below the gate oxide layer SiO2.
The value of the gate-to-source voltage VGS needed to cause surface inversion (to create
the conducting channel) is called the threshold voltage VTO. Any gate- to-source voltage
smaller than VT0 is not sufficient to establish an inversion layer; thus, the MOSFET can
conduct no current between its source and drain terminals unless VGS >VTO.The device
is held in depletion for this condition as shown in fig.1.10(a).

Fig.1.10(a) Enhancement MOSFET biased in depletion mode.

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 Fig.1.10(b) Enhancement MOSFET biased in linear mode

Fig.1.10(c) Enhancement MOSFET biased in saturation mode

For gate-to-source voltages larger than the threshold voltage, on the other hand, a larger
number of minority carriers (electrons) are attracted to the surface, which ultimately
contributes to channel current conduction. Also note that increasing the gate to-source
voltage above and beyond the threshold voltage will not affect the surface potential and
the depletion region depth. Both quantities will remain approximately constant and
equal to their values attained at the surface inversion.
Now if the drain is biased positive with respect to source ,the induced channel provides
an electrical connection between the two n+ regions, and it allows current flow, as long
as there is a potential difference between the source and the drain terminal voltages as
shown Fig.1.10(b).
The electron velocity, in the channel for this case is usually much lower than the drift
velocity limit. Note that as the drain voltage is increased, the inversion layer charge and
the channel depth at the drain end start to decrease. Eventually, for VDS = VDSAT, the
inversion charge at the drain is reduced to zero, which is called the pinch-off point
.When the source voltage is equal to drain voltage conducting channel at the drain
pinch-off(VGS-VT =VD.Thus, in linear region operation, the channel region acts as a
voltage-controlled resistor S). If VDS in further increased i.e VGS-VT<VDS condition is
reached and the pinch off point shift toward source side. the effective channel length
reduces due to this and the device is held in saturation mode.

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Beyond the pinch-off point, i.e., for VDS>VDSAT, a depleted surface region forms
adjacent to the drain, and this depletion region grows toward the source with increasing
drain voltages. This operation mode of the MOSFET is called the saturation mode or
the saturation region; For a MOSFET operating in the saturation region, the effective
channel length is reduced as the inversion layer near the drain vanishes, while the
channel-end voltage remains essentially constant and equal to VDSAT(Fig. 1.10(c)). Note
that the pinched-off (depleted) section of the channel absorbs most of the excess voltage
drop (VDS - VDSAT) and a high-field region forms between the channel-end and the drain
boundary. Electrons arriving from the source to the channel-end are injected into the
drain-depletion region and are accelerated toward the drain in this high electric field,
usually reaching the drift velocity limit. The pinch-off event, or the disruption of the
continuous channel under high drain bias, characterizes the saturation mode operation
of the MOSFET.

1.6 MOSFET Current Voltage characteristics and derivation of drain current ID

The analytical derivation of the MOSFET current-voltage relationships for various bias
conditions requires that several approximations be made to simplify the problem. Here,
we will use the gradual channel approximation (GCA) for establishing the MOSFET
current-voltage relationships, which will effectively reduce the analysis to a one-
dimensional current-flow problem from 2-D.

Gradual Channel Approximation

To begin with the current-flow analysis, consider the cross-sectional view of the n
channel MOSFET operating in the linear mode, as shown in Fig. 1.11. Here, the source
and the substrate terminals are connected to ground, i.e., Vs = VB = 0. The gate-to-
source voltage (VGS) and the drain-to-source voltage (VDS) are the external parameters
controlling the drain (channel) current ID.
The gate-to-source voltage is set to be larger than the threshold voltage VT. To create
a conducting inversion layer between the source and the drain. We define the coordinate
system for this structure such that the x-direction is perpendicular to the surface,
pointing down into the substrate, and the y-direction is parallel to the surface.
• The y-coordinate origin (y = 0) is at the source end of the channel.* Thechannel
voltage with respect to the source will be denoted by Vc(y).

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 • Now assume that the threshold voltage VT. is constant along the entire channel
region, between y = 0 and y = L. In reality, the threshold voltage changes along
the channel since the channel voltage is not constant.
• Next, assume that the electric field component Ey(due to VDS) along the y-
coordinate is dominant compared to the electric field component Ex(due to VGS)
along the x-coordinate.
• This assumption will allow us to reduce the current-flow problem in the channel
to the y dimension only. Note that the boundary conditions for the channel
voltage Vc(y) are:

------(1.14)
Also, it is assumed that the entire channel region between the source and the drain is
inverted, i.e.,

--------(1.15)
The channel current (drain current) IDis due to the electrons in the channel region
travelling from the source to the drain under the influence of the lateral electric field
component Ey(VDS). Since the current flow in the channel is primarily governed by the
lateral drift of the mobile electron charge in the surface inversion layer, we will consider
the amount and the bias-voltage dependence of this inversion layer in more detail. Let
Q(y) be the total mobile electron charge in the surface inversion layer. This charge can
be expressed as a function of the gate-to-source voltage VGSand of the channel voltage
V(y) as follows:

---------(1.16)
Figure 1.16 shows the spatial geometry of the surface inversion layer and indicates its
significant dimensions. Note that the thickness of the inversion layer tapers off as we
move from the source to the drain, since the gate-to-channel voltage causing surface
inversion is smaller at the drain end.
Now consider the incremental resistance dRof the differential channel segment shown
in Fig. 1.16. Assuming that all mobile electrons in the inversion layer have a constant
surface mobility jun, the incremental resistance can be expressed as follows. Note that
the minus sign is due to the negative polarity of the inversion layer charge Q1.

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 ----------(1.17)
The electron surface mobility µnused in (1.28) depends on the doping concentration of
the channel region, and its magnitude is typically about one-half of that of the bulk
electron mobility.

Fig.1.11 Simplified geometry of channel in linear region

We will assume that the channel current density is uniform across this segment.
According to our one-dimensional model, the channel (drain) current IDflows between
the source and the drain regions in the y-coordinate direction. Applying Ohm's law for
this segment yields the voltage drop along the incremental segment dy, in the y
direction.

----------(1.18)
This equation can now be integrated along the channel, i.e., from y = 0 to y = L, using
the boundary conditions given in.

------------(1.19)
The left-hand side of this equation is simply equal to L ID. The integral on the right-
hand side is evaluated by replacing Q1(y) with (1.27). Thus,

-----------(1.20)
Assuming that the channel voltage V, is the only variable in (1.31) that depends on
the position y, the drain current is found as follows.

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 --------------(1.21)
Equation (1.12) represents the drain current ID as a simple second-order function of
the two external voltages, VGS and VDS. This current equation can also be rewritten
as,

---------------(1.22)

---------------(1.23)
where the parameters k and k' are defined as

---------------(1.24)

---------------(1.25)
The drain current equation given in (1.33) is the simplest analytical approximation for
the MOSFET current-voltage relationship. Note that, in addition to the process
dependent constants k' and V, the current-voltage relationship is also affected by the
device dimensions, W and L. In fact, we will see that the ratio of W/L is one of the most
important design parameters in MOS digital circuit design. Now, we must determine
the region of validityfor this equation and what this means for the practical use of the
equation.shows that the current equation (1.32) is not valid beyond the linear
region/saturation region boundary, i.e., for

----------(1.26)
Also, drain current measurements with constant VDSshow that the current IDdoes not
show much variation as a function of the drain voltage. VDSbeyond the saturation
boundary, but rather remains approximately constant around the peak value reached for
VDS = VDSATThis saturation drain current level can be found simply by substituting
(1.27) for VDSin (1.22).

-----------(1.27)
Thus, the drain current IDbecomes a function only of the gate-to-source voltage VGS,
beyond the saturation boundary. Note that this constant saturation current
approximation is not very accurate in reality, and that the saturation-region drain current

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continues to have a certain dependence on the drain voltage. For simple hand
calculations, however,(1.27) provides a sufficiently accurate approximation of the
MOSFET drain (channel)current in saturation as shown in Fig.1.13 .

Fig.1.13 basic current voltage characteristic of nMOS transistor

Fig.1.14 MOSFET operated in channel length modulation.

If the drain-to-source voltage VDSis increased beyond the saturation edge so that VDS>
VDSAT, an even larger portion of the channel becomes pinched-off. Consequently, the
effective channel length(the length of the inversion layer where GCA is still valid) is
reduced to, Note that this current equation corresponds to a MOSFET with effective
channel length L', operating in saturation. Thus, (1.29) accounts for the actual
shortening of the channel, also called channel length modulation as shown in
Fig.1.14.The current voltage characteristic is shown in Fig.1.15 with channel length
modulation effect.

---------(1.28)

---------(1.29)

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 Fig.1.15 MOSFET current voltage characteristic with channel length modulation

A complete first-order characterization of the drain (channel) current as a nonlinear

function of the terminal voltages.

----------(1.30)

1.7 MOSFET scaling and small geometry effects

The design of high-density chips in MOS VLSI (Very Large-Scale Integration)

technology requires that the packing density of MOSFETs used in the circuits is as high

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as possible and, consequently, that the sizes of the transistors are as small as possible.
The reduction of the size, i.e., the dimensions of MOSFETs, is commonly referred to
as scaling. It is expected that the operational characteristics of the MOS transistor will
change with the reduction of its dimensions. Also, some physical limitations eventually
restrict the extent of scaling that is practically achievable. There are two basic types of
size-reduction strategies: full scaling(also called constant-field scaling) and constant
voltage scaling. Both types of scaling approaches will be shown to have unique effects
upon the operating characteristics of the MOS transistor. In the following, we will
examine in detail the scaling strategies and their effects, and we will also consider some
of the physical limitations and small-geometry effects that must be taken into account
for scaled MOSFETs.
Scaling of MOS transistors is concerned with systematic reduction of overall
dimensions of the devices as allowed by the available technology, while preserving the
geometric ratios found in the larger devices. The proportional scaling of all devices in
a circuit would certainly result in a reduction of the total silicon area occupied by the
circuit, thereby increasing the overall functional density of the chip. To describe device
scaling, we introduce a constant scaling factor S >1. All horizontal and vertical
dimensions of the large-sizetransistor are then divided by this scaling factor to obtain
the scaled device. The extent of scaling that is achievable is obviously determined by
the fabrication technology and more specifically, by the minimum feature size.
We consider the proportional scaling of all three dimensions by the same scaling factor
S. Figure 1.24 shows the reduction of key dimensions on a typical MOSFET, together
with the corresponding increase of the doping densities.

Fig.1.16 Scaling of MOSFET with factor S

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Full Scaling (Constant-Field Scaling)
In this type of scaling the magnitude of internal electric fields in the MOSFET is kept
constant, while the dimensions are scaled down by a factor of S. To achieve this, all
potentials must be scaled down proportionally, by the same scaling factor. This scaling
also affects the threshold voltage VT0. Finally, the Poisson equation describing the
relationship between charge densities and electric fields dictates that the charge
densities must be increased by a factor of S in order to maintain the field conditions.
Table 1.1.lists the scaling factors for all significant dimensions, potentials, and doping
densities of the MOS transistor. Table 1.2 shows the effect of full scaling on device
characteristics.

Table 1.1 MOSFET dimensions, doping and Voltages affected by Full scaling

Table 1.2 Effect of device full scaling on device characteristics

In constant-voltage scaling, all dimensions of the MOSFET are reduced by a factor of

S, as in full scaling. But the power supply voltage and the terminal voltages, on the
other hand, remain unchanged. The doping densities must be increased by a factor of S
/ 1.41 in order to preserve the charge-field relations. Table 1.3,1.4 shows the constant-
voltage scaling of key dimensions, voltages, and densities. Under constant-voltage
scaling, the changes in device characteristics are significantly different compared to
those in full scaling, as we will demonstrate. The gate oxide capacitance per unit area
Cox is increased by a factor of S, which means that the trans-conductance parameter is
also increased by S.

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 Table 1.3 Constant voltage scaling effect on device dimensions, doping and Voltages

Table 1.4 Effect of constant device scaling on device characteristics

Short-Channel Effects
A MOS transistor is called a short-channel device if its channel length is of the same
order of magnitude as the depletion region thicknesses of the source and drain junctions.
Alternatively,
A MOSFET can be defined as a short-channel device if the effective channel length Leff
is approximately equal to the source and drain junction depth x.. The short-channel
effect causes two physical phenomena: (i) Mobility degradation, and (ii) the
modification of the threshold voltage due to the shortening channel length.

Narrow channel effect

MOS transistors that have channel widths W on the same order of magnitude as the
maximum depletion region thickness xdm are defined as narrow-channel devices. Like
the short-channel effects, the narrow-channel MOSFETs also exhibit mobility and
threshold voltage degradation.
Channel length Modulation
Ideally Ids is independent of Vds for a transistor in saturation, making the transistor a
perfect current source. The reverse biased p-n junction between the drain and body
forms a depletion region with width Ld a that increases with vds.The depletion region
reduces the channel length. Leff= L-Ld. Hence increasing Vds decreases the effective
channel length. Shorter channel results in higher current thus, Ids increases with Vds in
saturation region. This can be crudely approximated by a factor of (1+λVds) where λ is
channel length modulation factor.

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Substrate bias effects
The potential difference between source and body affect threshold voltage. The
threshold voltage is modeled as Vt= Vto+ γ [sqrt(Фs +Vsb)- sqrt(Фs)].Where
Vto=threshold voltage at zero substrate bias effect Фs is surface potential at threshold
and γ is body effect coefficient unit V1/2.

1.8 MOSFET small signal capacitance model

In order to examine the transient (AC) response of MOSFETs and digital circuits
consisting of MOSFETs, on the other hand, we have to determine the nature and the
amount of parasitic capacitances associated with the MOS transistor. There are two
types of MOS capacitances appear between device terminals as shown in Fig.1.17,18
due to MOS structure ,Channel charge exists between source and drain diffusion areas
and reverse bias P N junction formed due to n+ diffusion(Source and drain) surrounded
by P+ channel stop diffusion as well as P type substrate. They can be classified as
follows.
1. Oxide related overlapping and channel charge capacitances
There are two overlapping capacitances due to overlap between Metal gate and source
drain diffusion.

Fig.1.17 Cross section and top view of MOS system.

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 Fig.1.18 Lumped capacitance of MOS transistor.

They as CGS and CGD = COX *W *LD Where COX is oxide capacitance W is width of
MOS transistor while LD is overlap length as shown in fig. below.
There is also a capacitance due to channel charge between gate and source drain region.
This capacitance is influenced by region of operation of MOS transistor as shown in
Table 1.5.
• When MOS is held in cut-off region i.e channel is absent.TheCgb (gate to bulk)
= COX *W *L
• When the MOS is held in linear mode Cgs = Cgd = 1/2 *COX *W *L
• When the MOS is held in saturation mode Cgs = 2/3 *COX *W *L
2. Junction Capacitances
The reverse bias PN junction between source / drain and body contribute parasitic
capacitances. This capacitance depends on area A and Perimeter P. Area = W*D while
perimeter P = 2*W+2*D. Total source/drain capacitance = A(S/D)*Cjbs+P(S/D)*Cjbssw,
where Cjbs=capacitance/area while Cjbssw= capacitance/length
Cjbs = CJ (1+VSB/ψo) –MJ where Cj is junction capacitance at zero bias, MJ is junction
grading coefficient ψo= υT (NA*ND)/ni2 and υT is thermal voltage.
Cjbssw = CJsw(1+VSB/ψo) –MJswCjbssw is junction sidewall capacitance at zero bias,MJsw
is junction grading co-efficient.

Fig.1.5 Approximate three oxide capacitance value for three operating regions.

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Exercises:

Detailed Questions
1. Describe MOS system under external bias with the help of energy band diagram.
2. What is Gradual channel approximation? Discuss in detail.
3. Derive the expression of drain current Id in linear and saturation region.
4. Why do we use scaling? Explain the different types of scaling with their merits and
demerits.
5. Discuss short and narrow channel effects arise due to scaling.
6. Discuss MOS capacitance model with necessary detail.
7. Discuss channel length modulation and substrate bias effect in detail.

Brief Questions
1. Define “electron affinity” and “work function”.
2. What is surface potential?
3. Name the types of scaling.
4. Name types of parasitic capacitances in MOS.
5. Give the advantages of scaling.
6. Define “channel length modulation”.
7. Define substrate bias effect.

Prepared by Prof (Dr) Shruti Oza-Rahurkar