3

MOS Inverters: Switching

Characteristics and Interconnect Effects
Contents:

3.1 Introduction
3.2 Delay Time Definitions
3.3 Calculation of Delay Times
3.4 Inverter design with delay constraints
3.5 Estimation of Interconnect Parasitics
3.6 Calculation of Interconnect Delay

Prepared by Prof (Dr) Shruti Oza-Rahurkar

3.1 Introduction
The switching characteristics of digital ICs determine the overall operating speed of
digital systems. The transient performance requirements of a digital system are the most
important design specifications. Thus, it is very important to estimate and optimize the
switching speed of the circuit during early design phase.

Figure 3.1 shows cascade connection of two CMOS inverter circuits along with
parasitic capacitances associated with each MOSFET. The capacitances Cgdand Cgs
are capacitance due to gate overlap with diffusion, while Cdband Csb are voltage-
dependent junction capacitances. The capacitance Cg is due to the thin gate oxide
capacitance. The capacitance Ci represents lumped parasitic capacitance contribution
of the metal or polysilicon interconnects. Assuming that a pulse waveform is applied at
the input of the first-stage inverter, the time-domain behavior of the first-stage output,
Vout can be analyzed.

Considering Fig. 3.1, combined lumped capacitance at the output node, denoted as
Cload, can be given by

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 …. (3.1)

In eqn. (3.1), some of the parasitic capacitances shown in Fig. 3.1 are not included, as
they have no effect on transient behaviour of the circuit.

Figure 3.2 shows single stage of inverter with lumped output capacitance Cload. Using
this figure, problem of analyzing transient behavior of inverter can be analyzed easily.
The question of inverter transient response is reduced to finding the charge-up and
charge-down times of a single capacitance that is charged and discharged through one
transistor.

3.2 Delay Time Definitions

Figure 3.3 shows the input and output voltage waveforms of a typical inverter circuit.

The propagation delay times τPHLand τPLHdetermine the input-to-output signal delay
during the high-to-low and low-to-high transitions of the output, respectively. Here,

τPHLis the time delay between the V50%-transition of the risinginput voltage and the
V50%-transition of the fallingoutput voltage. Similarly, τPLH is defined as the time delay
between the V50%-transition of the fallinginput voltage and the V50%-transition of the
risingoutput voltage.

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 Fig. 3.3 Input (ideal step) and output voltage waveforms of a typical inverter
with the definitions of propagation delay times.

Fig. 3.4 Output voltage rise and fall times.

In Fig. 3.3, the input voltage waveform is usually assumed to be an ideal step pulse with

zero rise and fall times. Under this condition, τPHLbecomes the time required for the
output voltage to fall fromVOH to theV50 % level, andτPLHbecomes the time required

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for the output voltage to rise from VOLto theV50 % level. The voltage point V50% is
defined as follows.

Referring Fig. 3.3, the propagation delay times τPHLandτPLHcan be written as

The average propagation delay τPof the inverter defines the average time required for
the input signal to propagate through the inverter.

Referring to Fig. 3.4, the rise timeτrise is defined here as the time required for the output

voltage to rise from the V10 % level toV90 %level. Similarly, the fall timeτfallis defined

here as the time required for the output voltage to drop from theV90 %level toV10 %

level. The voltage levelsV10 % andV90 % are defined as

Referring Fig. 3.4, the output rise and fall times can be written as follows.

3.3 Calculation of Delay Times

Based on average capacitance current estimation method:

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The simplest method for calculating the propagation delay times τPHLandτPLHis based
on estimating the average capacitance current during charge down and charge up,
respectively. If the capacitance current during an output transition is approximated by

a constant average current Iavgthe delay times are found as

The average current during high-to-low transition can be calculated by using the
current values at the beginning and the end of the transition:

Similarly, the average current during low-to-high transition can be calculated as

follows:

The average current method is simple and requires minimum calculations but neglects
variations of the capacitance current between the beginning and end points of the
transition. Thus, this method is not suitable for accurate estimation of the delay times.

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Fig. 3.5. Equivalent circuit of the CMOS inverter during high-to-low output transition.

Fig 3. 6. Input and output voltage waveforms during high-to-low transition

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3.4 Estimation of Interconnect Parasitics

To determine the switching speed of logic gate, the assumption made is that the loads
are mainly capacitive and lumped. The output load capacitance is having three main
components: (i) internal parasitic capacitances of the transistors, (ii) interconnect (line)
capacitances, and (iii) input capacitances of the fan-out gates.

Figure 3.7 shows an inverter is driving three other inverters, linked by interconnection
lines of different length and geometry. Here, for an accurate estimation of delay, the
capacitive/inductive coupling and the signal interference between neighboring lines
should be considered.

Fig. 3.7 An inverter driving three other inverters over interconnection lines
If the time of flight across the interconnection line is much shorter than the signal
rise/fall times, then the wire can be modeled as a capacitive load, or as a lumped or
distributed RC network. If the interconnection lines are sufficiently long and the rise
times of the signal waveforms are comparable to the time of flight across the line,
then the inductance also becomes important, and the interconnection lines must be
modeled as transmission lines. The following simple rule of thumb can be used to
determine when to use transmission-line models.

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Where, l is the interconnect line length, and v is the propagation speed. The
interconnection lines can be modeled by taking into consideration the RLCG
(resistance, inductance, capacitance, and conductance) parasitics as shown in Fig. 3.8.

Fig. 3.8 An RLCG interconnection tree

In submicron area, the intrinsic gate delays tend to decrease significantly. At the same
time, overall chip size and the worst-case line length on a chip tend to increase due to
increasing chip complexity, thus, the importance of interconnect delay increases in
submicron technologies. Figure 3.9 shows this fact, where typical intrinsic gate delay
and interconnect delay are plotted qualitatively, for different technologies. It can be
seen that for submicron technologies, the interconnect delay starts to dominate the gate
delay.

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Interconnect Capacitance Estimation

The capacitance components associated with parallel interconnection lines are shown
in Fig. 3.10.The capacitive coupling between neighboring lines is increased when the
thickness of the wire is comparable to its width. This coupling between the interconnect
lines is mainly responsible for signal crosstalk, where transitions in one line can cause
noise in the other lines.

Interconnect Resistance Estimation

The parasitic resistance of an interconnect line can also have a significant influence on
the signal propagation delay. The resistance of a line depends on the type of material
used (e.g., polysilicon, aluminum, or gold), the dimensions of the line and finally, the
number and locations of the contacts on that line. Referring Fig. 3.11, the total
resistance in the indicated current direction can be found as

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.

Fig. 3.11 Interconnect segment running parallel to the surface.

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Exercises:

Detailed Questions:

1. For CMOS inverter, describe various capacitance associated with it.

2. Derive the expression for propagation delay using average current method.

3. Derive the expression for τPHLusing state equation.

4. Explain RC delay model.
5. Discuss Elmore’s delay model with suitable example.
6. Derive the expression for switching power in CMOS.

Brief Questions:

Define following:

1. τPHLand τPLH.
2. Power delay product.
3. Rise time and fall time.
4. Interconnect resistance.
5. Interconnect capacitance.

Prepared by Prof (Dr) Shruti Oza-Rahurkar