4

Combinational MOS Logic Circuits

Content
4.1 Introduction
4.2 MOS logic circuits with depletion nMOS loads
4.3 CMOS logic circuits,
4.4 Complex logic circuits,
4.5 CMOS transmission gates

Prepared by Prof (Dr) Shruti Oza-Rahurkar

4.1 Introduction

The Combinational Logic Circuits is defined as a circuit which is used to perform

Boolean operations on multiple input variables and determine the outputs as Boolean
functions of the inputs. They are the basic building blocks of all digital systems. In this
chapter, we will examine the static and dynamic characteristics of various
combinational MOS logic circuits.
A generalized combinational logic circuit (logic gate) using positive logic is depicted
in Fig.4.1. Here, in this case logic value of " 1 " can be represented by a voltage VDD,
and logic value of "0" can be represented by voltage 0. The output node is loaded with
a capacitance CL, which represents the total parasitic capacitances seen at the output
node.

Fig.4.1Generic combinational logic circuit (gate).

For any logic gate following parameters are important from designers point of view.
• VTC and VOL(lower logic voltage) ,Vth
• Dynamic response characteristics
• Static and dynamic power Dissipation
• Silicon area

4.2 MOS logic circuits with depletion nMOS loads

The advantages of using depletion type nMOS as a load are as follows.

• Sharp VTC transition and better noise margins
• Single power supply, and
• Smaller overall layout area.

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Two-Input NOR Gate The Boolean OR operation is performed by the parallel
connection of the two enhancement-type nMOS driver transistors.

Figure 4.2. A two-input depletion-load NOR gate, its logic symbol, and the corresponding truth table. Note that the
substrates of all transistors are connected to ground.

• When both input voltages VA and VB are lower than the corresponding driver
threshold voltage, the driver transistors are turned off and conduct no drain
current. Consequently, the load device, which operates in the linear region, also
has zero drain current.

Output high logic level VOH = VDD

• When the input voltage VA or the input voltage VB is equal to the logic-high
level, the corresponding driver transistor turns on and provides a conducting
path between the output node and the ground. Hence, the output voltage
becomes low. In this case, the circuit operates like a depletion-load inverter with
respect to its static behavior.

In either case, or

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 VOL is given as

So if the (WIL) ratios of both drivers are identical, i.e., (W/L)A = (W/L)B the output
low voltage (VOL) values calculated for both case will be identical.
• When both VA and VB are high, two parallel conducting paths are created
between the output node and the ground. From the above discussion a simple
do not design strategy for NOR gates is as follows.
Kdriver,A=KdriverB=Kload
Transient analysis of two input NOR gate is as follows.

Fig. 4.3. Parasitic capacitances in the two input NOR gate and the lumped equivalent load capacitance.

Generalized NOR Structure with Multiple Inputs The generic n-input NOR gate
is shown in fig.4.4.From the circuit it can be said that n input require n driver
transistor and one depletion load transistor. It can also be said that (W/L) ratio of all
transistor i.e all driver and load must be same.

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 Fig.4.4 Generalized n-input NOR gate.

Two-Input NAND Gate The Boolean NOR operation is performed by the series
connection of the two enhancement-type nMOS driver transistors.

Fig 4.5. A two-input depletion-load NAND gate logic symbol, and the truth table.

• When both input voltages (VA and VB) and any one input is held at lower logic,
corresponding driver transistor is turned off and conduct no drain current.
Consequently, the load device, which operates in the linear region, also has zero
drain current so the output is high.
• When the input voltage VA and the input voltage VB is equal to the logic-high
level, both the driver transistors turns on and provides a conducting path

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 between the output node and the ground. Hence, the output voltage becomes
low.

4.3 CMOS logic circuits

CMOS logic circuit behavior is complementary in nature i.e. either pMOS or nMOS
logic is active at any time. In this case, the Boolean function is implemented via pMOS
as well as nMOS network. The pMOS network and nMOS network are dual of each
other .i.e. series connected pMOS is equal to parallel connected nMOS and vice versa.
The pMOS is known as pull up network and nMOS network is known as pull down
network. Consider fig.4.4 of NAND or NOR gate when input is low pMOS transistor
is on while nMOS is off and when input is high nMOS is on while pMOS is off.
The NAND gate of Fig. 4.4 requires both inputs to be high before the output will switch
low. Let's begin our analysis by determining the voltage transfer curve of a gate with
p-channel MOSFETs that have W =Wp, L =Lp and n-channel MOSFETs with W =
Wn, L = Ln If both inputs of the gate are tied together, the gate behaves like an inverter.
To determine the gate switching point voltage, Vsp we must remember that two
MOSFETs in parallel behave like a single MOSFET with a width equal to the sum of
the individual widths. For the two parallel p-channel MOSFETs in Fig. 4.4 we can write
W3+W4=2Wp.

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 Figure 4.4 NAND and NOR gate circuits and logic symbols.

Let us assume that all p-channel transistors are of the same size. The trans-conductance
parameters can also be combined into the trans-conductance parameter of a single
MOSFET, or β3+β4=2βp. If we neglect the body effect, then two MOSFETs in series
(with their gates tied together) behave like a single MOSFET with a channel length
equal to the sum of the individual MOSFET lengths. Referring to the figure above of
the NAND, we can write for the n-channel MOSFETs L1+L2=2Ln. and the trans-
conductance of the single MOSFET is given by β1+β2=βn/2.
If we model the NAND gate with both inputs tied together as an inverter with an n-
channel transistor having a width of Wn and length 2Ln and a p-channel MOSFET with
a width of 2Wp and length Lp ' then we can write the trans-conductance ratio as Trans-
conductance ratio of NAND gate = βn/ 4βp.The switching point voltage, with the help
of Eq. below, for two-input NAND gate is then given by,

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 Figure 4.5 Schematic of an n-input NAND gate.

The switching point voltage, with the help of eq. below, of the n-input NAND gate is
then given by,

Layout of Simple CMOS Logic Gates In Fig. 4.6 simplified (stick diagram) view of
the CMOS NOR2 gate given in Fig. 4.4 is shown. The stick-diagram layout does not
carry any information on the actual geometry relations of the individual features, but it
conveys valuable information on the relative placement of the transistors and their
interconnections. The stick diagram can be drawn as follows.
• The diffusion areas are depicted by rectangles,

• The metal connections and contacts are represented by solid lines and circles,
and

• The poly-silicon columns are represented by crosshatched strips.

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 Fig 4.6. Stick-diagram of CMOS 2 input NOR gate.

In the fig.4.7 and 4.8 simplified layouts of CMOS NOR2 and NAND2 gates are shown.
In this figure a sample layout of a 2 input CMOS NOR and NAND gate using single
layer metal and single-layer poly silicon is given. Here, the p-type diffusion area for
pMOS transistors and the n-type diffusion area for nMOS transistors are aligned in
parallel to perform the routing of the gate signals using two parallel poly silicon lines
running vertically.

Fig. 4.7 Sample layout of the CMOS NOR2 gate.

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 Fig. 4.8. Sample layout of the CMOS NAND2 gate.
4.4 Complex logic circuits

The ability to realize complex logic functions using a small number of transistors is one
of the most attractive features of nMOS and CMOS logic circuits. Consider the
following Boolean function as an example.

The nMOS depletion-load complex logic gate that is used to realize this function is
shown in Fig. 4.9. To implement the complex logic equation following information is
useful to the designer.
• OR operations are performed by parallel-connected drivers.
• AND operations are performed by series-connected drivers.
• Inversion is provided by the nature of MOS circuit operation.

Fig.4.9. nMOS complex logic gate realizing the Boolean function given above

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Complex CMOS Logic Gates The pMOS pull-up network, on the other hand, must be
the dual network of the nMOS pull down. This means that all parallel connections in
the nMOS pull-down network will correspond to a series connection in the pMOS pull-
up network, and all series connections in the pull-down network correspond to a parallel
connection in the pull-up network. Again consider the Boolean function,

The pull up and pull down graph is shown below in fig.4.10.Here,each driver
transistor nMOS or pMOS is represented as edge and each node is represented as
vertex.

Fig.4.10. A complex CMOS logic gate realizing the Boolean function

i

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Exercise:

Detailed Questions
1. What are the merits of using depletion load nMOS logic? Discuss each in brief.
2. Discuss the significance of DC and transient analysis performed for any logic gate.
3. Discuss CMOS logic implementation briefly using neat sketch of 3 input NAND and
NOR gate.
4. Derive the formula for switching point in case of 4 input NAND and NOR gate using
CMOS logic.
5. Discuss Transmission gates using appropriate example.

Brief Questions

1. Implement following logic functions using complex gates.

2. List performance parameters in case of digital logic gates.
3. Draw the Stik diagram of three input CMOS NOR gate.
4. Draw the layout of three input CMOS NAND gate.
5. Draw the pull up and pull-down graph of CMOS 3 input NOR and NAND gate.

Prepared by Prof (Dr) Shruti Oza-Rahurkar