RF Microelectronics

Laboratory (iCOE)

SAB24103 VLSI DESIGN

Associate Prof. Basir Saibon (UNIKLMSI Kulim Malaysia)

08.01.2017 ASSOC.PROF.BASIR SAIBON

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Chapter 3
MOS Transistors, Wires,
& Parasitic Effects

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Where We Are...

 Last time:
 CMOS Processing
 Today:
 Transistor Modes of Operation
 Pins and Terminals
 More about Wires & Vias
 Parasitic Effects

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 Roadmap for the term:
Major Topics
 VLSI Overview
 CMOS Processing & Fabrication
 Components: Transistors, Wires, & Parasitic Effects
 Fabrication Design Rules & Layout
 Standard-Cell Design with CAD/EDA Tools
 Analog /Mixed Signal Concerns
 Design Project

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Review - Transistor Structure
Substrate
Bulk

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‘N’ Transistor Operation - Cutoff
 Vgs << Vt : Transistor OFF
 Majority carrier in channel (holes)
 No current from source to drain

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‘N’ Transistor Operation -
Subthreshold

 0 < Vgs < Vt : Depletion region

 Electric field repels majority carriers (holes)
 Depletion region forms - no carriers in channel
 No current flows (except for leakage current)
VS =0 0<VGS <VT VDS =0

source drain

depletion region

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‘N’ Transistor Operation - ON
 Vgs > Vt , VDS=0: Transistor ON
 Electric field attracts minority carriers (electrons)
 Inversion region forms in channel
 Depletion region insulates channel from substrate
 Current can now flow from drain to source!

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‘N’ Transistor Operation - Linear
 Vgs > Vt , VDS <VGS -VT : Linear (Active) mode
 Combined electric fields shift channel and
depletion region
 Current flow dependent on VGS, VDS

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‘N’ Transistor Operation –
Fully Saturation
 Vgs > Vt , VDS >VGS -VT : Saturated mode
 Channel “pinched off”
 Current still flows due to electron drift
 Current flow dependent on VGS

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‘P’ Transistor Operation
 Opposite of N-Transistor
 Vgs >> Vt : Transistor OFF
 Majority carrier in channel (electrons)
 No current from source to drain
 0 > Vgs > Vt : Depletion region
 Electric field repels majority carriers (electrons)
 Depletion region forms - no carriers in channel
 No current flows (except for leakage current)
 Vgs < Vt , VDS=0: Transistor ON
 Electric field attracts minority carriers (holes)
 Inversion region forms in channel
 Depletion layer insulates channel from substrate
 Current can now flow from source to drain!

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‘P’ Transistor Modes of Operation
 Vgs <Vt , VDS >VGS -VT : Linear (Active) mode
 Combined electric fields shift channel and
depletion region
 Current flow dependent on VGS, VDS
 Vgs < Vt , VDS <VGS -VT : Saturation mode
 Channel “pinched off”
 Current still flows due to hole drift
 Current flow dependent on VGS

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N-type Transistor Structure
N-type transistor: L
S G D w

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 0.25 micron Transistor (Bell Labs)

Gate Oxide

Silicide

Source/Drain

Poly

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I-V Characteristics of MOS
Transistors

linear saturation

saturation linear

N transistor P transistor

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Ideal Transistor Equations
 Cutoff Region: Vgs < Vt I d  0
 Linear Region Vds < Vgs - Vt

1 W  1 2 2 me
 (EQ 2-1) I d  k' (Vgs  Vt )Vds  Vds k' 
2 L  2  tox

 Saturated Region Vds ≥ Vgs - Vt

1 W
 (EQ 2-2) I d  k' (Vgs  Vt ) 2 - Channel Length Modulation Parm.
2 L
1 W 2
 (EQ 2-16) I d  k' (Vgs  Vt ) (1 Vds )
2 L

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 More about Transistor Equations
mn OR mp
me
 More about k' k' 
tox
 µ - effective surface mobility of carrier
 e - permittivity of gate insulator
 tox - thickness of gate insulator
W
 Beta (b)- a measure of gain bk
L
 Important things to remember:
 these equations are approximations
 Use circuit simulator (Cadence/Synopsys/PSpice)
for more accurate modeling

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Conduction in Semiconductors

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Constants for Silicon

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 εox = Permittivity of SiO2 = 3.9ε0

ε0 = Permittivity of free space = 8.854 x 10-14 F/cm

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0.5 mm Transconductances
From a MOSIS process:
 n-type:
 kn’ = 73 mA/V2
 Vtn = 0.7 V
 p-type:
 kp’ = 21 mA/V2
 Vtp = -0.8 V

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Current Through a Transistor
Use 0.5 mm parameters. Let W/L = 3/2.
Measure at boundary between linear and
saturation regions.
 Vgs = 2V:
Id = 0.5k’(W/L)(Vgs-Vt)2= 93 mA
 Vgs = 5V:
Id = 1 mA

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MOSFET: Typical Fabrication Parameters

VDS(sat) = VGS – VTH = Veff = Overdrive Voltage

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*** Please Read “CMOS Device Modeling” Chapter3 article by Allen/Holberg

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Example

Depletion Region
Width of the Drain

Φ0 = Built in potential of the depletion region

Relative Permittivity of Si =11.8

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MOSFET Gate as Capacitor
 Basic structure of gate is parallel-plate
capacitor:

gate
+

Vg SiO2 tox
-

substrate

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Parallel Plate Capacitance
 Formula for parallel plate capacitance:
Cox = eox / tox
 Permittivity of silicon:
eox = 3.46 x 10-13 F/cm2
 Gate capacitance helps determine charge in
channel which forms inversion region.

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Threshold Voltage
Components of threshold voltage Vt:
 Vfb = flatband voltage; depends on difference
in work function between gate and substrate
and on fixed surface charge.
 s = surface potential (about 2f).

 Voltage on paralell plate capacitor.

 Additional ion implantation.

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 Body Effect
 Reorganize threshold voltage equation:
Vt = Vt0 + Vt
 Threshold voltage is a function of
source/substrate voltage Vsb.
 Body effect  is the coefficient(constant) for
the Vsb dependence factor.

γ= Bulk Threshold voltage (potential) Parameter for N or P type substrate; unit V

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Example: Threshold Voltage
of a Transistor
Vt0 = Vfb + s + Qb/Cox + VII
= -0.91 V + 0.58 V + (1.4E-8/1.73E-7) + 0.92 V
= 0.68 V
Body effect n = sqrt(2qeSiNA/Cox) = 0.1
Vt = n[sqrt(s + Vsb) - sqrt(s)]
= 0.16 V

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Channel Length Modulation
Length Parameter
  describes small dependence of drain
current on Vds in saturation.
 Factor is measured empirically.
 New drain current equation:
 Id = 0.5k’ (W/L)(Vgs - Vt) 2(l-  Vds)
 Equation has a discontinuity between linear
and saturation regions---small enough to be
ignored.

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Gate Voltage and The Channel

gate
current
source drain Vds < Vgs - Vt
Id

gate

current
source drain Vds = Vgs - Vt
Id

gate

source drain
Vds > Vgs - Vt
Id

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Leakage and Subthreshold
Current
 A variety of leakage currents draw current
away from the main logic path.
 The subthreshold current is one particularly
important type of leakage current.

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Types of Leakage Current
 Weak inversion current (a.k.a. subthreshold
current).
 Reverse-biased pn junctions.
 Drain-induced barrier lowering.
 Gate-induced drain leakage;
 Punchthrough currents.
 Gate oxide tunneling.
 Hot carriers.

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Subthreshold Current
 Subthreshold current:
 Isub = ke[(Vgs - Vt)/(S/ln 10)][1-e-qVds/kT]
 Subthreshold slope S characterizes weak
inversion current.
 Subthreshold current is a function of Vt.
 Can adjust Vt by changing the substrate bias to
control leakage.

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The Modern MOSFET
Features of deep submicron MOSFETs:
 epitaxial layer for heavily-doped channel;

 reduced area source/drain contacts for lower

capacitance;
 lightly-doped drains to reduce hot electron
effects;
 silicided poly, diffusion to reduce resistance.

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Circuit Simulation
 Circuit simulators like Cadence Spectre/Spice
numerically solve device models and
Kirchoff’s Laws to determine time-domain
circuit behavior.
 Numerical solution allows more sophisticated
models, non-functional (table-driven) models,
etc.

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Spice MOSFET Models
 Level 1: basic transistor equations of Section
2.2; not very accurate.
 Level 2: more accurate model (effective
channel length, etc.).
 Level 3: empirical model.
 Level 4 (BSIM): efficient empirical model.
 New models: level 28 (BSIM2), level 47
(BSIM3).

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Some (by no means all) Spice
Model Parameters
 L, W: transistor length width.
 KP: transconductance.
 GAMMA: body bias factor.
 AS, AD: source/drain areas.
 CJSW: zero-bias sidewall capacitance.
 CGBO: zero-bias gate/bulk overlap
capacitance.

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Threshold Voltage
 Depends on gate capacitance, physical
constants
 When Vsb=0: Permittivity of SiO2 = 3.9e0
Oxide thickness (cm)
 (EQN 2-4) Cox  e ox / x ox
Adjustment - Ion Implant
Qb
 V
(EQN 2-5) t0  Vfb   s   VII
C ox

 (EQN 2-6) Vfb   gs  (Q f / C ox ) Flatband voltage

kT N a N dp 
 (EQN 2-7)  gs   ln  2  Work function difference
q  n 
i
(EQN 2-9) kT N a
 s  1 f  ln Surface potential
q ni
 (EQN 2-10) Qb  2qe si Na s Charge stored in depletion region

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Threshold Voltage - Body Effect
 Vt increases when Vsb >0
Vt  Vt0  Vt
 (EQN 2-11)

Vt0   n  s  Vsb  s )
γn= Bulk Threshold voltage (potential) Parameter for N type substrate; unit V

 (EQN 2-12)

2qe Si N a
 gs 
C ox

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Subthreshold Current Issue
 Current can flow even when transistor is “OFF”

 (EQ 2-17)

 Vg s Vt 

1  ke 

 S / ln10 
  qVd s / kT
I sub  ke  

S - subthreshold slope (measured in mV/decade)

q - charge of an electron
k - Boltzmann’s constant
T - temperature (Kelvin)

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Wires, Vias, and Pins
 Creating wires (review):
 Deposit insulator on chip (SiO2)

 Deposit conducting material on chip

 Selectively remove using photolithography

 Use multiple layers so wires can cross over each

other
 Vias (Contacts) - Connect between layers
 “cuts” etched through insulator

 Metal connects between layers (with significant

resistance)

Wafer

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Transistor Layout
n-type (tubs may vary in size and location):

S G D w

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Evolution of NMOS
1970s to 2005

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Wires and Vias

metal 3

metal 2

vias
metal 1

poly poly

n+ p-tub n+

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Pins (in Layout) = Terminals (in Schematic)

Inverter Layout

PMOS N-Well
Tab

Pin Labels
Pin Label
N-Well

Pin Contact
Pin Contacts
NMOS

P-Substrate
Tab

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 Metal Migration (1/2)
 Current-carrying capacity of metal wire depends
on cross-section. Height is fixed, so width
determines current limit.

 Metal migration: when current is too high,

electron flow pushes around metal grains. Higher
resistance increases metal migration, leading to
destruction of wire.

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Metal Migration (2/2)
 High current density can cause metal molecules to
move
 Solution: size wires to keep current density with
recommended range (book: 1.5mA / µm width)
 Also a problem in vias

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Metal Migration Problems and
Solutions
 Marginal wires will fail after a small operating
period—infant mortality.
 Normal wires must be sized to accomodate
maximum current flow:
Imax = 1.5 mA/mm of metal width.
 Mainly applies to VDD/VSS lines.

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Wiring Examples – Intel Processes
k=3.6

Tungsten
Plugs

Tungsten
Intel 0.25µm Process (Al) Plugs
5 Layers - Tungsten Vias (Poly/diff. only)
Source: Intel Technical Journal 3Q98
Intel 0.13µm Process (Cu)
Source: Intel Technical Journal 2Q02

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Diffusion Wire Capacitance
 Capacitances formed by p-n junctions:

sidewall
capacitances depletion region

n+ (ND)

bottomwall
substrate (NA) capacitance

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Depletion Region Capacitance
 Zero-bias depletion capacitance:
 Cj0 = esi/xd.
 Depletion region width:
 xd0 = sqrt[(1/NA + 1/ND)2esiVbi/q].
 Junction capacitance is function of voltage
across junction (Vr):
 Cj(Vr) = Cj0/sqrt(1 + Vr/Vbi)

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Poly/Metal Wire Capacitance
 Two components:
 parallel plate;
 fringe.
Fringe

plate

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Metal Coupling Capacitances
 Can couple to adjacent wires on same layer,
wires on above/below layers:

metal 2

metal 1 metal 1

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 Example: Parasitic Capacitance
Measurement
 n-diffusion: bottomwall=2 fF, sidewall=2 fF.
 metal: plate=0.15 fF, fringe=0.72 fF.

1.5 mm

3 mm

0.75 mm 2.5 mm
1 mm

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Parasitic Elements
 So far, we’ve concentrated on getting circuit
elements that we want for analog/digital design
 Transistors
 Wires
 Parasitics - occur whether we want them or not
 Capacitors
 Resistors
 Transistors (bipolar and FET)

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Basic Transistor Parasitics (1/2)
 Gate to substrate, also gate to source/drain.
 Source/drain capacitance, resistance.

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Basic Transistor Parasitics (2/2)
 Gate capacitance Cg. Determined by active
area.
 Source/drain overlap capacitances Cgs, Cgd.
Determined by source/gate and drain/gate
overlaps. Independent of transistor L.
 Cgs = Col W
 Gate/bulk overlap capacitance.

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 Capacitance (1/2)
 Transistors
 Depends on area of transistor gate

 Depends on physical materials, thickness of insulator

 Given for a specific process as Cg

 Diffusion to substrate
 Sidewall capacitance - capacitance from periphery

 bottomwall capacitance - capacitance to substrate

 See Eqns. 2-19 thru 2-22 ; page 68-73

(CMOS VLSI DESIGN Book, Neil Weste & David Harris)

 Given for a specific process as Cdiff,bot, Cdiff,side

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Capacitance (2/2)
 Metal to substrate
 Parallel plate capacitance is dominant

 Need to account for fringing, too

 Poly to substrate
 Parallel plate plus fringing, like metal

 Gotcha: don’t confuse poly over substrate with gate

capacitance
 Sample parasitic values: Table 2-4, p. 85
 Also important: capacitance between conductors
 Metal1-Metal1

 Metal1-Metal2

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Wires
 Chips are mostly made of wires called
interconnect
 In stick diagram, wires set size
 Transistors are little things under the wires
 Many layers of wires
 Wires are as important as transistors
 Speed
 Power
 Noise
 Alternating layers run orthogonally
Slide 66
Wire Geometry
 Pitch = w + s
 Aspect ratio: AR = t/w
 Old processes had AR << 1
 Modern processes have AR  2 w s

 Pack in many skinny wires

l

Slide 67
Layer Stack
 AMI 0.6 mm process has 3 metal layers
 Modern processes use 6-10+ metal layers
Layer T (nm) W (nm) S (nm) AR

 Example: 6 1720 860 860 2.0

Intel 180 nm process 1000

 M1: thin, narrow (< 3) 5 1600

1000
800 800 2.0

 High density cells 4 1080 540 540 2.0

700

 M2-M4: thicker 3 700

700
320 320 2.2

2 700 320 320 2.2

 For longer wires 1

700
480 250 250 1.9
800
 M5-M6: thickest Substrate

 For VDD, GND, clk

Slide 68
Wire Resistance
 r = resistivity (W*m)
w
R
L

Slide 69
Wire Resistance
 r = resistivity (W*m)
r l w
R
t w
L

Slide 70
Wire Resistance
 r = resistivity (W*m)
r l l
R R
t w w
 R = sheet resistance (W/) w w

  is a dimensionless unit(!) w
l

 Count number of squares l l

 R = R * (# of squares)
t t

1 Rectangular Block 4 Rectangular Blocks

R = R (L/W) W R = R (2L/2W) W
= R (L/W) W

Slide 71
 Choice of Metals
 Until 180 nm generation, most wires were
aluminum
 Modern processes often use copper
 Cu atoms diffuse into silicon and damage FETs
 Must be surrounded by a diffusion barrier

Metal Bulk resistivity (mW*cm)

Silver (Ag) 1.6
Copper (Cu) 1.7
Gold (Au) 2.2
Aluminum (Al) 2.8
Tungsten (W) 5.3
Molybdenum (Mo) 5.3
Slide 72
Sheet Resistance
 Typical sheet resistances in 180 nm process
Layer Sheet Resistance (W/)
Diffusion (silicided) 3-10
Diffusion (no silicide) 50-200
Polysilicon (silicided) 3-10
Polysilicon (no silicide) 50-400
Metal1 0.08
Metal2 0.05
Metal3 0.05
Metal4 0.03
Metal5 0.02
Metal6 0.02

Slide 73
Contacts Resistance & Vias
 Contacts and vias also have 2-20 W
 Use many contacts for lower R
 Many small contacts for current crowding around
periphery
Vias
Vias

Slide 74
6: Wires
Resistance
 Depends on resistivity of material r (Rho)
 Sheet resistance Rs = r /t ; see Table 2-4, p. 80
 Resistance R = Rs * L / W
 Corner approximation - count a corner as half a square

Example:
R = Rs(poly) *[ 13 + 2*(1/2) + 3*(1/2) squares]
R = 4Ω/sq * 15.5 squares = 62Ω
Corner (1/2 Square) 1/2 Square

1/2 Square

Corner (1/2 Square) Corner (1/2 Square)

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Wire Resistance
 Resistance of any size square is constant:

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Sheet Resistance

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 80
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Typical Sheet Resistance

0.07~0.08

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Integrated Circuit Resistor

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Laying Out a Resistor

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Mean-Time-to-Failure
 MTF for metal wires = time required for 50%
of wires to fail.
 Depends on current density:
 proportional to j-n e Q/kT
 j is current density
 n is constant between 1 and 3
 Q is diffusion activation energy

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 Skin Effect
Skin effect is the tendency of an alternating electric current (AC) to become distributed
within a conductor such that the current density is largest near the surface of the
conductor, and decreases with greater depths in the conductor

 At low frequencies, most of copper conductor’s

cross section carries current.
 As frequency increases, current moves to skin of
conductor.
 Back EMF induces counter-current in body of
conductor.
 Skin effect most significant effects at gigahertz
frequencies range.
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Skin Effect, cont’d
 Isolated conductor:  Conductor and ground:

Low frequency
Low frequency

High frequency
High frequency
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 Skin Depth
 Skin depth is depth at which conductor’s current is
reduced to 1/3 = 37% of surface value:
 d = 1/sqrt(pfms)
 f = signal frequency
 m = magnetic permeability
 s = wire conductivity

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Effect on Resistance
 Low frequency resistance of wire:
 Rdc = 1/ s wt
 High frequency resistance with skin effect:
 Rhf = 1/2 sd(w + t)
 Resistance per unit length:
 Rac = sqrt(Rdc 2 + kRhf2)
 Typically (Thermal Conductivity), k = 1.2.

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Transistor Gate Parasitics
 Gate-source/drain overlap capacitance:

gate

source drain

overlap

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Transistor Source/Drain Parasitics
 Source/drain have significant capacitance,
resistance.
 Measured same way as for wires.
 Source/drain R, C may be included in Spice
model rather than as separate parasitics.

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Some Example Fabrication
Process Data
 0.5µm process
 AMI 1.5µm process (from www.mosis.org)
 TSMC 0. 5µm process (from www.mosis.org)

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Parasitics - Final Notes
 These are approximate calculations
 Grossly oversimplified
 Advanced CAD tools (e.g. field solver) needed for
accuracy
 Process Variation
 Parameter values are are not exact, but vary
depending on manufacturing, etc.
 Typical process specifies a range for each parameter
 Must design chips to work for worst case - “process
corners”

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Example Problems -
Parasitic Calculation (1/10)
30
metal1

1=0.25µm

poly
ndiff

**Determine;
Rmetal1=? Rpoly=? Rndiff=?
Cmetal1=? Cpoly=? Cndiff=?

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Example Problems -
Parasitic Calculation (2/10)
30
metal1

1=0.25µm

poly
ndiff

Rmetal1 = 30 / 3) * 0.08Ω/ = 0.8Ω plate

Resistance; R = Rs * L / W; Rs = Sheet Resistance in Ω/
Cmetal1 = (30* 0.25µm/)*(3* 0.25µm/)*0.04fF/µm2 +
(30 + 330 + 3)*0.25µm/* 0.09fF/µm
= 0.225fF + 1.485fF
= 1.71fF
fringe

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Example Problems -
Parasitic Calculation (3/10)
30
metal1

1=0.25µm

poly
ndiff

Rndiff = (11 / 3) * 2Ω/ = 7.33Ω

Cndiff = (11* 0.25µm/)*(3* 0.25µm/)*0.6fF/µm2 +

(11 + 311 + 3)*0.25µm/* 0.2fF/µm
= 1.24fF + 1.4fF
= 2.64fF

Note: see Table 2-4, p. 80 for parameters

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 Example Problems -
Parasitic Calculation (4/10)
30
metal1

Corner approx. 1=0.25µm

1/2

poly
ndiff
corner

Rpoly = [ (3 / 2) + 1/2 + (8 / 2) ]* 4Ω/ = 24Ω

Cpoly = ( ((3* 0.25µm/)*(2* 0.25µm/))

 ((10* 0.25µm/)*(2* 0.25µm/)))*0.09fF/µm2 +
(5 + 102 + 8+ 3+ 2)*0.25µm/* 0.04fF/µm
= 0.15fF + 0.3fF
= 0.45fF

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Example Problems -
Parasitic Calculation (5/10)
30
metal1

1=0.25µm

poly
ndiff

**Answer;
Rmetal1=0.8Ω Rndiff=7.33Ω Rpoly=24Ω
Cmetal1= 1.71fF Cndiff= 2.64fF Cpoly= 0.45fF

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Example Problems -
Parasitic Calculation (6/10)
gate
poly

1=0.25µm
A
Overhang

What are the parasitic capacitances visible from point “A”?

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Example Problems -
Parasitic Calculation (7/10)

1=0.25µm
A

What are the parasitic capacitances visible from point “A”?

Cpoly = (6* 0.25µm/)*(2* 0.25µm/)*0.09fF/µm2 +

(6 + 26 + 2)*0.25µm/* 0.04fF/µm
= 0.675fF + 0.16fF
= 0.84fF

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Example Problems -
Parasitic Calculation (8/10)

1=0.25µm
A

What are the parasitic capacitances visible from point “A”?

Cgate = (3* 0.25µm/)*(2* 0.25µm/)*0.9fF/µm2

= 0.34fF

Remember: use C g, not C poly for transistor Gates!

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Example Problems -
Parasitic Calculation (9/10)

1=0.25µm
A

What are the parasitic capacitances visible from point “A”?

Coverhang = (2* 0.25µm/)*(2* 0.25µm/)*0.09fF/µm2 +

(2 + 22 + 2)*0.25µm/* 0.04fF/µm
= 0.0225fF + 0.08fF
= 0.1fF

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Example Problems -
Parasitic Calculation (10/10)

1=0.25µm
A

What are the parasitic capacitances visible from point “A”?

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 109
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 110
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 111
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Example:

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Latch-Up
 CMOS ICs have parastic silicon-controlled
rectifiers (SCRs).
 When powered up, SCRs can turn on,
creating low-resistance path from power to
ground. Current can destroy chip.
 Early CMOS problem. Can be solved with
proper circuit/layout structures.

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Parasitic SCR (Silicon Controlled Rectifier)
Control of current using a small input current. Basically, it is a simple
direct current (DC) switch.

circuit I-V behavior

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Parasitic Transistors
 Parasitic bipolar transistors form at N/P junctions
 Latchup - when parasitic transistors turn on
 Preventing latchup:
 Add substrate contacts (“tub ties”) to reduce Rs, Rw
(more about this later) OR
 Use Silicon-on-Insulator

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 Controlling Latch-Up - Substrate
Contacts
 Purpose: connect well/substrate to power supply
 Alternative term: tub tie (used by book)
 Recommendations (source: Weste & Eshraghian)
 Conservative: 1 substrate contact for every supply
connection
 Less conservative: 1 substrate contact for every 5-10
transistors
 High-current circuits: use guard rings

Substrate Substrate
Contact Contact

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Solution to Latch-Up
Use tub ties to connect tub to power rail. Use
enough to create low-voltage connection.

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Tub Tie Layout (Solution to latch-up)

p+

metal (VDD)

p-tub

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Why We Need Design Rules
 Masks are tooling for manufacturing.
 Manufacturing processes have inherent
limitations in accuracy.
 Design rules specify geometry of masks
which will provide reasonable yields.
 Design rules are determined by experience.

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Design Rules and Yield
 Design rules are determined by
manufacturing process characteristics.
 Design rules should provide adequate yield if
followed.
 Types of design rules:
 Spacing.
 Separation.
 Composition.

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Yield Issues
 Gamma distribution for yield of a single type
of structure:
 Yi = [1/(1+Abi)]ai.
 Total yield for the process is the product of all
yield components:
 Y = P Yi .

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Manufacturing Issues
 Photoresist shrinkage, tearing.
 Variations in material deposition.
 Variations in temperature.
 Variations in oxide thickness.
 Impurities.
 Variations between lots.
 Variations across a wafer.

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Transistor Issues
 Varaiations in threshold voltage:
 oxide thickness;
 ion implanatation;
 poly variations.
 Changes in source/drain diffusion overlap.
 Variations in substrate.

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Wiring Issues
 Diffusion: changes in doping -> variations in
resistance, capacitance.
 Poly, metal: variations in height, width ->
variations in resistance, capacitance.
 Shorts and opens:

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Oxide Issues
 Variations in height.
 Lack of planarity -> step coverage.

metal 2

metal 2 metal 1

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Via Issues
 Via may not be cut all the way through.
 Undersize via creates too much resistance.
 Via may be too large and create shorts,
parasitic capacitance, and sheet resistance.

Metal
Wire
Via Via

Metal Wire

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Scaling Theory
 Chips get better as features shrink in
classical scaling theory:
 Capacitive load goes down faster than current.
 Classical scaling theory runs into
complications at nanometer features.
 Leakage.
 Smaller supply voltage.

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Scaling Model
  /x.
 W  W/x, L  L/x.
 tox tox /x.
 Nd Nd/x.
 VDD  VSS  (VDD  VSS)/x.

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Current and Capacitance Scaling
 Saturation drain current scales as 1/x.
 Capacitance scales as 1/x.
 Total performance over scaling:
 [C’V’/l’]/[CV/l] = 1/x.
 Circuit speeds up by factor x.

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Interconnect Scaling
 Two varieties of interconnect scaling:
 Ideal scaling reduces vertical and horizontal
dimensions equally.
 Constant dimension does not change wiring sizes.
 Higher levels of interconnect are constant
dimension---same as older technologies.

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Interconnect Scaling Trends

Ideal scaling Constant dimension

Line width/spacing S 1
Wire thickness S 1
Interlevel dielectric S 1
Wire length 1/sqrt(S) 1/sqrt(S)
Resistance/unit length 1/S2 1
Capacitance/unit length 1 1
RC delay 1/S3 1/S
Current density 1/S S

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 http://www.itrs2.net/
ITRS roadmap
International Technology Roadmap for Semiconductors

 Semiconductor industry projects fabrication

trends.
 Helps plan future technologies.
 Roadmap describes features, technology
required to get to those goals.

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 ITRS roadmap 2005-2012

2005 2006 2007 2008 2009 2010 2011 2012

CPU 90 75 68 59 52 45 40 36
metal
pitch
CPU 32 28 25 23 20 18 16 14
gate
length
ASIC 45 38 32 28 25 23 20 18
gate
length

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CMOS Scaling from the 80’s

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CMOS Scaling Benefits

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CMOS Scaling Benefits

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CMOS Scaling Benefits

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CMOS Scaling Benefits

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 END
OF
CHAPTER 3.0

*** Please Read “CMOS Device Modeling” Chapter 3 article by Allen/Holberg

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