dce

2023
dce
2023

Digital Systems – Instructor: Assoc. Prof. Dr. Tran Ngoc Thinh

• Email: [email protected]
• Phone: 38647256 (5837)
BK
Tran Ngoc Thinh BK
• Office: A3 building
TP.HCM
HCMC University of Technology
TP.HCM
• Office hours: Tuesdays, 08:00-11:30
https://e-learning.hcmut.edu.vn/course/view.php?id=110469

dce dce
2023
Administrative Issues 2023
Administrative Issues (cont.)
• Class
– Time and venue:
• Grades
Wed CC02: 13:00 - 14:50, 406B4, CC01: 16:00 - 17:50, 406B4
– 30% Lab
Thu CN01: 07:00 - 08:50, 311B1, CC04: 09:00 - 10:50, 406B4

– Textbook:
– 20% midterm
• [1] Digital Systems - Digital Systems: Principles and
Applications- Ronald J. Tocci, Neal S. Widmer, Gregory L. – 50% final exam
Moss
– 12th Edition”, Prentice-Hall 2011
– 10th Edition, Prentice-Hall 2007
• [2] “Fundamentals of Digital Logic with Verilog Design– 3rd
edition” – Stephen Brown, Zvonko Vranesic, McGraw Hill 2013
• [3] “Digital Design -3rd Edition” –John F. Wakerly, Prentice-Hall
2001
• [4] “Digital Logic Design Principles” – N. Balabanian, B.
Carlson, John Wiley & Sons, Inc , 2004
3 4

1
dce dce
2023
What is This Course All About? 2023
Overview of the course
• What is covered? Number presentation and codes (week 1)
– This course provides fundamentals of logic Boolean algebra and logic gates (weeks
design, such as: number presentation and
codes, Boolean algebra and logic gates,
2,3,4)
analysis and design of combinational and Combinational circuits
sequential circuits. Arithmetic Circuits (week 8)
• Learning outcomes MSI Logic Circuits (weeks 11,12)
– Knowledge: Number presentation and codes,
Boolean algebra and logic gates. Sequential circuits
– Skill: Design and Analyze combinational Flip-Flops and Related Devices (weeks 5,6)
circuits and sequential circuits. Counters and Registers (weeks 9,10)

5 6

dce dce
2023
Course Outline – Part I 2023
Course Outline – Part II
• Number system and codes • Combinational Logic Circuits
– Decimal, Binary, Octal, Hexadecimal Number Systems – Sum-of-Product Form
– Conversions – Simplifying Logic Circuits
– Codes: Gray, Alphanumeric Codes – Algebraic Simplification
– Parity Method for Error Detection
– Designing Combinational Logic Circuits
• Logic gates and Boolean Algebra – Karnaugh Map Method
– Boolean Constants and Variables
– Parity Generator and Checker
– Truth Tables
– Enable/Disable Circuits
– Basic gates: OR AND NOT Operation with OR Gates
– NOR Gates and NAND Gates
– Basic Characteristics of Digital ICs
– Boolean Theorems – Troubleshooting Digital Systems
– DeMorgan’s, DeMorgan’s Theorems

7 8

2
dce dce
2023
Course Outline – Part III 2023
Course Outline – Part IV
• Flip-Flops and Related Devices • Operation and Circuits
– Latches, D Latch – Representing Signed Numbers
– Addition, Subtraction in the 2’s-Complement System
– Clock Signals and Clocked Flip-Flops
– Multiplication, Division of Binary Numbers
– S-C, J-K, D Master/Slave Flip-Flops – BCD Addition
– Flip-Flop Application – Hexadecimal Arithmetic
• Detecting an Input Sequence – Arithmetic Circuits
• Data Storage and Transfer • Parallel Binary Adder
• Serial Data Transfer: Shift Registers • Design of a Full Adder
• Frequency Division and Counting • Carry Propagation
• Microcomputer Application • Integrated Circuit Parallel Adder
– Schmitt-Trigger, On-shot Devices – 2’s Complement System
– Analyzing Sequential & Clock Generator Circuits – BCD Adder
– ALU Integrated Circuits

9 10

dce dce
2023
Course Outline – Part V 2023
Course Outline – Part VI
• Counters and Registers
– Asynchronous & Synchronous Counters
• MSI Logic Circuits
– Decoders
– Up/Down Counters
– Encoders
– Cascading BCD Counters
– Multiplexers
– Synchronous Counter Design – Demultiplexers
– Shift-Register Counters
– Counter Application: Frequency Counter, Digital Clock
– Integrated-Circuit Registers
– Some ICs:
• Parallel In/Parallel Out – The 74ALS174/HC174
• Serial In/Serial Out – The 4731B
• Parallel In/Serial Out – The 74ALS185/HC165
• Serial In/Parallel Out – The 74ALS164/HC164

11 12

3
dce dce
2023
Introduction to Chapter 1 2023
Numerical Representations
• Digital technology is widely used. Examples: • Analog Representation
– Computers
– A continuously variable, proportional indicator.
– Manufacturing systems
– Medical Science
– Examples of analog representation:
• Sound through a microphone causes voltage
– Transportation
changes.
– Entertainment
• Mercury thermometer varies over a range of
– Telecommunications values with temperature.
• Basic digital concepts and terminology are
• Digital Representation
introduced
• https://study.com/articles/What_is_Digital_Logic.html
– Varies in discrete (separate) steps.
– Examples of digital representation:
• Passing time is shown as a change in the display
on a digital clock at one minute intervals.
13 14

dce dce
2023
Digital and Analog Systems 2023
Digital and Analog Systems
• Digital system • Advantages of digital
– A combination of devices that manipulate – Ease of design
values represented in digital form. – Well suited for storing information.
• Analog system – Accuracy and precision are easier to maintain
– A combination of devices that manipulate – Programmable operation
values represented in analog form – Less affected by noise
– Ease of fabrication on IC chips
45 45
42 41
40 40
37
35 35 34 35

30
C

30 29
temperature 0C

0
temperature

25 25 25 25
23 22
20 20
18
15 15

10 10
7
5 5 4
1 2
0 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
time samples

15 16

4
dce dce
2023
Digital and Analog Systems 2023
Digital and Analog Systems
• There are limits to digital techniques: • Analog-to-digital conversion (ADC) and
– The world is analog digital-to-analog conversion (DAC)
– The analog nature of the world requires a
complicate circuitry.
time consuming conversion process:
1. Convert the physical variable to an electrical
signal (analog).
2. Convert the analog signal to digital form.
3. Process (operate on) the digital information
4. Convert the digital output back to real-world
analog form.

17 18

dce dce
2023
Digital and Analog Systems 2023
Digital Number Systems
• The audio CD is a typical hybrid (combination) • Number systems differ in the number of symbols
system. they use
– Analog sound is converted into analog voltage. – Decimal – 10 symbols (base 10)
– Analog voltage is changed into digital through an
– Hexadecimal – 16 symbols (base 16)
ADC in the recorder.
– Digital information is stored on the CD . – Octal – 8 symbols (base 8)
– At playback the digital information is changed into – Binary – 2 symbols (base 2)
analog by a DAC in the CD player. • Generalized form of number system base b
– The analog voltage is amplified and used to drive a
speaker that produces the original analog sound.

19 20

5
dce dce
2023
1-3 Digital Number Systems 2023
Digital Number Systems
• Example • The Decimal (base 10) System
– 10 symbols: 0, 1, 2, 3, 4, 5, 6 , 7, 8, 9
– Each number is a digit (from Latin for finger)
– Most significant digit (MSD) and least significant digit (LSD)
– Positional value may be stated as a digit multiplied by a power of
10

24.6(8) = 2 x 81 + 4 x 80 + 6 x 8-1 = 20.75(10)

21 22

dce dce
2023

Digital Number Systems

2023
Digital Number Systems
• The Binary (base 2) System
– 2 symbols: 0,1
• Decimal Counting – Lends itself to electronic circuit design since only two
different voltage levels are required.
– Other number systems are used to represent binary
quantities.
– Positional value may be stated as a digit multiplied by
a power of 2.

23 24

6
dce dce
2023
Digital Number Systems 2023

Representing Binary Quantities

• Binary Counting • Open and closed switches
• Paper Tape

25 26

dce dce
2023
Representing Binary Quantities 2023
Representing Binary Quantities
• Other two state devices: • Exact voltage level is not important in digital
– Light bulb (off or on) systems.
– Diode (conducting or not conducting) • A voltage of 3.6 V will mean the same (binary 1)
as a voltage of 4.3 V.
– Relay (energized or not energized)
– Transistor (cutoff or saturation)
– Photocell (illuminated or dark)

27 28

7
dce dce
2023
Representing Binary Quantities 2023
Digital Circuits/Logic Circuits
• Digital Signals and Timing Diagrams • Digital circuits - produce and respond to
– Timing diagrams show voltage versus time. predefined voltage ranges.
– Horizontal scale represents regular intervals of time
beginning at time zero. • Logic circuits – used interchangeably with
– Timing diagrams are used to show how digital signals the term, digital circuits.
change with time. • Digital integrated circuits (ICs) – provide
– Timing diagrams are used to compare two or more
digital signals.
logic operations in a small reliable
– The oscilloscope and logic analyzer are used to package.
produce timing diagrams.

29 30

dce dce
2023
Parallel and Serial Transmission 2023
Parallel and Serial Transmission
• Parallel transmission – all bits in a binary • Parallel transmission is faster but requires
number are transmitted simultaneously. A more paths.
separate line is required for each bit. • Serial is slower but requires a single path.
• Serial transmission – each bit in a binary • Both methods have useful applications
number is transmitted per some time which will be seen in later chapters.
interval.

31 32

8
dce dce
2023
Memory 2023
Digital Computers
• A circuit which retains a response to a • Computer – a system of hardware that
momentary input is displaying memory. performs arithmetic operations,
• Memory is important because it provides a way manipulates data (usually in binary form),
to store binary numbers temporarily or and makes decisions.
permanently.
• Computers perform operations based on
• Memory elements include:
– Magnetic
instructions in the form of a program at
– Optical high speed and with a high degree of
– Electronic latching circuits accuracy.

33 34

dce dce
2023
Block diagram of digital computer 2023
Digital Computers
Von Neumann-architecture computers • Major parts of a computer
– Input unit – processes instructions and data into the
memory.
– Memory unit – stores data and instructions.
– Control unit – interprets instructions and sends appropriate
signals to other units as instructed.
– Arithmetic/logic unit – arithmetic calculations and logical
decisions are performed.
– Output unit – presents information from the memory to the
operator or process.
– The control and arithmetic/logic units are often treated as
one and called the central processing unit (CPU)

35 36

9
dce dce
2023
Digital Computers 2023
Conversion
• The hexadecimal number system is introduced.
• Types of computers
• Since different number systems may be used in a
– Microcomputer
system, it is important for a technician to understand how
• Most common (desktop PCs, notebook computers)
• Has become very powerful
to convert between them.
– Minicomputer (workstation) • Binary codes that are used to represent different
– Mainframe information are also described.
– Microcontroller
• Designed for a specific application
• Dedicated or embedded controllers
• Used in appliances, manufacturing processes, auto ignition
systems, ABS systems, and many other applications.

37 38

dce dce
2023
Binary to Decimal Conversion 2023
Decimal to Binary Conversion
• Convert binary to decimal by summing the • Two methods to convert decimal to
positions that contain a 1. binary:
– Reverse process described above
– Use repeated division
1 0 0 1 0 12
25  2 4  23  2 2  21  20 
32  0  0  4  0  1  37 10

1011.1012 = ?

39 40

10
dce dce
2023
Decimal to Binary Conversion 2023
Decimal to Binary Conversion
• Repeated division steps:
• Reverse process described above – Divide the decimal number by 2
– Note that all positions must be accounted for – Write the remainder after each division until a quotient
of zero is obtained.
– The first remainder is the LSB and the last is the MSB

3710  25  0  0  2 2  0  20
1 0 0 1 0 12

41 42

dce dce
2023
Decimal to Binary Conversion 2023
Hexadecimal Number System
• Repeated division – • Most digital systems deal with groups of bits in
This flowchart even powers of 2 such as 8, 16, 32, and 64 bits.
describes the • Hexadecimal uses groups of 4 bits.
process and can be • Base 16
used to convert from
– 16 possible symbols
decimal to any other
– 0-9 and A-F
number system.
• Allows for convenient handling of long binary
strings.

43 44

11
dce dce
2023
Hexadecimal Number System 2023
Hexadecimal Number System
• Convert from hex to decimal by multiplying • Convert from decimal to hex by using the
each hex digit by its positional weight. repeated division method used for decimal to
binary and decimal to octal conversion.
Example: 16316 • Divide the decimal number by 16
• The first remainder is the LSB and the last is
16316  1 (16 2 )  6  (161 )  3  (160 ) the MSB.
– Note, when done on a calculator a decimal
 1 256  6 16  3 1 remainder can be multiplied by 16 to get the result.
If the remainder is greater than 9, the letters A
 35510 through F are used.

45 46

dce dce
2023
Hexadecimal Number System 2023
Binary to Hex Conversion
• Example of hex to binary conversion: • Convert from binary to hex by grouping bits in four
starting with the LSB.
• Each group is then converted to the hex equivalent
9F216 = 9 F 2 • Leading zeros can be added to the left of the MSB to fill
1001 1111 0010 = out the last group.
• Example:
(Note the addition of leading zeroes)
1001111100102
11101001102 = 0011 1010 0110
= 3 A 6
= 3A616

47 48

12
dce dce
2023
Hexadecimal Number System 2023
Number Systems Conversion
• Hexadecimal is useful for representing
long strings of bits.
• Understanding the conversion process
and memorizing the 4 bit patterns for each
hexadecimal digit will prove valuable later.

49 50

dce dce
2023
BCD 2023
BCD
• Binary Coded Decimal (BCD) is another way to
present decimal numbers in binary form. • To convert the number 87410 to BCD:
• BCD is widely used and combines features of
both decimal and binary systems. 8 7 4
• Each digit is converted to a binary equivalent. 1000 0111 0100 = 100001110100BCD

• Each decimal digit is represented using 4 bits.

• Each 4-bit group can never be greater than 9.
• Reverse the process to convert BCD to
decimal.

51 52

13
dce dce
2023
BCD 2023
Gray Code
• BCD is not a number system. • The gray code is used in applications where
• BCD is a decimal number with each digit numbers change rapidly.
encoded to its binary equivalent. • In the gray code, only one bit changes from each
• A BCD number is not the same as a value to the next.
straight binary number. Binary Gray Code
000 000
• The primary advantage of BCD is the 001 001
relative ease of converting to and from 010 011
decimal. 011 010
100 110
101 111
110 101
111 100
53 54

dce dce
2023
Gray Code 2023
Putting It All Together
Decimal Binary Hexadecimal BCD Gray
0 0 0 0 0
1 1 1 0001 0001
2 10 2 0010 0011
3 11 3 0011 0010
4 100 4 0100 0110
5 101 5 0101 0111
6 110 6 0110 0101
7 111 7 0111 0100
8 1000 8 1000 1100
9 1001 9 1001 1101
10 1010 A 0001 0000 1111
11 1011 B 0001 0001 1110
12 1100 C 0001 0010 1010
13 1101 D 0001 0011 1011
14 1110 E 0001 0100 1001
15 1111 F 0001 0101 1000

55 56

14
dce dce
2023
The Byte, Nibble, and Word 2023
Alphanumeric Codes
• 1 byte = 8 bits • Represents characters and functions found on a
computer keyboard.
• 1 nibble = 4 bits
• ASCII – American Standard Code for
• 1 word = size depends on data pathway Information Interchange.
size. – Seven-bit code: 27 = 128 possible code groups
– Word size in a simple system may be one – Examples of use are: to transfer information between
byte (8 bits) computers, between computers and printers, and for
internal storage.
– Word size in a PC is eight bytes (64 bits)

57 58

dce dce
2023
Parity Method for Error Detection 2023
Parity Method for Error Detection
• Binary data and codes are frequently moved • The parity method of error detection
between locations. For example:
requires the addition of an extra bit to a
– Digitized voice over a microwave link.
– Storage and retrieval of data from magnetic and code group.
optical disks. • This extra bit is called the parity bit.
– Communication between computer systems over
telephone lines using a modem. • The bit can be either a 0 or 1, depending
• Electrical noise can cause errors during on the number of 1s in the code group.
transmission.
• There are two methods, even and odd.
• Many digital systems employ methods for error
detection (and sometimes correction).

59 60

15
dce dce
2023
Parity Method for Error Detection 2023
Parity Method for Error Detection

• Even parity method – the total number of • Odd parity method – the total number of
bits in a group including the parity bit must bits in a group including the parity bit must
add up to an even number. add up to an odd number.
– The binary group 1 0 1 1 would require the – The binary group 1 1 1 1 would require the
addition of a parity bit 1 1 0 1 1 addition of a parity bit 1 1 1 1 1

61 62

dce dce
2023
Parity Method for Error Detection 2023
Odd Parity Error Detection

• The transmitter and receiver must “agree” • Original data 10011010

on the type of parity checking used. • With Odd Parity 110011010
• Two bit errors would not indicate a parity • 1-bit error 110111010
error. • Number of 1s even indicates 1-bit error
• Both odd and even parity methods are • 2-bit error 110110010
used, but even seems to be used more • Number of 1s odd no error indicated
often. • 3-bit error 100110010
• Number of 1s even indicates error

63 64

16
dce dce
2019 2019
Boolean Constants and Variables
• Boolean algebra is an important tool in
describing, analyzing, designing, and
implementing digital circuits.
• Boolean algebra allows only two values; 0
and 1.
• Logic 0 can be: false, off, low, no, open
switch.
BK
TP.HCM
Digital Systems • Logic 1 can be: true, on, high, yes, closed
Tran Ngoc Thinh switch.
HCMC University of Technology • Three basic logic operations: OR, AND,
http://www.cse.hcmut.edu.vn/~tnthinh and NOT.
2

dce dce
2019
Truth Tables 2019
Truth Tables
• A truth table describes the relationship • Examples of truth tables with 2, 3, and 4 inputs.
between the input and output of a logic
circuit.
• The number of entries corresponds to the
number of inputs. For example a 2-input
table would have 22 = 4 entries. A 3-input
table would have 23 = 8 entries.

https://www.youtube.com/watch?v=Xi18hI1LqAA

3 4

1
dce dce
2019
OR Operation With OR Gates 2019
OR Operation With OR Gates
• The Boolean expression for the OR operation is • The OR operation is similar to addition but
X=A+B
when A = 1 and B = 1, the OR operation
– This is read as “x equals A or B.” produces 1 + 1 = 1.
– X = 1 when A = 1 or B = 1. • In the Boolean expression
• Truth table, circuit symbol and timing diagram for a x=1+1+1+1=1
two input OR gate: We could say that x is true (1) when A is true (1)
OR B is true (1) OR C is true (1) OR D is true (1).
• In general, the output of an OR gate is HIGH
whenever one or more inputs are HIGH

A A
B
B
C
x D
x
5 6

dce dce
2019
OR Operation With OR Gates 2019
AND Operations with AND gates
• There are many examples of • The Boolean expression for the AND operation is
X=A•B
applications where an output function is – This is read as “x equals A and B.”
desired when one of multiple inputs is – x = 1 when A = 1 and B = 1.

activated. • Truth table and circuit symbol for a two input AND gate are
shown. Notice the difference between OR and AND gates.

7 8

2
dce dce
2019
AND Operation With AND Gates 2019
NOT Operation
• The AND operation is similar to multiplication. • The Boolean expression for the NOT operation is
• In the Boolean expression XA X  A'
X=A•B•C • This is read as:
X = 1 only when A = 1, B = 1, and C = 1. – x equals NOT A, or
• The output of an AND gate is HIGH only when all inputs – x equals the inverse of A, or
are HIGH. – x equals the complement of A
• Truth table, symbol, and sample waveform for the NOT
circuit.

9 10

dce dce
2019
Describing Logic Circuits Algebraically 2019

Describing Logic Circuits Algebraically

• The three basic Boolean operations (OR, • The output of an inverter is equivalent to
AND, NOT) can describe any logic circuit. the input with a bar over it. Input A through
an inverter equals A’.
• Examples of Boolean expressions for logic
• Examples using inverters.
circuits:

11 12

3
dce dce
2019

More Examples
2019
Evaluating Logic Circuit Outputs
• Rules for evaluating a Boolean expression:
– Perform all inversions of single terms.
– Perform all operations within parenthesis.
– Perform AND operation before an OR
operation unless parenthesis indicate
otherwise.
– If an expression has a bar over it, perform the
operations inside the expression and then
invert the result.

13 14

dce dce
2019
Evaluating Logic Circuit Outputs 2019
Evaluating Logic Circuit Outputs

• Evaluate Boolean expressions by • Output logic levels can be determined

substituting values and performing the directly from a circuit diagram.
indicated operations: • Technicians frequently use this method.
A  0, B  1, C  1, and D  1 • The output of each gate is noted until a
x  ABC(A  D) final output is found.
 0 11 (0  1)
 1 1 1  (0  1)
 1 1 1  (1)
 1 1 1  0
0
15 16

4
dce dce
2019
Implementing Circuits From Boolean Expressions 2019
Example
• It is important to be able to draw a • Draw the circuit diagram to implement the expression
logic circuit from a Boolean
expression. x  ( A  B)( B  C )
• The expression
x  A  BC
could be drawn as a three input
AND gate.
• A more complex example such as

y  AC  BC  ABC
could be drawn as two 2-input
AND gates and one 3-input AND
gate feeding into a 3-input OR
gate. Two of the AND gates have
inverted inputs.
17 18

dce dce
2019
NOR Gates and NAND Gates 2019
NOR Gates and NAND Gates
• Combine basic AND, OR, and NOT operations. • The NAND gate is an inverted AND gate. An
• The NOR gate is an inverted OR gate. An inversion inversion “bubble” is placed at the output of
“bubble” is placed at the output of the OR gate. the AND gate.
• The Boolean expression is
x AB • The Boolean expression is x  AB

A A

B B

x x

19 20

5
dce dce
2019
Laws of Boolean Algebra 2019
Commutative Laws of Boolean Algebra
• Commutative Laws A+B=B+A
• Associative Laws
• Distributive Laws

A•B= B•A

21 22

dce dce
2019
Associative Laws of Boolean Algebra 2019
Distributive Laws of Boolean Algebra
A + (B + C) = (A + B) + C A • (B + C) = A • B + A • C
A (B + C) = A B + A C

A • (B • C) = (A • B) • C A • (B • C) = (A • B) • C

23 24

6
dce dce
2019
Rules of Boolean Algebra 2019
Rules of Boolean Algebra
A • (B + C) = A • B + A • C A • (B + C) = A • B + A • C
A (B + C) = A B + A C A (B + C) = A B + A C

25 26

dce dce
2019
Rules of Boolean Algebra 2019
Rules of Boolean Algebra
A • (B + C) = A • B + A • C
A (B + C) = A B + A C

• Rule 10: A + AB = A

27 28

7
dce dce
2019
Rules of Boolean Algebra 2019
Examples
• Rule 11: A + A’B = A +B
• Simplify the expression
y  A BD  A B D
y  AB
z  (A  B)( A  B )
• Rule 12: (A + B)(A + C) = A + BC
zB
x  ACD  A BCD
x  ACD  BCD
y  AC  ABC

29
y  AC 30

dce dce
2019
DeMorgan’s Theorems 2019

DeMorgan’s Theorems
• Theorem 1: When the OR sum of two • A NOR gate is equivalent to an AND gate
variables is inverted, it is equivalent to with inverted inputs.
inverting each variable individually and • A NAND gate is equivalent to an OR gate
ANDing them. with inverted inputs.
A  B  A. B
For N variables, DeMorgan’s theorem is expressed as:

• Theorem 2: When the AND product of two and

variables is inverted, it is equivalent to
inverting each variable individually and
ORing them.
A.B  A  B
31 32

8
dce dce
2019
Implications of DeMorgan’s Theorems 2019
Implications of DeMorgan’s Theorems
• Determine the output expression for the below
circuit and simplify it using DeMorgan’s Theorem

• Use DeMorgan’s theorems to convert below expression

to an expression containing only single-variable
inversions
y  A  B  CD
y  A B (C  D )
33 34

dce dce
2019
Example of DeMorgan’s Theorems 2019
Examples
• Simplify the expressions
F  XY  P.Q
– z = (A’ + B)(A+B)
F  X Y  P Q
• De Morgan’s
• Simplify the expression
– z = ((a’+c) . (b+d’))’
z  (A  C )(B  D )
• to one having only single variables
inverted.
z  AC  B D

35 36

9
dce dce
2019
Examples 2019
Universality of NAND and NOR Gates
• NAND or NOR gates can be used to
• Simplify the expressions create the three basic logic expressions
(OR, AND, and INVERT)
– z = (A’ + B)(A+B)
= A’A + A’B + AB + BB = 0 + (A’+A)B + B = B

• De Morgan’s
– z = ((a’+c) . (b+d’))’
= (a’+c)’ + (b+d’)’ = ac’ + b’d

37 38

dce dce
2019
Universality of NAND and NOR Gates 2019
Alternate Logic-Gate Representations

• To convert a standard symbol to an

alternate:
– Invert each input and output (add an inversion
bubble where there are none on the standard
symbol, and remove bubbles where they exist
on the standard symbol.
– Change a standard OR gate to and AND gate,
or an AND gate to an OR gate.

39 40

10
dce dce
2019
Alternate Logic-Gate Representations 2019
Alternate Logic-Gate Representations
• Standard and alternate symbols for various logic
gates and inverter • The equivalence can be applied to gates
with any number of inputs.
• No standard symbols have bubbles on
their inputs. All of the alternate symbols
do.
• The standard and alternate symbols
represent the same physical circuitry.

41 42

dce dce
2019
Alternate Logic-Gate Representations 2019
Alternate Logic-Gate Representations
• Interpretation of the two NAND gate
• Active high – an input or output has no
symbols.
inversion bubble.
• Active low – an input or output has an
inversion bubble.
• An AND gate will produce an active output
when all inputs are in their active states.
• An OR gate will produce an active output
when any input is in an active state.

43 44

11
dce dce
2019
Alternate Logic-Gate Representations 2019
Which Gate Representation to Use
• Interpretation of the two OR gate symbols.
• Using alternate and standard logic gate
symbols together can make circuit
operation clearer.
• When possible choose gate symbols so
that bubble outputs are connected to
bubble input and nonbubble outputs are
connected to nonbubble inputs.

45 46

dce dce
2019
Which Gate Representation to Use 2019

• When a logic signal is in the active state

(a) Original circuit
(high or low) it is said to be asserted. using standard NAND
• When a logic signal is in the inactive state symbols; (b)
(high or low) it is said to be unasserted. equivalent
representation where
• A bar over a signal means asserted (active) output Z is active-
low. HIGH; (c) equivalent
• The absence of a bar over a signal means representation where
output Z is active-
asserted (active) high. LOW; (d) truth table.

47 48

12
dce dce
2019
Example 2019
Methods of describing logic circuits

(a) Boolean
expression;
(b) schematic
diagram;
(c) truth table;
(d) timing
diagram.

Alarm is activated when Z goes high. Modify the circuit so that it represents
the circuit operation more effectively.

49 50

dce dce
2019
Summary of Methods to Describe Logic Circuits 2019
Summary
• Boolean Algebra: a mathematical tool used in the analysis
• The three basic logic functions are AND, and design of digital circuits
OR, and NOT. • OR, AND, NOT: basic Boolean operations
• Logic functions allow us to represent a • OR: HIGH output when any input is HIGH
decision process. • AND: HIGH output only when all inputs are HIGH
• NOT: output is the opposite logic level as the input
– If it is raining OR it looks like rain I will take an
• NOR: OR with its output connected to an INVERTER
umbrella.
• NAND: AND with its output connected to an INVERTER
– If I get paid AND I go to the bank I will have
• Boolean theorems and rules: to simplify the expression of
money to spend. a logic circuit and can lead to a simpler way of
implementing the circuit
• NAND, NOR: can be used to implement any of the basic
Boolean operations
51 52

13
dce dce
2019 2019

Introduction
• Basic logic gate functions will be combined in
combinational logic circuits.
• Simplification of logic circuits will be done using
Boolean algebra and a mapping technique.

BK
TP.HCM
Chapter 3:
Combinational Circuits

dce dce
2019
Sum-of-Products & Product-of-sums Forms
2019

Simplifying Logic Circuits

• A Sum-of-products (SOP) expression will • The circuits below both provide the same output,
appear as two or more AND terms ORed but the lower one is clearly less complex.
together.
ABC  ABC
AB  ABC  C D  D
• A Product-of-sums(POS) expression is
sometimes used in logic design.
• We will study simplifying logic circuits using
Boolean algebra and Karnaugh mapping
( A  B  C )( A  B  C )
3 4

Digital Systems, Chapter 3 1

dce dce
2019

Algebraic Simplification 2019

Designing Combinational Logic Circuits

• Place the expression in SOP form by • To solve any logic design problem:
applying DeMorgan’s theorems and
– Interpret the problem and set up its truth table.
multiplying terms.
• Check the SOP form for common factors – Write the AND (product) term for each case
and perform factoring where possible. where the output equals 1.

• Note that this process may involve some – Combine the terms in SOP form.
trial and error to obtain the simplest result. – Simplify the output expression if possible.

– Implement the circuit for the final, simplified

expression.

5 6

dce dce
2019
Example of Logic Design 2019

Karnaugh Map Method

• Design a logic circuit that has three inputs, A B C X
A, B, and C, whose output will be HIGH only 0 0 0 0 • A graphical method of simplifying logic
when a majority of the inputs are HIGH. 0 0 1 0 equations or truth tables. Also called a K
0 1 0 0
X = A’BC + AB’C + ABC’ + ABC map.
0 1 1 1
X = A’BC + ABC + AB’C + ABC + ABC’ + ABC 1 0 0 0 • Theoretically can be used for any number
1 0 1 1 of input variables, but practically limited to
X = BC (A’+ A) + AC(B’+ B) + AB(C’ + C) 1 1 0 1
5 or 6 variables.
X = BC + AC + AB 1 1 1 1

7 8

Digital Systems, Chapter 3 2

dce dce
2019

Karnaugh Map Method 2019

Karnaugh Map Method

• The truth table values are placed in the • Looping adjacent groups of 2, 4, or 8 1s
K map. will result in further simplification.
• Adjacent K map square differ in only • When the largest possible groups have
one variable both horizontally and been looped, only the common terms are
vertically. placed in the final expression.
• The pattern from top to bottom and left • Looping may also be wrapped between
to right must be in the form AB, AB, AB, AB top, bottom, and sides.
• A SOP expression can be obtained by
ORing all squares that contain a 1.

9 10

dce dce
2019

Karnaugh Map for 2, 3 variables 2019

Karnaugh Map for 4 variables

• Looping adjacent groups of 2, 4, or 8 1s will result in • Looping adjacent groups of 2, 4, or 8 1s will result in
further simplification. further simplification.

11 12

Digital Systems, Chapter 3 3

dce dce
2019

Minimization Technique 2019

Example of pairs of adjacent of 1s

• Minimization is done by spotting patterns of 1's and 0's
• Simple theorems are then used to simplify the Boolean
description of the patterns
• Pairs of adjacent 1's
– remember that adjacent squares differ by only one variable
– hence the combination of 2 adjacent squares has the form

– P ( A + A’ )
– this can be simplified (from before) to just P

13 14

dce
2019
dce
2019

Example of grouping of fours 1s (quads) Example of grouping of eight 1s (octals)

15 16

Digital Systems, Chapter 3 4

dce dce
2019

Complete Simplification Process 2019

Example
• Complete K map simplification process:
– Construct the K map, place 1s as indicated in the
truth table.
– Loop 1s that are not adjacent to any other 1s.
– Loop 1s that are in pairs
– Loop 1s in octets even if they have already been
looped.
– Loop quads that have one or more 1s not already
looped.
– Loop any pairs necessary to include 1st not
already looped.
– Form the OR sum of terms generated by each
loop.

17 18

dce dce
2019
Example 2019
Don’t Care Conditions
• In certain cases some of the minterms may never occur
or it may not matter what happens if they do
– In such cases we fill in the Karnaugh map with X
• meaning don't care
– When minimizing an X is like a "joker"
• X can be 0 or 1 - whatever helps best with the minimization

• “Don’t care” conditions should be changed to either 0 or

1 to produce K-map looping that yields the simplest
expression.

19 20

Digital Systems, Chapter 3 5

dce dce
2019
Terminology: Minterms 2019
Terminology: Sum of minterms form
• A minterm is a special product of literals, in which each input • Every function can be written as a sum of minterms, which is a
variable appears exactly once. special kind of sum of products form
• A function with n variables has 2n minterms (since each variable can • The sum of minterms form for any function is unique
appear complemented or not)
• If you have a truth table for a function, you can write a sum of
• A three-variable function, such as f(x,y,z), has 23 = 8 minterms: minterms expression just by picking out the rows of the table where
x’y’z’ x’y’z x’yz’ x’yz the function output is 1.
xy’z’ xy’z xyz’ xyz
f = x’y’z’ + x’y’z + x’yz’ + x’yz + xyz’
• Each minterm is true for exactly one combination of inputs: x y z f(x,y,z) f’(x,y,z) = m0 + m1 + m2 + m3 + m6
0 0 0 1 0 = m(0,1,2,3,6)
Minterm Is true when… Shorthand 0 0 1 1 0
x’y’z’ x=0, y=0, z=0 m0 0 1 0 1 0 f’ = xy’z’ + xy’z + xyz
x’y’z x=0, y=0, z=1 m1 0 1 1 1 0 = m4 + m5 + m7
x’yz’ x=0, y=1, z=0 m2
1 0 0 0 1 = m(4,5,7)
x’yz x=0, y=1, z=1 m3
1 0 1 0 1
xy’z’ x=1, y=0, z=0 m4 f’ contains all the minterms not in f
1 1 0 1 0
xy’z x=1, y=0, z=1 m5
1 1 1 0 1
xyz’ x=1, y=1, z=0 m6
xyz x=1, y=1, z=1 m7
21 22

dce dce
2019
Minterms and Maxterms & Binary representations 2019
SOP-POS Conversion
A B C Min- Max- • Minterm values present in SOP expression not
terms terms present in corresponding POS expression
0 0 0 A.B.C A B C • Maxterm values present in POS expression not
0 0 1 A.B.C A B C present in corresponding SOP expression
0 1 0 A.B.C A B C • Relationship between minterm mi and maxterm
0 1 1 A.B.C A B C Mi:
1 0 0 A.B.C A B C – For f(A,B,C), (m1)' = (A'B'C)' = A + B + C' = M1
1 0 1 A.B.C A  B  C – In general, (mi)' = Mi
1 1 0 A.B.C A  B  C
(Mi)' = ((mi)')' = mi
1 1 1 A.B.C A  B  C

23 24

Digital Systems, Chapter 3 6

dce dce
2019
SOP-POS Conversion 2019
Boolean Expressions and Truth Tables

• Canonical Sum  A ,B ,C (0,2,3,5,7) • Standard SOP & POS expressions

converted to truth table form
A BC  ABC  ABC  A BC  ABC • Standard SOP & POS expressions
• Canonical Product determined from truth table
 A ,B ,C (1,4,6)

( A  B  C)( A  B  C)( A  B  C)

•  A ,B ,C (0,2,3,5,7) =  A ,B ,C (1,4,6)

25 26

SOP-Truth Table Conversion POS-Truth Table Conversion

AB  BC ( A  B)(B  C)  A ,B,C (1,2,3,5)
 A ,B ,C (3,4,5,7)  ABC  ABC  ABC  ABC  ( A  B  C)( A  B  C)( A  B  C)( A  B  C)
Input Output Input Output
A B C F A B C F
0 0 0 0 0 0 0 1
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 0 1 1 0
1 0 0 1 1 0 0 1
1 0 1 1 1 0 1 0
1 1 0 0 1 1 0 1
1 1 1 1 1 1 1 1

Digital Systems, Chapter 3 7

dce dce
2019
Simplification of POS expressions using K-map 2019
Simplification of POS expressions using K-map

• Mapping of expression
• Forming of Groups of 0s
( A  B).(B  C)
• Each group represents sum term
0 1
AB\C
A\BC 00 01 11 10
00 0 0
0 0 0 1 1
01 1 1
1 1 1 1 0
11 1 1

10 0 1 ( A  B).( A  B  C)

dce dce
2019
Simplification of POS expressions using K-map 2019
Example
• Let’s design a logic circuit that controls an elevator door
in a three-story building.
– The circuit has four inputs.
( A  C).(C  D).(B  C  D) – M is a logic signal that indicates when the elevator is moving (M=
1) or stopped (M = 0).
AB\CD 00 01 11 10 – F1,F2, and F3 are floor indicator signals that are normally LOW,
and they go HIGH only when the elevator is positioned at the
00 0 0 1 0 level of that particular floor.
– For example, when the elevator is lined up level with the second
01 0 0 1 1 floor, F2 = 1 and F1 = F3 = 0. The circuit output is the OPEN
signal, which is normally LOW and will go HIGH when the
11 1 0 1 1 elevator door is to be opened.

10 1 0 1 0

32

Digital Systems, Chapter 3 8

dce dce
2019
Example 2019
K Map Method Summary
• Compared to the algebraic method, the K-map process
is a more orderly process requiring fewer steps and
always producing a minimum expression.
• The minimum expression in generally is NOT unique.
• For the circuits with large numbers of inputs (larger than
four), other more complex techniques are used.

33 34

dce dce
2019
Summary 2019
Example: 2-input NAND gates
• Implement The following function using only two-input
• SOP and POS –useful forms of Boolean equations NAND gates.
• Design of a comb. Logic circuit • B = x'y'b + x'yb' + x'yb + xyb
– (1) construct its truth table, (2) convert it to a SOP, (3)
= x'(y'b + yb') + yb(x'+x) by distributivity
simplify using Boolean algebra or K mapping, (4)
implement = x'(y'b + yb') + yb by complement
= x'((y'b)' (yb')')' + yb by De Morgan's law
• K map: a graphical method for representing a
circuit’s truth table and generating a simplified = ((x' ((y'b)' (yb')')')' (yb)' )' by De Morgan's law
expression
• “Don’t cares” entries in K map can take on values of
1 or 0. Therefore can be exploited to help
simplification

35 36

Digital Systems, Chapter 3 9

dce dce
2019
Exclusive-OR 2019
Exclusive-NOR
• The exclusive OR (XOR) produces a HIGH output • The exclusive NOR (XNOR) produces a HIGH output
whenever the two inputs are at opposite levels. whenever the two inputs are at the same level.
• XOR and XNOR outputs are opposite.

37 38

dce dce
2019

Parity Generator and Checker 2019

Enable/Disable Circuits
• XOR and XNOR gates are useful in circuits for
parity generation and checking. • A circuit is enabled when it allows the
passage of an input signal to the output.
• A circuit is disabled when it prevents the
passage of an input signal to the output.
• Situations requiring enable/disable
circuits occur frequently in digital circuit
design.

39 40

Digital Systems, Chapter 3 10

dce dce
2019

Enable/Disable Circuits 2019

Enable/Disable Circuits
• Design a logic circuit that will allow a signal to pass
to the output only when control inputs B and C are
• AND gate function act as enable/disable circuits both HIGH; otherwise, the output will stay LOW.

• Design a logic circuit that will allow a signal to pass

• NAND gate function act as enable/disable circuits to the output only when one, but not both, of the
control inputs are HIGH; otherwise, the output will
stay HIGH.

41 42

dce dce
2019

Merging & Inversion Circuits 2019

Basic Characteristics of Digital ICs

• OR gate performs signal merging function
• IC “chips” consist of resistors, diodes, and
transistors fabricated on a piece of semiconductor
material called a substrate.
• Digital ICs may be categorized according to the
number of logic gates on the substrate:
– SSI – less than 12
• XOR gate performs selectable inversion function
– MSI – 12 to 99
– LSI – 100 to 9999
– VLSI – 10,000 to 99,999
– ULSI – 100,000 to 999,999
– GSI – 1,000,000 or more

43 44

Digital Systems, Chapter 3 11

dce dce
Basic Characteristics of Digital ICs Basic Characteristics of Digital ICs
2019 2019

• ICs are also categorized by the type of components

• The first package we will examine is the dual in used in their circuits.
line package (DIP). – Bipolar ICs use NPN and PNP transistors
– Unipolar ICs use FET transistors.
• The transistor-transistor logic (TTL) and the
complementary metal-oxide semiconductor (CMOS)
families will both be examined.

45 46

dce dce
Basic Characteristics of Digital ICs Basic Characteristics of Digital ICs
2019 2019

• The TTL family consists of subfamilies as • The CMOS family consists of several series,
listed in the table. some of which are shown in the table.

47 48

Digital Systems, Chapter 3 12

dce dce
Basic Characteristics of Digital ICs Basic Characteristics of Digital ICs
2019 2019

• Power (referred to as VCC) and ground connections are • Inputs that are not connected are said to be
required for chip operation.
floating. The consequences of floating inputs
• VCC for TTL devices is normally +5 V. differ for TTL and CMOS.
• VDD for CMOS devices can be from +3 to +18 V. – Floating TTL input acts like a logic 1. The voltage
measurement may appear in the indeterminate
range, but the device will behave as if there is a 1 on
the floating input.
– Floating CMOS inputs can cause overheating and
damage to the device. Some ICs have protection
circuits built in, but the best practice is to tie all
unused inputs either high or low.

49 50

dce dce
Troubleshooting Digital Systems Troubleshooting Digital Systems
2019 2019

• 3 basic steps • The logic probe will indicate the presence or

– Fault detection, determine operation to expected absence of a signal when touched to a pin
operation.
as indicated below.
– Fault isolation, test and measure to isolate the fault.
– Fault correction, repair the fault.
• Good troubleshooting skills come through
experience in actual hands-on troubleshooting.
• The basic troubleshooting tools used here will
be: the logic probe, oscilloscope, and logic
pulser.
• The most important tool is the technician’s brain.

51 52

Digital Systems, Chapter 3 13

dce dce
2019

Internal Digital IC Faults 2019

Internal Digital IC Faults

• Most common internal failures: • Malfunction in internal circuitry
– Outputs do not respond properly to inputs. Outputs are
– Malfunction in the internal circuitry. unpredictable.
– Inputs or outputs shorted to ground or VCC • Input internally shorted to ground or supply
– The input will be stuck in LOW or HIGH state.
– Inputs or outputs open-circuited • Output internally shorted to ground or supply
– Short between two pins (other than ground – Output will be stuck in LOW or HIGH state.
or VCC) • Open-circuited input or output
– Floating input in a TTL device will result in a HIGH output.
Floating input in a CMOS device will result in erratic or
possibly destructive output.
– An open output will result in a floating indication.
• Short between two pins
– The signal at those pins will always be identical.

53 54

dce dce
External Faults External Faults
2019 2019

• Open signal lines – signal is prevented from • Shorted signal lines – the same signal will
moving between points. Some causes: appear on two or more pins. VCC or ground
– Broken wire may also be shorted. Some causes:
– Sloppy wiring
– Poor connections (solder or wire-wrap)
– Solder bridges
– Cut or crack on PC board trace
– Incomplete etching
– Bent or broken IC pins.
• Detect visually and verify with an ohmmeter.
– Faulty IC socket
• Detect visually and verify with an ohmmeter.

55 56

Digital Systems, Chapter 3 14

dce dce
External Faults External Faults
2019 2019

• Faulty power supply – ICs will not operate or • Output loading – caused by connecting too
will operate erratically. many inputs to the output of an IC.
– May lose regulation due to an internal fault or – Causes output voltage to fall into the indeterminate
because circuits are drawing too much current. range.
– Always verify that power supplies are providing the – This is called loading the output.
specified range of voltages and are properly – Usually a result of poor design or bad connection.
grounded.
– Use an oscilloscope to verify that AC signals are not
present.

57 58

Digital Systems, Chapter 3 15

dce dce
2019 2019

Introduction
• So far we have seen Combinational Logic
– The output(s) depends only on the current values of the input
variables

Digital Systems • Here we will look at Sequential Logic circuits

– The output(s) can depend on present and also past values of
the input and the output variables
FLIP-FLOPs • Sequential circuits exist in one of a defined number of
states at any one time
– They move "sequentially" through a defined sequence of
BK
TP.HCM
transitions from one state to the next
– The output variables are used to describe the state of a
sequential circuit either directly or by deriving state variables
from them

dce
2019
General Digital System dce
2019
Synchronous and Asynchronous
Sequential Logic
• Synchronous
– The timing of all state transitions is controlled by a common
clock
– Changes in all variables occur simultaneously
• Asynchronous
– State transitions occur independently of any clock and normally
dependent on the timing of transitions in the input variables
– Changes in more than one output do not necessarily occur
simultaneously
• Clock
– A clock signal is a square wave of fixed frequency
– Often, transitions will occur on one of the edges of clock pulses
• i.e. the rising edge or the falling edge

3 4

Digital Systems 1
dce General flip-flop symbol and definition of its two dce
2019

possible output states

2019

NAND Gate Latch

• The NAND gate latch or simply latch is a basic
FF.
• The inputs are set and clear (reset)
• The inputs are active low, that is, the output will
change when the input is pulsed low.
• When the latch is set
• We now introduce the concept of memory. The flip-
flop, abbreviated FF, is a key memory element.
Q  1 and Q  0
• When the latch is clear or reset
• The outputs of a flip flop are Q and Q’
• Q is understood to be the normal output, Q’ is always Q  0 and Q  1
the opposite.

5 6

dce dce
2019
A NAND latch is an example of a bistable device 2019
Setting the NAND Flip-Flop

NAND
001
011
101
110

NAND
001
011
101
110

7 8

Digital Systems 2
dce dce
2019
Resetting the NAND Flip-Flop 2019
Function table of a NAND latch

NAND
001
011
101
110

9 10

dce dce
2019

NAND Gate Latch 2019

Other Representations of a NAND latch

• Summary of the NAND latch:

– SET = RESET = 1. Normal resting state, outputs
remain in state prior to input.
– SET = 0, RESET = 1. Q will go high and remain
high even if the SET input goes high.
– SET = 1, RESET = 0. Q will go low and remain low
even if the RESET input goes high.
– SET = RESET = 0. Output is unpredictable because
the latch is being set and reset at the same time.
• Symbols indicate Q is set (high) when S is
low.

11 12

Digital Systems 3
dce dce
2019
Determine Q 2019 A example of NAND latch Application

• NAND latch used to debounce a mechanical switch

13 14

dce dce
2019

NOR Gate Latch 2019

NOR gate latch
• (a) NOR gate latch; (b) function table; (c) simplified block
• The NOR latch is similar to the NAND latch symbol.
except that the Q and Q’ outputs are reversed.
• The SET and RESET inputs are active high, that
is, the output will change when the input is
pulsed high.
• In order to ensure that a FF begins operation at • Determine Q for a NOR latch given the inputs below
a known level, a pulse may be applied to the
SET or RESET inputs when a device is powered
up.

15 16

Digital Systems 4
dce SR latch useful when temporary setting is used to dce
2019

activate switch
2019

Digital Pulses
The NAND FF is used to • The transition from low to high on a positive
provide a bounce free switch pulse is called rise time (tr).
so that the 1 KHz pulse can
propagate to the output – Rise time is measured between the 10% and 90%
without distortion. points on the leading edge of the voltage waveform.
• The transition from high to low on a positive
pulse is called fall time (tf).
– Fall time is measured between the 90% and 10%
points on the trailing edge of the voltage waveform.

17 18

dce dce
2019
Rise and Fall times 2019
Rise and Fall times

Signal that activates an active-low output with:

tw = 50ns, tr =15ns, and tf = 10 ns.

19 20

Digital Systems 5
dce dce
2019

Clock Signals and Clocked Flip-Flops

2019
Ideal Clock Signals

• Asynchronous system – outputs can change

state at any time the input(s) change.
• Synchronous system – output can change state
only at a specific time in the clock cycle.
– The clock signal is a rectangular pulse train or
square wave.
– Positive going transition (PGT) – when clock pulse
goes from 0 to 1.
– Negative going transition (NGT) – when clock pulse
goes from 1 to 0.
– Transitions are also called edges.
21 22

dce dce
2019

Clock Signals and Clocked Flip-Flops

2019
Clocked Flip-Flops

• Clocked FFs change state on one or the other

clock transitions. Some common characteristics:
– Clock inputs are labeled CLK, CK, or CP.
– A small triangle at the CLK input indicates that the
input is activated with a PGT.
– A bubble and a triangle indicates that the CLK input is
activated with a NGT.
– Control inputs have an effect on the output only at the
active clock transition (NGT or PGT). These are also
called synchronous control inputs.
– The control inputs get the FF outputs ready to change,
but the change is not triggered until the CLK edge.

23 24

Digital Systems 6
dce dce
2019

Clock Signals and Clocked Flip-Flops

2019

Clocked S-R Flip-Flop

• Setup time (tS) is the minimum time interval before the • The SET-RESET (or SET-CLEAR) FF will change states
active CLK transition that the control input must be at the positive going or negative going clock edge.
kept at the proper level.
• Hold time (tH) is the time after the active CLK transition
during which the control input must kept at the proper
level.

25 26

dce dce
2019
Clocked SR Flip-Flop 2019 Clocked SR Flip-Flop
• Clocked S-R flip-flop that triggers only on negative-going • Implementation of edge-detector circuits used in edge-
transitions. triggered flip-flops: (a) PGT; (b) NGT. The duration of the
CLK* pulses is typically 2–5 ns.

• Simplified version of
the internal circuitry
for an edge-
triggered S-R flip-
flop.

27 28

Digital Systems 7
dce dce
2019

Clocked J-K Flip-Flop 2019

Clocked JK Flip-Flop
• Operates like the S-R FF. J is set, K is clear.
• When J and K are both high the output is
toggled from whatever state it is in to the
opposite state.
• May be positive going or negative going clock
trigger.
• Has the ability to do everything the S-C FF
does, plus operate in toggle mode.

29 30

dce dce
2019
Edge-triggered J-K flip-flop 2019

Clocked D Flip-Flop
• One data input.
• The output changes to the value of the input at
either the positive going or negative going clock
trigger.

CLK* must be high for FF to change states. This condition only

occurs at the edge of a CLK transition.
31 32

Digital Systems 8
dce Edge-triggered D flip-flop dce
2019 2019
Parallel transfer of binary data using D flip-flops
implementation from a J-K flip-flop

33 34

dce dce
2019

D Latch (Transparent Latch) 2019

D Latch
• D latch: (a) structure; (b) function table; (c) logic symbol.
• One data input.
• The clock has been replaced by an
enable line.
• The device is NOT edge triggered.
• The output follows the input only when
EN is high.

EN must be high for D-Latch to change states.

35 36

Digital Systems 9
dce dce
2019
D Latch 2019

Asynchronous Inputs
• Waveforms showing the two modes of operation of the
transparent D latch. • Inputs that depend on the clock are synchronous.
• Most clocked FFs have asynchronous inputs that
do not depend on the clock.
• The labels PRE and CLR are used for
asynchronous inputs.
• Active low asynchronous inputs will have a bar
over the labels and inversion bubbles.
• If the asynchronous inputs are not used they will
be tied to their inactive state.

37 38

dce
2019 Clocked J-K flip-flop with asynchronous inputs dce
2019 Clocked J-K flip-flop with asynchronous inputs

39 40

Digital Systems 10
dce dce
Flip–Flop Propagation Delays
Flip-Flop Timing Considerations
2019 2019

• Important timing parameters:

– Setup and hold times
– Propagation delay: the time for a signal at the input to be
shown at the output.
– Maximum clocking frequency: highest clock frequency that
will give a reliable output.
– Clock pulse high and low times: minimum time that the clock
must be high before going low, and low before going high.
– Asynchronous active pulse width: the minimum time
PRESET or CLEAR must be held for the FF to set or clear
reliably.
– Clock transition times: maximum time for the clock
transitions, generally less than 50 ns for TTL, or 200 ns for
CMOS devices.
41 42

dce dce
Clock LOW and HIGH time
Potential Timing Problems in FF Circuits
2019 2019

• When the output of one FF is connected to the

input of another FF and both devices are
triggered by the same clock, there is a potential
timing problem.
synchronous asynchronous
• Propagation delay may cause unpredictable
outputs.
tw(L) is the minimum time that the CLK must remain low before it
• The low hold time parameter of most FFs mean
goes high.
tw(H) is the minimum time that the CLK must remain high before it this won’t normally be a problem.
goes low.

Similarly for asynchronous signals - but may have a different value

than the CLK signal.
43 44

Digital Systems 11
dce dce
2019
Propagation Delay in Synchronous Circuits 2019

Flip-Flop Synchronization
• Most systems are primarily synchronous
in operation, in that changes depend on
the clock.
•The input (J2) to Q2 must • Asynchronous and synchronous
be held for tH after the operations are often combined.
clock edge.
• The random nature of asynchronous
•This will occur only if tPHL inputs can result in unpredictable results.
> tH.

•Usually, this is the case.

45 46

dce Asynchronous Signals may have Undesirable Side dce

2019 2019
Edge-triggered flip-flop can Synchronize
Effects
Circuit
• The signal A has
no effect until
negative edge of
clock.

• Asynchronous signal A can produce

partial pulses at X

47 48

Digital Systems 12
dce dce
2019

Data Storage and Transfer 2019

Asynchronous Data Transfer Operation

• Asynchronous transfers are controlled by PRE

and CLR inputs.
• Transferring the bits of a register
simultaneously is a parallel transfer.
• Transferring the bits of a register a bit at a time
is a serial transfer.

• Uses PRE and CLR inputs to load data into FF

• PRE and CLR won’t be both low at the same time
A = 1, EN =1, PRE = 0, sets B = 1

49
A =0, EN =1, CLR = 0, sets B = 0 50

dce dce
2019 Synchronous transfer of contents of register X into 2019

register Y Serial Data Transfer: Shift Registers

• When FFs are arranged as a shift register, bits
will shift with each clock pulse.
• FFs used as shift registers must have very low
hold time parameters to perform predictably.
Modern FFs have tH values well within what is
required.
• The direction of data shifts will depend on the
circuit requirements and the design.

51 52

Digital Systems 13
dce dce
2019
Serial Data Transfer: Shift Registers 2019
Four-bit Shift Register

• Parallel transfers – register contents are

transferred simultaneously with a single clock
cycle.
• Serial transfers – register contents are
transferred one bit at a time, with a clock pulse
for each bit.
• Serial transfers are slower, but the circuitry is
simpler. Parallel transfers are faster, but
circuitry is more complex.
• Serial and parallel are often combined to exploit
the benefits of each.

53 54

dce dce
Serial transfer from X register into Y register
Frequency Division and Counting
2019 2019

• FFs are often used to divide a frequency as

illustrated in next slide. Here the output
frequency is 1/8th the input (clock) frequency.
• The same circuit is also acting as a binary
counter. The outputs will count from 0002 to
1112
• The number of states possible in a counter is
the modulus or MOD number. Next slide is a
MOD-8 (23) counter. If another FF is added it
would become a MOD-16 (24) counter.

55 56

Digital Systems 14
dce dce
2019
MOD-8 Asynchronous Counter 2019
State Table & Diagram of MOD-8 Asynchronous Counter

57 58

dce dce
Example of Microprocessor Interfacing
2019

Microcomputer Application 2019

• Microprocessor units (MPUs) which will be

studied later, perform many functions that
involve the use of registers for data transfer and
storage.
• MPUs may send data to external registers for
many purposes, including:
– Solenoid or relay control
– Motor starting
– Device positioning
– Motor speed controls

59 60

Digital Systems 15
dce dce
Schmitt-Trigger Response (two thresholds)
2019

Schmitt-Trigger Devices 2019

• Not a FF but shows a memory characteristic

• Accepts slow changing signals and produces a
signal that transitions quickly.
• A Schmitt trigger device will not respond to an
input until it exceeds the positive or negative
going threshold.
• There is a separation between the two
threshold levels. This means that the device
will “remember” the last threshold exceeded
until the input goes to the opposite threshold.
Standard inverter response to slow noisy input, and

(b) Schmitt-trigger response to slow noisy input.

Often used with noisy signals

61 62

dce dce
2019
Schmitt-Trigger Response (two thresholds) 2019

One-shot (Monostable Multivibrator)

• Changes from stable state to quasi-stable state
for a period of time determined by external
components (usually resistors and capacitors).
• Nonretriggerable devices will trigger and return
to stable state.
• Retriggerable devices can be triggered while in
the quasi-stable state to begin another pulse.
• One shots are called monostable multivibrators
because they have only one stable state.
• They are prone to triggering by noise so, tend to
be used in simple timing applications.
Standard inverter response to slow noisy input, and
Often used with noisy signals
(b) Schmitt-trigger response to slow noisy input.
63 64

Digital Systems 16
dce dce
2019
One-shot 2019
Retriggerable and Nonretriggerable Operation

65 66

dce Logic symbols for the 74121 nonretriggerable dce

2019

one-shot
2019

Clock Generator Circuits

• FFs have two stable states, so are considered
bistable multivibrators.
• One shots have one stable state and are
considered monostable multivibrators.
• Astable or free-running multivibrators switch back
and forth between two unstable states. This makes
it useful for generating clock signals for
synchronous circuits.
• Crystal control may be used if a very stable clock is
needed. Crystal control is used in microprocessor
based systems and microcomputers where
accurate timing intervals are essential.

67 68

Digital Systems 17
dce dce
2019
Clock Generator Circuit: Schmitt-trigger Oscillator 2019 Clock Generator Circuit: 555 Timer
555 timer IC used astable multivibrator.
Schmitt-trigger oscillator using a 7414 INVERTER. A 7413
Schmitt-trigger NAND may also be used.

Circuit will not oscillate if R is not kept within these limits.

69 70

Digital Systems 18