CMOS Inverter

Digital MOS LSI Circuiits [EE524]

Dr. Hitesh Shrimali

Indian Institute of Technology Mandi
Kamand Campus, Himachal Pradesh
 Today's agenda
●
Review: last lecture
– NMOS and PMOS transistor
– CMOS technology
– Moore's law
– CMOS inverter
●
CMOS Inverter
– CMOS implementation
●
Logic gates and their implementations
 Important terms to learn
●
What is large signal?
●
Rail to rail is the value from positive supply to
the negative supply value.
●
Remember: none of the circuit in the world can
give amplification beyond it's rail
Combination logic circuits
●
Made up of gates
– AND
– OR
– NAND (Universal)
– NOR (Universal)
– XOR
– XNOR
●
Explanation of gates
– Truth table
Pull up and pull down realization
●
Silver bullets
●
PUN (pull up network)
is realized using
PMOS only
●
PDN (pull down
network) is realized
using NMOS only
 NMOS logic rules

A B
A B

Series combination conducts if

A' AND B'
Parallel combination conducts if A' OR B'
AND gate: CMOS realization
Vd d = 1

A F= A* B
F= A+ B
B
F

A B

0
OR gate: CMOS realization
Vdd = 1

A B

F
A
F= A+ B
B F=A* B

0
NAND gate: CMOS realization
Vdd = 1

A B

F
A
F= A* B= A+ B
B F=A* B

0
NOR gate: CMOS realization
Vdd = 1
F= A+ B= A* B
A F=A+B

B
F

A B

0
 Important terms: revisit
●
Large signal
●
Rail to rail
●
Saturation (non-linearity) because of rail-to-rail
limitation
 Illustration - I
Implement the function (F) using CMOS technology

F = A*B + A'*B*C
CMOS Inverter: transfer chs.
Vout

Vin
 RC circuit
vi n R vout

●
Draw the transient response when an applied input is a square wave,
●
Find out the transfer function of the system,
●
Identify poles and zeros if there are any,
●
Draw the frequency response for the system.
 RC circuit: useful informations?
vi n R vout

●
Draw the transient response when an applied input is a square wave,
●
RC delay
●
Settled value at steady state
●
Find out the transfer function of the system,
●
Nature of the circuit
●
Identify poles and zeros if there are any,
●
Resonance
●
Draw the frequency response for the system.
●
Bandwidth
CMOS Inverter
●
Silver bullets
●
In CMOS inverter, nMOS
and pMOS have been
used as switches.
●
Every switch will have
finite resistance.
Switch model
Discharge path
CMOS Inverter
●
Silver bullets
●
Every wire (or path) has a
finite resistance,
●
Capacitor blocks DC and
allows AC,
●
Parasitic capacitor created
at high frequency (greater
than 0 Hz),
●
There is a parasitic
capacitance between two
dissimilar metals.
MOS device layouts

G G
D m
etal S D m
etal S
si o2 si o2
n + n + p + p +
p n

B B
CMOS Inverter: device implementation
Vd d

p +

p +
Vi n Vou t

n +

n +
CMOS Inverter: parasitic behavior
Vd d ●
Silver bullets
●
Every wire (or path) has a
finite resistance,
p +

p +
●
Capacitor blocks DC and
Vi n Vou t
allows AC,
n +
p
●
Parasitic capacitor created
at high frequency (greater
n +
than 0 Hz),
●
There is a parasitic
capacitance between two
dissimilar metals.
Key terms associated with logic gates
●
Noise margin
– For high level
– For low level
●
Switching threshold
●
Propagation delay
●
Power consumption
– Through switching
 Illustration - I
Realize the full adder using CMOS technology
Illustration – II
Vout

Vin
 Inverter DC Characteristic

Note: Anoop and Sandeep did the measurement. (2012 batch BTech EE students.)
 Inverter DC Characteristic

Note: Anoop and Sandeep did the measurement. (2012 batch BTech EE students.)
Illustration – II
Illustration – II: reality
CMOS Inverter
●
Silver bullets
●
In CMOS inverter, nMOS
and pMOS have been
used as switches.
●
Every switch will have
finite resistance.
Switch model
Discharge path
CMOS Inverter
●
Silver bullets
●
Every wire (or path) has a
finite resistance,
●
Capacitor blocks DC and
allows AC,
●
Parasitic capacitor created
at high frequency (greater
than 0 Hz),
●
There is a parasitic
capacitance between two
dissimilar metals.
MOS device layouts

G G
D m
etal S D m
etal S
si o2 si o2
n + n + p + p +
p n

B B
CMOS Inverter: device implementation
Vd d

p +

p +
Vi n Vou t

n +

n +
CMOS Inverter: parasitic behavior
Vd d ●
Silver bullets
●
Every wire (or path) has a
finite resistance,
p +

p +
●
Capacitor blocks DC and
Vi n Vou t
allows AC,
n +
p
●
Parasitic capacitor created
at high frequency (greater
n +
than 0 Hz),
●
There is a parasitic
capacitance between two
dissimilar metals.
Delay
●
Propagation
delay
●
tpHL
●
tpLH
 Power consumption
●
Static power consumption
– Average power dissipation
– During ON time
– During OFF time
●
Dynamic power consumption
– At switching
– Depends upon switching frequency
– Depends on supply level
– Depends upon the load capacitance
 Power consumption at leakage
●
When both the transistors are OFF
●
Still there is a leakage
●
Reason for leakage?
●
Technology dependency
Key terms associated with logic gates
●
Noise margin
– For high level
– For low level
●
Propagation delay
●
Power consumption
– Through switching
●
Switching threshold
– The input voltage level after which state of logic gate changes (0 → 1 or
1 → 0)
– Ideally, the switching threshold is the point when both PUN and PDN are
ON.
 Illustration – III
Design a multiplexer circuit which can
select the one signal out of available four
signals. The available input signals are DC,
sine wave, triangular wave and square
wave. There is only a single push-button
available to select one of the input signal.
Quick review: opamp as a black box
●
Three configuration
●
Open loop
●
Negative feedback
●
Solved by golden rules
●
Positive feedback (Schmit trigger)
Opamp in an open loop configuration
●
Comparator in an open loop configuration
●
Zero crossing detector
 Illustration – II
●
Comparator
●
An open loop system
●
Voltage inputs
●
1 bit ADC
 Illustration – III
10 V

R=1K
1V

R=1K

0V
 Illustration – IV
●
For a water tank with the height of 100 ft, how
many number of bits of ADC required to detect
the minimal level of 1 ft. Design the complete
system using all your known components.