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FPGA Implementation of Digital Modulation Schemes: BPSK and QPSK Using

VHDL

Conference Paper · January 2014

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ISSN : 2230-7109 (Online) | ISSN : 2230-9543 (Print) IJECT Vol. 5, Issue Spl - 2, Jan - March 2014

FPGA Implementation of Digital Modulation

Schemes: BPSK and QPSK Using VHDL
Rajib Das
Dept. of ECE, Sir J. C. Bose School of Engineering, West Bengal, India

Abstract STAGE0 generates the carrier sinusoidal signal (A sin (2πft))

This paper presents the simulation results of digital modulation whose frequency is 322 MHz and initial phase is 0º represented
schemes BPSK and QPSK. Digital modulation is less complex, by SinWave0. Similarly, STAGE1 generates the carrier sinusoidal
more secure and more efficient in long distance transmission. The signal (A sin (2πft + π)) whose frequency is 322 MHz and
noise detection and correction in digital is more efficient than initial phase is 180º represented by SinWave180. So the output
analog. So it has more importance in modern communication of STAGE0 and STAGE1 are same but they are out of phase.
system. These digital modulation schemes can be realized using STAGE2 represents the Bit Separator block. This block separates
FPGA ( Field Programmable Gate Array) . In this paper, BPSK and one successive massage signal bit by one time period of sinusoidal
QPSK modulation techniques have been implemented on FPGA signal. Three input signals of bit separator are clk, start and data.
using VHSIC (Very High Speed Integrated Circuit) Hardware Start signal acts as enable signal for BPSK Modulator.
Description Language (VHDL) on Xilinx ISE 14.1 and simulated
with MdelSim SE 6.0

Keywords
Digital Modulation Techniques, BPSK, QPSK, FPGA, VHDL

I. Introduction
Despite simple transmitter and receiver architecture of BPSK
modulator, BPSK modulation is still commonly used in wireless
communication such as WPAN ( Wireless Personal Area Network)
[1]. QPSK is used in different communication systems like CDMA
, 3G, Wi-Fi (IEEE 802.11) and WiMAX ( IEEE 802.16). The
bandwidth required by QPSK is one-half than that of BPSK for
the same Bit Error Rate (BER) and transmission data rate in QPSK
is higher because of reducer bandwidth.
Field-programmable gate arrays(FPGAs) are semiconductor
devices containing programmable Logic Elements (LEs) and a
hierarchy of reconfigurable interconnects to realize any complex
combinational or sequential logic functions. Today’s FPGAs
consist of configurable embedded static random-access memories
(SRAMs), high-speed transceivers, high-speed input/output
(I/O) elements, network interfaces, and even hard-embedded
processors. A literature survey shows that FPGAs are widely used
in different applications, such as motor controllers [2], neural Fig. 1: Block Diagram of BPSK Modulator
network implementations [3-5], Finite Impulse-Response (FIR)
filter realization [6-7], fuzzy-logic controllers [8], etc. Data signal represents the digital massage signal bit. The output
signal of Bit Separator acts as a select input for STAGE3 which
II. BPSK Modulator is basically a multiplexer and represented by MUX_BPSK. This
In Binary Phase Shift Keying (BPSK), the phase of the sinusoidal signal selects output of STAGE0 or STAGE1 as input signal of
carrier signal is varied in accordance with the value of the binary multiplexer. The output of multiplexer (BPSK_OUT) is the BPSK
information data bit to be transmitted. It is also called bi-phase Modulated signal (indicated by violet color waveform in fig. 3).
modulation or phase reversal keying [9]. The phase of the carrier Fig. 3 shows the simulation result of BPSK MODULATOR.
signal is changed between 0º and 180º by the binary data. The
BPSK signal can be expressed as: IV. QPSK Modulator
Quadrature Phase Shift Keying (QPSK) is an M-ary constant
amplitude digital modulation scheme in which number of bits
is two and number of signaling elements are four. In QPSK two
Where, A sin (2πft) is carrier signal with 0º initial phase. When successive bits in a bit stream is combined together to form a
the input binary data changes from 1 to 0 or vice versa , the BPSK symbol. Each symbol is then represented by a distinct value of
output signal phase shifts from 0º to 180º or vice versa. phase shift of the carrier. Each signaling element is represented
by two bits. This is called dibit system. QPSK signal can carry
III. FPGA Based BPSK Modulator Design twice as much data in the same bandwidth as can a single-bit
Using Xilinx ISE 14.1 , BPSK modulated signal can be created. system, provided the SNR is high enough. It has four different
Fig-1 shows the proposed block diagram in FPGA. phase shifts, separated by multiples of 90º of the carrier signal.
In this BPSK modulator, when clock signal (clk) is applied then C(t) = A sin (2πft). Four output phases are possible for a single

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IJECT Vol. 5, Issue Spl - 2, Jan - March 2014 ISSN : 2230-7109 (Online) | ISSN : 2230-9543 (Print)

carrier frequency, corresponding to 00, 01, 10 and 11 dibts. Each Similarly, STAGE1, STAGE2 and STAGE3 generate the carrier
dibit code generates one of the four possible output phases (0º , sinusoidal signal whose frequency is 322 MHz and initial phase
90º, 180º, 270º). A single change in output phase occurs for each is 90º, 180º, 270º represented by SinWave90, SinWave180,
two-bit dibit. The rate of change at the output (baud) is equal to SinWave270 respectively. STAGE4 represents the Bit Separator
one-half the input bit rate. block. This block separates two successive massage signal bits
Mathematically, the QPSK signal for one symbol duration, by one time period of sinusoidal signal. Three input signals of bit
consisting of two bits each, can be expressed as: separator are clk, start and data. Start signal acts as enable signal
for QPSK Modulator. Data signal represents the digital massage
signal bits. The output signal of Bit Separator acts as a select input
for STAGE5 which is basically a multiplexer and epresented by
MUX_QPSK. This signal selects output of STAGE0 or STAGE1
or STAGE2 or STAGE3 as input signal of multiplexer. The output
of multiplexer is the QPSK Modulated signal (indicated by violet
Table 1 Depicts the Relationship Between Symbols, Bits and color waveform in fig. 4). Fig. 4 shows the simulation result of
Phase Shifts in QPSK Carrier Signal [9] QPSK MODULATOR.

Table 1: Symbols Bits and Phase Shifts in QPSK Signal VI. Conclusion and Future Works
Symbol Bit in symbol Phase shift in carrier signal The purpose of this paper is can be implemented BPSK and QPSK
modulation techniques based on FPGA. Here modulation is done
S1 00 0º
without multiplication of binary massage signal with sinusoidal
S2 01 90º carrier signal. Instead of multiplication, for each case, sample
S3 10 180º of different carrier signal was saved in ROM. In an AWGN
S4 11 270º (Additive White Gaussian Noise) channel, the BER (Bit Error
Rate) decreases approximately exponentially as the SNR (Signal
V. FPGA Based QPSK Modulator Design to Noise Ratio) [10]. BPSK and QPSK produce good BER and
Using Xilinx ISE 14.1 , BPSK modulated signal can be created. noise immunity than ASK, FSK. The bandwidth for BPSK is
Fig-2 shows the proposed block diagram in FPGA. same as that of ASK, and less than that of BFSK. The bandwidth
In this QPSK modulator, when clock signal (clk) is applied then required by QPSK is one-half that of BPSK for the same BER.
STAGE0 generates the carrier sinusoidal signal (A sin (2πft)) The transmission data rate in QPSK is Higher because of reduced
whose frequency is 322 MHz and initial phase is 0º represented bandwidth. The variation in QPSK signal amplitude is not much,
by SinWave0. hence carrier power almost remain constant.
In the future works, the proposed BPSK and QPSK modulator
will be implemented on the Spartan 3E Starter Kit. The design has
been written in the VHD programming code by Xilinx software.
After implementing the BPSK and QPSK modulator, I want to
realize a BPSK and QPSK system. The system will consist of a
modulator and demodulator and the signal from the modulator
to demodulator will pass through a channel affected by AWGN.
The modulated and demodulated signals will be also routed to
VGA monitors, but also to oscilloscopes.

Fig. 2: Block Diagram of QPSK Modulator.

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Fig. 3: Simulation Result of BPSK Modulator

Fig. 4: Simulation Result of QPSK Modulator

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