ADDIS ABABA INSTITUTE OF TECHNOLOGY
School of Electrical And Computer Engineering
Electronics Stream
DIGITAL SYSTEM DESIGN ASSIGNMENT-2
Name — Rahel Brhanie
ID — UGR/8220/13
Submitted to:Mr.Henok T.
Submission day: 8/7/2024G.C.
1. Design a combinational circuit (MUX 4 to 1) using hardware description language and prepare a
report.
● VHDL code
VHDL CODE for 4_to_1 MUX
library IEEE;
use IEEE.std_logic_1164.all;
use work.all;
entity mux4to1 is
port(
I:in std_logic_vector(3 downto 0);
S: in std_logic_vector(1 downto 0);
Y:out std_logic
);
end mux4to1;
architecture behav of mux4to1 is
begin
Y<=I(0) when S ="00" else
I(1) when S ="01" else
I(2) when S="10" else
I(3);
end behav;
● Testbench code
TESTBENCH FOR 4_TO_1 MUX
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4to1_tb is
end mux4to1_tb ;
architecture tb_arch of mux4to1_tb is
component mux4to1
port(
I : in std_logic_vector(3 downto 0);
S : in std_logic_vector(1 downto 0);
Y : out std_logic
);
end component;
signal I_input : std_logic_vector(3 downto 0);
signal S_input : std_logic_vector(1 downto 0);
signal Y_output : std_logic;
mapping: mux4to1 port map ( I_input,S_input, Y_output);
process
begin
-- Loop through all possible input combinations
for i in 0 to 3 loop
for j in 0 to 15 loop
-- Convert loop index to binary and assign to input signals
S_input <= std_logic_vector(to_unsigned(i, S_input'length));
I_input <= std_logic_vector(to_unsigned(j, I_input'length));
wait for 10 ns;
end loop;
end loop;
end process;
end tb_arch;
● Simulation waveform
WAVEFORM
● Synthesis, RTL viewer and Technology map viewer
SYNTHESIS IN QUARTUS:
RTL VIEWER:
TECHNOLOGY MAP VIEWER(POST MAPPING):
TECHNOLOGY MAP VIEWER(POST FITTING):
2. Submit VHDL codes for LAB 1 (Part1 up to Part5)
Part I
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- - Simple entity that connects the SW switches to the LEDR lights
ENTITY part1 IS
PORT ( SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
END part1;
ARCHITECTURE Behavior OF part1 IS
BEGIN
LEDR <= SW;
END Behavior
Part II
library ieee;
use ieee.std_logic_1164.all;
entity 4bit is
port (
-- S
SW9: in std_logic;
-- X
SW3: in std_logic;
SW2: in std_logic;
SW1: in std_logic;
SWO : in std_logic;
--Y
SW7: in std_logic;
SW6 : in std_logic;
SW5: in std_logic;
SW4: in std_logic;
LEDR9: out std_logic;
LEDR3 : out std_logic;
LEDR2: out std_logic;
LEDR1: out std_logic;
LEDRO: out std_logic;
Unused
LEDR8: out std_logic;
LEDR7: out std_logic;
LEDR6: out std_logic;
LEDR5: out std_logic;
LEDR4: out std_logic;
end 4bit;
architecture behavior of 4bit is
begin
LEDR9 <= SW9;
LEDRO <= (NOT (SW9) AND SWO) OR (SWS AND SW4);
LEDR1 <= (NOT (SW9) AND SW1) OR (SW9 AND SW5);
LEDR2 <= (NOT (SW9) AND SW2) OR (SW9 AND SW6);
LEDR3 <= (NOT (SW9) AND SW3) OR (SW9 AND SW7);
LEDR4 <= 0;
LEDR5 <= 0;
LEDR6 <= 0;
LEDR7 <= 0;
LEDR8 <= 0;
end architecture behavior;
Part III
library ieee;
use ieee.std_logic_1164.all;
entity 2bit is
port (
- - SO AND S1
SW9 : in std_logic;
SW8: in std_logic;
- - UO AND U1
SW7: in std_logic;
SW6: in std_logic;
- - VO AND V1
SW5: in std_logic;
SW4: in std_logic;
- - WO AND W1
SW3: in std_logic;
SW2: in std_logic;
- - XO AND X1
SW1: in std_logic;
SWO: in std_logic;
- - MO AND M1
LEDR1: out std_logic;
LEDRO: out std_logic;
- - Unused
LEDR9: out std_logic;
LEDR8: out std_logic;
LEDR7: out std_logic;
LEDR6: out std_logic;
LEDR5: out std_logic;
LEDR4: out std_logic;
LEDR3: out std_logic;
LEDR2: out std_logic;
end 2bit;
architecture behavior of 2bit is
begin
LEDR9 <= 0;
LEDRO <=(
(NOT (S8) AND (NOT (SW9) AND SW7) OR (SW9 AND SW5))
OR
(S8 AND (NOT (SW9) AND SW3) OR (SW9 AND SW1)))
);
LEDR1 <= (
(NOT(S8) AND (NOT (SW9) AND SW6) OR (SW9 AND SW4))
OR
(S8 AND (NOT (SW9) AND SW2) OR (SW9 AND SWO)))
);
LEDR2 <= 0;
LEDR3 <= 0;
LEDR4 <= 0;
LEDR5 <= 0;
LEDR6 <= 0;
LEDR7 <= 0;
LEDR8 <= 0;
end architecture behavior;
Part IV
library IEEE;
use IEEE.std_logic_1164.all;
Entity for 7-segment decoder
- - ENTITY seven_segment_decoder IS
- - Inputs
PORT (
c1: IN STD_LOGIC;
co: IN STD_LOGIC
);
- - Outputs
PORT (
HEXO: OUT STD_LOGIC_VECTOR(0 TO 6)
);
END ENTITY seven_segment_decoder;
Architecture for 7-segment decoder
- - ARCHITECTURE behavior OF seven_segment_decoder IS
BEGIN
- - Combinational logic for each segment
ΗΕΧ0 (0) <= NOT (c0 AND c1); - - Segment a (active low)
HEXH (1) <= c1; - - Segment b (active low)
HEXTH (2) <= NOT c1; - - Segment c (active low)
HEXTH (3) <= c0 AND c1; - - Segment d (active low)
HEXTH (4) <= NOT CO; - - Segment e (active low)
ΗΕΧ0 (5) <= NOT (c0 OR c1); - - Segment f (active low)
HEXTH (6) <= c0; - - Segment g (active low)
END ARCHITECTURE behavior;
Part V
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY part5 IS
PORT ( SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6) );
END part5;
ARCHITECTURE Behavior OF part5 IS
COMPONENT mux_2bit_4to1
PORT ( S, U, V, W, X : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END COMPONENT;
COMPONENT char_7seg
PORT ( C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Display : OUT STD_LOGIC_VECTOR(0 TO 6));
END COMPONENT;
SIGNAL M0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
U0: mux_2bit_4to1 PORT MAP (SW(9 DOWNTO 8), SW(7 DOWNTO 6), SW(5
DOWNTO 4),
SW(3 DOWNTO 2), SW(1 DOWNTO 0), M0);
H0: char_7seg PORT MAP (M0, HEX0);
...
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- - implements a 2-bit wide 4-to-1 multiplexer
ENTITY mux_2bit_4to1 IS
PORT ( S, U, V, W, X : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END mux_2bit_4to1;
ARCHITECTURE Behavior OF mux_2bit_4to1 IS
. . . code not shown
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY char_7seg IS
PORT ( C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Display : OUT STD_LOGIC_VECTOR(0 TO 6));
END char_7seg;
ARCHITECTURE Behavior OF char_7seg IS
. . . code not shown
END Behavior;
