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BQ25601D
SLUSDA2 – JULY 2018

BQ25601D I2C Controlled 3-A Single-Cell Battery Charger With USB Charger Detection for
High Input Voltage and Narrow Voltage DC (NVDC) Power Path Management
1 Features • High Accuracy
1• High-Efficiency, 1.5-MHz, Synchronous Switch- – ±0.5% Charge Voltage Regulation
Mode Buck Charger – ±5% at 1.5-A Charge Current Regulation
– 92% Charge Efficiency at 2 A from 5-V Input – ±10% at 0.9-A Input Current Regulation
– Optimized for USB Voltage Input (5 V) • Create a Custom Design Using the BQ25601D
– Selectable Low Power Pulse Frequency With the WEBENCH® Power Designer
Modulation (PFM) Mode for Light Load
Operations 2 Applications
• Supports USB On-The-Go (OTG) • Smart Phones
– Boost Converter With Up to 1.2-A Output • Portable Internet Devices and Accessory
– 92% Boost Efficiency at 1-A Output
– Accurate Constant Current (CC) Limit
3 Description
The BQ25601D device is a highly-integrated 3-A
– Soft-Start Up To 500-µF Capacitive Load switch-mode battery charge management and system
– Output Short Circuit Protection power path management device for single cell Li-Ion
– Selectable Low Power PFM Mode for Light and Li-polymer battery. The low impedance power
Load Operations path optimizes switch-mode operation efficiency,
reduces battery charging time and extends battery life
• Single Input to Support USB Input and High during discharging phase. The I2C serial interface
Voltage Adapters with charging and system settings makes the device
– Support 3.9-V to 13.5-V Input Voltage Range a truly flexible solution.
With 22-V Absolute Maximum Input Voltage
Rating Device Information(1)
– Programmable Input Current Limit (100 mA to PART NUMBER PACKAGE BODY SIZE (NOM)
3.2 A With 100-mA Resolution) to Support BQ25601D WQFN (24) 4.00 mm × 4.00 mm
USB 2.0, USB 3.0 Standards and High Voltage (1) For all available packages, see the orderable addendum at
Adaptors (IINDPM) the end of the data sheet.
– Maximum Power Tracking by Input Voltage
Simplified Application
Limit Up to 5.4 V (VINDPM)
– VINDPM Threshold Automatically Tracks
VBUS SW
Battery Voltage USB
D+/D-
– Auto Detect USB BC1.2, SDP, CDP, DCP and BTST
USB Detection
Non-Standard Adaptors SYS
• High Battery Discharge Efficiency With 19.5-mΩ I2C Bus BAT
Battery Discharge MOSFET Host ICHG +
• Narrow VDC (NVDC) Power Path Management Host Control
REGN
– Instant-On Works with No Battery or Deeply /QON
Discharged Battery TS
– Ideal Diode Operation in Battery Supplement
Optional
Mode
• BATFET Control to Support Ship Mode, Wake Up
and Full System Reset
• Flexible Autonomous and I2C Mode for Optimal
System Performance
• High Integration Includes All MOSFETs, Current
Sensing and Loop Compensation
• 17-µA Low Battery Leakage Current
1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 9.5 Protections .............................................................. 29
2 Applications ........................................................... 1 9.6 Programming........................................................... 30
3 Description ............................................................. 1 9.7 Register Maps ......................................................... 34
4 Revision History..................................................... 2 10 Application and Implementation........................ 46
10.1 Application information.......................................... 46
5 Description (continued)......................................... 3
10.2 Typical Application ................................................ 47
6 Device Comparison Table..................................... 4
11 Power Supply Recommendations ..................... 53
7 Pin Configuration and Functions ......................... 5
12 Layout................................................................... 54
8 Specifications......................................................... 7
12.1 Layout Guidelines ................................................. 54
8.1 Absolute Maximum Ratings ...................................... 7
12.2 Layout Example .................................................... 54
8.2 ESD Ratings.............................................................. 7
8.3 Recommended Operating Conditions....................... 7 13 Device and Documentation Support ................. 56
13.1 Device Support...................................................... 56
8.4 Thermal information .................................................. 8
13.2 Documentation Support ....................................... 56
8.5 Electrical Characteristics........................................... 8
13.3 Receiving Notification of Documentation Updates 56
8.6 Timing Requirements .............................................. 13
13.4 Community Resources.......................................... 56
8.7 Typical Characteristics ............................................ 14
13.5 Trademarks ........................................................... 56
9 Detailed Description ............................................ 16
13.6 Electrostatic Discharge Caution ............................ 56
9.1 Overview ................................................................. 16
13.7 Glossary ................................................................ 57
9.2 Functional Block Diagram ....................................... 17
9.3 Feature Description................................................. 18 14 Mechanical, Packaging, and Orderable
Information ........................................................... 58
9.4 Device Functional Modes........................................ 25

4 Revision History
DATE REVISION NOTES
July 2018 * Initial release.

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5 Description (continued)
The BQ25601D is a highly-integrated 3.0-A switch-mode battery charge management and system power path
management device for single cell Li-Ion and Li-polymer battery. It features fast charging with high input voltage
support for a wide range of smart phones, tablets and portable devices. Its low impedance power path optimizes
switch-mode operation efficiency, reduces battery charging time and extends battery life during discharging
phase. Its input voltage and current regulation deliver maximum charging power to battery. The solution is highly
integrated with input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side
switching FET (LSFET, Q3), and battery FET (BATFET, Q4) between system and battery. It also integrates the
bootstrap diode for the high-side gate drive for simplified system design. The I2C serial interface with charging
and system settings makes the device a truly flexible solution.
The device supports a wide range of input sources, including standard USB host port, USB charging port, and
USB compliant high voltage adapter. The device sets default input current limit based on the built-in USB
interface. To set the default input current limit, the device uses the built-in USB interface, or takes the result from
detection circuit in the system, such as USB PHY device. The device is compliant with USB 2.0 and USB 3.0
power spec with input current and voltage regulation. The device also meets USB On-the-Go (OTG) operation
power rating specification by supplying 5.15 V on VBUS with constant current limit up to 1.2A.
The power path management regulates the system slightly above battery voltage but does not drop below 3.5 V
minimum system voltage (programmable). With this feature, the system maintains operation even when the
battery is completely depleted or removed. When the input current limit or voltage limit is reached, the power
path management automatically reduces the charge current to zero. As the system load continues to increase,
the power path discharges the battery until the system power requirement is met. This Supplement Mode
prevents overloading the input source.
The device initiates and completes a charging cycle without software control. It senses the battery voltage and
charges the battery in three phases: pre-conditioning, constant current and constant voltage. At the end of the
charging cycle, the charger automatically terminates when the charge current is below a preset limit and the
battery voltage is higher than recharge threshold. If the fully charged battery falls below the recharge threshold,
the charger automatically starts another charging cycle.
The charger provides various safety features for battery charging and system operations, including battery
negative temperature coefficient thermistor monitoring, charging safety timer and overvoltage and overcurrent
protections. The thermal regulation reduces charge current when the junction temperature exceeds 110°C
(programmable). The STAT output reports the charging status and any fault conditions. Other safety features
include battery temperature sensing for charge and boost mode, thermal regulation and thermal shutdown and
input UVLO and overvoltage protection. The VBUS_GD bit indicates if a good power source is present. The INT
output Immediately notifies host when fault occurs.
The device also provides QON pin for BATFET enable and reset control to exit low power ship mode or full
system reset function.
The device is available in 24-pin, 4 mm × 4 mm x 0.75 mm thin WQFN package.

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6 Device Comparison Table

BQ25600(D) BQ25601(D) BQ25606

Number of Series Cells 1 1 1
Cell Chemistry Li-Ion/Li-Polymer Li-Ion/Li-Polymer Li-Ion/Li-Polymer
Operation Input Voltage Range (V) 3.9 - 13.5 3.9 - 13.5 3.9 - 13.5
Absolute Max Rating, VBUS (V) 22 22 22
Charge Voltage (V) 3.85 - 4.62 3.85 - 4.62 4.2/4.35/4.4
Charge Current ICHG (A) 3 3 3
Power Path Yes Yes Yes
Discharge Current Rating (A) 6 6 6
I2C / Standalone (I2C Address) I2C (6BH) I2C (6BH) Standalone
USB Detection BQ25600: PSEL; BQ25600D: D+/D- BQ25601: PSEL; BQ25601D: D+/D- D+/D-
BAT Remote Sense Yes No No
Termination Current (A) 60 - 780 60 - 780 5% of ICHG
Precharge Current (A) 60 -780 60 -780 5% of ICHG
Package WCSP30 - 2x2.4 QFN24 - 4x4 QFN24 - 4x4

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7 Pin Configuration and Functions

RTW Package
24-Pin WQFN
Top View

REGN

BTST
PMID
VAC

SW

SW
24

23

22
21
20

19
VBUS 1 18 GND

D+ 2 17 GND

D- 3 Thermal 16 SYS
Pad
STAT 4 15 SYS

SCL 5 14 BAT
SDA 6 13 BAT
7 8 9 10 11 12
INT

NC

CE
NC

TS

QON (Not to scale)

Pin Functions
Pin (1)
TYPE DESCRIPTION
NAME NO.
13 Battery connection point to the positive terminal of the battery pack. The internal BATFET and current sensing is
BAT P
14 connected between SYS and BAT. Connect a 10 µF close to the BAT pin.

PWM high side driver positive supply. Internally, the BTST pin is connected to the cathode of the boost-strap
BTST 21 P
diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
CE 9 DI Charge enable pin. When this pin is driven low, battery charging is enabled.
17
GND — Ground pins.
18
Open-drain interrupt Output. Connect the INT to a logic rail through 10-kΩ resistor. The INT pin sends an active
INT 7 DO
low, 256-µs pulse to host to report charger device status and fault.
8
NC — No Connect. Keep the pins float.
10
Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes
D– 3 AIO
data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard adaptors
Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Put 10 μF ceramic
PMID 23 DO
capacitor on PMID to GND.
Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data
D+ 2 AIO
contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard adaptors
BATFET enable/reset control input. When BATFET is in ship mode, a logic low of tSHIPMODE duration turns on
BATFET to exit shipping mode. When VBUS is not pluggeD–in, a logic low of tQON_RST (minimum 8 s) duration
QON 12 DI
resets SYS (system power) by turning BATFET off for tBATFET_RST (minimum 250 ms) and then re-enable BATFET
to provide full system power reset. The pin contains an internal pull-up to maintain default high logic.
LSFET driver and internal supply output. Internally, REGN is connected to the anode of the boost-strap diode.
REGN 22 P Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to GND. The capacitor should be placed close to the
IC.
SCL 5 DI I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA 6 DIO I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor.

(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P
= Power
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Pin Functions (continued)

Pin
TYPE (1) DESCRIPTION
NAME NO.
Open-drain charge status output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin indicates
charger status. Collect a current limit resister and a LED from a rail to this pin.
Charge in progress: LOW
STAT 4 DO
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response): 1-Hz, 50% duty cycle Pulses
This pin can be disabled via EN_ICHG_MON[1:0] register bits.
19
SW P Switching node output. Connected to output inductor. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
20
15 Converter output connection point. The internal current sensing network is connected between SYS and BAT.
SYS P
16 Connect a 20 µF capacitor close to the SYS pin.

Temperature qualification voltage input to support JEITA profile. Connect a negative temperature coefficient
thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when
TS 11 AI
TS pin is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and connect a 10-kΩ
resistor from TS to GND. It is recommended to use a 103AT-2 thermistor.
VAC 24 AI Charge input voltage sense. This pin must be connected to VBUS pin.
Charger input. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID
VBUS 1 P
pins. Place a 1-uF ceramic capacitor from VBUS to GND close to device.
Thermal pad and ground reference. This pad is ground reference for the device and it is also the thermal pad used
Thermal Pad — P to conduct heat from the device. This pad should be tied externally to a ground plane through PCB vias under the
pad.

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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Voltage Range (with respect to
VAC, VBUS (converter not switching) (2) –2 22 V
GND)
Voltage Range (with respect to
BTST, PMID (converter not switching) (2) –0.3 22 V
GND)
Voltage Range (with respect to
SW –2 16 V
GND)
Voltage Range (with respect to BTST to SW –0.3 7 V
GND)
Voltage Range (with respect to
D+, D– –0.3 7 V
GND)
Voltage Range (with respect to REGN, TS, CE, BAT, SYS (converter not switching) –0.3 7 V
GND)
Output Sink Current STAT 6 mA
Voltage Range (with respect to
SDA, SCL, INT, /QON, STAT –0.3 7 V
GND)
Voltage Range (with respect to
PGND to GND (QFN package only) –0.3 0.3 V
GND)
Output Sink Current INT 6 mA
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
(2) VBUS is specified up to 22 V for a maximum of one hour at room temperature

8.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins (1)
V(ESD) Electrostatic discharge Charged device model (CDM), per V
JEDEC specification JESD22-C101, all ±250
pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VBUS Input voltage 3.9 13.5 (1) V
Iin Input current (VBUS) 3.25 A
ISWOP Output current (SW) 3.25 A
VBATOP Battery voltage 4.615 V
IBATOP Fast charging current 3.0 A
IBATOP Discharging current (continuous) 6 A
TA Operating ambient temperature –40 85 °C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum voltage rating on either the BTST or SW pins. A
tight layout minimizes switching noise.

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8.4 Thermal information

BQ25601D
THERMAL METRIC (1) RTW (WQFN) UNIT
24 PinS
RθJA Junction-to-ambient thermal resistance 35.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 22.7 °C/W
RθJB Junction-to-board thermal resistance 11.9 °C/W
ΨJT Junction-to-top characterization parameter 0.2 °C/W
ΨJB Junction-to-board characterization parameter 12 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.6 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

8.5 Electrical Characteristics

VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
VBAT = 4.5 V, VBUS < VAC-UVLOZ,
Battery discharge current (BAT,
IBAT leakage between BAT and VBUS, 5 µA
SW, SYS) in buck mode
TJ< 85°C
VBAT = 4.5 V, HIZ Mode and
Battery discharge current (BAT) OVPFET_DIS = 1 or No VBUS, I2C
IBAT 17 33 µA
in buck mode disabled, BATFET Disabled. TJ <
85°C
VBAT = 4.5 V, HIZ Mode and
Battery discharge current (BAT, OVPFET_DIS = 1 or No VBUS, I2C
IBAT 58 85 µA
SW, SYS) Disabled, BATFET Enabled. TJ <
85°C
IVBUS_HIZ Input supply current (VBUS) in VVBUS = 5 V, High-Z Mode and 37 55 µA
buck mode OVPFET_DIS = 1, No battery
Input supply current (VBUS) in VVBUS = 12 V, High-Z Mode and
IVBUS_HIZ 68 93 µA
buck mode OVPFET_DIS = 1, No battery
Input supply current (VBUS) in VVBUS = 12 V, VVBUS > VVBAT,
IVBUS 1.5 3 mA
buck mode converter not switching
VVBUS > VUVLO, VVBUS > VVBAT,
Input supply current (VBUS) in
IVBUS converter switching, VBAT = 3.8V, 3 mA
buck mode
ISYS = 0A
Battery Discharge Current in VBAT = 4.2 V, boost mode, IVBUS = 0
IBOOST 3 mA
boost mode A, converter switching
VBUS, VAC AND BAT PIN POWER-UP
VBUS_OP VBUS operating range VVBUS rising 3.9 13.5 V
VBUS for active I2C, no battery V
VVAC_UVLOZ VVAC rising 3.3 3.6
Sense VAC pin voltage
VVAC_UVLOZ_HYS I2C active hysteresis VAC falling from above VVAC_UVLOZ 300 mV
One of the conditions to turn on V
VVAC_PRESENT VVAC rising 3.65 3.9
REGN
One of the conditions to turn on mV
VVAC_PRESENT_HYS VVAC falling 500
REGN
(VVAC–VVBAT ), VBUSMIN_FALL ≤ VBAT
VSLEEP Sleep mode falling threshold 15 60 131 mV
≤ VREG, VAC falling
(VVAC–VVBAT ), VBUSMIN_FALL ≤ VBAT
VSLEEPZ Sleep mode rising threshold 115 220 340 mV
≤ VREG, VAC rising
VAC 6.5-V Overvoltage rising
VVAC_OV_RISE VAC rising; OVP (REG06[7:6]) = '01' 6.1 6.4 6.7 V
threshold

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Electrical Characteristics (continued)

VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VAC 10.5-V Overvoltage rising
VVAC_OV_RISE VAC rising, OVP (REG06[7:6]) = '10' 10.35 10.9 11.5 V
threshold
VAC 14-V Overvoltage rising
VVAC_OV_RISE VAC rising, OVP (REG06[7:6]) = '11' 13.5 14.2 14.85 V
threshold
VAC 6.5-V Overvoltage VAC falling, OVP (REG06[7:6]) =
VVAC_OV_HYS 320 mV
hysteresis '01'
VAC 10.5-V Overvoltage VAC falling, OVP (REG06[7:6]) =
VVAC_OV_HYS 250 mV
hysteresis '10'
VAC falling, OVP (REG06[7:6]) =
VVAC_OV_HYS VAC 14-V Overvoltage hysteresis 300 mV
'11'
2
VBAT_UVLOZ BAT for active I C, no adapter VBAT rising 2.5 V
VBAT_DPL_FALL Battery Depletion Threshold VBAT falling 2.2 2.6 V
VBAT_DPL_RISE Battery Depletion Threshold VBAT rising 2.34 2.86 V
Battery Depletion rising
VBAT_DPL_HYST VBAT rising 180 mV
hysteresis
Bad adapter detection falling
VBUSMIN_FALL VBUS falling 3.75 3.9 4.0 V
threshold
VBUSMIN_HYST Bad adapter detection hysteresis 80 mV
Bad adapter detection current
IBADSRC Sink current from VBUS to GND 30 mA
source
POWER-PATH
VVBAT < SYS_MIN[2:0] = 101,
VSYS_MIN System regulation voltage 3.5 3.68 V
BATFET Disabled (REG07[5] = 1)
ISYS = 0 A, VVBAT > VSYSMIN, VVBAT
VBAT +
VSYS System Regulation Voltage = 4.400 V, BATFET disabled V
50 mV
(REG07[5] = 1)
Maximum DC system voltage ISYS = 0 A, , Q4 off, VVBAT≤ 4.400 V,
VSYS_MAX 4.4 4.45 4.48 V
output VVBAT > VSYSMIN = 3.5V
Top reverse blocking MOSFET
RON(RBFET) on-resistance between VBUS and -40°C≤ TA ≤ 125°C 45 mΩ
PMID - Q1
Top switching MOSFET on-
RON(HSFET) resistance between PMID and VREGN = 5 V , -40°C≤ TA ≤ 125°C 62 mΩ
SW - Q2
Bottom switching MOSFET on-
RON(LSFET) resistance between SW and GND VREGN = 5 V , -40°C≤ TA ≤ 125°C 71 mΩ
- Q3
BATFET forward voltage in
VFWD 30 mV
supplement mode
QFN package, Measured from BAT
RON(BAT-SYS) SYS-BAT MOSFET on-resistance 19.5 24 mΩ
to SYS, VBAT = 4.2V, TJ = 25°C
QFN package, Measured from BAT
RON(BAT-SYS) SYS-BAT MOSFET on-resistance to SYS, VBAT = 4.2V, TJ = –40 - 19.5 30 mΩ
125°C
BATTERY CHARGER
VBATREG_RANGE Charge voltage program range 3.847 4.615 V
VBATREG_STEP Charge voltage step 32 mV
VREG (REG04[7:3]) = 4.20 V
4.178 4.200 4.220
(01011), V, –40 ≤ TJ ≤ 85°C
VREG (REG04[7:3]) = 4.343 V
VBATREG Charge voltage setting 4.321 4.343 4.365 V
(01111), V, –40 ≤ TJ ≤ 85°C
VREG (REG04[7:3]) = 4.391 V
4.373 4.391 4.407 V
(10001), V, –40 ≤ TJ ≤ 85°C

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Electrical Characteristics (continued)

VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICHG_REG_RANGE Charge current regulation range 0 3000 mA
ICHG_REG_STEP Charge current regulation step 60 mA
ICHG = 240 mA, VVBAT = 3.1V or
ICHG_REG Charge current regulation setting 0.216 0.24 0.264 A
VVBAT = 3.8 V
Charge current regulation ICHG = 240 mA, VVBAT = 3.1 V or
ICHG_REG_ACC –10% 10%
accuracy VVBAT = 3.8 V
ICHG_REG Charge current regulation setting ICHG = 720 mA, VVBAT = 3.1 V or 0.685 0.720 0.761 A
VVBAT = 3.8 V
Charge current regulation ICHG_REG = 720 mA, VBAT = 3.1 V or
ICHG_REG -5% 6%
accuracy VBAT = 3.8 V
ICHG = 1.38 A, VVBAT = 3.1 V or
ICHG_REG Charge current regulation setting 1.311 1.380 1.449 A
VVBAT = 3.8 V
Charge current regulation ICHG = 720 mA or ICHG = 1.38 A,
ICHG_REG_ACC –5% 5%
accuracy VVBAT = 3.1 V or VVBAT = 3.8 V
VBATLOWV_FALL Battery LOWV falling threshold ICHG = 240 mA 2.7 2.8 2.9 V
VBATLOWV_RISE Battery LOWV rising threshold Pre-charge to fast charge 3.0 3.12 3.24 V
IPRECHG Precharge current regulation IPRECHG[3:0] = '0010' = 180 mA 153 171 189 mA
Precharge current regulation
IPRECHG_ACC IPRECHG[3:0] = '0010' = 180 mA –15% 5%
accuracy
ITERM Termination current regulation ICHG > 780 mA, ITERM[3:0] = '0010' 150 180 216
mA
= 180 mA, VVBAT = 4.208 V
Termination current regulation ICHG > 780 mA, , ITERM[3:0] =
ITERM_ACC -16.7% 20%
accuracy '0010' = 180 mA, VVBAT = 4.208 V
ICHG ≤ 780 mA, , ITERM[3:0] =
ITERM Termination current regulation 162 180 192 mA
'0010' = 180 mA
Termination current regulation ICHG ≤ 780 mA, , ITERM[3:0] =
ITERM_ACC -10% 10%
accuracy '0010' = 180 mA
ITERM Termination current regulation ICHG = 600 mA, ITERM[3:0] = '0000' 45 60 85
mA
= 60 mA, VVBAT = 4.208 V
Termination current regulation ICHG = 600 mA, ITERM[3:0] = '0000'
ITERM_ACC -25% 42%
accuracy = 60 mA, VVBAT = 4.208 V
VSHORT Battery short voltage VVBAT falling 1.85 2 2.15 V
VSHORTZ Battery short voltage VVBAT rising 2.15 2.25 2.35 V
ISHORT Battery short current VVBAT < VSHORTZ 70 90 110 mA
Recharge Threshold below
VRECHG VBAT falling, REG04[0] = 0 90 120 150 mV
VBAT_REG
Recharge Threshold below
VRECHG VBAT falling, REG04[0] = 1 200 230 265 mV
VBAT_REG
ISYSLOAD System discharge load current VSYS = 4.2 V 30 mA
INPUT VOLTAGE AND CURRENT REGULATION
VINDPM Input voltage regulation limit VINDPM (REG06[3:0] = 0000) = 3.9 V 3.78 3.95 4.1 V
VINDPM_ACC Input voltage regulation accuracy –3% 5%
VINDPM Input voltage regulation limit VINDPM (REG06[3:0] = 0110) = 4.4 V 4.268 4.4 4.532 V
VINDPM_ACC Input voltage regulation accuracy –3% 3%
VDPM_VBAT Input voltage regulation limit VINDPM = 3.9V, 4.171 4.3 4.43
tracking VBAT VDPM_VBAT_TRACK = 300mV, V
VBAT = 4.0V
VDPM_VBAT_ACC Input voltage regulation accuracy –3% 3%
tracking VBAT

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Electrical Characteristics (continued)

VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VVBUS = 5 V, current pulled from
SW, IINDPM (REG[4:0] = 00100) = 450 500 mA
500 mA, –40 ≤ TJ ≤ 85°C
VVBUS = 5 V, current pulled from
IINDPM USB input current regulation limit SW, IINDPM (REG[4:0] = 01000) = 750 900 mA
900 mA, –40 ≤ TJ ≤ 85°C
VVBUS = 5 V, current pulled from
SW, IINDPM (REG[4:0] = 01110) = 1.3 1.5 A
1.5 A, –40 ≤ TJ ≤ 85°C
Input current limit during system
IIN_START 200 mA
start-up sequence
BAT PIN OVERVOLTAGE PROTECTION
VBAT rising, as percentage of
VBATOVP_RISE Battery overvoltage threshold 103% 104% 105%
VBAT_REG
VBAT falling, as percentage of
VBATOVP_FALL Battery overvoltage threshold 101% 102% 103%
VBAT_REG
THERMAL REGULATION AND THERMAL SHUTDOWN
Junction Temperature Regulation Temperature Increasing, TREG
TJUNCTION_REG 110 °C
Threshold (REG05[1] = 1) = 110℃
TJUNCTION_REG Junction Temperature Regulation Temperature Increasing, TREG 90 °C
Threshold (REG05[1] = 0) = 90℃
Thermal Shutdown Rising
TSHUT Temperature Increasing 160 °C
Temperature
TSHUT_HYST Thermal Shutdown Hysteresis 30 °C
JEITA Thermistor Comparator (BUCK MODE)
T1 (0°C) threshold, Charge
Charger suspends charge. As
VT1 suspended T1 below this 72.4% 73.3% 74.2%
Percentage to VREGN
temperature.
VT1 Falling As Percentage to VREGN 69% 71.5% 74%
T2 (10°C) threshold, Charge back
VT2 to ICHG/2 and 4.2 V below this As percentage of VREGN 67.2% 68% 69%
temperature
VT2 Falling As Percentage to VREGN 66% 66.8% 67.7%
T3 (45°C) threshold, charge back
Charger suspends charge. As
VT3 to ICHG and 4.05V above this 43.8% 44.7% 45.8%
Percentage to VREGN
temperature.
VT3 Falling As Percentage to VREGN 45.1% 45.7% 46.3%
T5 (60°C) threshold, charge
VT5 suspended above this As Percentage to VREGN 33.7% 34.2% 35.1%
temperature.
VT5 Falling As Percentage to VREGN 34.5% 35.3% 36.3%
COLD OR HOT THERMISTER COMPARATOR (BOOST MODE)
As Percentage to VREGN (Approx.
Cold Temperature Threshold, TS
VBCOLD -20°C w/ 103AT), TJ = –20°C - 79.5% 80% 80.5%
pin Voltage Rising Threshold
125°C
VBCOLD Falling TJ = –20°C - 125°C 78.3% 79% 79.7%
Hot Temperature Threshold, TS As Percentage to VREGN (Approx.
VBHOT 30.2% 31.2% 32.2%
pin Voltage falling Threshold 60°C w/ 103AT), TJ = –20°C - 125°C
VBHOT Rising TJ = –20°C - 125°C 33.8% 34.4% 34.9%

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Electrical Characteristics (continued)

VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
HSFET cycle-by-cycle over-
IHSFET_OCP 5.2 8.0 A
current threshold
IBATFET_OCP System over load threshold 6.0 A
PWM
Oscillator frequency, buck mode 1320 1500 1680 kHz
fSW PWM switching frequency
Oscillator frequency, boost mode 1150 1412 1660 kHz
DMAX Maximum PWM duty cycle (1) 97%
BOOST MODE OPERATION
VVBAT = 3.8 V, I(PMID) = 0 A,
VOTG_REG Boost mode regulation voltage 4.97 5.126 5.280 V
BOOSTV[1:0] = '10' = 5.15 V
Boost mode regulation voltage VVBAT = 3.8 V, I(PMID) = 0 A,
VOTG_REG_ACC -3% 3%
accuracy BOOSTV[1:0] = '10' = 5.15 V
VVBAT falling, MIN_VBAT_SEL
2.6 2.8 2.93 V
(REG01[0]) = 0
VVBAT rising, MIN_VBAT_SEL 2.9 3.0 3.15 V
Battery voltage exiting boost (REG01[0]) = 0
VBATLOWV_OTG
mode VVBAT falling, MIN_VBAT_SEL 2.38 2.5 2.6 V
(REG01[0]) = 1
VVBAT rising, MIN_VBAT_SEL 2.7 2.8 2.93 V
(REG01[0]) = 1
IOTG OTG mode output current BOOST_LIM (REG02[7]) = 1 1.2 1.4 1.6 A
Boost mode RBFET over-current
IOTG_OCP_ACC BOOST_LIM = 0.5 A (REG02[7] = 0) 0.5 0.722 A
protection accuracy
VOTG_OVP OTG overvoltage threshold Rising threshold 5.55 5.8 6.15 V
REGN LDO
VREGN REGN LDO output voltage VVBUS = 9V, IREGN = 40mA 5.6 6 6.55 V
VREGN REGN LDO output voltage VVBUS = 5V, IREGN = 20mA 4.6 4.7 4.8 V
LOGIC I/O PIN CHARACTERISTICS (CE, INT, STAT)
VILO Input low threshold 0.4 V
VIH Input high threshold 1.3 V
IBIAS High-level leakage current Pull up rail 1.8 V 1 µA
I2C Interface (SCL, SDA)
VIH Input high threshold level Pull up rail 1.8 V 1.3 V
VIL Input t low threshold level Pull up rail 1.8 V 0.4 V
VOL Output low threshold level Sink current = 5 mA, 0.4 V

(1) Specified by design. Not production tested.

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8.6 Timing Requirements

MIN NOM MAX UNIT
VBUS/BAT POWER UP
VAC rising above ACOV threshold to
tACOV VAC OVP reaction time 200 ns
turn off Q2
tBADSRC Bad adapter detection duration 30 ms
BATTERY CHARGER
tTERM_DGL Deglitch time for charge termination 250 ms
tRECHG_DGL Deglitch time for recharge 250 ms
System over-current deglitch time to
tSYSOVLD_DGL 100 µs
turn off Q4
Battery over-voltage deglitch time to
tBATOVP 1 µs
disable charge
tSAFETY Typical Charge Safety Timer Range CHG_TIMER = 1 8 10 12 hr
tTOP_OFF Typical Top-Off Timer Range TOP_OFF_TIMER[1:0] = 10 (30 min) 24 30 36 min
QON TIMING
/QON low time to turn on BATFET and
tSHIPMODE –10℃ ≤ TJ ≤ 60℃ 0.9 1.3 s
exit ship mode
tQON_RST_2 QON low time to reset BATFET –10℃ ≤ TJ ≤ 60℃ 8 12 s
BATFET off time during full system
tBATFET_RST –10℃ ≤ TJ ≤ 60℃ 250 400 ms
reset
tSM_DLY Enter ship mode delay –10℃ ≤ TJ ≤ 60℃ 10 15 s
DIGITAL CLOCK AND WATCHDOG TIMER
tWDT REG05[4]=1 REGN LDO disabled 40 s
fLPDIG Digital Low Power Clock REGN LDO disabled 30 kHz
fDIG Digital Clock REGN LDO enabled 500 kHz
fSCL SCL clock frequency 400 kHz

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8.7 Typical Characteristics

100 100

95 95

90
Charge Efficiency (%)

90

Efficiency (%)
85
85
80
80
75
75
70 VBUS Voltage
5V VBAT = 3.2 V
65 9V 70 VBAT = 3.8 V
12 V VBAT = 4.1 V
60 65
0 0.5 1 1.5 2 2.5 3 0.2 0.4 0.6 0.8 1 1.2 1.4
Charge Current (A) D001
OTG Current (A) D001
fSW = 1.5 MHz inductor DCR = 18 mΩ VOTG = 5.15 V inductor DCR = 18 mΩ
VBAT=3.8V

Figure 1. Charge Efficiency vs. Charge Current Figure 2. Efficiency vs. OTG Current
6 6

5 Charge Current Accuracy (%) 4

OTG Output Voltage (V)

2
4
0
3
-2
2
-4

1 -6

0 -8
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
Output Current (A) D001
Charge Current (A) D001
IOTG = 1.2 A VOTG = 5.15 V
VVBAT = 3.8 V

Figure 3. OTG Output Voltage vs. Output Current Figure 4. Charge Current Accuracy
3.85 4.5
VBATREG = 4.208 V
3.8 VBATREG = 4.352 V
BATREG Charge Voltage (V)

4.4
SYSMIN Voltage (V)

3.75

4.3
3.7

3.65
4.2

3.6
4.1
3.55

3.5 4
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C) D001
Junction Temperature (°C) D001

Figure 5. SYSMIN Voltage vs. Junction Temperature Figure 6. BATREG Charge Voltage vs. Junction
Temperature

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Typical Characteristics (continued)

2.5 2
IINDPM = 0.5 A ICHG = 0.24 A
2.25 IINDPM = 0.9 A 1.8 ICHG = 0.72 A
2 IINDPM = 1.5 A 1.6 ICHG = 1.38 A
Input Current Limit (A)

Charge Current (A)

1.75 1.4
1.5 1.2
1.25 1
1 0.8
0.75 0.6
0.5 0.4
0.25 0.2
0 0
-40 -25 -10 5 20 35 50 65 80 95 -40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C) D001
Junction Temperature (°C) D001

Figure 7. Input Current Limit vs. Junction Temperature Figure 8. Charge Current vs. Junction Temperature
2.25

1.75
Charge Current (A)

1.5

1.25

0.75

0.5

0.25 110 °C
90 °C
0
55 65 75 85 95 105 115 125 135
Junction Temperature (°C) D001

Figure 9. Charge Current vs. Junction Temperature

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9 Detailed Description

9.1 Overview
The BQ25601D device is a highly integrated 3.0-A switch-mode battery charger for single cell Li-Ion and Li-
polymer battery. It includes the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2),
low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side gate
drive.

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9.2 Functional Block Diagram

VBUS PMID
VVVAC_PRESENT RBFET (Q1)
+ UVLO
VVAC
IIN ± Q1 Gate
VBAT + VSLEEP Control
+ SLEEP EN_REGN REGN
VVAC
± REGN
EN_HIZ LDO
VVAC
+ ACOV
VVAC_OV
±
FBO BTST

VVBUS
VAC + VBUS_OVP_BOOST
VAC VOTG_OVP
±
IQ2
+ Q2_UCP_BOOST
VOTG_HSZCP
VVBUS ±
± HSFET (Q2)
VINDPM IQ3
+ Q3_OCP_BOOST SW
+
VOTG_BAT
IIN ± CONVERTER
+ REGN
Control
IINDPM BAT
± + BATOVP
IC TJ 104% × V BAT_REG LSFET (Q3) PGND
+ ±
TREG BATSNS ILSFET_UCP IQ2
± + + UCP Q2_OCP +
SYS IQ3 IHSFET_OCP
VBAT_REG
± ± ± ±
VSYSMIN VBTST - VSW
ICHG EN_HIZ
+ + REFRESH +
EN_CHARGE VBTST_REFRESH
ICHG_REG
± EN_BOOST ±
SYS

ICHG
VBAT_REG
ICHG_REG Q4 Gate BATFET
Control (Q4)
IBADSRC BAT
REF BAD_SRC +
DAC IDC
Converter ±
Control State IC TJ
Machine TSHUT +
TSHUT
±
BATSNS
D+ BAT_GD +
VQON
Input VBATGD
Source ±
'Å Detection USB
Adapter VREG -VRECHG
RECHRG +
BAT SNS
± QON
INT ICHG
TERMINATION +
ITERM
±
CHARGE VBATLOWV
STAT CONTROL BATLOWV +
STATE BAT SNS
MACHINE ± BQ25601D
VSHORT
BATSHORT +
I2C BAT SNS
Interface ± Battery
SUSPEND
Temperature TS
Sensing

SCL SDA CE

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9.3 Feature Description

9.3.1 Power-On-Reset (POR)
The device powers internal bias circuits from the higher voltage of VBUS and BAT. When VBUS rises above
VVBUS_UVLOZ or BAT rises above VBAT_UVLOZ , the sleep comparator, battery depletion comparator and BATFET
driver are active. I2C interface is ready for communication and all the registers are reset to default value. The
host can access all the registers after POR.

9.3.2 Device Power Up from Battery without Input Source

If only battery is present and the voltage is above depletion threshold (VBAT_DPL_RISE), the BATFET turns on and
connects battery to system. The REGN stays off to minimize the quiescent current. The low RDSON of BATFET
and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
The device always monitors the discharge current through BATFET (Supplement Mode). When the system is
overloaded or shorted (IBAT > IBATFET_OCP), the device turns off BATFET immediately and set BATFET_DIS bit to
indicate BATFET is disabled until the input source plugs in again or one of the methods described in BATFET
Enable (Exit Shipping Mode) is applied to re-enable BATFET.

9.3.3 Power Up from Input Source

When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the
bias circuits. It detects and sets the input current limit before the buck converter is started. The power up
sequence from input source is as listed:
1. Power Up REGN LDO
2. Poor Source Qualification
3. Input Source Type Detection is based on D+/D– to set default input current limit (IINDPM) register or input
source type.
4. Input Voltage Limit Threshold Setting (VINDPM threshold)
5. Converter Power-up

9.3.3.1 Power Up REGN Regulation

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The REGN also
provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The
REGN is enabled when all the below conditions are valid:
• VVAC above VVAC_PRESENT
• VVAC above VBAT + VSLEEPZ in buck mode or VBUS below VBAT + VSLEEP in boost mode
• After 220-ms delay is completed
If any one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off.
The device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when
the device is in HIZ.

9.3.3.2 Poor Source Qualification

After REGN LDO powers up, the device confirms the current capability of the input source. The input source
must meet both of the following requirements in order to start the buck converter.
• VBUS voltage below VVAC_OV
• VBUS voltage above VVBUSMIN when pulling IBADSRC (typical 30 mA)
Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT
pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source qualification
every 2 seconds.

9.3.3.3 Input Source Type Detection

After the VBUS_GD bit is set and REGN LDO is powered, the device runs input source detection through D+/D–
lines. The BQ25601D follows the USB Battery Charging Specification 1.2 (BC1.2) to detect input source (SDP/
DCP) and non-standard adapter through USB D+/D– lines.

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Feature Description (continued)

After input source type detection is completed, an INT pulse is asserted to the host. in addition, the following
registers and pin are changed:
1. Input Current Limit (IINDPM) register is changed to set current limit
2. PG_STAT bit is set
3. VBUS_STAT bit is updated to indicate USB or other input source
The host can over-write IINDPM register to change the input current limit if needed. The charger input current is
always limited by the IINDPM register.

9.3.3.3.1 D+/D– Detection Sets Input Current Limit in BQ25601D

The BQ25601D contains a D+/D– based input source detection to set the input current limit at VBUS plug-in. The
D+/D– detection includes standard USB BC1.2 and non-standard adapter. When input source is plugged in, the
device starts standard USB BC1.2 detections. The USB BC1.2 is capable to identify Standard Downstream Port
(SDP) and Dedicated Charging Port (DCP). When the Data Contact Detection (DCD) timer expires, the non-
standard adapter detection is applied to set the input current limit. The non-standard detection is used to
distinguish vendor specific adapters (Apple and Samsung) based on their unique dividers on the D+/D– pins. If
an adapter is detected as DCP, the input current limit is set at 2.4 A. If an adapter is detected as unknown, the
input current limit is set at 0.5 A.

Table 1. Non-Standard Adapter Detection

NON-STANDARD
D+ THRESHOLD D– THRESHOLD INPUT CURRENT LIMIT (A)
ADAPTER
Divider 1 VD+ within V2P7_VTH VD– within V2P0_VTH 2.1
Divider 2 VD+ within V1P2_VTH VD– within V1P2_VTH 2
Divider 3 VD+ within V2P0_VTH VD– within V2P7_VTH 1
Divider 4 VD+ within V2P7_VTH VD– within V2P7_VTH 2.4

Table 2. Input Current Limit Setting from D+/D– Detection

D+/D– DETECTION INPUT CURRENT LIMIT (IINLIM)
USB SDP (USB500) 500 mA
USB DCP 2.4 A
Divider 3 1A
Divider 1 2.1 A
Divider 4 2.4 A
Divider 2 2A
Unknown 5-V Adapter

9.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)

The device supports wide range of input voltage limit (3.9 V – 5.4V) for USBThe device's VINDPM is set at 4.5V.
The device supports dynamic VINDPM trackingsettings which tracks the battery voltage. This function can be
enabled via the VDPM_BAT_TRACK[1:0] register bits. When enabled, the actual input voltage limit will be the
higher of the VINDPM register and VBAT + VDPM_BAT_TRACK offset.

9.3.3.5 Converter Power-Up

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery
charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.
The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input
current is limited to is to the lower of 200 mA or IINDPM register setting. After the system rises above 2.2 V, the
device limits input current to the value set by IINDPM register.
As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed
frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery
voltage, charge current and temperature, simplifying output filter design.
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The device switches to PFM control at light load or when battery is below minimum system voltage setting or
charging is disabled. The PFM_DIS bit can be used to prevent PFM operation in either buck or boost
configuration.

9.3.4 Boost Mode Operation From Battery

The device supports boost converter operation to deliver power from the battery to other portable devices
through USB port. The boost mode output current rating meets the USB On-The-Go 500 mA output requirement.
The maximum output current is up to 1.2 A. The boost operation can be enabled if the conditions are valid:
1. BAT above VOTG_BAT
2. VBUS less than BAT+VSLEEP (in sleep mode)
3. Boost mode operation is enabled (OTG_CONFIG bit = 1)
4. Voltage at TS (thermistor) pin is within acceptable range (VBHOT < VTS < VBCOLD)
5. After 30-ms delay from boost mode enable
During boost mode, the status register VBUS_STAT bits is set to 111, the VBUS output is 5.15 V and the output
current can reach up to 1.2 A, selected through I2C (BOOST_LIM bit). The boost output is maintained when BAT
is above VOTG_BAT threshold.
When OTG is enabled, the device starts up with PFM and later transits to PWM to minimize the overshoot. The
PFM_DIS bit can be used to prevent PFM operation in either buck or boost configuration.

9.3.5 Host Mode and Standalone Power Management

9.3.5.1 Host Mode and Default Mode in BQ25601D

The BQ25601D is a host controlled charger, but it can operate in default mode without host management. in
default mode, the device can be used as an autonomous charger with no host or while host is in sleep mode.
When the charger is in default mode, WATCHDOG_FAULT bit is HIGH. When the charger is in host mode,
WATCHDOG_FAULT bit is LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the
registers are in the default settings.
in default mode, the device keeps charging the battery with default 10-hour fast charging safety timer. At the end
of the 10-hour, the charging is stopped and the buck converter continues to operate to supply system load.
Writing a 1 to the WD_RST bit transitions the charger from default mode to host mode. All the device parameters
can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by
writing 1 to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog
timer by setting WATCHDOG bits = 00.
When the watchdog timer expires (WATCHDOG_FAULT bit = 1), the device returns to default mode and all
registers are reset to default values except IINDPM, VINDPM, BATFET_RST_EN, BATFET_DLY, and
BATFET_DIS bits.

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POR
watchdog timer expired
Reset registers
I2C interface enabled

Y Host Mode
I2C Write? Start watchdog timer
Host programs registers

Default Mode Y
Reset watchdog timer WD_RST bit = 1?
Reset selective registers

N Y
I2C Write? Y N
Watchdog Timer
Expired?

Figure 10. Watchdog Timer Flow Chart

9.3.6 Power Path Management

The device accommodates a wide range of input sources from USB, wall adapter, to car charger. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.

9.3.7 Battery Charging Management

The device charges 1-cell Li-Ion battery with up to 3.0-A charge current for high capacity tablet battery. The 19.5-
mΩ BATFET improves charging efficiency and minimize the voltage drop during discharging.

9.3.7.1 Autonomous Charging Cycle

With battery charging is enabled (CHG_CONFIG bit = 1 and CE pin is LOW), the device autonomously
completes a charging cycle without host involvement. The device default charging parameters are listed in
Table 3. The host can always control the charging operations and optimize the charging parameters by writing to
the corresponding registers through I2C.

Table 3. Charging Parameter Default Setting

DEFAULT MODE BQ25601D
Charging voltage 4.208V
Charging current 2.048 A
Pre-charge current 180 mA
Termination current 180 mA
Temperature profile JEITA
Safety timer 10 hours

A new charge cycle starts when the following conditions are valid:
• Converter starts
• Battery charging is enabled (CHG_CONFIG bit = 1 and ICHG register is not 0 mA and CE is low)
• No thermistor fault on TS
• No safety timer fault
• BATFET is not forced to turn off (BATFET_DIS bit = 0)

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The charger device automatically terminates the charging cycle when the charging current is below termination
threshold, battery voltage is above recharge threshold, and device not is in DPM mode or thermal regulation.
When a fully charged battery is discharged below recharge threshold (selectable through VRECHG bit), the
device automatically starts a new charging cycle. After the charge is done, toggle CE pin or CHG_CONFIG bit
can initiate a new charging cycle.
The STAT output indicates the charging status: charging (LOW), charging complete or charge disable (HIGH) or
charging fault (Blinking). The STAT output can be disabled by setting EN_ICHG_MON bits = 11. in addition, the
status register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast
charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is completed, an
INT is asserted to notify the host.

9.3.7.2 Battery Charging Profile

The device charges the battery in five phases: battery short, preconditioning, constant current, constant voltage
and top-off trickle charging (optional). At the beginning of a charging cycle, the device checks the battery voltage
and regulates current and voltage accordingly.

Table 4. Charging Current Setting

REGISTER DEFAULT
VBAT CHARGING CURRENT CHRG_STAT
SETTING
< 2.2 V ISHORT 100 mA 01
2.2 V to 3 V IPRECHG 180 mA 01
>3V ICHG 2.048 A 10

If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will
be less than the programmed value. in this case, termination is temporarily disabled and the charging safety
timer is counted at half the clock rate.

Regulation Voltage
VREG[7:3]
Battery Voltage
Charge Current
ICHG[5:0]

Charge Current

VBATLOWV (3 V)

VSHORTZ (2.2 V)

IPRECHG[7:4]
ITERM[3:0]
ISHORT

Trickle Charge Pre-charge Fast Charge and Voltage Regulation

Top-off Timer Safety Timer
(optional) Expiration

Figure 11. Battery Charging Profile

9.3.7.3 Charging Termination

The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps
running to power the system, and BATFET can turn on again to engage Supplement Mode.

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When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host.
Termination is temporarily disabled when the charger device is in input current, voltage or thermal regulation.
Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.
At low termination currents (25 mA-50 mA), due to the comparator offset, the actual termination current may be
10 mA-20 mA higher than the termination target. in order to compensate for comparator offset, a programmable
top-off timer can be applied after termination is detected. The termination timer will follow safety timer
constraints, such that if safety timer is suspended, so will the termination timer. Similarly, if safety timer is
doubled, so will the termination timer. TOPOFF_ACTIVE bit reports whether the top off timer is active or not. The
host can read CHRG_STAT and TOPOFF_ACTIVE to find out the termination status.
Top off timer gets reset at one of the following conditions:
1. Charge disable to enable
2. Termination status low to high
3. REG_RST register bit is set
The top-off timer settings are read in once termination is detected by the charger. Programming a top-off timer
value after termination will have no effect unless a recharge cycle is initiated. An INT is asserted to the host
when entering top-off timer segment as well as when top-off timer expires.

9.3.7.4 Thermistor Qualification

The charger device provides a single thermistor input for battery temperature monitor.

9.3.7.5 JEITA Guideline Compliance During Charging Mode

To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline
emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high
temperature ranges.
To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds
the T1-T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5
range.
At cool temperature (T1-T2), JEITA recommends the charge current to be reduced to half of the charge current
or lower. At warm temperature (T3-T5), JEITA recommends charge voltage less than 4.1 V.
The charger provides flexible voltage/current settings beyond the JEITA requirement. The voltage setting at
warm temperature (T3-T5) can be VREG or 4.1V (configured by JEITA_VSET). The current setting at cool
temperature (T1-T2) can be further reduced to 20% of fast charge current (JEITA_ISET).

100 VBATREG JEITA_VSET = 1

90 4.1V JEITA_VSET = 0

80
Charging Voltage (V)
Charging Current (%)

70
60 JEITA_ISET= 0
50

40
30 JEITA_ISET= 1
20

10 0
T1 T2 T3 T5
0 ±5 0 5 10 15 20 25 30 35 40 45 50 55 60 65
T1 T2 T3 T5
Battery Thermistor Temperature (°C)
±5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
Battery Thermistor Temperature (°C)

Figure 12. JEITA Profile: Charging Current Figure 13. JEITA Profile: Charging Voltage

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Equation 1 through Equation 2 describe updates to the resistor bias network.

æ 1 1 ö
VREGN ´ RTHCOLD ´ RTHHOT ´ ç - ÷
RT2 = è VT1 VT5 ø
æ VREGN ö æ VREGN ö
RTHHOT ´ ç - 1÷ - RTHCOLD ´ ç - 1÷
è VT5 ø è VT1 ø (1)
æ æ VREGN ö ö
çç ÷ - 1÷
RT1 = èè VT1 ø ø
æ 1 ö æ 1 ö
ç RT2 ÷ + ç RTH ÷
è ø è COLD ø (2)
Select 0°C to 60°C range for Li-ion or Li-polymer battery:
• RTHCOLD = 27.28 KΩ
• RTHHOT = 3.02 KΩ
• RT1 = 5.23 KΩ
• RT2 = 30.9 KΩ

9.3.7.6 Boost Mode Thermistor Monitor during Battery Discharge Mode

For battery protection during boost mode, the device monitors the battery temperature to be within the VBCOLD
to VBHOTthresholds. When temperature is outside of the temperature thresholds, the boost mode is suspended.
In additional, VBUS_STAT bits are set to 000 and NTC_FAULT is reported. Once temperature returns within
thresholds, the boost mode is recovered and NTC_FAULT is cleared.
Temperature Range to Boost
VREGN

Boost Disabled
VBCOLD
(±10°C)

Boost Enabled
VBHOT
(65°C)

Boost Disabled
AGND

Figure 14. TS Pin Thermistor Sense Threshold in Boost Mode

9.3.7.7 Charging Safety Timer

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The
safety timer is 2 hours when the battery is below VBATLOWV threshold and 10 hours when the battery is higher
than VBATLOWV threshold.
The user can program fast charge safety timer through I2C (CHG_TIMER bits). When safety timer expires, the
fault register CHRG_FAULT bits are set to 11 and an INT is asserted to the host. The safety timer feature can be
disabled through I2C by setting EN_TIMER bit
During input voltage, current, JEITA cool or thermal regulation, the safety timer counts at half clock rate as the
actual charge current is likely to be below the register setting. For example, if the charger is in input current
regulation (IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to 5 hours, the
safety timer will expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.
During the fault, timer is suspended. Once the fault goes away, fault resumes. If user stops the current charging
cycle, and start again, timer gets reset (toggle CE pin or CHRG_CONFIG bit).

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9.4 Device Functional Modes

9.4.1 Narrow VDC Architecture
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The
minimum system voltage is set by SYS_Min bits. Even with a fully depleted battery, the system is regulated
above the minimum system voltage.
When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),
and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage rises
above the minimum system voltage, BATFET is fully on and the voltage difference between the system and
battery is the VDS of BATFET.
When the battery charging is disabled and above minimum system voltage setting or charging is terminated, the
system is always regulated at typically 50mV above battery voltage. The status register VSYS_STAT bit goes
high when the system is in minimum system voltage regulation.
4.5
Charge Disabled
4.3 Charge Enabled
Minimum System Voltage

4.1
SYS (V)

3.9

3.7

3.5

3.3

3.1
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3
BAT (V) D002

Plot1

Figure 15. System Voltage vs Battery Voltage

9.4.2 Dynamic Power Management

To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic
Power management (DPM), which continuously monitors the input current and input voltage. When input source
is over-loaded, either the current exceeds the input current limit (IIDPM) or the voltage falls below the input
voltage limit (VINDPM). The device then reduces the charge current until the input current falls below the input
current limit and the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to
drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement
mode where the BATFET turns on and battery starts discharging so that the system is supported from both the
input source and battery.
During DPM mode, the status register bits VDPM_STAT (VINDPM) or IDPM_STAT (IINDPM) goes high.
Figure 16 shows the DPM response with 9-V/1.2-A adapter, 3.2-V battery, 2.8-A charge current and 3.5-V
minimum system voltage setting.

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Device Functional Modes (continued)

Voltage
VBUS
9V

SYS
3.6V
3.4V
3.2V BAT
3.18V

Current
4A

3.2A ICHG
2.8A
ISYS

1.2A IIN
1.0A
0.5A

-0.6A
DPM DPM
Supplement

Figure 16. DPM Response

9.4.3 Supplement Mode

When the system voltage falls 180 mV (VBAT > VSYSMin) or 45 mV (VBAT < VSYSMin) below the battery
voltage, the BATFET turns on and the BATFET gate is regulated the gate drive of BATFET so that the minimum
BATFET VDS stays at 30 mV when the current is low. This prevents oscillation from entering and exiting the
supplement mode.
As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until
the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge
current. Figure 17 shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit
supplement mode when the battery is below battery depletion threshold.
4.5

3.5

3
Current (A)

2.5

1.5

0.5

0
0 5 10 15 20 25 30 35 40 45 50 55
V(BAT-SYS) (mV) D001

Plot1

Figure 17. BAFET V-I Curve

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Device Functional Modes (continued)

9.4.4 Shipping Mode and QON Pin

9.4.4.1 BATFET Disable Mode (Shipping Mode)

To extend battery life and minimize power when system is powered off during system idle, shipping, or storage,
the device can turn off BATFET so that the system voltage is zero to minimize the battery leakage current. When
the host set BATFET_DIS bit, the charger can turn off BATFET immediately or delay by tSM_DLY as configured by
BATFET_DLY bit.

9.4.4.2 BATFET Enable (Exit Shipping Mode)

When the BATFET is disabled (in shipping mode) and indicated by setting BATFET_DIS, one of the following
events can enable BATFET to restore system power:
1. Plug in adapter
2. Clear BATFET_DIS bit
3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)
4. A logic high to low transition on QON pin with tSHIPMODE deglitch time to enable BATFET to exit shipping
mode

9.4.4.3 BATFET Full System Reset

The BATFET functions as a load switch between battery and system when input source is not pluggeD–in. By
changing the state of BATFET from on to off, systems connected to SYS can be effectively forced to have a
power-on-reset. The QON pin supports push-button interface to reset system power without host by changing the
state of BATFET.
When the QON pin is driven to logic low for tQON_RST while input source is not plugged in and BATFET is enabled
(BATFET_DIS = 0), the BATFET is turned off for tBATFET_RST and then it is re-enabled to reset system power. This
function can be disabled by setting BATFET_RST_EN bit to 0.

9.4.4.4 QON Pin Operations

The QON pin incorporates two functions to control BATFET.
1. BATFET Enable: A QON logic transition from high to low with longer than tSHIPMODE deglitch turns on
BATFET and exit shipping mode. When exiting shipping mode, HIZ is enabled (EN_HIZ = 1) as well. HIZ can
be disabled (EN_HIZ = 0) by the host after exiting shipping mode. OTG cannot be enabled (OTG_CONFIG =
1) until HIZ is disabled.
2. BATFET Reset: When QON is driven to logic low by at least tQON_RST while adapter is not plugged in (and
BATFET_DIS = 0), the BATFET is turned off for tBATFET_RST. The BATFET is re-enabled after tBATFET_RST
duration. This function allows systems connected to SYS to have power-on-reset. This function can be
disabled by setting BATFET_RST_EN bit to 0.
Figure 18 shows the sample external configurations for each.

QON
Press Press
push button push button

tQON_RST
tSHIPMODE tBATFET_RST
Q4 Status

2 Q4
Q4 off due to I C or Q4 on Q4 on
system overload off

Turn on Q4 FET Reset Q4 FET

when BATFET_DIS = 1 or SLEEPZ = 1 When BATFET_DIS = 0 and SLEEPZ = 0

Figure 18. QON Timing

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Device Functional Modes (continued)

SYS

Q4
Control
BAT

VPULL-UP +

QON

Figure 19. QON Circuit

9.4.5 Status Outputs (PG, STAT, INT)

9.4.5.1 Power Good indicator ( PGPin PG_STAT Bit)

The PG_STAT bit goes HIGH to indicate a good input source when:
• VBUS above VVBUS_UVLO
• VBUS above battery (not in sleep)
• VBUS below VVAC_OV threshold
• VBUS above VVBUSMin (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
• Completed input Source Type Detection

9.4.5.2 Charging Status indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED. The STAT pin
function can be disabled by setting the EN_ICHG_MON bits = 11.

Table 5. STAT Pin State

CHARGING STATE STAT INDICATOR
Charging in progress (including recharge) LOW
Charging complete HIGH
Sleep mode, charge disable HIGH
Charge suspend (input overvoltage, TS fault, timer fault or system overvoltage)
Blinking at 1 Hz
Boost Mode suspend (due to TS fault)

9.4.5.3 Interrupt to Host (INT)

In some applications, the host does not always monitor the charger operation. The INT pulse notifies the system
on the device operation. The following events will generate 256-μs INT pulse.
• USB/adapter source identified (through DPDM detection)
• Good input source detected
– VBUS above battery (not in sleep)
– VBUS below VVAC_OV threshold
– VBUS above VVBUSMin (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
• input removed
• Charge Complete
• Any FAULT event in REG09

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• VINDPM / IINDPM event detected (maskable)

When a fault occurs, the charger device sends out INT and keeps the fault state in REG09 until the host reads
the fault register. Before the host reads REG09 and all the faults are cleared, the charger device would not send
any INT upon new faults. To read the current fault status, the host has to read REG09 two times consecutively.
The first read reports the pre-existing fault register status and the second read reports the current fault register
status.

9.5 Protections
9.5.1 Voltage and Current Monitoring in Converter Operation
The device closely monitors the input and system voltage, as well as internal FET currents for safe buck and
boost mode operation.

9.5.1.1 Voltage and Current Monitoring in Buck Mode

9.5.1.1.1 Input Overvoltage (ACOV)

If VBUS voltage exceeds VVAC_OV (programmable via OVP[2:0] bits), the device stops switching immediately.
During input overvoltage event (ACOV), the fault register CHRG_FAULT bits are set to 01. An INT pulse is
asserted to the host. The device will automatically resume normal operation once the input voltage drops back
below the OVP threshold.

9.5.1.1.2 System Overvoltage Protection (SYSOVP)

The charger device clamps the system voltage during load transient so that the components connect to system
would not be damaged due to high voltage. SYSOVP threshold is 350 mV above minimum system regulation
voltage when the system is regulate at VSYSMIN. Upon SYSOVP, converter stops switching immediately to clamp
the overshoot. The charger provides 30 mA discharge current to bring down the system voltage.

9.5.2 Voltage and Current Monitoring in Boost Mode

The device closely monitors the VBUS voltage, as well as RBFET and LSFET current to ensure safe boost mode
operation.

9.5.2.1 VBUS Soft Start

When the boost function is enabled, the device soft-starts boost mode to avoid inrush current.

9.5.2.2 VBUS Output Protection

The device monitors boost output voltage and other conditions to provide output short circuit and overvoltage
protection. The Boost build in accurate constant current regulation to allow OTG to adaptive to various types of
load. If short circuit is detected on VBUS, the Boost turns off and retry 7 times. If retries are not successful, OTG
is disabled with OTG_CONFIG bit cleared. In addition, the BOOST_FAULT bit is set and INT pulse is generated.
The BOOST_FAULT bit can be cleared by host by re-enabling boost mode.

9.5.2.3 Boost Mode Overvoltage Protection

When the VBUS voltage rises above regulation target and exceeds VOTG_OVP, the device enters overvoltage
protection which stops switching, clears OTG_CONFIG bit and exits boost mode. At Boost overvoltage duration,
the fault register bit (BOOST_FAULT) is set high to indicate fault in boost operation. An INT is also asserted to
the host.

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Protections (continued)
9.5.3 Thermal Regulation and Thermal Shutdown

9.5.3.1 Thermal Protection in Buck Mode

The BQ25601D monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface
temperature in buck mode. When the internal junction temperature exceeds thermal regulation limit (110°C), the
device lowers down the charge current. During thermal regulation, the actual charging current is usually below
the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the
clock rate, and the status register THERM_STAT bit goes high.
Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface
temperature exceeds TSHUT(160ºC). The fault register CHRG_FAULT is set to 1 and an INT is asserted to the
host. The BATFET and converter is enabled to recover when IC temperature is TSHUT_HYS (30ºC) below
TSHUT(160ºC).

9.5.3.2 Thermal Protection in Boost Mode

The device monitors the internal junction temperature to provide thermal shutdown during boost mode. When IC
junction temperature exceeds TSHUT (160ºC), the boost mode is disabled by setting OTG_CONFIG bit low and
BATFET is turned off. When IC junction temperature is below TSHUT(160ºC) - TSHUT_HYS (30ºC), the BATFET is
enabled automatically to allow system to restore and the host can re-enable OTG_CONFIG bit to recover.

9.5.4 Battery Protection

9.5.4.1 Battery overvoltage Protection (BATOVP)

The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage
occurs, the charger device immediately disables charging. The fault register BAT_FAULT bit goes high and an
INT is asserted to the host.

9.5.4.2 Battery Over-Discharge Protection

When battery is discharged below VBAT_DPL_FALL, the BATFET is turned off to protect battery from over discharge.
To recover from over-discharge latch-off, an input source plug-in is required at VBUS. The battery is charged
with ISHORT (typically 100 mA) current when the VBAT < VSHORT, or precharge current as set in IPRECHG
register when the battery voltage is between VSHORTZ and VBAT_LOWV.

9.5.4.3 System Over-Current Protection

When the system is shorted or significantly overloaded (IBAT > IBATOP) and the current exceeds BATFET
overcurrent limit, the BATFET latches off. Section BATFET Enable (Exit Shipping Mode) can reset the latch-off
condition and turn on BATFET.

9.6 Programming
9.6.1 Serial Interface
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2CTM is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP
Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices
can be considered as masters or slaves when performing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device
addressed is considered a slave.
The device operates as a slave device with address 6BH, receiving control inputs from the master device like
micro controller or a digital signal processor through REG00-REG0B. Register read beyond REG0B (0x0B)
returns 0xFF. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits).
connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines
are HIGH. The SDA and SCL pins are open drain.

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Programming (continued)
9.6.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.

SDA

SCL

Data line stable; Change of data

Data valid allowed

Figure 20. Bit Transfer on the I2C Bus

9.6.1.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The
bus is considered busy after the START condition, and free after the STOP condition.

SDA SDA

SCL SCL

START (S) STOP (P)

Figure 21. TS START and STOP Conditions

9.6.1.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the mAster into a wait state (clock stretching). Data
transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
Acknowledgement Acknowledgement
signal from slave signal from receiver

MSB
SDA

1 2 7 8 9 1 2 8 9
SCL S or Sr P or Sr
START or ACK ACK STOP or
Repeated Repeated
START START

Figure 22. Data Transfer on the I2C Bus

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Programming (continued)
9.6.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge ninth clock pulse, are generated by the master. The transmitter releases the SDA line during the
acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH
period of this clock pulse.
When SDA remains HIGH during the ninth clock pulse, this is the Not Acknowledge signal. The master can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.

9.6.1.5 Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction
bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

SDA

1-7 8 9 1-7 8 9 1-7 8 9

SCL S P

START ADDRESS R/W ACK DATA ACK DATA ACK STOP

Figure 23. Complete Data Transfer

9.6.1.6 Single Read and Write

If the register address is not defined, the charger IC send back NACK and go back to the idle state.

1 7 1 1 8 1 8 1 1

S Slave Address 0 ACK Reg Addr ACK Data to Addr ACK P

Figure 24. Single Write

1 7 1 1 8 1 1 7 1 1

S Slave Address 0 ACK Reg Addr ACK S Slave Addr 1 ACK

8 1 1

Data NCK P

Figure 25. Single Read

9.6.1.7 Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG0B.

1 7 1 1 8 1

S Slave Address 0 ACK Reg Addr ACK

8 1 8 1 8 1 1

Data to Addr ACK Data to Addr + N ACK Data to Addr + N ACK P

Figure 26. Multi-Write

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Programming (continued)

1 7 1 1 8 1 1 7 1 1

S Slave Address 0 ACK Reg Addr ACK S Slave Address 1 ACK

8 1 8 1 8 1 1

Data @ Addr ACK Data @ Addr + 1 ACK Data @ Addr + N NCK P

Figure 27. Multi-Read

REG09 is a fault register. It keeps all the fault information from last read until the host issues a new read. For
example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the
fault when it is read the first time, but returns to normal when it is read the second time. in order to get the fault
information at present, the host has to read REG09 for the second time. The only exception is NTC_FAULT
which always reports the actual condition on the TS pin. in addition, REG09 does not support multi-read and
multi-write.

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9.7 Register Maps

I2C Slave Address: 6BH

9.7.1 REG00 (address = 00) [reset = 00010111]

Figure 28. REG00 Register
7 6 5 4 3 2 1 0
EN_HIZ EN_ICHG_MO EN_ICHG_MO IINDPM[4] IINDPM[3] IINDPM[2] IINDPM[1] IINDPM[0]
N[1] N[0]
R/W R/W R/W R/W R/W R/W R/W R/W

Table 6. REG00 Field Descriptions

Bit Field POR Type (1) Reset Description Comment
7 by REG_RST Enable HIZ Mode
EN_HIZ 0 R/W 0 – Disable, 1 – Enable 0 – Disable (default)
by Watchdog 1 – Enable
6 EN_ICHG_MON[1] 0 R/W by REG_RST 00 - Enable STAT pin function
(default)
01 - Reserved
5 EN_ICHG_MON[0] 0 R/W by REG_RST 10 - Reserved
11 - Disable STAT pin function
(float pin)
4 IINDPM[4] 1 R/W by REG_RST 1600 mA Input Current Limit
3 IINDPM[3] 0 R/W by REG_RST 800 mA Offset: 100 mA
Range: 100 mA (000000) – 3.2 A
2 IINDPM[2] 1 R/W by REG_RST 400 mA (11111)
1 IINDPM[1] 1 R/W by REG_RST 200 mA Default:2400 mA (10111),
maximum input current limit, not
typical.
IINDPM bits are changed
automatically after input source
0 IINDPM[0] 1 R/W by REG_RST 100 mA detection is completed
Host can over-write IINDPM
register bits after input source
detection is completed.

(1) LEGEND: R/W = Read/Write; R = Read only

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9.7.2 REG01 (address = 01) [reset = 00011010]

Figure 29. REG01 Register
7 6 5 4 3 2 1 0
PFM _DIS WD_RST OTG_CONFIG CHG_CONFIG SYS_Min[2] SYS_Min[1] SYS_Min[0] Min_VBAT_SEL
R/W R/W R/W R/W R/W R/W R/W R/W

Table 7. REG01 Field Descriptions

Bit Field POR Type (1) Reset Description Comment
0 – Enable PFM
7 PFM _DIS 0 R/W by REG_RST Default: 0 - Enable
1 – Disable PFM
by REG_RST I2C Watchdog Timer Reset 0 – Default: Normal (0) Back to 0 after
6 WD_RST 0 R/W
by Watchdog Normal ; 1 – Reset watchdog timer reset
Default: OTG disable (0)
by REG_RST 0 – OTG Disable Note:
5 OTG_CONFIG 0 R/W 1. OTG_CONFIG would over-ride
by Watchdog 1 – OTG Enable Charge Enable Function in
CHG_CONFIG
Default: Charge Battery (1)
by REG_RST 0 - Charge Disable Note:
4 CHG_CONFIG 1 R/W 1. Charge is enabled when both
by Watchdog 1- Charge Enable CE pin is pulled low AND
CHG_CONFIG bit is 1.
3 SYS_Min[2] 1 R/W by REG_RST 000: 2.6 V
001: 2.8 V
2 SYS_Min[1] 0 R/W by REG_RST
010: 3 V
011: 3.2 V
System Minimum Voltage 100: 3.4 V
101: 3.5 V
1 SYS_Min[0] 1 R/W by REG_RST
110: 3.6 V
111: 3.7 V
Default: 3.5 V (101)
Minimum battery voltage for OTG
0 – 2.8 V BAT falling,
0 Min_VBAT_SEL 0 R/W by REG_RST mode. Default falling 2.8 V (0);
1 – 2.5 V BAT falling
Rising threshold 3.0 V (0)

(1) LEGEND: R/W = Read/Write; R = Read only

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9.7.3 REG02 (address = 02) [reset = 10100010]

Figure 30. REG02 Register
7 6 5 4 3 2 1 0
BOOST_LIM Q1_FULLON ICHG[5] ICHG[4] ICHG[3] ICHG[2] ICHG[1] ICHG[0]
R/W R/W R/W R/W R/W R/W R/W R/W

Table 8. REG02 Field Descriptions

Bit Field POR Type (1) Reset Description Comment
by REG_RST Default: 1.2 A (1)
by Watchdog 0 = 0.5 A Note:
7 BOOST_LIM 1 R/W
1 = 1.2 A The current limit options listed are
minimum current limit specs.
by REG_RST 0 – Use higher Q1 RDSON when
programmed IINDPM < 700mA
In boost mode, full FET is always
6 Q1_FULLON 0 R/W (better accuracy)
used and this bit has no effect
1 – Use lower Q1 RDSON always
(better efficiency)
by REG_RST
5 ICHG[5] 1 R/W 1920 mA
by Watchdog
by REG_RST Fast Charge Current
4 ICHG[4] 0 R/W 960 mA
by Watchdog Default: 2040mA (100010)
by REG_RST Range: 0 mA (0000000) – 3000
3 ICHG[3] 0 R/W 480 mA mA (110010)
by Watchdog
Note:
by REG_RST ICHG = 0 mA disables charge.
2 ICHG[2] 0 R/W 240 mA
by Watchdog ICHG > 3000 mA (110010 clamped
by REG_RST to register value 3000 mA
1 ICHG[1] 1 R/W 120 mA (110010))
by Watchdog
by REG_RST
0 ICHG[0] 0 R/W 60 mA
by Watchdog

(1) LEGEND: R/W = Read/Write; R = Read only

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9.7.4 REG03 (address = 03) [reset = 00100010]

Figure 31. Register REG03
7 6 5 4 3 2 1 0
IPRECHG[3] IPRECHG[2] IPRECHG[1] IPRECHG[0] ITERM[3] ITERM[2] ITERM[1] ITERM[0]
R/W R/W R/W R/W R/W R/W R/W R/W

Table 9. REG03 Field Descriptions

Bit Field POR Type (1) Reset Description Comment
7 IPRECHG[3] 0 R/W by REG_RST
480 mA
by Watchdog
6 IPRECHG[2] 0 R/W by REG_RST Precharge Current
240 mA Default: 180 mA (0010)
by Watchdog
Offset: 60 mA
5 IPRECHG[1] 1 R/W by REG_RST Note: IPRECHG > 780 mA
120 mA
by Watchdog clamped to 780 mA (1100)
4 IPRECHG[0] 0 R/W by REG_RST
60 mA
by Watchdog
3 ITERM[3] 0 R/W by REG_RST
480 mA
by Watchdog
2 ITERM[2] 0 R/W by REG_RST
240 mA Termination Current
by Watchdog
Default: 180 mA (0010)
1 ITERM[1] 1 R/W by REG_RST Offset: 60 mA
120 mA
by Watchdog
0 ITERM[0] 0 R/W by REG_RST
60 mA
by Watchdog

(1) LEGEND: R/W = Read/Write; R = Read only

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9.7.5 REG04 (address = 04) [reset = 01011000]

Figure 32. Register REG04
7 6 5 4 3 2 1 0
VREG[4] VREG[3] VREG[2] VREG[1] VREG[0] TOPOFF_TIME TOPOFF_TIME VRECHG
R[1] R[0]
R/W R/W R/W R/W R/W R/W R/W R/W

Table 10. REG04 Field Descriptions

Bit Field POR Type (1) Reset Description Comment
by REG_RST
7 VREG[4] 0 R/W 512 mV Charge Voltage
by Watchdog
Offset: 3.847 V
by REG_RST
6 VREG[3] 1 R/W 256 mV Range: 3.847 V to 4.615 V
by Watchdog
(11000)
by REG_RST Default: 4.199 V (01011)
5 VREG[2] 0 R/W 128 mV
by Watchdog
Special Value:
by REG_RST
4 VREG[1] 1 R/W 64 mV (01111): 4.343 V
by Watchdog Note: Value above 11000 (4.615
by REG_RST V) is clamped to register value
3 VREG[0] 1 R/W 32 mV 11000 (4.615 V)
by Watchdog
by REG_RST 00 – Disabled (Default) The extended time following the
2 TOPOFF_TIMER[1] 0 R/W
by Watchdog 01 – 15 minutes termination condition is met. When
by REG_RST 10 – 30 minutes disabled, charge terminated when
1 TOPOFF_TIMER[0] 0 R/W
by Watchdog 11 – 45 minutes termination conditions are met

by REG_RST 0 – 100 mV Recharge threshold

0 VRECHG 0 R/W
by Watchdog 1 – 200 mV Default: 100mV (0)

(1) LEGEND: R/W = Read/Write; R = Read only

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9.7.6 REG05 (address = 05) [reset = 10011111]

Figure 33. Register REG05
7 6 5 4 3 2 1 0
EN_TERM Reserved WATCHDOG[1] WATCHDOG[0] EN_TIMER CHG_TIMER TREG JEITA_ISET
R/W R/W R/W R/W R/W R/W R/W R/W

Table 11. REG05 Field Descriptions

Bit Field POR Type (1) Reset Description Comment
by REG_RST 0 – Disable
7 EN_TERM 1 R/W Default: Enable termination (1)
by Watchdog 1 – Enable
by REG_RST
6 Reserved 0 R/W Reserved Reserved
by Watchdog
by REG_RST
5 WATCHDOG[1] 0 R/W
by Watchdog 00 – Disable timer, 01 – 40 s, 10 –
Default: 40 s (01)
by REG_RST 80 s,11 – 160 s
4 WATCHDOG[0] 1 R/W
by Watchdog
0 – Disable
by REG_RST
3 EN_TIMER 1 R/W 1 – Enable both fast charge and Default: Enable (1)
by Watchdog
precharge timer
by REG_RST 0 – 5 hrs
2 CHG_TIMER 1 R/W Default: 10 hours (1)
by Watchdog 1 – 10 hrs
Thermal Regulation Threshold:
by REG_RST
1 TREG 1 R/W 0 - 90°C Default: 110°C (1)
by Watchdog
1 - 110°C
JEITA_ISET by REG_RST 0 – 50% of ICHG
0 1 R/W Default: 20% (1)
(0C-10C) by Watchdog 1 – 20% of ICHG

(1) LEGEND: R/W = Read/Write; R = Read only

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9.7.7 REG06 (address = 06) [reset = 01100110]

Figure 34. Register REG06
7 6 5 4 3 2 1 0
OVP[1] OVP[0] BOOSTV[1] BOOSTV[0] VINDPM[3] VINDPM[2] VINDPM[1] VINDPM[0]
R/W R/W R/W R/W R/W R/W R/W R/W

Table 12. REG06 Field Descriptions

Bit Field POR Type (1) Reset Description Comment
7 OVP[1] 0 R/W by REG_RST VAC OVP threshold:
00 - 5.5 V
Default: 6.5V (01) 01 – 6.5 V (5-V input)
6 OVP[0] 1 R/W by REG_RST 10 – 10.5 V (9-V input)
11 – 14 V (12-V input)
5 BOOSTV[1] 1 R/W by REG_RST Boost Regulation Voltage:
00 - 4.85V
01 - 5.00V
4 BOOSTV[0] 0 R/W by REG_RST 10 - 5.15V
11 - 5.30V
3 VINDPM[3] 0 R/W by REG_RST 800 mV Absolute VINDPM Threshold
2 VINDPM[2] 1 R/W by REG_RST 400 mV Offset: 3.9 V
Range: 3.9 V (0000) – 5.4 V
1 VINDPM[1] 1 R/W by REG_RST 200 mV (1111)
0 VINDPM[0] 0 R/W by REG_RST 100 mV Default: 4.5V (0110)

(1) LEGEND: R/W = Read/Write; R = Read only

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9.7.8 REG07 (address = 07) [reset = 01001100]

Figure 35. Register REG07
7 6 5 4 3 2 1 0
IINDET_EN TMR2X_EN BATFET_DIS JEITA_VSET BATFET_DLY BATFET_RST_ VDPM_BAT_T VDPM_BAT_T
EN RACK[1] RACK[0]
R/W R/W R/W R/W R/W R/W R/W R/W

Table 13. REG07 Field Descriptions

Bit Field POR Type (1) Reset Description Comment
0 - Not in input current limit
by REG_RST detection Returns to 0 after input detection
7 IINDET_EN 0 R/W
by Watchdog 1 - Force input current limit is complete
detection when VBUS is present
0 – Disable
by REG_RST 1 – Safety timer slowed by 2X
6 TMR2X_EN 1 R/W
by Watchdog during input DPM (both V and I) or
JEITA cool, or thermal regulation
0 – Allow Q4 turn on, 1 – Turn off
5 BATFET_DIS 0 R/W by REG_RST Q4 with tBATFET_DLY delay time Default: Allow Q4 turn on(0)
(REG07[3])

JEITA_VSET by REG_RST 0 – Set Charge Voltage to 4.1V (

4 0 R/W max),
(45C-60C) by Watchdog 1 – Set Charge Voltage to VREG

0 – Turn off BATFET immediately

Default: 1
when BATFET_DIS bit is set
Turn off BATFET after tBATFET_DLY
3 BATFET_DLY 1 R/W by REG_RST 1 –Turn off BATFET after
(typ. 10 s) when BATFET_DIS bit
tBATFET_DLY (typ. 10 s) when
is set
BATFET_DIS bit is set

by REG_RST 0 – Disable BATFET reset Default: 1

2 BATFET_RST_EN 1 R/W function
by Watchdog 1 – Enable BATFET reset function Enable BATFET reset function

1 VDPM_BAT_TRACK[1] 0 R/W by REG_RST 00 - Disable function (VINDPM set

Sets VINDPM to track BAT
by register)
voltage. Actual VINDPM is higher
01 - VBAT + 200mV
0 VDPM_BAT_TRACK[0] 0 R/W by REG_RST 10 - VBAT + 250mV of register value and VBAT +
VDPM_BAT_TRACK
11 - VBAT + 300mV

(1) LEGEND: R/W = Read/Write; R = Read only

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9.7.9 REG08 (address = 08) [reset = xxxxxxxx]

Figure 36. Register REG08
7 6 5 4 3 2 1 0
VBUS_STAT[2] VBUS_STAT[1] VBUS_STAT[0] CHRG_STAT[1 CHRG_STAT[0 PG_STAT THERM_STAT VSYS_STAT
] ]
R R R R R R R R

Table 14. REG08 Field Descriptions

Bit Field POR Type (1) Reset Description
7 VBUS_STAT[2] x R NA VBUS Status register
BQ25601D
6 VBUS_STAT[1] x R NA
000: No input
001: USB Host SDP
010: USB CDP: (1.5A)
011: USB DCP (2.4 A)
5 VBUS_STAT[0] x R NA 101: Unknown Adapter (500 mA)
110: Non-Standard Adapter (1A/2A/2.1A/2.4A)
111: OTG
Software current limit is reported in IINDPM register
4 CHRG_STAT[1] x R NA Charging status:
00 – Not Charging
01 – Pre-charge (< VBATLOWV)
3 CHRG_STAT[0] x R NA 10 – Fast Charging
11 – Charge Termination
Power Good status:
2 PG_STAT x R NA 0 – Power Not Good
1 – Power Good
0 – Not in ther mAl regulation
1 THERM_STAT x R NA
1 – in ther mAl regulation
0 – Not in VSYSMin regulation (BAT > VSYSMin)
0 VSYS_STAT x R NA
1 – in VSYSMin regulation (BAT < VSYSMin)

(1) LEGEND: R/W = Read/Write

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9.7.10 REG09 (address = 09) [reset = xxxxxxxx]

Figure 37. Register REG09
7 6 5 4 3 2 1 0
WATCHDOG_F BOOST_FAUL CHRG_FAULT[ CHRG_FAULT[ BAT_FAULT NTC_FAULT[2] NTC_FAULT[1] NTC_FAULT[0]
AULT T 1] 0]
R R R R R R R R

Table 15. REG09 Field Descriptions

Bit Field POR Type (1) Reset Description
7 WATCHDOG_FAULT x R NA 0 – Normal, 1- Watchdog timer expiration
0 – Normal, 1 – VBUS overloaded in OTG, or VBUS OVP, or battery is
6 BOOST_FAULT x R NA
too low (any conditions that we cannot start boost function)
5 CHRG_FAULT[1] x R NA 00 – Normal, 01 – input fault (VAC OVP or VBAT < VBUS < 3.8 V), 10
4 CHRG_FAULT[0] x R NA - Thermal shutdown, 11 – Charge Safety Timer Expiration
3 BAT_FAULT x R NA 0 – Normal, 1 – BATOVP
2 NTC_FAULT[2] x R NA JEITA
000 – Normal, 010 – Warm, 011 – Cool, 101 – Cold, 110 – Hot (Buck
1 NTC_FAULT[1] x R NA
mode)
0 NTC_FAULT[0] x R NA 000 – Normal, 101 – Cold, 110 – Hot (Boost mode)

(1) LEGEND: R/W = Read/Write; R = Read only

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9.7.11 REG0A (address = 0A) [reset = xxxxxx00]

Figure 38. Register REG0A
7 6 5 4 3 2 1 0
VBUS_GD VINDPM_STAT IINDPM_STAT Reserved TOPOFF_ACTI ACOV_STAT VINDPM_INT_ IINDPM_INT_
VE MASK MASK
R R R R R R R/W R/W

Table 16. REG0A Field Descriptions

Bit Field POR Type (1) Reset Description
0 – Not VBUS attached,
7 VBUS_GD x R NA
1 – VBUS Attached
6 VINDPM_STAT x R NA 0 – Not in VINDPM, 1 – in VINDPM
5 IINDPM_STAT x R NA 0 – Not in IINDPM, 1 – in IINDPM
4 Reserved x R NA
0 – Top off timer not counting.
3 TOPOFF_ACTIVE x R NA
1 – Top off timer counting
0 – Device is NOT in ACOV
2 ACOV_STAT x R NA
1 – Device is in ACOV
0 - Allow VINDPM INT pulse
1 VINDPM_INT_ MASK 0 R/W by REG_RST
1 - Mask VINDPM INT pulse
0 - Allow IINDPM INT pulse
0 IINDPM_INT_ MASK 0 R/W by REG_RST
1 - Mask IINDPM INT pulse

(1) LEGEND: R/W = Read/Write; R = Read only

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9.7.12 REG0B (address = 0B) [reset = 00111xxx]

Figure 39. Register REG0B
7 6 5 4 3 2 1 0
REG_RST PN[3] PN[2] PN[1] PN[0] Reserved DEV_REV[1] DEV_REV[0]
R/W R R R R R R R

Table 17. REG0B Field Descriptions

Bit Field POR Type (1) Reset Description
Register reset
0 – Keep current register setting
7 REG_RST 0 R/W NA
1 – Reset to default register value and reset safety timer
Note: Bit resets to 0 after register reset is completed
6 PN[3] 0 R NA
5 PN[2] 1 R NA
BQ25601D : 0111
4 PN[1] 1 R NA
3 PN[0] 1 R NA
2 Reserved x R NA
1 DEV_REV[1] x R NA
0 DEV_REV[0] x R NA

(1) LEGEND: R/W = Read/Write; R = Read only

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10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application information

A typical application consists of the device configured as an I2C controlled power path management device and a
single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smart phones and other
portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2),
low-side switching FET (LSFET, Q3), and battery FET (BATFET Q4) between the system and battery. The
device also integrates a bootstrap diode for the high-side gate drive.

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10.2 Typical Application

SYSTEM
1 H 3.5 V ± 4.6 V
VBUS SW
10 F
1 F 47 nF 10 F

PMID BTST

10 F REGN
4.7 µF
GND
VAC
SYS
Opt. SYS

2.2 k
BAT
VREF STAT BQ25601D
10 F

3 x 10 k
REGN
SDA
5.23 k
SCL
Host TS
INT +
30.1 k 10 k

CE

QON
D+
USB
D-
Optional

Figure 40. Power Path Management Application

10.2.1 Design Requirements

Table 18. Design Requirements

PARAMETER VALUE
Input Voltage 3.9V to 13.5V
Input Current 3.0A
Fast Charge Current 3.0A
Battery Regulation Voltage 4.2V

10.2.2 Detailed Design Procedure

10.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the BQ25601D device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
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• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.

10.2.2.2 Inductor Selection

The 1.5-MHz switching frequency allows the use of small inductor and capacitor values to maintain an inductor
saturation current higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
ISAT ≥ ICHG + (1/2) IRIPPLE (3)
The inductor ripple current depends on the input voltage (VVBUS), the duty cycle (D = VBAT/VVBUS), the switching
frequency (fS) and the inductance (L).
V ´ D ´ (1 - D)
IRIPPLE = IN
fs ´ L (4)
The maximum inductor ripple current occurs when the duty cycle (D) is 0.5 or approximately 0.5. Usually inductor
ripple is designed in the range between 20% and 40% maximum charging current as a trade-off between
inductor size and efficiency for a practical design.

10.2.2.3 Input Capacitor

Design input capacitance to provide enough ripple current rating to absorb input switching ripple current. The
worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not
operate at 50% duty cycle, then the worst case capacitor RMS current ICin occurs where the duty cycle is closest
to 50% and can be estimated using Equation 5.
ICIN = ICHG ´ D ´ (1 - D) (5)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. A rating of 25-V or higher capacitor is
preferred for 15 V input voltage. Capacitance of 22-μF is suggested for typical of 3A charging current.

10.2.2.4 Output Capacitor

Ensure that the output capacitance has enough ripple current rating to absorb the output switching ripple current.
Equation 6 shows the output capacitor RMS current ICOUT calculation.
I
ICOUT = RIPPLE » 0.29 ´ IRIPPLE
2´ 3 (6)
The output capacitor voltage ripple can be calculated as follows:
V æ V ö
DVO = OUT2 ç 1 - OUT ÷
8LCfs è VIN ø (7)
At certain input and output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
The charger device has internal loop compensation optimized for >20μF ceramic output capacitance. The
preferred ceramic capacitor is 10V rating, X7R or X5R.

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10.2.3 Application Curves

VVBUS = 5 V VVBAT = 3.2 V VVBUS = 5 V VVBAT = 3.2 V

ICHG = 2 A

Figure 41. Power-Up with Charge Disabled Figure 42. Power-Up with Charge Enabled

VVBUS = 5 V VVBUS = 9 V
ISYS = 50 mA Charge Disabled ISYS = 50 mA Charge Disabled

Figure 43. PFM Switching in Buck Mode Figure 44. PFM Switching in Buck Mode

VVBUS = 12 V VVBUS = 5 V VVBAT = 3.8 V

ISYS = 50 mA Charge Disabled ICHG = 2 A

Figure 45. PFM Switching in Buck Mode Figure 46. PWM Switching in Buck Mode

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VVBUS = 12 V VVBAT = 3.8 V VVBUS = 5 V VVBAT = 3.2 V

ICHG = 2 A ICHG = 2 A

Figure 47. PWM Switching in Buck Mode Figure 48. Charge Enable

VVBUS = 5 V VVBAT = 3.2 V VVBAT = 4 V

ICHG = 2 A ILOAD= 50 mA PFM Enabled

Figure 49. Charge Disable Figure 50. OTG Switching

VVBAT = 4 V VVBAT = 4 V
ILOAD= 1 A PFM Enabled ILOAD= 0 A PFM Disabled

Figure 51. OTG Switching Figure 52. OTG Switching

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VVBUS = 5 V IINDPM = 1 A VVBUS = 5 V IINDPM = 2 A

ISYS from 0 A to 2 A ICHG = 1 A ISYS from 0 A to 4 A ICHG = 1 A
VBAT = 3.7 V VBAT = 3.7 V

Figure 53. System Load Transient Figure 54. System Load Transient

VVBUS = 5 V IINDPM = 1 A VVBUS = 5 V IINDPM = 1 A

ISYS from 0 A to 2 A ICHG = 2 A ISYS from 0 A to 4 A ICHG = 2 A
VBAT = 3.7 V VBAT = 3.7 V

Figure 55. System Load Transient Figure 56. System Load Transient

VVBUS = 5 V IINDPM = 2 A VVBUS = 5 V IINDPM = 2 A

ISYS from 0 A to 2 A ICHG = 2 A ISYS from 0 A to 4 A ICHG = 2 A
VBAT = 3.7 V VBAT = 3.7 V

Figure 57. System Load Transient Figure 58. System Load Transient

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VBAT = 3.8 V CLOAD = 470 µF Adaptor ILIM = 1 A

Figure 59. OTG Start-Up Figure 60. VINDPM Tracking Battery Voltage

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11 Power Supply Recommendations

in order to provide an output voltage on SYS, the BQ25601D device requires a power supply between 3.9 V and
14.2 V input with at least 100-mA current rating connected to VBUS and a single-cell Li-Ion battery with voltage >
VBATUVLO connected to BAT. The source current rating needs to be at least 3 A in order for the buck converter of
the charger to provide maximum output power to SYS.

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BQ25601D
SLUSDA2 – JULY 2018 www.ti.com

12 Layout

12.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 61) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Follow this specific order carefully to achieve the
proper layout.
1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper
trace connection or GND plane.
2. Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other
trace or plane.
3. Put output capacitor near to the inductor and the device. Ground connections need to be tied to the IC
ground with a short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using thermal pad as the single ground
connection point. Or using a 0-Ω resistor to tie analog ground to power ground.
5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the
device. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
6. Place decoupling capacitors next to the IC pins and make trace connection as short as possible.
7. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on
the other layers.
8. Ensure that the number and sizes of vias allow enough copper for a given current path.
See the EVM user's guide SLUUBL4 for the recommended component placement with trace and via locations.
For the VQFN information, refer to SCBA017 and SLUA271.

12.2 Layout Example

+
+
±

Figure 61. High Frequency Current Path

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Layout Example (continued)

Figure 62. Layout Example

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13 Device and Documentation Support

13.1 Device Support

13.1.1 Development Support

13.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the BQ25601D device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.

13.2 Documentation Support

13.2.1 Related Documentation
For related documentation see the following:
• EVM User's Guide (SLUUBL4)

13.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

13.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

13.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

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13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

58 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

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 PACKAGE OPTION ADDENDUM

www.ti.com 25-Jul-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

BQ25601DRTWR PREVIEW WQFN RTW 24 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ
& no Sb/Br) 25601D
BQ25601DRTWT PREVIEW WQFN RTW 24 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ
& no Sb/Br) 25601D

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 25-Jul-2018

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Jul-2018

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25601DRTWR WQFN RTW 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
BQ25601DRTWT WQFN RTW 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Jul-2018

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ25601DRTWR WQFN RTW 24 3000 367.0 367.0 35.0
BQ25601DRTWT WQFN RTW 24 250 210.0 185.0 35.0

Pack Materials-Page 2
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