LME49830TB Ultra-High Fidelity High Power Amplifier Reference Design

National Semiconductor
LME49830TB Ultra-High Application Note 1850
Fidelity High Power Troy Huebner John DeCelles
July 1, 2008
Amplifier Reference Design
validate the solution’s sonic performance in the desired test
Introduction environment. The solution presented has undergone listening
The LME49830 EF125WT1 amplifier PCB module showcas- evaluations in a dedicated sound room for verification of sonic
es National Semiconductor’s LME ultra-high fidelity power performance.
amplifier input stage ICs (drivers). The LME49830 is a fully
complementary bipolar 200V input stage IC with 56mA (typi- Overview
cal) of output current that has been optimized for audio ap-
plications. With 56mA of current drive, the IC can drive The LME49830 IC in combination with a properly designed
numerous power transistors to achieve high levels of output high-current output stage, with adequate thermal manage-
power. ment, can provide output power levels in excess of 1kW.
Figure 1 represents a simple schematic of a typical power
The LME49830’s ultra-low distortion and low-noise, com-
amplifier utilizing the LME49830. The LME49830 simplifies
bined with a user adjustable compensation scheme results in
power amplifier design by providing a highly reliable, consis-
a tightly controlled, but highly dynamic listening experience.
tent performing low distortion input stage. With the addition of
User adjustable compensation provides for high-frequency
an output stage and a simple DC biasing circuit, the end result
distortion minimization and for slew rate and power bandwidth
is a very high fidelity power amplifier. The LME49830 was
optimization. The IC’s high performance level, features and
designed for output stages using MOSFET devices but may
user customization make the driver a highly reliable, unique
be used with other output device types as well. The
input stage solution for high power amplifiers.
LME49830 can be used with just about any MOSFET desired
While the amplifier module provides a convenient way for as a result of the 16V DC bias range for the output stage.
performance measurement verification, it also can be used to

AN-1850

30063201

FIGURE 1. Simple Power Amplifier Schematic

© 2008 National Semiconductor Corporation 300632 www.national.com

AN-1850 With a 200V operating voltage range, an amplifier solution The LME49830 can be configured with a number of different
using the LME49830 is mainly limited by the number of output output stage topologies, providing for end-product differenti-
power stage transistors in conjunction with adequate thermal ation and customization. Shown in Figure 2 is the common
management to keep the power transistors operating within source-follower output stage with three transistors paralleled
their safe operating area (SOA). per side.

30063202

FIGURE 2. Source-Follower Output Stage

THD. For higher device count output stages, the LME49830's

Operational Details drive current may not be sufficient to meet design target spec-
The complete amplifier schematic for the EF125WT1 FET ifications.
PCB is shown in Figure 3. Important aspects and explanation The LME49830 amplifier module when running on ±60V pow-
of various sections of the circuit will be covered below. The er supplies is capable providing the output power levels
amplifier module is a two device per side MOSFET output shown below with a 1kHz signal.
stage driven directly from the LME49830. With only two de-
vices per side in the output stage there is no need for an Load 0.1% THD+N 1% THD+N 10% THD+N
additional current gain stage for higher output stage drive 4Ω 335W 350W 430W
current. The LME49830's drive current of 56mA (typical) pro-
vides plenty of drive current for high slew rate and excellent 8Ω 175W 185W 230W

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30063230

FIGURE 3. LME49830 EF125WT1 FET PCB Amplifier Schematic

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AN-1850
AN-1850 It is important to note that the LME49830 EF125WT1 FET TABLE 1. Output Stage Maximum Power Dissipation
PCB amplifier module contains no output stage protection Output Stage Maximum Power Dissipation
mechanisms. A proper current limit set on the evaluation pow-
er supply is the minimum precaution for safety. Load VCC = ±60V VCC = ±75V
The power supply voltage limitation for the EF125WT1 FET RL = 8Ω 91W 142W
module is based on the Toshiba 2SK1530/2SJ201 MOSFET
RL = 4Ω 182W 285W
devices, which have a VDSS of 200V as well as the LME49830
which has an absolute maximum supply voltage rating of With two power transistors per side on the LME49830
±100V (200V). Based on this, it is recommended that the EF125WT1 FET PCB amplifier module, each transistor will
maximum power supply voltage applied to the amplifier mod- dissipate an average of 1/4th of the total output stage power
ule be less than ±80V. To allow for additional safety margin it dissipation. It is easy to see that each power transistor would
is recommended that the maximum power supply voltage is need to dissipate an average of 71W when driving a sine-
±75V. wave continuously into a 4Ω resistive load with a ±75V power
While power supply voltages up to ±75V can be applied to the supply. Each output device is rated for 150W of power dissi-
amplifier module, it is recommended that caution be applied pation at a case temperature of 25°C. The power dissipation
when driving a load with an impedance less than 8Ω with of each device must be de-rated linearly based on case tem-
continuous sinusoidal signals. Only two output power tran- perature. At a case temperature of 75°C the power dissipation
sistors per side with limited power dissipation capabilities on rating for each device is down to 90W, based on the device
the provided heat sink does not allow for continuous total out- datasheets. Instantaneous power dissipation when driving re-
put stage power dissipation levels above 140W with only active loads will be even greater and may exceed the
convection cooling. The amplifier module’s limiting factor is transistor’s safe operating area (SOA).
the output stage power transistor safe operating area (SOA) The heat sink used for the amplifier module is a 4 inch extru-
along with the power dissipation capabilities of the provided sion from Aavid Thermalloy, part number 65605 with a rating
heat sink. Continuous operation at both high supply voltages of 0.62°C/W. Adding a fan on the heat sink can greatly reduce
and into loads less than 8Ω, with sinusoidal signals will require the thermal resistance depending on the air flow rate of the
additional thermal capacity. Utilizing a high air velocity fan will fan. More information and thermal modeling for the amplifier
aid in power dissipation, although this method will still not heat sink can be found on Aavid Thermalloy's website.
guarantee SOA violations under high supply voltage and con- Determining the maximum power dissipation while de-rating
tinuous signal driving situations. the output devices base on case temperature with the pro-
It is recommended that the PCB amplifier module be operated vided heat sink can be determined by mathematical deriva-
with ±60V, driving an 8Ω resistive load with sinusoidal signals tion. The power dissipation of the output devices are de-rated
for standard performance characterization. When operating linearly with case temperature. The general formula for a line
above ±60V supply rails or into low impedance loads, care is y = mx + b. For both output devices, 2SJ201 and 2SK1530,
must be taken to keep from exceeding the output power tran- the thermal properties are the same. The power dissipation
sistor SOA. It is highly recommended to minimize the time that de-rating graph end points are set by the power dissipation
continuous signals are applied to the amplifier under extreme rating at a case temperature (TC) of 25°C and the maximum
operating conditions. Standard audio performance measure- channel temperature, which is at 0W power dissipation.
ments can be obtained at higher supply voltages with time for These specifications are 150W and 150°C respectively. Two
the heat sink and devices to cool in between measurements. points on the line are know allowing for the solution to the
The LME49830 EF125WT1 FET PCB amplifier module is in- general formula resulting in Equation 1.
tended to be used for performance verification and critical PD(IC) = -1.2W/°C * TC + 180W (W) (1)
listening evaluations. The PCB module indicates the high lev-
el of performance that can be achieved from minimal external To determine the case temperature from the device power
components, while still providing significant user design flex- dissipation the equation is given in Equation 2.
ibility for end-product differentiation. The PCB module is not TC = -0.83°C/W * PD(IC) + 150°C (°C) (2)
intended to be used for long-term temperature and reliability
Inspection of the formula above reveals that the junction-to-
testing or significant high-power analysis due to limited ther-
case thermal resistance, θJC, of the device is the absolute
mal capabilities.
value of the slope of the curve in °C/W which is 0.83°C/W.
For continual high-power driving analysis, long-term temper-
To determine the maximum device power dissipation while
ature and reliability testing, it is recommended that the am-
de-rating for increase device case temperature with a given
plifier be designed with adequate thermal management for
heat sink and ambient temperature a second equation for
the operating conditions.
case temperature can be determined resulting in:
OUTPUT STAGE POWER DISSIPATION Device Case Temperature (°C) = Heat Sink Temp (°C) + [De-
The output stage’s worst-case maximum power dissipation vice Power Dissipation (W) * Case Thermal Resistance (°C/
for purely resistive loads can be determined by the following W)]
equation. TC (°C) = THS (°C) + [PD(IC) (W) * θCS (°C/W)]
PD(AMP)MAX = VCC2/(2π2RL) (Watts) The heat sink temperature is the total power dissipation mul-
Where VCC is the total supply voltage. For ±75V calculations tiplied by it's thermal resistance plus the ambient temperature:
VCC used in the equation would be 150V. THS (°C) = [PD(TOTAL) (W) * θSA (°C/W)] + TA (°C)
Table 1 represents the output stage’s maximum power dissi- For any number of output devices, PD(TOTAL) = Number of
pation for stated power supply voltages and purely resistive Output Devices * PD(IC) (W). Combining the above gives
loads. Equation 3.
TC = (PD(TOTAL) * θSA) + TA + (PD(IC) * θCS) (°C) (3)

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 AN-1850
Setting Equation 2 equal to equation 3 gives: The heat sink used on the EF125WT1 FET amplifier module
is from Aavid Thermalloy, part number 530101B00150, with
-0.83°C/W * PD(IC) + 150°C = (PD(TOTAL) * θSA) + TA
a thermal resistance of 6.3°C/W. As shown in the equation
+ (PD(IC) * θCS)
below, even at ±100V rails, the heat sink is sufficient.
Solving for PD(IC) with four output devices results in Equation
θSA = [(TJ(MAX) - TA) - PD(MAX)(θJC - θCS)] / PD(MAX)
4.
= [(150°C - 50°C) - 5W(4°C/W + 0.5°C/W)] / 5W
PD(IC) = (150°C - TA) / (4 * θSA + θCS + θJC) (W) (4) ≤ 15.5°C/W
This heat sink used for the LME49830 was selected inten-
Given: tionally for ease of IC mounting, thermal robustness, and
TA = 25°C mechanical stability. It is recommended that a separate heat
θCS = 0.25°C/W, flat, thermal greased surface. sink from the output stage heat sink be used for the
LME49830 to maintain a low operating die temperature and
θSA = 0.62°C/W, rating of provided heat sink.
minimize thermal interaction.
θJC = 0.83°C/W = (TJ(MAX) - TA) / (PD(MAX) at TA).
PCB Connections
Results in PD(IC) = 35.1W maximum average power dissipa-
tion per device de-rating for case temperature rise with the INPUT CONNECTIONS
provided heat sink at an ambient temperature of 25°C. The An analog input signal is applied to the LME49830
total average output stage power dissipation is 140.4W. Un- EF125WT1 FET PCB through either the two pin header, J2 or
der these conditions each device's channel temperature will through the standard RCA input connector, J4. For optimum
be 150°C, each device case temperature will be 120.9°C, and performance a shielded twisted pair cable should be used
the heat sink will be 112.1°C. between the signal source and PCB amplifier module with the
With some additional substitutions and inspection gives shield terminated only at the signal source.
Equation 5 as the very general version of Equation 4. The input is DC coupled, unbalanced and terminated in a
PD(IC) = (TJ(MAX) - TA) / {# of Devices * θSA + θCS 6.8kΩ resistor. The input termination, RT, and the accompa-
+ [(TJ(MAX) - TA) / (PD(MAX) at TA)]} (W) (5) nying gain-setting feedback resistor, RF, can be changed to
a higher value such as 10kΩ or 47kΩ, resulting in a slightly
The above calculations are for continuous average power
higher THD+N specification due to added resistor thermal
dissipation with sine waves. Music and other program mate-
noise. RIN and RI should also be adjusted to maintain the
rial will have average power dissipation levels lower than a
same gain setting. An input high-frequency roll-off filter ca-
sine wave reducing the heat sink and device temperatures.
pacitor limiting high-frequency amplification, CT, is in parallel
LME49830 POWER DISSIPATION with RT. The combination of these two values set the pole
location to 130kHz.
The LME49830 die is contained in a TO-247 package with a
junction-to-ambient thermal resistance, θJA, of 73°C/W and a The input sensitivity for this amplifier is 1.37V, resulting in an
junction-to-case thermal resistance, θJC, of 4°C/W. The output power of 175W at 0.1% THD+N into 8Ω running off of
TO-247 package is an non-isolated package and any at- ±60V power supply rails.
tached heat sink will be at the same potential as the negative
OUTPUT CONNECTIONS
supply rail.
The output is connected through the two pin header, J3. The
The LME49830 integrates a complete power amplifier input
intended impedance for this amplifier is 8Ω or 4Ω, running off
stage and has an output current drive capability of 56mA. The
of ±60V power supply rails. While the PCB amplifier module
LME49830 is intended to drive MOSFET transistors in the
is capable of running off of supply rails up to ±100V, the main
output stage providing a high-impedance load to the
limitation is the safe operating area of the output stage power
LME49830.
transistors. Please refer to the Operational Details section for
Shown in Table 2 are maximum power dissipation levels and limitations and recommendations.
required minimum heat sink thermal resistances for the stated
An RC output snubber network has been provided on the PCB
power supply voltages to keep the LME49830 die tempera-
acting as a high-frequency load. A 0.1µF capacitor, CSN1 is in
ture below 150°C. The calculations use a 50°C ambient, a
series with a 10Ω resistor, RSN1, which has a 3 watt rating at
LME49830 θJC of 4°C/W, plus 0.5°C/W additional thermal re-
the output. The RC snubber is not needed to provide any
sistance from case-to-sink (θCS).
snubbing of high-frequency instabilities on the output wave-
TABLE 2. LME49830 Power Dissipation & Heat Sink form, generally created in the quasi-saturation region when
Information close to clipping. However, output snubbers are commonly
employed to provide a load impedance to the amplifier at high
LME49830 frequencies.
Power Dissipation & Heat Sink Thermal Resistances
LME49830 VCC = ±60V VCC = ±75V POWER SUPPLY CONNECTIONS
The power supply to the amplifier module is applied to con-
ICCQ(max) = 25mA 3W 3.75W
nector J1. This connector powers both the output stage power
θSA < 28.8°C/W < 22°C/W transistors and the LME49830. Operating voltages from ±20V
to ±100V may be applied to the amplifier module. Please refer
to the Operational Details section for limitations and precau-
tions when operating at elevated supply voltages.
The power supply cabling to the amplifier PCB should have
sufficient current handling capability for the desired amplifier
output power. It is recommended that 18 gauge stranded wire

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AN-1850 be used to connect the low-impedance power supply to the power supply star GND, providing a reference between the
PCB, keeping connections as short as possible. input and output. Only one option in Figure 4 should be used
for the clean GND. This is because there is no electrical
GND CONNECTION OPTIMIZATION ground connection between the input stage and the output
Shown in Figure 4, is a detailed diagram showing optimum stage power supply bypass capacitors on the PCB amplifier
ground connections with two options for the clean signal GND module. This was done intentionally to eliminate any interac-
connection. It is important to note that a separate ground con- tion of ground currents between the input and output stages.
nection must be made from the signal generator GND to the

30063204

FIGURE 4. Amplifier Module Test Setup GND Connections

If the signal source is not grounded back to the power supply possible. 39,000µF of reservoir capacitance per supply rail
star point, the output will float up, drawing a large amount of was used for bench testing to obtain the performance indi-
current from the positive power supply. Therefore, it is impor- cated in this document.
tant that the PCB’s low-level clean signal ground is referenced
back to the star ground from either a connection at the Audio MUTE FUNCTION
Precision or from analog ground, J10 on the PCB, but only one A reference voltage is used for the mute circuit in the
connection typically gives the best THD+N performance. EF125WT1 FET amplifier module, as shown in Figure 5. This
Also note that there is no output load ground return connec- reference voltage allows varying power supply voltages to be
tion on the PCB. This was also done intentionally to ensure applied to the LME49830 without continually adjusting the
that the high-current output ground return current is tied back mute resistance. The mute current is set to 160μA using the
at the star ground point. on-board (+12V) mute voltage. J11 and J12 allow for an exter-
nal mute voltage of 2.6V to 5V to be used or the user can
In order to obtain the lowest level distortion measurements, it
adjust the value of the RM2 mute resistor for any desired volt-
is important to make an oscilloscope chassis ground connec-
age.
tion to the power supply star ground point while NOT using
the scope probe ground clip. Connecting the scope probe
ground clip to AGND, while probing the output stage, may
significantly increase distortion.
Due to the physical size limitation of providing large valued
reservoir capacitors on the PCB, it is expected that the user
provide a low-inductance connection to either a low
impedance power supply or bulk capacitance.
In order to minimize amplifier distortion in a lab environment,
it is recommended to provide high-valued reservoir capacitors
between the lab power supply and the PCB amplifier module.
It is also recommended to keep connections between the
reservoir capacitors and the amplifier module as short as

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 AN-1850
30063206

FIGURE 6. Gain And Low Frequency Response

Experimentation with high quality film capacitors in these lo-

cations may result in additional sonic improvements. Such
investigation is not covered in this document.

Output Stage Biasing

30063205
The LME49830 is a robust, consistently high-performing am-
FIGURE 5. Mute Circuit Reference Voltage plifier input stage that eliminates numerous discrete input
stage design issues. Intricate inter-stage design dependen-
Detailed design information for proper mute circuit operation cies that commonly affect optimum distortion performance
and reference voltage set up can be found in the LME49830 are no longer a problem for discrete designers, ensuring that
datasheet. Also shown in the datasheet is the excellent level new amplifier designs get to market faster and more reliably.
of mute attenuation of -120dB for audio signals. The One of the key benefits of designing with the LME49830 is the
LME49830 mute function has a smooth turn-on/off transition ability to select a preferred output stage topology and power
so that clicks and pops are minimized. Adding a capacitor to devices. This simple, yet flexible input stage solution makes
the MUTE pin can totally eliminate any clicks and pops that it easy to combine a preferred output topology and achieve
may occur with the trade-off being a delay when changing ultra high-fidelity performance with an integrated form-factor.
modes. A 47μF Mute capacitor is supplied on the EF125WT1 System designers can continue to differentiate their power
FET PCB for a virtually silent mode change with minimal de- amplifier solutions from their competitors, by utilizing their
lay. time-developed output stage intellectual property. The
LME49830 also provides an integration factor that increases
GAIN AND FREQUENCY RESPONSE the number of channels per chassis area, while maintaining
The amplifier module is configured as non-inverting mode. an ultra high-fidelity level never before obtained from an in-
The gain is set by: tegrated circuit.
AV = 1 + RF1 / RI (V/V) With the benefits and flexibility that this solution provides,
there is a little complexity and some variability in setting the
The gain is set to 28.3V/V (29dB) with RF1 set to 6.8kΩ and output stage’s DC bias voltage. The DC bias voltage, or mode
RI set to 249Ω. The low frequency response is set by the of operation - Class A, B, or A/B, is set by the designer and is
combination of CI1 and RI by the equation: partially dependent upon the topology and the output power
f = 1/(2πCI1RI) (Hz) device selected. Different MOSFET devices have significantly
varying threshold voltages. There are other topology config-
The low frequency -3dB roll-off point is 2.9Hz. Additionally, urations but other topologies are beyond the scope of this
there are component footprints for additional capacitors in document.
parallel with CI1 (CI2) and RI (CI3) as shown in Figure 6.
Besides the DC voltage bias setting, there is a bias circuit
difference depending upon whether BJTs or MOSFETs are
used as the power delivery device. BJTs are subject to ther-
mal runaway and therefore require a thermally compensated
bias circuit. If MOSFETs are selected as the power device,
there may not be a need for a thermally compensated bias
circuit depending on the specific MOSFET devices.
Shown below in Table 3 is a list of recommended MOSFETs
that have been evaluated with the LME49830. This list of parts
was not meant to be an exhaustive list, but rather some of the
more common power devices that are currently used in audio
power amplifiers. For more information regarding MOSFET
driving issues and recommendations, please refer to
AN-1645, “LM4702 Driving a MOSFET Output Stage”.

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AN-1850 TABLE 3. Recommended MOSFET Power Devices
Manufacturer NFET PFET
Toshiba 2SK1530 2SJ201
International IRFP240 IRFP9240
Rectifier
Renesas(1) 2SK1058 2SJ162

(1) Renesas devices have a different pin out compared to the

Toshiba and IR devices (Source and Drain pins reversed) re-
quiring a different PCB.
The LME49830 has a maximum DC bias voltage of 16V for
use with just about any MOSFET device. The high output
drive current from the LME49830 makes it ideal for very high
power amplifier applications.

VBE MULTIPLIER
The LME49830’s BIASP and BIASM pins are available to cre-
ate the DC bias of the output stage. Depending on the device
characteristics and design goals, a thermally compensated
circuit may be needed in order to have stable bias at the de-
sired current across temperature. A non-compensated bias
circuit would consist of a resistor or potentiometer and one or
two capacitors between the BIAS pins of the LME49830. The
EF125WT1 FET PCB uses a thermally compensated VBE
multiplier for the bias circuit with the Toshiba
2SK1530/2SJ201 devices in the output stage.
The VBE multiplier’s transistor, which needs to be mounted
directly next to one of the power transistors on the heat sink, 30063207
will sense the output device's temperature with some tem-
perature gradient through the common heat sink. With a FIGURE 7. Output Stage DC Biasing VBE Multiplier Circuit
correctly designed VBE multiplier circuit the bias current of the
output stage will remain relatively stable over the device tem- The DC bias voltage can be measured by connecting a volt-
perature operating range. meter between pins 1 and 2 of J9. The DC bias voltage is
The VBE multiplier circuit created by QVBE1 with associated measured from gate-to-gate of the output stage. When RP1 is
resistors and capacitors is shown in Figure 7. The output set at its minimum, the total output stage bias current will be
stage bias can initially be adjusted through potentiometer, approximately 500mA. When set at its maximum, the total
RP1 in order to optimize for lowest crossover distortion, de- output stage bias current will be approximately 175mA. The
sired sound quality or mode of operation – Class A, B, or AB. bias current setting of the EF125WT1 FET module before
leaving the factory, and for all performance data, is approxi-
mately 225mA. This equates to approximately 112mA per
power transistor of power stage quiescent current (~250mA
from each supply rail at ±60V). Changing the value of RB2 to
620Ω will change the bias range to approximately 115mA to
325mA.
It should be noted that the bias adjustment potentiometer,
RP1, is available for your convenience in analyzing the per-
formance effects of output stage bias adjustment. The poten-
tiometer can be replaced in a final design with a simple
resistor once the desired DC biasing voltage has been se-
lected.
Please also note that the VBE Multiplier terminals are very
sensitive to loading, so when obtaining any performance
measurements, be sure that the multi-meter or scope probe
has been removed from DC Bias Monitoring header, J9.
The QVBE1 thermal properties are not an exact match to the
MOSFET output device thermal properties. An additional,
temperature independent bias resistor, RB3, is used to adjust
the bias voltage to more closely match the output devices for
stable bias current over temperature. This resistor changes
the slope of the bias voltage vs. temperature curve by reduc-
ing the effect of the VBE voltage of QVBE1.
Shown in the equation below is the relationship between the
voltage setting resistors and the VBE multiplier’s output volt-
age, VCE.

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 AN-1850
VBIAS = (RB3 * 2mA) + VBE [1 + RB2 / (RB1 + RP1)]
For a Class AB amplifier design, bias current is chosen such
that crossover distortion is minimized while also keeping qui-
escent power dissipation low. Higher bias current reduces
harmonic distortion levels at the cost of increased power dis-
sipation. At some point there is little reduction with increased
bias current and resulting power dissipation. A tradeoff in the
bias current level must be made between THD performance
and power dissipation.
MOSFET output stages typically need higher bias current
than BJT output stages for good performance in a Class AB
amplifier design. What amount of bias current each solution’s
output stage will require depends completely on the user’s
specific tastes and/or target specifications. Shown in Table
4 are THD+N measurements with a 1kHz signal at 10W into
8Ω load with a 22kHz measurement bandwidth at different
total supply current settings. The LM49830 current is approx-
imately 25mA so the output stage bias current is equal to the 30063246

total supply current minus 25mA.

FIGURE 8. THD+N Versus Frequency Versus Bias
TABLE 4. Bias Current And Measured THD+N Current
1kHz THD+N at
Supply Current
10W/8Ω, 22kHz
per Supply
BW
50mA 0.00364%
100mA 0.00176%
150mA 0.00120%
200mA 0.00089%
250mA 0.00078%
300mA 0.00070%
500mA 0.00067%
1A 0.00067%
Table 4 indicates that the a range of 200mA to 300mA of sup-
ply current per power supply produces low magnitude har-
monics and manageable power dissipation.
30063243
Different bias current levels are shown in the graphs and os-
cilloscope photos below. For each graph the output power FIGURE 9. 100mA Bias Current Distortion Residual
level is 10W into an 8Ω resistive load with 1kHz signal. Each
oscilloscope photo shows the input and output signal plus the
An under biased output stage is clearly exhibited by sharp,
time domain distortion residual. The measurement equipment
narrow glitches on the distortion residual at the zero crossing
is set to notch out the fundamental frequency of the test sig-
point of the output voltage.
nal. The fundamental is reduced by more than -110dB relative
to 0dB. 0dB is set equal to the voltage for 10W into 8Ω. The
graphs show how an insufficient bias current results in THD
that is dominated by crossover distortion. Under bias is also
indicated by the high level and number of harmonics in the
FFT graphs.
THD+N curves over frequency representing the level of
crossover distortion associated with varying output stage bias
currents are shown in Figure 8. The output power level is 10W
into an 8Ω load with an 80kHz measurement bandwidth for
all plots.

30063232

FIGURE 10. 100mA Bias Current Output FFT

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AN-1850 The under biased time domain distortion residual is repre-
sented above by an FFT that exhibits high odd harmonic
distortion over a large number of harmonics. The odd har-
monics increase significantly from an optimally biased FFT,
while the even order harmonics remain relatively unchanged.

30063244

FIGURE 13. 1A Bias Current Distortion Residual

A high bias (Class A) output stage shows no crossover dis-

tortion and a very flat time domain distortion residual.
30063245

FIGURE 11. 250mA Bias Current Distortion Residual

A correctly biased output stage shows a very flat distortion

residual except for the zero crossing point where very small
glitches can be observed.
Notice that while the distortion residual at the crossover re-
gion is quite small, the overall distortion of the amplifier with
this level of residual is 0.00078% THD+N.

30063233

FIGURE 14. 1A Bias Current Output FFT

A class A bias level shows very low harmonics in number and

amplitude. The tradeoff is high power dissipation and low ef-
ficiency.

BIAS STABILITY
The Total Quiescent Current versus Time graph (Figure 15)
30063234
was created by running the output stage at 40W into an 8Ω
resistive load until steady state device case and heat sink
FIGURE 12. 250mA Bias Current Output FFT temperature are reached. The input signal is turned off (Time
= 0) and the bias current recorded over time. It should be not-
A correctly biased time domain distortion residual is repre- ed that the graph units are not linear as indicated. Bias current
sented above by an FFT that exhibits fairly evenly balanced is measured at 10 second intervals for the first two minutes
amplitudes of even and odd harmonics as they decrease over after the input signal was turned off then at 30 second inter-
frequency. Most of the distortion products are below the fun- vals up to five minutes. One final measurement is taken at 10
damental or test signal of 1kHz. minutes. The time steps are one reason for the different
slopes on the time curve. There are two plots on the graph,
one indicating the quiescent bias at a heat sink temperature
of 35°C and the other indicating the bias over time after pro-
ducing 40W of output power. There are several factors that
affect the data such as θJC of the package and heat sink size
which contribute to thermal delay.

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 AN-1850
30063215 30063216

FIGURE 15. Bias Current Vs. Time FIGURE 16. Bias Current Vs. Heat Sink Temperature

It is not possible to measure the exact instantaneous channel Figure 17 shows how the bias current changes as a percent
temperature of discrete devices. There is a temperature gra- verses heat sink temperature. The percent change uses the
dient from the channel or junction of the output device to the bias current at a heat sink temperature of 30°C for a baseline.
heat sink. An additional temperature gradient exist along the
heat sink to the QVBE1 transistor and the thermal resistances
of the QVBE1 transistor case. When the output devices are
producing power (and dissipating more power than quiescent
conditions) the temperature gradient from the channel of the
output devices to the junction of the QVBE1 transistor is greater
than under quiescent conditions. The thermal resistance is
relatively constant but as the power dissipation increases the
temperature gradient linearly increases. With the channel
temperature higher than the bias voltage setting, the output
device current is higher. The current will reduce down to qui-
escent levels as the channel cools and the temperature gra-
dient from output device channel to QVBE1 junction is equal to
quiescent steady state conditions. The graph in Figure 15
shows the phenomenon as the total current is higher when
the input signal is first turned off and then returns down to the
steady state bias levels by 10 minutes. It should be noted that
within 40 seconds the bias current has returned to within
~4mA of the steady state bias current. With a different heat
sink and device mounting placement the response will be dif- 30063229

ferent.
FIGURE 17. Bias Current Change Percent Vs. Heat Sink
Figure 16 shows the bias current as a function of heat sink Temperature
temperature. The bias current is set when the heat sink reach-
es 30°C and all the thermal gradients are established at a Based on the data above the bias resistors are set to RB1 =
steady state mode. Using different values for RB1 and RB3 with 392Ω, RB2 = 750Ω, and RB3 = 1.10kΩ.
RB2 set to 750Ω shows how the thermal compensation can be
increased (over compensated) for reduced current at higher BIASING PROCEDURE
heat sink temperatures. The data for Figures 16, 17 are taken Where to set the bias current of the output stage is entirely up
as the heat sink temperature increases under quiescent con- to the designer, essentially one of the features of the solution.
ditions (no signal) up to 50°C. For the higher heat sink tem- It is however, important to set up the biasing of the output
peratures, the heat sink is heated to 87°C by driving a load stage after being warmed up a while,
then the current recorded as the heat sink cools. Because of
By allowing the amplifier to first warm up, the distortion is op-
the larger temperature gradients when driving a signal the
timized at the temperature that the amplifier will normally be
data is collected starting at 70°C when the temperature gra-
operated. The amplifier will then be operating at its optimum
dients are near steady state quiescent conditions. To remove
bias point with reduced distortion under normal operating
differences in bias settings, the bias currents are normalized
temperature conditions.
to 250mA.
Set the DC bias voltage to your preference of distortion level
once the amplifier has warmed up to a temperature indicative
of normal operation. It is common to evaluate the distortion
residual in the time domain and/or the residual’s harmonics
in the frequency domain when optimizing the DC bias. Addi-
tionally, it is common to evaluate the DC bias setting for higher

11 www.national.com
AN-1850 frequencies where crossover distortion is easily recognized TABLE 6. LME49830 Slew Rate vs Compensation
above the measurement unit’s noise floor. Frequencies of Capacitor
3kHz and 5kHz generally allow for significant harmonics to be Compensation
present even when using a 30kHz measurement-unit low- Slew Rate
Capacitor, CCOMP
pass filter. (V/µs)
(pF)
The goal is to determine the desired potentiometer setting (or
eventually a fixed resistance) that will be required for the end- 5 110
design. This is accomplished by optimizing the distortion 10 55
residuals from a measurement perspective or by optimizing 12 46
the desired sound quality from a listening perspective. Re-
moving the amplifier’s input signal allows for measurement of 15 37
the DC bias voltage and the quiescent current running 18 31
through each leg of power transistors. Simple DC voltage 20 27
measurement across the source degeneration resistors pro-
vides each leg’s quiescent current. 25 22
Please note that the VBE multiplier terminals are very sensitive 30 19
to loading, so when obtaining any performance measure- 60 9
ments, be sure that the multi-meter or scope probe has been 100 5.5
removed from DC Bias Monitoring header, J9.
Since slew rate requirements are different depending upon
Compensation desired power bandwidth and output power level, we can cal-
culate the needed compensation capacitor for a given design
SINGLE-POLE COMPENSATION based on the equation below.
The slew rate specification of an amplifier defines its “speed” CCOMP = ITAIL / 2πfVOpk
by establishing an upper limit of how fast its output can re-
spond to input signal transient changes. The amplifier’s slew Shown in Table 7 are appropriate compensation capacitor
rate is defined by the equation below. values for 100kHz power bandwidths at the stated amplifier
output power levels.
One of the features of the LME49830 is the ability to set the
amplifier’s slew rate and power bandwidth through the selec- TABLE 7. Compensation Capacitor Required Per
tion of the external compensation capacitor value. Lowering Reference Design
the value of the compensation capacitor increases the
amplifier’s slew rate and hence its power bandwidth. Reference Compensation Power
Slew Rate
Design Capacitor, CCOMP Bandwidt
Slew Rate = ΔV/Δt = 2πfMAXVOpk (8Ω) (pF)
(V/µs)
h (kHz)
The amplifier’s power bandwidth is also determined through 125W 20 28 100
this equation and can be related to the amplifier’s slew rate
250W 12 40 100
as shown below.
450W 10 53 100
fPBW = Slew Rate/2πVOpk
Figure 18 represents a 24V/µs slew rate from a 20pF com-
The power bandwidth equation indicates that higher output
pensation capacitor. This value is a tad shy of the estimated
power amplifiers will require larger slew rates to maintain a
27V/µs, however, taking into account the tolerances of the
constant power bandwidth. Shown in Table 5 are the required
compensation capacitor (±5%) and the IC’s tail current, a 24V/
amplifier slew rates for a 100kHz power bandwidth for differ-
µs slew rate is a realistic value.
ent output power levels.

TABLE 5. Slew Rates For 100kHz Power Bandwidth

Output Power
Slew Rate (μs)
(W) VO(PEAK) (V)
(fBW = 100kHz)
(RL = 8Ω)
125 44.7 28
250 63.2 40
500 89.4 56
The maximum slew rate for an amplifier will be dependent
upon the value of the compensation capacitor, in conjunction
with the maximum tail current of the input differential transistor
pair.
Slew Rate = dV/dt = IMAX / CCOMP
The LME49830 has a maximum input differential pair tail cur-
rent of 550µA, so corresponding slew rates for compensation 30063218
capacitor values are shown in Table 6.
FIGURE 18. Single-Pole Compensation Slew Rate

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 AN-1850
The power bandwidth for the power amplifier at 150W into The PCB comes from the factory with RC2 (0Ω) installed for a
8Ω when using a 20pF compensation capacitor is 10Hz - single-pole compensation scheme and must be removed in
90kHz (±0.5dB) and 10Hz - 130kHz (±3dB) as shown in order for CC2 to be effective in the circuit. Mica capacitors from
Figure 19 below. The snubber is removed before taking the Cornell Dubilier are used for frequency compensation. Typi-
graph with the CT capacitor still in place. The slew rate limi- cally, the second compensation capacitor is chosen to be
tation of 24V/µs dominates the frequency response. between two and 10 times the value of CC1. A value five times
CC1 is a safe starting point. The resistance value is then se-
lected based on the location of the desired pole. Recom-
mended starting values are 12pF for CC2 and 5.1kΩ for RC1.

30063219

FIGURE 19. Single-Pole Compensation Power Bandwidth

vs Frequency

TWO-POLE COMPENSATION
In addition to single-pole compensation, there are component
placeholders on the EF125WT1 FET PCB amplifier module
for a two-pole compensation scheme as shown in Figure 20.
The addition of passive components RC1 and CC2 create a
pole at the frequency stated by the equation below. 30063220

fP2 = 1/2πCC2RC1 = 1/2π(62pF)(6.2kΩ) = 414kHz FIGURE 20. Two-Pole Compensation Connections

The two-pole compensation scheme allows for increased
loop gain at higher frequencies, resulting in increased slew Not only is there a reduction in higher frequency distortion,
rate, dynamics and reduced high-frequency distortion. Ex- there is also a power bandwidth benefit from using 2-pole
perimentation with these components will show the benefit of compensation as a result of increase slew rate.
reduced distortion at higher frequencies, but care must be
taken to not extend the pole out too far or instabilities may
result.

13 www.national.com
AN-1850 ply rails driving either an 8Ω or 4Ω load. These performance
Performance Graphs (±60V) graphs represent the high performance capabilities of the so-
The following pages contain standard audio performance lution.
graphs of the amplifier module, running off ±60V power sup-

FFT vs Frequency (Reading) FFT vs Frequency (Reading)

f = 1kHz, POUT = 1W, RL = 8Ω f = 1kHz, POUT = 10W, RL = 8Ω
22kHz BW 22kHz BW

30063239 30063236

FFT vs Frequency (Reading) FFT vs Frequency (Reading)

f = 1kHz, POUT = 50W, RL = 8Ω f = 1kHz, POUT = 150W, RL = 8Ω
22kHz BW 22kHz BW

30063242 30063237

THD+N vs Frequency THD+N vs Output Power

POUT = 1W, 50W, 150W, RL = 8Ω f = 20Hz, 1kHz, 20kHz, RL = 8Ω
80kHz BW 80kHz BW

30063248 30063252

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 AN-1850
THD+N vs Output Power THD+N vs Output Power
f = 1kHz, RL = 8Ω f = 20Hz, RL = 8Ω
22kHz and 80kHz BW 22kHz and 80kHz BW

30063250 30063254

FFT vs Frequency (Reading) FFT vs Frequency (Reading)

f = 1kHz, POUT = 1W, RL = 4Ω f = 1kHz, POUT = 10W, RL = 4Ω
22kHz BW 22kHz BW

30063238 30063235

FFT vs Frequency (Reading) FFT vs Frequency (Reading)

f = 1kHz, POUT = 50W, RL = 4Ω f = 1kHz, POUT = 300W, RL = 4Ω
22kHz BW 22kHz BW

30063209 30063240

15 www.national.com
AN-1850
THD+N vs Frequency THD+N vs Output Power
POUT = 1W, 50W, 300W, RL = 4Ω f = 20Hz, 1kHz, 20kHz, RL = 4Ω
80kHz BW 80kHz BW

30063247 30063251

THD+N vs Output Power THD+N vs Output Power

f = 1kHz, RL = 4Ω f = 20Hz, RL = 4Ω
22kHz and 80kHz BW 22kHz and 80kHz BW

30063249 30063253

Frequency Response
POUT = 300W, RL = 4Ω

30063231

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 AN-1850
Board Layer Views

30063226

FIGURE 21. PCB Composite View From Top

17 www.national.com
AN-1850

30063227

FIGURE 22. PCB Top Silk Screen View

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 AN-1850
30063228

FIGURE 23. PCB Top Layer View

19 www.national.com
AN-1850

30063225

FIGURE 24. PCB Bottom Layer View

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 AN-1850
Bill of Materials
Reference Value Tolerance Description Manufacturer Part Number
250V, metalized
CS1, CS2, CS3,
polyester film,
CS4, CS5, CS6, 0.1µF 10% Panasonic ECQ-E2104KF
7.5mm lead
CS9, CSN1
spacing
100V, radial
electrolytic,
CS7, CS8 470µF 20% Panasonic EEU-FC2A471
7.5mm lead
spacing
500V multilayer
CDE Cornell
CC1 20pF 5% mica, 3.6mm lead CD15ED200J03
Dubilier
spacing
500V multilayer
CDE Cornell
CB1 30pF 5% mica, 3.6mm lead CD15ED300J03
Dubilier
spacing
16V, radial
CB2, CM 47µF 20% electrolytic, 2mm Panasonic EEU-FC1C470
lead spacing
35V radial
electrolytic,
CI1 220µF 20% Panasonic EEU-FC1V221L
3.5mm lead
spacing
Polyester film,
CT 180pF 10% Panasonic ECQ-B1H181KF
5mm lead spacing
CC2, CI2, CI3 Not Used
500mW Zener Fairchild
D1 12V 5% 1N5242BTR
Diode, DO-35 Semiconductor
DG1, DG2, DG3,
1W Zener diode, Fairchild
DG4, DG5, DG6, 10V 5% 1N4740A
DO-41 Semiconductor
DG7, DG8
Complementary
MOSFET power National
U1 200V LME49830TB
amplifier input Semiconductor
stage
NPN transistor, Fairchild
QVBE1 80V, 1.5A BD13916STU
TO-126 Semiconductor
N-Channel
MOSFET, 150W,
Q1, Q3 200V, 12A Toshiba 2SK1530-YF
TO-3PL
(2-21F1B)
P-Channel
Q2, Q4 200V, 12A MOSFET, 150W, Toshiba 2SJ201-YF
TO-3PL(2-21F1B)
3 Watt metail
Vishay/ NFR0300001009J
RSN1 10Ω 5% oxide, axial
BCcomponents AC00
through hole
¼ Watt metal film, International
RG1, RG3 22.1Ω 1% MFR-25FBF-22R1
axial through hole Yageo Corp.
¼ Watt metal film, International
RG2, RG4 10.0Ω 1% MFR-25FBF-10R0
axial through hole Yageo Corp.
5 Watt silicone
RE1, RE2, RE3,
0.1Ω 1% wirewound, Vishay/Dale RS005R1000FS73
RE4
through hole

21 www.national.com
AN-1850 Reference Value Tolerance Description Manufacturer Part Number
¼ Watt metail film,
RC2 0Ω 5% Panasonic ERJ-S080R00V
SMT 1206 (3216)
¼ Watt metal film, International
RB1 392Ω 1% MFR-25FBF-392R
axial through hole Yageo Corp.
¼ Watt metal film, International
RB2 750Ω 1% MFR-25FBF-750R
axial through hole Yageo Corp.
¼ Watt metal film, International
RB3 1.10kΩ 1% MFR-25FBF-1K10
axial through hole Yageo Corp.
0.2 Watt single
turn
RP1 200Ω 25% Bourns Inc. 3306W-1-201
potentiometer,
through hole
¼ Watt metal film, International
RIN, RI 249Ω 1% MFR-25FBF-249R
axial through hole Yageo Corp.
¼ Watt metal film, International
RT, RF1 6.81kΩ 1% MFR-25FBF-6K81
axial through hole Yageo Corp.
¼ Watt metal film, International
RM1 75.0kΩ 1% MFR-25FBF-75K0
axial through hole Yageo Corp.
¼ Watt metal film, International
RM2 20.0kΩ 1% MFR-25FBF-20K0
axial through hole Yageo Corp.
¼ Watt metal film, International
RZ1 39.2kΩ 1% MFR-25FBF-39K2
axial through hole Yageo Corp.
RBO1, RBO2,
Note Used
RC1
SPDT On-On right
C&K
S1 20V angle, through ET01MD1ABE
Components
hole
3 pin 156mil
Molex/Waldom
J1 header, straight, 26-60-4030
Electronics Corp.
tin plating
2 pin 156mil
Molex/Waldom
J3 header, straight, 26-60-4020
Electronics Corp.
tin plating
RCA phono jack,
J4 Kobiconn 161-0097-E
PCB mount, black
2 pin 100mil
Molex/Waldom
J2, J9, J10, J12 header, straight, 22-23-2021
Electronics Corp.
tin plating
3 pin 100mil
Molex/Waldom
J11 header, straight, 22-03-2031
Electronics Corp.
tin plating
LME49830 heat
6.3°C/W Aavid Thermalloy 530101B00150
sink
Output stage heat
0.62°C/W Aavid Thermalloy 65605
sink, 4 inch length

www.national.com 22
 AN-1850
Revision History
Rev Date Description
1.0 07/01/08 Initial release.

23 www.national.com
LME49830TB Ultra-High Fidelity High Power Amplifier Reference Design
Notes

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AN-1850

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