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PRA2

The document describes the VHDL implementation of a digital system based on an AVR microcontroller. It explains the design of the main components like the control unit, ALU, registers and status register. It provides code examples to implement these components in VHDL.

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12 views13 pages

PRA2

The document describes the VHDL implementation of a digital system based on an AVR microcontroller. It explains the design of the main components like the control unit, ALU, registers and status register. It provides code examples to implement these components in VHDL.

Uploaded by

najlaecasalsgracia
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital Systems - Mini AVR 2

Pere Palà - Alexis López

iTIC http://itic.cat

April 2016
VHDL Implementation of the Status Register

type status_reg is
record
Z : std_logic ;
C : std_logic ;
end record ;

signal pr_SR ,
nx_SR : status_reg ;
Control Unit
I Input: Present opcode
I Decode the instruction
I Generate signals:
I Register write enable reg_we
I Output multiplexer selection: decide if data written to register
comes from:
I The present opcode (such as LDI)
I The ALU (such as ADC)
I Generate d and r register addresses d_reg, s_reg
I Indicate the desired operation to the ALU alu_op

Control: reg_we
out_mux
16
8 k
pr_op 4 d_reg
4 r_reg
3 alu_op
VHDL Implementation of the Control Unit (1/2)

type out_mux_type is ( mux_alu , mux_lit );


signal out_mux : out_mux_type ;

CONTROL : process ( pr_op , pr_pc )


begin
r_reg <= ( others = > ’ - ’); -- D e f a u l t s
d_reg <= ( others = > ’ - ’);
k <= ( others = > ’ - ’);
ALU_op <= ( others = > ’ - ’);
reg_we <= ’0 ’;
case pr_op (15 downto 12) is -- These bits are enough to
-- decide among our reduced
-- i n s t r u c t i o n set !
when NOP = > -- - - - - - - - - - - - - - - - - - - - - - - - NOP I n s t r u c t i o n
null ;

when LDI = > -- - - - - - - - - - - - - - - - - - - - - - - - LDI I n s t r u c t i o n


d_reg <= pr_op (7 downto 4);
out_mux <= mux_lit ;
k <= pr_op (11 downto 8) & pr_op (3 downto 0);
reg_we <= ’1 ’;
VHDL implementation of the Control Unit (2/2)

when MOV = > -- - - - - - - - - - - - - - - - - - - - - - - - MOV I n s t r u c t i o n


r_reg <= pr_op (3 downto 0); -- Source r e g i s t e r
d_reg <= pr_op (7 downto 4); -- D e s t i n a t i o n r e g i s t e r
out_mux <= mux_alu ;
reg_we <= ’1 ’; -- Enable r e g i s t e r write
ALU_op <= ALU_MOV ;

when ADC = > -- - - - - - - - - - - - - - - - - - - - - - - - ADC I n s t r u c t i o n


r_reg <= pr_op (3 downto 0);
d_reg <= pr_op (7 downto 4);
out_mux <= mux_alu ;
reg_we <= ’1 ’; -- Enable r e g i s t e r write
ALU_op <= ALU_ADC ;

when others = >


null ;
end case ;
end process ;

constant ALU_MOV : s td _ l o g i c _ v e c t o r (2 downto 0) := " 010 " ;


constant ALU_ADC : s td _ l o g i c _ v e c t o r (2 downto 0) := " 001 " ;
The ALU: Arithmetic and Logic Unit
I Inputs
I Operands alu_in_a, alu_in_b
I Operation code alu_op
I Status register (for carry) pr_SR
I Outputs
I Operation result alu_out
I Updated status register nx_SR
alu_in_a alu_in_b

alu_op ALU:

pr_SR
(Z,C) 8 2

alu_out nx_SR
(Z,C)
VHDL implementation of the ALU
ALU : process ( alu_op , alu_in_a , alu_in_b , pr_SR , add_temp )
begin
nx_SR <= pr_SR ; -- by default , p r e s e r v e status r e g i s t e r
add_temp <= ( others = > ’ - ’);
case alu_op is
when ALU_MOV = > -- - - - - - - - - - - - - - - - - - - - MOV : in_b --> out
alu_out <= alu_in_b ;
when ALU_ADC = > -- - - - - - - - - - - - - - - - - - - - ADC : Carry in / out
add_temp <= s t d _ l o g i c_ v e c t o r ( -- a u x i l i a r SLV (9..0)
unsigned ( ’0 ’ & alu_in_a & ’1 ’) +
unsigned ( ’0 ’ & alu_in_b & pr_SR . C )); -- Carry In
alu_out <= add_temp (8 downto 1);
nx_SR . C <= add_temp (9); -- Update Carry Flag
if add_temp (8 downto 1) = x " 00 " then -- Update Zero Flag
nx_SR . Z <= ’1 ’;
else
nx_SR . Z <= ’0 ’;
end if ;
when others = > -- - - - - - - - - - - - - - - - - - - - - - - - - Should not happen
alu_out <= ( others = > ’ - ’); -- Don ’ t care
end case ;
end process ;
Register Data-In Multiplexer

I Decide which data has to be stored in one of the registers


I Data from the ALU, as in ADC or MOV instructions
I Data from the opcode, as in the LDI instruction

nx_reg

8
out_mux

8 8

k alu_out
VHDL implementation of the Register Multiplexer

MUX : process ( out_mux , alu_out , k )


begin
case out_mux is
when mux_alu = > nx_reg <= alu_out ;
when mux_lit = > nx_reg <= k ;
when others = > nx_reg <= ( others = > ’ - ’);
end case ;
end process ;
Synchronous Elements

I Registered signals
I Program counter pr_pc
I Stauts register pr_SR

pr_pc pr_SR
(Z,C)
2

+1

8 2
nx_pc clk
clk nx_SR
(Z,C)
VHDL implementation of the Synchronous Elements

process ( clk , reset ) -- S y n c h r o n o u s e l e m e n t s


begin
if reset = ’1 ’ then -- I n i t i a l i z e P r o c e s s o r
pr_pc <= ( others = > ’0 ’);
pr_SR . C <= ’0 ’;
pr_SR . Z <= ’0 ’;
elsif ( rising_edge ( clk )) then
pr_pc <= nx_pc ;
pr_SR <= nx_SR ;
end if ;
end process ;

nx_pc <= s t d _ l o g i c _ v e c t o r ( unsigned ( pr_pc ) + 1);


Whole Processor

I Entity
entity mini_avr_01 is
port (
clk : in std_logic ;
reset : in std_logic ;
-- Let ’ s have some r e g i s t e r s as outputs :
r16 : out s t d _ l o g i c _ v e c t o r ( 7 downto 0);
r17 : out s t d _ l o g i c _ v e c t o r ( 7 downto 0)
);
end entity ;

I Auxiliar signals for debugging


r16 <= regs (0);
r17 <= regs (1);
debug_carry <= pr_SR . C ;
debug_zero <= pr_SR . Z ;
Simulation

NOP
LDI r16,x83
x83+x83=x106 ADC r16,r16
ADC r16,r16
MOV r17,r16
NOP

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