Digital Systems - Mini AVR 1

Pere Palà - Alexis López

iTIC http://itic.cat

March 2016
Processor Basics

I Processor: A specific (and interesting)

(and complex) kind of digital system
I A processor inside a digital system
I Specialized tasks
I Multiple small processors
I Other digital circuitry complements the
system
I Processor basics
I A list of instructions
I Space to store data
I Core that acts according to instructions Intel 4004
I Input and output ports to interact with
the real world
I Architectures
I Von Neumann
I Harvard
Harvard Architecture

I Separate memories
I Program (instruction) memory
I Data memory

Program Data
CPU
Memory Memory

Separate buses

I Allows accessing instructions and data simultaneously

I Eliminates bottleneck of common bus
I Common in small micro-controllers, such as the Atmel AVR
The Mini AVR
I Objective
I To build a small AVR-compatible micro-controller
I With a reduced number of instructions
I Why?
I Just for fun!
I To be able to port an AVR program to our micro-controller
I Instructions
I NOP : No operation
I LDI : Load immediate
I ADC : Add with carry
I MOV : Move
I AND, OR, EOR : And, or, exclusive-or operations
I RJMP : Relative jump
I BREQ : Branch if equal
I Some flags of the Status Register (SREG)
I C: Carry Flag
I Z: Zero Flag
Overview (don’t panic yet!)

reg_we
RegW: 8
nx_reg 8

Control: clk
out_mux
ROM: 16 8 k 4 4
4
pr_op d_reg
r_reg 8 8
alu_in_a alu_in_b
pr_pc alu_op 3
pr_SR ALU:
8
(Z,C)
2
alu_out 8
+1

8 2
nx_pc
clk clk nx_SR
(Z,C)
Documentation of AVR instructions : NOP

I NOP – No Operation
I Description
I This instruction performs a single cycle No Operation.
I Operation: No
I Syntax: NOP
I Operands: None
I Program Counter: PC ← PC + 1
I 16-bit Opcode: 0000 0000 0000 0000
I Status Register (SREG) and Boolean Formula:
I T H S V N Z C
- - - - - - - -
Documentation of AVR instructions : LDI

I LDI – Load Immediate

I Description:
I Loads an 8 bit constant directly to register 16 to 31.
I Operation: Rd ← K
I Syntax: LDI Rd,K
I Operands: 16 ≤ d ≤ 31, 0 ≤ K ≤ 255
I Program Counter: PC ← PC + 1
I 16-bit Opcode: 1110 KKKK dddd KKKK
I Status Register (SREG) and Boolean Formula:
I T H S V N Z C
- - - - - - - -
Documentation of AVR instructions : ADC
I ADC – Add with Carry
I Description:
I Description: Adds two registers and the contents of the C Flag
and places the result in the destination register Rd.
I Operation: Rd ← Rd + Rr + C
I Syntax: ADC Rd,Rr
I Operands: 0 ≤ d ≤ 31, 0 ≤ r ≤ 31
I Program Counter: PC ← PC + 1
I 16-bit Opcode: 0001 11rd dddd rrrr
I Status Register (SREG) and Boolean Formula:
I T H S V N Z C
- - ⇔⇔⇔⇔⇔⇔
I Z: Set if the result is x”00”; cleared otherwise.
I C: Set if there was carry from the MSB of the result; cleared
otherwise
Documentation of AVR instructions : MOV

I MOV – Copy Register

I Description:
I This instruction makes a copy of one register into another.
The source register Rr is left unchanged, while the destination
register Rd is loaded with a copy of Rr.
I Operation: Rd ← Rr
I Syntax: MOV Rd,Rr
I Operands: 0 ≤ d ≤ 31, 0 ≤ r ≤ 31
I Program Counter: PC ← PC + 1
I 16-bit Opcode: 0010 11rd dddd rrrr
I Status Register (SREG) and Boolean Formula:
I T H S V N Z C
- - - - - - - -
References

I Further information:
I 8-bit AVR Instruction Set
I http://ww1.microchip.com/downloads/en/devicedoc/
atmel-0856-avr-instruction-set-manual.pdf
Registers

I Implement only registers from 16 to 31

I ADC 16-bit Opcode
I 0001 11rd dddd rrrr
I 0001 1111 dddd rrrr
I No stack, stack pointer, etc
reg_we
RegW: 8
nx_reg 8

clk

4 4
4
d_reg
r_reg 8 8
alu_in_a alu_in_b
VHDL implementation of registers

type register_bank is
array (15 downto 0) of s t d _ l o g i c _ v e ct o r (7 downto 0);
signal regs : register_bank ; -- R e g i s t e r s r16 .. r31

RegW : process ( clk ) -- R e g i s t e r write

begin
if rising_edge ( clk ) then
if reg_we = ’1 ’ then -- write
regs ( to_integer ( unsigned ( d_reg ))) <= nx_reg ;
end if ;
end if ;
end process RegW ;

-- R eg i s t e r read : ALU inputs

alu_in_a <= regs ( to_integer ( unsigned ( d_reg )));
alu_in_b <= regs ( to_integer ( unsigned ( r_reg )));
Program ROM

I 256 positions (arbitrary limit)

I Program Counter has to be 8 bits long
I 16-bit opcodes
I Not clocked: Purely combinational ROM
I Given pr_pc, the present program counter, the system
outputs pr_op, the present opcode

ROM: 16
pr_op

8
pr_pc
Program listing
I A simple program code:
NOP ; do nothing
LDI r16 , x83 ; r16 ← x83
ADC r16 , r16 ; x83 + x83 = x106 : r16 ← 06 and C is set !
ADC r16 , r16 ; x06 + x06 + x01 = x0D and C is cleared
MOV r17 , r16 ; r17 ← x0D
NOP : do nothing

I NOP : 0000 0000 0000 0000

I LDI : 1110 kkkk dddd kkkk
I ADC : 0001 1111 dddd rrrr (0001 11rd dddd rrrr)
I MOV : 0010 1111 dddd rrrr (0010 11rd dddd rrrr)
I The first 4 bits are enough to determine the instruction
I VHDL definition:
constant NOP : s t d _ l o gi c _ v e c t o r (3 downto 0) := " 0000 " ;
constant LDI : s t d _ l o gi c _ v e c t o r (3 downto 0) := " 1110 " ;
constant ADC : s t d _ l o gi c _ v e c t o r (3 downto 0) := " 0001 " ;
constant MOV : s t d _ l o gi c _ v e c t o r (3 downto 0) := " 0010 " ;
VHDL implementation of the program memory
ROM : process ( pr_pc ) -- Program ROM
begin
case pr_pc is
when X " 00 " = >
pr_op <= NOP & " 0000 " & " - -- - - - - - " ; -- NOP
when X " 01 " = >
pr_op <= LDI & " 1000 " & " 0000 " & " 0011 " ; -- LDI r16 , x83
when X " 02 " = >
pr_op <= ADC & " 1111 " & " 0000 " & " 0000 " ; -- ADC r16 , r16
when X " 03 " = >
pr_op <= ADC & " 1111 " & " 0000 " & " 0000 " ; -- ADC r16 , r16
when X " 04 " = >
pr_op <= MOV & " 1111 " & " 0001 " & " 0000 " ; -- MOV r17 , r16
when X " 05 " = >
pr_op <= NOP & NOP & " --------"; -- NOP
when others = > pr_op <= ( others = > ’ - ’);
end case ;
end process ;

I This works as a first try! Later we will learn to describe a

ROM in a way that allows the synthesis tools to choose
(much) better implementations.