LTM 8060

LTM8060
Quad 40VIN, Silent Switcher μModule Regulator

with Configurable 3A Output Array
FEATURES DESCRIPTION
n Four Complete Step-Down Switching Power Supplies The LTM ®8060 is quad 40V IN, 3A step-down
n Low Noise Silent Switcher® Architecture Silent Switcher μModule® regulator. The Silent Switcher
n CISPR22 Class B and CISPR25 Class 5 Compliant architecture minimizes EMI while delivering high efficiency
n Wide Input Voltage Range: 3V to 40V at frequencies up to 3MHz. Included in the package are the
n Wide Output Voltage Range: 0.8V to 8V controllers, power switches, inductors, and support com-
n 3A Continuous Output Current per Channel at 12VIN, ponents. Operating over a wide input voltage range, the
3.3VOUT, TA = 80°C LTM8060 supports output voltages from 0.8V to 8V, and
n 4A Continuous Output Current per Channel at 12VIN, a switching frequency range of 200kHz to 3MHz, each set
3.3VOUT, fSW = 2MHz, TA = 60°C by a single resistor. Only the bulk input and output filter
n Multiphase or Multi-μModule Parallelable for capacitors, are needed to finish the design. The LTM8060
Increased Output Current product video is available on website.
n Low Thermal Resistance, θJA = 8.4°C/W, The LTM8060 is packaged in a compact (16mm × 11.9mm
θJCtop = 5.0°C/W, θJCbot = 1.8°C/W × 3.32mm) over-molded ball grid array (BGA) package
n Selectable Switching Frequency: 200kHz to 3MHz suitable for automated assembly by standard surface
n Compact Package mount equipment. The LTM8060 is RoHS compliant.
Configurable Output Array
APPLICATIONS
The LTM8060 outputs can be paralleled in an array for up
n Automated Test Equipment to 12A capability.
n Industrial Supplies 3A
n Medical Equipment 3A
6A
9A
12A
3A
All registered trademarks and trademarks are the property of their respective owners. 6A
3A 3A
TYPICAL APPLICATION
Quad 3A Output from 8.5V to 40V Input Efficiency, VIN = 24V, BIAS = 5V
95
VIN1 BIAS12
VIN
RUN1 AUX1 90
8.5V TO 40V
VOUT1 VOUT1
5V 85
27.4k
RT12 3A
47µF
EFFICIENCY (%)
47.5k 80
fSW = 1.2MHz
FB1
SYNC12 75
VOUT2 VOUT2
3.3V 70
3A
47µF
VIN2 78.7k 65
FB2
RUN2 5VOUT
LTM8060 GND 60
3.3VOUT
PINS NOT USED: VIN34
AUX2, AUX3, TRSS1, BIAS34 EXTERNAL 5V 55
TRSS2, TRSS3, RUN3 0 1 2 3 4
RUN4 VOUT3 VOUT3 LOAD CURRENT (A)
TRSS4, SHARE1,
1.5V 8060 TA01b
SHARE2, SHARE3, 64.9k 100µF 3A
SHARE4, PG1, RT34
fSW = 600kHz 287k ×2
PG2, PG3, PG4, FB3
CLKOUT12, SYNC34
CLKOUT34 VOUT4 VOUT4
1V
100µF 3A
1M ×2
4.7µF FB4
×4
GND
8060 TA01a
Rev. C
Document Feedback For more information www.analog.com 1

LTM8060
ABSOLUTE MAXIMUM RATINGS (Note 1)
VINn, RUNn, PGn .......................................................42V Maximum Internal Temperature (Note 2)............... 125°C
VOUTn, BIASn, AUXn .................................................10V Storage Temperature ............................. –55°C to 125°C
FBn, TRSSn, SHAREn, RTn .........................................4V Peak Solder Reflow Package Body Temperature ... 245°C
SYNCn ........................................................................6V
PIN CONFIGURATION
TOP VIEW
SYNC12 RUN2 RUN1 FB1 RT12 TRSS2 TRSS1

11
BANK4 BANK6
CLKOUT12 PG2 DNC VIN2 VIN1 FB2 AUX2 BIAS12 AUX1
10
BANK3 BANK8
VOUT2 PG1 SHARE2 VOUT1
9
SHARE1
8
7
BANK2 GND
6
5
SHARE3
4
SHARE4 PG3
3
BANK1 BANK7
VOUT3 AUX3 BIAS34 AUX4 FB4 DNC PG4 CLKOUT34 VOUT4
2
TRSS3 TRSS4 RT34 FB3 BANK5 VIN34 RUN3 RUN4 SYNC34

1
A B C D E F G H J K L M N P R
BGA PACKAGE
165-PIN (16mm × 11.9mm × 3.32mm)
TJMAX = 125°C; θJA = 8.4°C/W;
θJC_top = 5.0°C/W; θJC_bottom =1.8°C/W; WEIGHT = 1.98g
NOTES:
1) θ VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS.
2) θJA VALUE IS OBTAINED WITH DEMO BOARD.
3) REFER TO APPLICATIONS INFORMATION SECTION FOR LAB MEASUREMENT AND
DERATING INFORMATION.
ORDER INFORMATION
PART MARKING PACKAGE MSL TEMPERATURE RANGE
PART NUMBER BALL FINISH DEVICE FINISH CODE TYPE RATING (SEE NOTE 2)
LTM8060EY#PBF SAC305 (RoHS) LTM8060Y e1 BGA 4 –40°C to 125°C
LTM8060IY#PBF SAC305 (RoHS) LTM8060Y e1 BGA 4 –40°C to 125°C
• Device temperature grade is indicated by a label on the shipping container. • This product is not recommended for second side reflow.
This product is moisture sensitive. For more information, go to
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
Recommended BGA PCB Assembly and Manufacturing Procedures.
• BGA Package and Tray Drawings
Rev. C
2 For more information www.analog.com

LTM8060
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
internal temperature range, otherwise specifications are at TA = 25°C. VINn = 12V, RUNn = 2V unless otherwise noted (Notes 2, 3).
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum VIN1 Input Voltage l 3.0 V
Minimum VIN34 Input Voltage l 3.0 V
Minimum VIN2 Input Voltage VIN1 = 3V l 2.0 V
Output DC Voltage FBn Open 0.8 V
FBn = 21.5k 10 V
Maximum Output DC Current (Note 4) 6 A
Quiescent Current into VINn RUNn = 0 8 μA
BIASn = 5V, SYNCn = 3.3V, No Load 7 mA
Current into BIASn RUNn = 0, BIASn = 5V 0.5 μA
BIASn = 5V, SYNCn = 3.3V, No Load 18 mA
Line Regulation 5V < VINn < 40V, IOUTn = 1A 0.05 %
Load Regulation 12VINn, 0.1A < IOUTn < 4A 0.1 %
Output RMS Ripple 3.3VOUTn, IOUTn = 4A 10 mV
FBn Voltage 792 800 808 mV
l 784 800 816 mV
Current out of FBn VOUTn = 1V, FBn = 0V 4 μA
Minimum BIASn for Proper Operation 3.2 V
Switching Frequency RTn = 200k 200 kHz
RTn = 35.7k 1 MHz
RTn = 8.06k 3 MHz
RUNn Threshold 0.74 V
RUNn Input Current RUNn = 0V 100 nA
PGn Threshold at FBn Lower Threshold 740 mV
Upper Threshold 860 mV
PGn Output Sink Current PGn = 0.1V 100 μA
CLKOUTn VOL 0.2 V
CLKOUTn VOH 3.2 V
SYNCn Input High Threshold 1.5 V
SYNCn Input Low Threshold 0.8 V
SYNCn Threshold to Enable Spread Spectrum 2.8 4.0 V
SYNCn Current SYNCn = 6V 60 μA
TRSSn Source Current TRSSn = 0V 2 μA
TRSSn Pull-Down Resistance Fault Condition, TRSSn = 0.1V 200 Ω
Note 1: Stresses beyond those listed under Absolute Maximum Ratings LTM8060I is guaranteed to meet specifications over the full –40°C to
may cause permanent damage to the device. Exposure to any Absolute 125°C internal operating temperature range. Note that the maximum
Maximum Rating condition for extended periods may affect device internal temperature is determined by specific operating conditions in
reliability and lifetime. conjunction with board layout, the rated package thermal resistance and
Note 2: The LTM8060E is guaranteed to meet performance specifications other environmental factors.
from 0°C to 125°C internal. Specifications over the full –40°C to Note 3: n Represents each individual channel. Four outputs are tested
125°C internal operating temperature range are assured by design, separately and the same testing condition is applied to each output.
characterization and correlation with statistical process controls. The Note 4: The maximum current out of any channel may be limited by the
internal temperature of the LTM8060. See output current derating curves
for different VIN, VOUT and TA.
Rev. C
For more information www.analog.com 3

LTM8060
TYPICAL
T PERFORMANCE CHARACTERISTICS A = 25°C, operating per Table 1,unless otherwise noted.
Efficiency and Power Loss Efficiency and Power Loss Efficiency and Power Loss
VOUT = 0.8V, BIAS = 5V, Burst Mode VOUT = 1V, BIAS = 5V, Burst Mode VOUT = 1.2V, BIAS = 5V, Burst Mode
90 4 90 4 90 4
EFFICIENCY
EFFICIENCY EFFICIENCY
80 3 80 3 80 3
POWER LOSS (W)
POWER LOSS (W)
POWER LOSS (W)

EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
70 2 70 2 70 2
12V 12V 12V
24V 24V 24V
36V 36V 36V
60 1 60 1 60 1
POWER LOSS POWER LOSS POWER LOSS

50 0 50 0 50 0
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
8060 G01 8060 G02 8060 G03
VOUT = 1.5V, BIAS = 5V, Burst Mode VOUT = 1.8V, BIAS = 5V, Burst Mode VOUT = 2V, BIAS = 5V, Burst Mode
95 4 95 4 95 4
EFFICIENCY
85 3 85 3 85 3
POWER LOSS (W)
POWER LOSS (W)

POWER LOSS (W)
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
75 2 75 2 75 2
12V 12V 12V
24V 24V 24V
36V 36V 36V
65 1 65 1 65 1
POWER LOSS POWER LOSS POWER LOSS

55 0 55 0 55 0
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4
8060 G04 8060 G05 8060 G06
VOUT = 2.5V, BIAS = 5V, Burst Mode VOUT = 3.3V, BIAS = 5V, Burst Mode VOUT = 5V, BIAS = 5V, Burst Mode
95 4 100 4 100 4
EFFICIENCY
85 3 90 3 90 3
POWER LOSS (W)
POWER LOSS (W)

POWER LOSS (W)
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
75 2 80 2 80 2
12V 12V 12V
24V 24V 24V
36V 36V 36V
65 1 70 1 70 1
POWER LOSS POWER LOSS

POWER LOSS
55 0 60 0 60 0
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4
8060 G07 8060 G08 8060 G09
Rev. C

LTM8060
TYPICAL
Efficiency and Power Loss Input vs Load Current, VOUT = 0.8V Input vs Load Current, VOUT = 1V
VOUT = 8V, BIAS = 5V, Burst Mode BIAS = 5V Burst Mode BIAS = 5V, Burst Mode
100 4 0.4 0.6
EFFICIENCY 12VIN 12VIN
24VIN 24VIN
36VIN 36VIN
90 3 0.3
INPUT CURRENT (A)
INPUT CURRENT (A)

0.4
POWER LOSS (W)

EFFICIENCY (%)
80 12V 2 0.2
24V
36V
0.2
70 1 0.1
POWER LOSS
60 0 0 0
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4
8060 G10 8060 G11 8060 G12
Input vs Load Current, VOUT = 1.2V Input vs Load Current, VOUT = 1.5V Input vs Load Current, VOUT = 1.8V
BIAS = 5V, Burst Mode BIAS = 5V, Burst Mode BIAS = 5V, Burst Mode
0.6 0.8 0.8
12VIN 12VIN 12VIN
24VIN 24VIN 24VIN
36VIN 36VIN 36VIN
0.6 0.6
INPUT CURRENT (A)

INPUT CURRENT (A)
INPUT CURRENT (A)
0.4
0.4 0.4
0.2
0.2 0.2
0 0 0
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4
8060 G13 8060 G14 8060 G15
Input vs Load Current, VOUT = 2V Input vs Load Current, VOUT = 2.5V Input vs Load Current, VOUT = 3.3V
BIAS = 5V, Burst Mode BIAS = 5V, Burst Mode BIAS = 5V, Burst Mode
0.8 1.2 1.6
12VIN 12VIN 12VIN
24VIN 24VIN 24VIN
36VIN 36VIN 36VIN
0.6 0.9 1.2
INPUT CURRENT (A)
INPUT CURRENT (A)
INPUT CURRENT (A)
0.4 0.6 0.8
0.2 0.3 0.4
0 0 0
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4
8060 G16 8060 G17 8060 G18
Rev. C

LTM8060
TYPICAL
Derating, VOUT = 0.8V
BIAS = 5V, DC2820A Demo Board
Input vs Load Current, VOUT = 5V Input vs Load Current, VOUT = 8V TJ = 120°C, Burst Mode
BIAS = 5V, Burst Mode BIAS = 5V, Burst Mode All Channels at Same Load
2.0 3.2 18.0
12VIN 12VIN
16.0 0LFM
MAXIMUM TOTAL LOAD CURRENT (A)

24VIN 24VIN
36VIN 36VIN
14.0
1.5 2.4
INPUT CURRENT (A)
INPUT CURRENT (A)

12.0
10.0
1.0 1.6
8.0
6.0
0.5 0.8
4.0 12VIN
24VIN
2.0 36VIN
0 0 0
0 1 2 3 4 0 1 2 3 4 0 25 50 75 100 125
LOAD CURRENT (A) LOAD CURRENT (A) AMBIENT TEMPERATURE (° C)
8060 G19 8060 G20 8060 G21
Derating, VOUT = 1V Derating, VOUT = 1.2V Derating, VOUT = 1.5V

BIAS = 5V, DC2820A Demo Board BIAS = 5V, DC2820A Demo Board BIAS = 5V, DC2820A Demo Board
TJ = 120°C, Burst Mode TJ = 120°C, Burst Mode TJ = 120°C, Burst Mode
All Channels at Same Load All Channels at Same Load All Channels at Same Load
18.0 18.0 18.0
16.0 0LFM 16.0 0LFM 16.0 0LFM

14.0 14.0 14.0
12.0 12.0 12.0
10.0 10.0 10.0
8.0 8.0 8.0
6.0 6.0 6.0
4.0 12VIN 4.0 12VIN 4.0 12VIN

24VIN 24VIN 24VIN
2.0 2.0 2.0 36VIN
36VIN 36VIN
0 0 0
0 25 50 75 100 125 0 25 50 75 100 125 0 25 50 75 100 125
AMBIENT TEMPERATURE (° C) AMBIENT TEMPERATURE (° C) AMBIENT TEMPERATURE (° C)
8060 G22 8060 G23 8060 G24
Derating, VOUT = 1.8V Derating, VOUT = 2V Derating, VOUT = 2.5V

18.0 18.0 18.0
16.0 0LFM 16.0 0LFM 16.0 0LFM


14.0 14.0 14.0
12.0 12.0 12.0
10.0 10.0 10.0
8.0 8.0 8.0
6.0 6.0 6.0
4.0 12VIN 4.0 12VIN 4.0 12VIN

24VIN 24VIN 24VIN
2.0 2.0 36VIN 2.0
36VIN 36VIN
0 0 0
0 25 50 75 100 125 0 25 50 75 100 125 0 25 50 75 100 125
8060 G25 8060 G26 8060 G27
Rev. C

LTM8060
TYPICAL
Derating, VOUT = 3.3V Derating, VOUT = 3.3V, fSW = 2MHz Derating, VOUT = 5V
18.0 18.0 18.0
16.0 0LFM 16.0 0LFM 16.0 0LFM


14.0 14.0 14.0
12.0 12.0 12.0
10.0 10.0 10.0
8.0 8.0 8.0
6.0 6.0 6.0
4.0 12VIN 4.0 12VIN 4.0 12VIN

24VIN 24VIN 24VIN
2.0 36VIN 2.0 36VIN 2.0 36VIN
0 0 0
0 25 50 75 100 125 0 25 50 75 100 125 0 25 50 75 100 125
8060 G28 8060 G29 8060 G30
Derating, VOUT = 5V, fSW = 2MHz Derating, VOUT = 8V CISPR22 Class B Emissions
BIAS = 5V, DC2820A Demo Board BIAS = 5V, DC2820A Demo Board DC2820A Demo Board
TJ = 120°C, Burst Mode TJ = 120°C, Burst Mode VIN = 24V, VOUT = 5V, fSW = 1.2MHz
All Channels at Same Load All Channels at Same Load All Channels Paralleled, IOUT = 10A
18.0 18.0 55
16.0 0LFM 16.0 0LFM

45
14.0 14.0
AMPLITUDE (dBuV/m)
12.0 12.0 35
10.0 10.0
25
8.0 8.0
6.0 6.0 15
4.0 12VIN 4.0 12VIN NOISE FLOOR

24VIN 5 FIXED FREQUENCY
24VIN
2.0 36VIN 2.0 SPREAD SPECTRUM
36VIN
CLASS B PEAK LIMIT
0 0 –5
0 25 50 75 100 125 0 25 50 75 100 125 0 200 400 600 800 1000
AMBIENT TEMPERATURE (° C) AMBIENT TEMPERATURE (° C) FREQUENCY (MHz)
8060 G31 8060 G32 8060 G33
CISPR25 Radiated Emission with Class 5 Output Voltage Ripple Output Noise Spectrum
Peak Limit DC2820A Demo Board DC2820A Demo Board DC2820A Demo Board
VIN = 14V, VOUT = 5V, fSW = 1.2MHz VIN = 12V, VOUT = 3.3V VIN = 24V, VOUT = 5V
All Channels Paralleled, IOUT = 12A IOUT = 3A, fSW = 1MHz IOUT = 3A, fSW = 1.2MHz
50 60
NOISE FLOOR
NORMALIZED OUTPUT NOISE
40
40
OUTPUT NOISE (dBμV/Hz)
AMPLITUDE (dBuV/m)
20
30 5mV/DIV
AC-COUPLED 0
20
–20
10 8060 G35 –40

CLASS 5 PEAK LIMIT 500ns/DIV
SPREAD SPECTRUM
FIXED FREQUENCY
0 –60
0 200 400 600 800 1000 0.01 0.1 1 10 100 1k
FREQUENCY (MHz) FREQUENCY (MHz)
8060 G34 8060 G36
Rev. C

LTM8060
TYPICAL
BIAS Current vs Frequency
12VIN to 3.3VOUT Input Current vs VIN
Forced Continuous Mode Dropout Voltage vs Load Current VOUT Short-Circuited
25 1.6 2000
Burst Mode OPERATION
FORCED CONTINUOUS MODE
20
1.2 1500
DROPOUT VOLTAGE (V)
INPUT CURRENT (mA)

BIAS CURRENT (mA)
15
0.8 1000
10
0.4 500
5
0 0 0
0 1 2 3 0 2 4 6 5 10 15 20 25 30 35 40
SWITCHING FREQUENCY (MHz) LOAD CURRENT (A) VIN (V)
8060 G37 8060 G38 8060 G39
Single Channel Derating, VOUT = Single Channel Derating, VOUT = Single Channel Derating, VOUT =
1.5V CH1 ON, CH2-CH4 OFF 3.3V CH1 ON, CH2-CH4 OFF 5V CH1 ON, CH2-CH4 OFF
7 7 7
0LFM 0LFM 0LFM
6 6 6
LOAD CURRENT PER CHANNEL (A)

5 5 5
4 4 4
3 3 3
2 2 2
12V 12V 12V
1 24V 1 24V 1 24V
36V 36V 36V
0 0 0
0 25 50 75 100 125 0 25 50 75 100 125 0 25 50 75 100 125
8060 G40 8060 G41 8060 G42
Dual Channel Derating, VOUT = Dual Channel Derating, VOUT = Dual Channel Derating, VOUT = 5V
1.5V CH1/CH3 ON, CH2/CH4 OFF 3.3V CH1/CH3 ON, CH2/CH4 OFF CH1/CH3 ON, CH2/CH4 OFF
7 7 7
0LFM 0LFM 0LFM
6 6 6
5 5 5
4 4 4
3 3 3
2 2 2
12V 12V 12V
1 24V 1 24V 1 24V
36V 36V 36V
0 0 0
0 25 50 75 100 125 0 25 50 75 100 125 0 25 50 75 100 125
8060 G43 8060 G44 8060 G45
Rev. C

LTM8060
PIN FUNCTIONS
GND (Bank 2): Tie these GND pins to a local ground plane SYNC12,34 (Pins C11, N1): External Clock Synchronization
below the LTM8060 and the circuit components. In most Input. Ground these pins for low ripple Burst Mode®
applications, the bulk of the heat flow out of the LTM8060 operation at low output loads; this will also disable the
is through these pads, so the printed circuit design has a CLKOUT function. Apply a DC voltage between 2.8V and
large impact on the thermal performance of the part. See 4V for forced continuous mode operation with spread
the PCB Layout and Thermal Considerations sections for spectrum modulation. Float the SYNCn pin for forced
more details. Return the feedback divider (RFB) to this net. continuous mode operation without spread spectrum
modulation. Apply a clock source to the SYNCn pin for
VIN2 (Bank 4): Input power for the channel 2 regulator.
synchronization to an external frequency. The LTM8060
Decouple VIN2 to ground with an external, low ESR capaci-
will be in forced continuous mode when an external fre-
tor. See Table 1 for recommended values.
quency is applied.
VIN34 (Bank 5): Input power for the channel 3 and channel
PG1-4 (Pins E9, D10, L3, M2): The PGn pins are the
4 regulator. The VIN34 bank powers the internal control cir-
open-drain output of an internal comparator. PGn remains
cuitry for both channel 3 and channel 4 and is monitored
low until the FBn pin is within ±7.5% of the final regulation
by undervoltage lockout circuitry. The VIN34 voltage must
voltage, and there are no fault conditions. PGn is pulled
be greater than 3V for either channel 3 and channel 4 of
low during VINn UVLO, thermal shutdown, or when the
the LTM8060 to operate. Decouple VIN34 to ground with
RUNn pins are low.
an external, low ESR capacitor. See Table 1 for recom-
mended values. DNC (Pins E10, L2): Do not connect.
VIN1 (Bank 6): Input power for the channel 1 regulator. RUN1-4 (Pins E11, D11, L1, M1): The corresponding
The VIN1 powers the internal control circuitry for chan- channel of the LTM8060 is shutdown when these pins
nel 1 and channel 2 and is monitored by undervoltage are low and active when these pins are high. Tie to VINn if
lockout circuitry. The VIN1 voltage must be greater than shutdown feature is not used. An external resistor divider
3V for either channel 1 and channel 2 of the LTM8060 to from VINn can be used to program a VINn threshold below
operate. Decouple VIN1 to ground with an external, low which the corresponding channel of the LTM8060 will
ESR capacitor. See Table 1 for recommended values. shut down. Do not float these pins.
VOUT1-4 (Banks 8, 3, 1, 7): Power Output for Channel 1, SHARE1-4 (Pins K8, K9, F4, F3): Channel 1 through
through Channel 4, Respectively. Apply the output filter Channel 4 Current Sharing Control. Tie SHAREn together
capacitor and the output load between these pins and when paralleling outputs. LTM8060 can also share cur-
GND plane. rent between modules. See Typical Application section
for current sharing between channels and current sharing
CLKOUT12,34 (Pins C10, N2): Synchronization Output.
between modules.
When SYNC12,34 > 2.8V, the CLKOUT12,34 pins provide
a waveform about 90 degrees out-of-phase with chan- FB1-4 (Pins K11, K10, F1, F2): The LTM8060 regulates
nel 1 and channel 3, respectively. This allows synchro- the FBn pin to 800mV. Connect the feedback resistor to
nization with other regulators with up to four phases. this pin to set the output voltage.
When an external clock is applied to the SYNC12,34 RT12,34 (Pins L11, E1): Connect a resistor between RTn
pins, the CLKOUT12,34 pins will output a waveform and ground to set the switching frequency. Do not drive
with about the same phase, duty cycle, and frequency these pins.
as the SYNC12,34 waveform. In Burst Mode operation,
the CLKOUT12,34 pins will be internally grounded. Float
these pin if the CLKOUT12,34 function is not used. Do
not drive these pins.
Rev. C

LTM8060
PIN FUNCTIONS
BIAS12,34 (Pins M10, D2): The internal regulator will TRSS1,2 (Pins N11, M11): Output Tracking and Soft-Start
draw current from BIASn instead of VIN1 or VIN34 when Pins. These pins allow user control of output voltage ramp
BIASn is tied to a voltage higher than 3.2V. For output rate during start-up. A TRSSn voltage below 0.8V forces
voltages of 3.3V and above these pins should be tied to the LTM8060 to regulate the FBn pin to equal the TRSSn
VOUTn. If these pins are tied to a supply other than VOUTn pin voltage. When TRSSn is above 0.8V, the tracking func-
use a local bypass capacitor on these pins. tion is disabled and the internal reference resumes control
of the error amplifier. An internal 2μA pull-up current on
AUX1-4 (Pins N10, L10, C2, E2): Low Current Voltage
these pins allow a capacitor to program output voltage
Source for BIAS. In many designs, the BIAS pin is simply
slew rate. These pins are pulled to ground during shut-
connected to VOUT by way of the AUX pin. The AUXn pins
down and fault conditions; use a series resistor if driving
are internally connected to VOUTn and placed adjacent
from a low impedance output. These pins may be left
to the BIASn pins to ease printed circuit board routing.
floating if the soft-start feature is not being used.
Although these pins are internally connected to VOUT, it
is not intended to deliver a higher current, so do NOT
connect these pins to the load. If these pins are not tied
to BIAS, leave it floating.
Rev. C

LTM8060
BLOCK DIAGRAM
VIN1
HOUSEKEEPING AUX1
10nF 1.5µH CIRCUITRY
RUN1 CURRENT MODE VOUT1
CONTROLLER 249k
TRSS1 10pF 0.1µF
±1% FB1
VIN2
AUX2
10nF 1.5µH
CONTROLLER 249k
TRSS2 10pF 0.1µF
±1% FB2
VIN34
HOUSEKEEPING AUX3
10nF 1.5µH CIRCUITRY
CONTROLLER 249k
TRSS3 10pF 0.1µF
±1% FB3
AUX4
1.5µH VOUT4
RUN4 CURRENT MODE
CONTROLLER
TRSS4 249k 10pF 0.1µF
FB4
CLKOUT12
CLKOUT34
SHARE1
SHARE2
SHARE3
SHARE4
SYNC12
SYNC34
BIAS12
BIAS34
RT12
RT34
PG1
PG2
PG3
PG4
8060 BD
Rev. C

LTM8060
OPERATION
The LTM8060 is a quad standalone nonisolated step- To enhance efficiency, the LTM8060 automatically
down switching DC/DC power supply that can deliver a switches to Burst Mode operation in light or no load
peak current of up to 6A per channel. The continuous cur- situations. Between bursts, all circuitry associated with
rent is determined by the internal operating temperature. controlling the output switch is shut down reducing the
It provides a precisely regulated output voltage program- input supply current to just a few µA.
mable via one external resistor from 0.8V to 8V. The input The TRSSn node acts as an auxiliary input to the error
voltage range for VIN1 and VIN34 is 3V to 40V, while the amplifier. The voltage at FBn servos to the TRSSn voltage
input voltage range for VIN2 is 2V to 40V. until TRSSn goes above 0.8V. Soft-start is implemented
Given that the LTM8060 is a step-down converter, make by generating a voltage ramp at the TRSSn pin using an
sure that the input voltage is high enough to support the external capacitor which is charged by an internal 2μA
desired output voltage and load current. See simplified constant current. Alternatively, driving the TRSSn pin with
Block Diagram. a signal source or resistive network provides a tracking
function. Do not drive the TRSSn pin with a low imped-
The LTM8060 contains current mode controllers, power
ance voltage source. See the Applications Information
switching elements, power inductors and a modest
section for more details.
amount of input and output capacitance. The LTM8060 is
a fixed frequency PWM regulator. The switching frequency The LTM8060 contains power good comparators which
is set by simply connecting the appropriate resistor value trip when the FBn pin is at about ±8% of its regulated
from the RTn pin to GND. value. The PGn output is an open-drain transistor that is
off when the output is in regulation, allowing an external
Internal regulators provide power to the control circuit-
resistor to pull the PGn pin high.
ries. Bias regulators normally draw power from the VINn
pin, but if the BIASn pin is connected to an external volt- The LTM8060 is equipped with a thermal shutdown that
age higher than 3.2V, bias power is drawn from the exter- inhibits power switching at high junction temperatures.
nal source (typically the regulated output voltage). This The activation threshold of this function is above the max-
improves efficiency. Tie BIASn to GND if it is not used. imum temperature rating to avoid interfering with normal
operation, so prolonged or repetitive operation under a
condition in which the thermal shutdown activates may
damage or impair the reliability of the device.
Rev. C

LTM8060
APPLICATIONS INFORMATION
For most applications, the design process is straight
forward, summarized as follows: CURRENT MODE
CONTROLLER VOUT
1. Look at Table 1 and find the row that has the desired 1.5µH
0.8V
input range and output voltage. 0.1µF 249k 10pF
2. Apply the recommended CIN, COUT, RFB and RT values. FB
3. Connect BIAS as indicated. RFB

8060 F01
When using the LTM8060 with different output voltages,

the higher frequency recommended by Table 1 will usu- Figure 1. Set Output Voltage with a FB Resistor
ally result in the best operation. While these component
combinations have been tested for proper operation, it is conditions. Applying capacitor values below those indi-
incumbent upon the user to verify proper operation over cated in Table 1 is not recommended and may result in
the intended system’s line, load and environmental condi- undesirable operation. Using larger values is generally
tions. Bear in mind that the maximum output current is acceptable, and can yield improved dynamic response,
limited by junction temperature, the relationship between if it is necessary. Again, it is incumbent upon the user to
the input and output voltage magnitude and other fac- verify proper operation over the intended system’s line,
tors. Please refer to the graphs in the Typical Performance load and environmental conditions.
Characteristics section for guidance. Ceramic capacitors are small, robust and have very low
The maximum frequency (and attendant RT value) at ESR. However, not all ceramic capacitors are suitable. X5R
which the LTM8060 should be allowed to switch is given and X7R types are stable over temperature and applied
in Table 1 in the Maximum fSW column, while the recom- voltage and give dependable service. Other types, includ-
mended frequency (and RT value) for optimal efficiency ing Y5V and Z5U have very large temperature and voltage
over the given input condition is given in the fSW column. coefficients of capacitance. In an application circuit they
There are additional conditions that must be satisfied if may have only a small fraction of their nominal capaci-
the synchronization function is used. Please refer to the tance resulting in much higher output voltage ripple
Synchronization section for details. than expected.
Ceramic capacitors are also piezoelectric. In Burst Mode
Set Output Voltage operation, the LTM8060’s switching frequency depends
The Output Voltage is programmed with a FB resistor as on the load current, and can excite a ceramic capacitor
shown in Figure 1. Choose the resistor value according at audio frequencies, generating audible noise. Since the
to Equation 1. LTM8060 operates at a lower current limit during Burst
Mode operation, the noise is typically very quiet to a
249kΩ
R FB = (1) casual ear.
VOUT
−1 If this audible noise is unacceptable, use a high perfor-
0.8V
mance electrolytic capacitor at the output. It may also be
1% resistor is recommended to maintain output a parallel combination of a ceramic capacitor and a low
voltage accuracy. cost electrolytic capacitor.
Capacitor Selection Considerations A final precaution regarding ceramic capacitors concerns

the maximum input voltage rating of the LTM8060. A
The CIN and COUT capacitor values in Table 1 are the mini- ceramic input capacitor combined with trace or cable
mum recommended values for the associated operating inductance forms a high-Q (underdamped) tank circuit.
Rev. C

LTM8060
Table 1. Recommended Component Values and Configuration (TA = 25°C)
VIN* VOUT RFB CIN** COUT BIAS CFF fSW RT MAX fSW MIN RT
(V) (V) (Ω) (μF) (μF) (V) (pF) (Hz) (kΩ) (Hz) (kΩ)
3 to 40 0.8 Open 4.7 50V X5R 1206 100 ×2 4V X5R 0805 3.2 to 10 100 400k 100 600k 64.9
3 to 40 1 1M 4.7 50V X5R 1206 100 ×2 4V X5R 0805 3.2 to 10 100 400k 100 725k 52.3
3 to 40 1.2 499k 4.7 50V X5R 1206 100 ×2 4V X5R 0805 3.2 to 10 68 500k 76.8 875k 42.2
3.2 to 40 1.5 287k 4.7 50V X5R 1206 100 ×2 4V X5R 0805 3.2 to 10 – 600k 64.9 1M 35.7
3.5 to 40 1.8 200k 4.7 50V X5R 1206 100 ×1 4V X5R 0805 3.2 to 10 – 650k 59 1.3M 25.5
3.5 to 40 2 165k 4.7 50V X5R 1206 100 ×1 4V X5R 0805 3.2 to 10 – 700k 54.9 1.4M 23.2
4.2 to 40 2.5 118k 4.7 50V X5R 1206 47 ×1 4V X5R 0805 3.2 to 10 – 800k 46.4 1.7M 18.2
5.5 to 40 3.3 78.7k 4.7 50V X5R 1206 47 ×1 6.3V X5R 0805 3.2 to 10 – 1M 35.7 2.2M 12.7
8.5 to 40 5 47.5k 4.7 50V X5R 1206 47 ×1 6.3V X5R 1206 3.2 to 10 – 1.2M 27.4 3M 8.06
11 to 40 8 27.4k 4.7 50V X5R 1206 47 ×1 10V X5R 1206 3.2 to 10 – 1.6M 19.6 3M 8.06
*The LTM8060 may be capable of the operating at lower input voltages but may skip switching cycles.
**A bulk input capacitor is required.
If the LTM8060 circuit is plugged into a live supply, the excessive heat or even damage the LTM8060 if the output
input voltage can ring to twice its nominal value, possi- is overloaded or short-circuited. A frequency that is too
bly exceeding the device’s rating. This situation is easily low can result in a final design that has too much output
avoided; see the Hot-Plugging Safely section. ripple or too large of an output capacitor.
Frequency Selection Table 2. Switching Frequency vs RT Value

fSW RT
The LTM8060 uses a constant frequency PWM architec- (MHz) (kΩ)
ture that can be programmed to switch from 200kHz to 0.2 200
3MHz by using a resistor tied from the RT pin to ground. 0.3 137
Table 2 provides a list of RT resistor values and their resul- 0.4 100
tant frequencies. The resistors in the table are standard 0.5 76.8
1% E96 values.
0.6 64.9
0.7 54.9
Operating Frequency Trade-Offs
0.8 46.4
It is recommended that the user apply the optimal RT value 0.9 41.2
given in Table 2 for the input and output operating condi- 1.0 35.7
tion. When using the LTM8060 with different output volt- 1.2 27.4
ages, the higher frequency recommended by Table 2 will 1.4 23.2
usually result in the best operation. System level or other 1.6 19.6
considerations, however, may necessitate another operat- 1.8 16.9
ing frequency. While the LTM8060 is flexible enough to
2.0 14.7
accommodate a wide range of operating frequencies, a
2.2 12.7
haphazardly chosen one may result in undesirable opera-
2.4 11.3
tion under certain operating or fault conditions. A fre-
2.6 10.2
quency that is too high can reduce efficiency, generate
2.8 9.09
3.0 8.06
Rev. C

LTM8060
BIASn Pin Considerations temperature, the power delivered, and the heat sinking
The BIASn pin is used to provide drive power for the capability of the system. For example, if VOUT1 of LTM8060
internal power switching stage and operate other internal is configured to regulate at 1.5V, and the other 3 chan-
circuitry. For proper operation, it must be powered by at nels are turned off, VOUT1 may continuously deliver 6A
least 3.2V. If the output voltage is programmed to 3.2V from 24VIN if the ambient temperature is controlled to less
or higher, BIASn may be simply tied to VOUTn. If VOUTn than 60°C. This is quite a bit higher than the 3A continu-
is less than 3.2V, BIASn can be tied to VINn or some ous rating. Please see graphs in the Typical Performance
other voltage source. If the BIASn pin voltage is too high, Characteristics section. Similarly, if all 4 channels of the
the efficiency of the LTM8060 may suffer. The optimum LTM8060 are delivering 3.3VOUT and the ambient tem-
BIASn voltage is dependent upon many factors, such as perature is 100°C, each channel will deliver at most 1.5A
load current, input voltage, output voltage and switching from 24VIN, which is less than the 3A continuous rating.
frequency. In all cases, ensure that the maximum volt-
Power Derating
age at the BIASn pin is less than 10V. If BIASn power is
applied from a remote or noisy voltage source, it may be Figure 2 through Figure 4 power loss curves can be used
necessary to apply a decoupling capacitor locally to the in coordination with the load current derating curves
pin. A 1µF ceramic capacitor works well. The BIASn pin (Figure 5 through Figure 13) for calculating an approxi-
may also be tied to GND at the cost of a small degrada- mate θJA thermal resistance for the LTM8060 with air-
tion in efficiency. flow conditions. The power loss curves are taken at room
temperature, and are increased with a 1.35 to 1.4 mul-
Maximum Load tiplicative factor at 125°C. These factors come from the
The maximum practical continuous load that the LTM8060 fact that the power loss of the regulator increases about
can drive per channel, while rated at 3A, actually depends 45% from 25°C to 150°C, thus a 45% spread over 125°C
upon both the internal current limit and the internal tem- delta equates to ~0.35%/°C loss increase. A 125°C maxi-
perature. The internal current limit is designed to pre- mum junction minus 25°C room temperature equates
vent damage to the LTM8060 in the case of overload or to a 100°C increase. This 100°C increase multiplied by
short-circuit. The internal temperature of the LTM8060 0.35%/°C equals a 35% power loss increase at the 125°C
depends upon operating conditions such as the ambient junction, thus the 1.35 multiplier.
4 4 4
12V 12V 12V
24V 24V 24V
36V 36V 36V
3 3 3
POWER LOSS (W)
POWER LOSS (W)
POWER LOSS (W)
2 2 2
1 1 1
0 0 0
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4
8060 F02 8060 F03 8060 F04
Figure 2. Power Loss Curves Figure 3. Power Loss Curves Figure 4. Power Loss Curves
Rev. C

LTM8060
18.0 18.0 18.0
16.0 16.0 16.0

14.0 14.0 14.0
12.0 12.0 12.0
10.0 10.0 10.0
8.0 8.0 8.0
6.0 6.0 6.0
4.0 0LFM 4.0 0LFM 4.0 0LFM

200LFM 200LFM 200LFM
2.0 2.0 2.0 400LFM
400LFM 400LFM
0 0 0
0 25 50 75 100 125 0 25 50 75 100 125 0 25 50 75 100 125
8060 F05 8060 F06 8060 F07
Figure 5. 12VIN to 1.5VOUT Figure 6. 24VIN to 1.5VOUT Figure 7. 36VIN to 1.5VOUT

Derating with Airflow Derating with Airflow Derating with Airflow
18.0 18.0 18.0
16.0 16.0 16.0

14.0 14.0 14.0
12.0 12.0 12.0
10.0 10.0 10.0
8.0 8.0 8.0
6.0 6.0 6.0
4.0 0LFM 4.0 0LFM 4.0 0LFM

2.0 2.0 2.0 400LFM
400LFM 400LFM
0 0 0
0 25 50 75 100 125 0 25 50 75 100 125 0 25 50 75 100 125
8060 F08 8060 F09 8060 F10
Figure 8. 12VIN to 3.3VOUT Figure 9. 24VIN to 3.3VOUT Figure 10. 36VIN to 3.3VOUT
Derating with Airflow Derating with Airflow Derating with Airflow
18.0 18.0 18.0
16.0 16.0 16.0

14.0 14.0 14.0
12.0 12.0 12.0
10.0 10.0 10.0
8.0 8.0 8.0
6.0 6.0 6.0
4.0 0LFM 4.0 0LFM 4.0 0LFM

2.0 400LFM 2.0 2.0
400LFM 400LFM
0 0 0
0 25 50 75 100 125 0 25 50 75 100 125 0 25 50 75 100 125
8060 F11 8060 F12 8060 F13
Figure 11. 12VIN to 5VOUT Derating Figure 12. 24VIN to 5VOUT Derating with Figure 13. 36VIN to 5VOUT Derating with
with Airflow Airflow Airflow
Rev. C

LTM8060
The derating curves are plotted with four VOUTn at the be derived from the power loss curves and adjusted with
same operating condition starting at 16A of total load the above ambient temperature multiplicative factors. The
current and low ambient temperature. The derating curves printed circuit board is a 1.6mm thick 6-layer board with
with airflow are measured at output voltages of 1.5V, 3.3V two ounce copper (50μm) for all the layers.
and 5V. These are chosen to include the lower and higher
output voltage ranges for correlating the thermal resis- Load Sharing
tance. Thermal models are derived from several tempera- The four LTM8060 channels may be paralleled to produce
ture measurements in a controlled temperature chamber higher currents. To do this on two or more LTM8060, tie
along with thermal FEA modeling. the VINn, VOUTn, FBn and SHAREn pins of all the paral-
The junction temperatures are monitored while ambient leled channels/modules together. To ensure that paralleled
temperature is increased with and without airflow. The channels start up together, the TRSSn pins may be tied
power loss increase with ambient temperature change together, as well. If it is inconvenient to tie the TRSSn
is factored into the derating curves. The junctions are pins together, make sure that the same value soft-start
maintained at ~120°C maximum while lowering output capacitors are used for each µModule regulator. When
current or power while increasing ambient temperature. load sharing among n units and using a single RFB resis-
The decreased output current will decrease the internal tor, the value of the resistor is given by Equation 2.
module loss as ambient temperature is increased. 199.2
RFB = ,where RFB is in kΩ (2)
The derived thermal resistances in Table 3 through Table 5 n(VOUT − 0.8)
for the various conditions can be multiplied by the calcu-
lated power loss as a function of ambient temperature to Examples of load sharing applications are given in
derive temperature rise above ambient, thus maximum Figure 18 through Figure 21.
junction temperature. Room temperature power loss can
Table 3. 1.5V Output

DERATING CURVE VIN (V) POWER LOSS CURVES AIRFLOW (LFM) HEAT SINK θJA (°C/W)
Figure 5, Figure 6, Figure 7 12, 24, 36 Figure 2 0 None 9
Figure 5, Figure 6, Figure 7 12, 24, 36 Figure 2 200 None 7.5
Table 4. 3.3V Output

Table 5. 5V Output
Rev. C

LTM8060
Burst Mode Operation thus regulating the FBn pin voltage to that of the TRSSn
pin. When TRSSn is above 0.8V, tracking is disabled and
To enhance efficiency at light loads, the LTM8060
the feedback voltage will regulate to the internal reference
automatically switches to Burst Mode operation which
voltage. The TRSSn pin may be left floating if the function
keeps the output capacitor charged to the proper volt-
is not needed.
age while minimizing the input quiescent current. During
Burst Mode operation, the LTM8060 delivers single cycle An active pull-down circuit is connected to the TRSSn pin
bursts of current to the output capacitor followed by sleep which will discharge the external soft-start capacitor in
periods where most of the internal circuitry is powered off the case of fault conditions and restart the ramp when the
and energy is delivered to the load by the output capacitor. faults are cleared. Fault conditions that clear the soft-start
During the sleep time, VINn and BIASn quiescent currents capacitor are the RUNn pin transitioning low, VINn voltage
are greatly reduced, so, as the load current decreases falling too low, or thermal shutdown.
towards a no load condition, the percentage of time that
the LTM8060 operates in sleep mode increases and the Pre-Biased Output
average input current is greatly reduced, resulting in As discussed in the Output Voltage Tracking and Soft-Start
higher light load efficiency. section, the LTM8060 regulates the output to the FBn
Burst Mode operation is enabled by tying SYNC to GND. voltage determined by the TRSSn pin whenever TRSSn is
less than 0.8V. If the LTM8060 output is higher than the
Minimum Input Voltage target output voltage, and SYNCn is not held below 0.8V,
the LTM8060 will attempt to regulate the output to the
The LTM8060 is a step-down converter, so a minimum
target voltage by returning a small amount of energy back
amount of headroom is required to keep the output in
to the input supply. If there is nothing loading the input
regulation. Keep the input above 3V to ensure proper
supply, its voltage may rise. Take care that it does not
operation. Voltage transients or ripple valleys that cause
rise so high that the input voltage exceeds the absolute
the input to fall below 3V may turn off the LTM8060.
maximum rating of the LTM8060. If SYNC is grounded,
VIN1 must be above 3V for channel 1 and channel 2 to the LTM8060 will not return current to the input.
operate. If VIN1 is above 3V, channel 2 will operate as long
as VIN2 is above 2V. Frequency Foldback
VIN34 must be above 3V for channel 3 and channel 4 The LTM8060 is equipped with frequency foldback which
to operate. acts to reduce the thermal and energy stress on the inter-
nal power elements during a short circuit or output over-
Output Voltage Tracking and Soft-Start load condition. If the LTM8060 detects that the output
The LTM8060 allows the user to adjust its output volt- has fallen out of regulation, the switching frequency is
age ramp rate by means of the TRSSn pin. An internal reduced as a function of how far the output is below the
2μA pulls up the TRSSn pin to about 2.4V. Putting an target voltage. This in turn limits the amount of energy
external capacitor on TRSSn enables soft starting the out- that can be delivered to the load under fault. During the
put to reduce current surges on the input supply. During start-up time, frequency foldback is also active to limit
the soft-start ramp the output voltage will proportionally the energy delivered to the potentially large output capaci-
track the TRSSn pin voltage. For output tracking applica- tance of the load. When a clock is applied to the SYNCn
tions, TRSSn can be externally driven by another voltage pin, the SYNCn pin is floated or held high, the frequency
source. From 0V to 0.8V, the TRSSn voltage will override foldback is disabled, and the switching frequency will
the internal 0.8V reference input to the error amplifier, slow down only during overcurrent conditions.
Rev. C

LTM8060
Synchronization while the output is held high, parasitic diodes inside the
LTM8060 can pull large currents from the output through
To select low ripple Burst Mode operation, tie the SYNCn
the VINn pin. Figure 14 shows a circuit that runs only when
pin below about 0.8V (this can be ground or a logic low
the input voltage is present and that protects against a
output). To synchronize the LTM8060 oscillator to an
shorted or reversed input.
external frequency, connect a square wave (with about
20% to 80% duty cycle) to the SYNCn pin. The square VIN VIN
wave amplitude should have valleys that are below 0.8V
and peaks above 1.5V. LTM8060
The LTM8060 may be synchronized over a 200kHz to RUN
3MHz range. The LTM8060 will not enter Burst Mode 8060 F14
operation at light output loads while synchronized to an

external clock. The RT resistor should be chosen to set
Figure 14. The Input Diode Prevents a Shorted Input from
the switching frequency equal to or below the lowest Discharging a Backup Battery Tied to the Output. It Also
synchronization input. For example, if the synchroniza- Protects the Circuit from a Reversed Input. The LTM8060 Runs
tion signal will be 500kHz and higher, the RT should be Only When the Input Is Present.
selected for 500kHz or lower.
PCB Layout
The LTM8060 features spread spectrum operation to fur-
Most of the headaches associated with PCB layout have
ther reduce EMI/EMC emissions. To enable spread spec-
been alleviated or even eliminated by the high level of
trum operation, apply between 2.8V and 4V to the SYNCn
integration of the LTM8060. The LTM8060 is neverthe-
pin. In this mode, triangular frequency modulation is used
less a switching power supply, and care must be taken to
to vary the switching frequency between the value pro-
minimize EMI and ensure proper operation. Even with the
grammed by RT to about 20% higher than that value. The
high level of integration, you may fail to achieve specified
modulation frequency is about 7kHz. For example, when
operation with a haphazard or poor layout. See Figure 15
the LTM8060 is programmed to 2MHz, the frequency will
for a suggested layout. Ensure that the grounding and
vary from 2MHz to 2.4MHz at a 7kHz rate. When spread
heat sinking are acceptable.
spectrum operation is selected, Burst Mode operation is
disabled, and the part may run in discontinuous mode. CIN1 CIN2
Shorted Input Protection RT12
Care needs to be taken in systems where the output is

held high when the input to the LTM8060 is absent. This
COUT2 COUT3
may occur in battery charging applications or in battery
backup systems where a battery or some other supply
is diode OR’ed with the LTM8060’s output. If the VINn
pin is allowed to float and the RUNn pin is held high COUT3 COUT4
(either by a logic signal or because it is tied to VINn),

then the LTM8060’s internal circuitry pulls its quiescent CIN34 CIN34
current through its internal power switch. This is fine if RT34
your system can tolerate a few milliamps in this state.
If you ground the RUNn pin, the internal current drops 8060 F15
to essentially zero. However, if the VINn pin is grounded Figure 15. Layout Showing Suggested External Components,
GND Plane and Thermal Vias
Rev. C

LTM8060
A few rules to keep in mind are: input voltage, possibly exceeding the LTM8060’s rating
and damaging the part. If the input supply is poorly con-
1. Place the RFB and RT resistors as close as possible to
trolled or the LTM8060 is hot-plugged into an energized
their respective pins.
supply, the input network should be designed to prevent
2. Place the CIN capacitor as close as possible to the VIN this overshoot. This can be accomplished by installing
and GND connection of the LTM8060. a small resistor in series to VINn, but the most popular
3. Place the COUT capacitor as close as possible to the method of controlling input voltage overshoot is add an
VOUT and GND connection of the LTM8060. electrolytic bulk cap to the VINn net. This capacitor’s rela-
tively high equivalent series resistance damps the circuit
4. Place the CIN and COUT capacitors such that their and eliminates the voltage overshoot. The extra capacitor
ground current flow directly adjacent to or underneath improves low frequency ripple filtering and can slightly
the LTM8060. improve the efficiency of the circuit, though it is likely to
5. Connect all of the GND connections to as large a copper be the largest component in the circuit.
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external Thermal Considerations
components and the LTM8060. The LTM8060 output current may need to be derated if
6. Use vias to connect the GND copper area to the board’s it is required to operate in a high ambient temperature.
internal ground planes. Liberally distribute these GND The amount of current derating is dependent upon the
vias to provide both a good ground connection and input voltage, output power and ambient temperature.
thermal path to the internal planes of the printed circuit The derating curves given in the Typical Performance
board. Pay attention to the location and density of the Characteristics section can be used as a guide. These
thermal vias in Figure 15. The LTM8060 can benefit curves were generated by the LTM8060 mounted to a
from the heat sinking afforded by vias that connect 104cm2 6-layer FR4 printed circuit board. Boards of
to internal GND planes at these locations, due to their other sizes and layer count can exhibit different thermal
proximity to internal power handling components. behavior, so it is incumbent upon the user to verify proper
The optimum number of thermal vias depends upon operation over the intended system’s line, load and envi-
the printed circuit board design. For example, a board ronmental operating conditions.
might use very small via holes. It should employ more For increased accuracy and fidelity to the actual applica-
thermal vias than a board that uses larger holes. tion, many designers use FEA (Finite Element Analysis) or
CFD (Computational Fluid Dynamics) to predict thermal
Hot-Plugging Safely performance. To that end, the Pin Configuration typically
The small size, robustness and low impedance of ceramic gives three dominant thermal coefficients:
capacitors make them an attractive option for the input 1. θJA – Thermal resistance from junction to ambient
bypass capacitor of LTM8060. However, these capacitors
can cause problems if the LTM8060 is plugged into a 2. θJCbot – Thermal resistance from junction to the bottom
live supply (see Application Note 88 for a complete dis- of the product case
cussion). The low loss ceramic capacitor combined with 3. θJCtop – Thermal resistance from junction to top of the
stray inductance in series with the power source forms an product case
underdamped tank circuit, and the voltage at the VINn pin
While the meaning of each of these coefficients may seem
of the LTM8060 can ring to more than twice the nominal
to be intuitive, JEDEC has defined each to avoid confu-
sion and inconsistency. These definitions are given in
JESD51‑12, and are quoted or paraphrased below:
Rev. C

LTM8060
1. θJA is the natural convection junction-to-ambient air Given these definitions, it should now be apparent that
thermal resistance measured in a one cubic foot sealed none of these thermal coefficients reflects an actual physi-
enclosure. This environment is sometimes referred to cal operating condition of a µModule regulator. Thus, none
as “still air” although natural convection causes the of them can be individually used to accurately predict the
air to move. This value is determined with the part thermal performance of the product. Likewise, it would
mounted to a JESD 51-9 defined test board, which be inappropriate to attempt to use any one coefficient to
does not reflect an actual application or viable operat- correlate to the junction temperature vs load graphs given
ing condition. in the product’s data sheet. The only appropriate way to
2. θJCbot is the junction-to-board thermal resistance with use the coefficients is when running a detailed thermal
all of the component power dissipation flowing through analysis, such as FEA, which considers all of the thermal
the bottom of the package. In the typical µModule reg- resistances simultaneously.
ulator, the bulk of the heat flows out the bottom of A graphical approximation of these dominant thermal
the package, but there is always heat flow out into the resistances is given in Figure 16. Some thermal resis-
ambient environment. As a result, this thermal resistance elements, such as heat flow out the side of the
tance value may be useful for comparing packages but package, are not defined by the JEDEC standard, and are
the test conditions don’t generally match the user’s not shown. The blue resistances are contained within the
application. µModule regulator, and the green are outside.
3. θJCtop is determined with nearly all of the compo- The die temperature of the LTM8060 must be lower than
nent power dissipation flowing through the top of the the maximum rating, so care should be taken in the layout
package. As the electrical connections of the typical of the circuit to ensure good heat sinking of the LTM8060.
µModule regulator are on the bottom of the package, The bulk of the heat flow out of the LTM8060 is through
it is rare for an application to operate such that most the bottom of the package and the pads into the printed
of the heat flows from the junction to the top of the circuit board. Consequently a poor printed circuit board
part. As in the case of θJCbot, this value may be useful design can cause excessive heating, resulting in impaired
for comparing packages but the test conditions don’t performance or reliability. Please refer to the PCB Layout
generally match the user’s application. section for printed circuit board design suggestions.
µModule DEVICE θJA JUNCTION-TO-AMBIENT RESISTANCE
θJCtop JUNCTION-TO-CASE CASE (TOP)-TO-AMBIENT

(TOP) RESISTANCE RESISTANCE
JUNCTION AMBIENT
θJCbot JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT

(BOTTOM) RESISTANCE RESISTANCE RESISTANCE
8060 F16
Figure 16. Graphical Representation of Thermal Coefficients, Including JESD51-12 Terms
Rev. C

LTM8060
TYPICAL APPLICATION
VIN1 BIAS12
VIN
8.5V TO 40V RUN1 AUX1
VOUT1 VOUT1
5V
14.7k 47µF 3A
RT12 47.5k
FB1
fSW = 2MHz
SYNC12
VOUT2 VOUT2
3.3V
78.7K 47µF 3A
FB2
VIN2
GND
RUN2 LTM8060
VIN34 BIAS34
AUX3
RUN3
VOUT3 VOUT3
RUN4
PINS NOT USED: 5V
14.7k 3A
AUX2, AUX4, TRSS1, RT34 47.5k 47µF
FB3
TRSS2, TRSS3, TRSS4, fSW = 2MHz
SHARE1, SHARE2, SYNC34
SHARE3, SHARE4, VOUT4
VOUT4
PG1, PG2, PG3, 3.3V
PG4, CLKOUT12, 78.7k 47µF 3A
CLKOUT34 FB4
4.7µF GND
×4
8060 F17
Figure 17. 8.5V to 40V Input to 5V at 3A, 3.3V at 3A, 5V at 3A, and 3.3V at 3A
Rev. C

LTM8060
TYPICAL APPLICATION
VIN12 VIN1 TRSS1
5.5V TO 40V C4
RUN1 TRSS2 1nF
VOUT1
35.7k
RT12 39.2k
FB1
fSW12 = 1MHz
FB2
SYNC12
VOUT2 VOUT12
3.3V
47µF 6A
×2
VIN2 GND
4.7µF RUN2 LTM8060 SHARE1
×2 SHARE2
VIN34 VIN34 TRSS3

3.2V TO 40V C5
TRSS4 1nF
4.7µF RUN3
×2 RUN4 VOUT3
64.9k
RT34 143k
FB3
fSW34 = 600kHz
FB4
SYNC34
VOUT4 VOUT34
1.5V
100µF 6A
×2
PINS NOT USED: GND
AUX1, AUX2, AUX3, AUX4, SHARE3
BIAS12, BIAS34
SHARE4
PG1, PG2, PG3,
PG4, CLKOUT12, 8060 F18
CLKOUT34
Figure 18. 5.5V to 40V Input to Paralleled 3.3V at 6A, 3.2V to 40V Input to Paralleled 1.5V at 6A
Rev. C

LTM8060
TYPICAL APPLICATION
C5
VIN1 1nF
TRSS1
TRSS2
TRSS3
TRSS4
VIN
3V TO 40V RUN1
VOUT1
100k
RT12
fSW12 = 400kHz
SYNC12
VOUT2
249k
FB1
VIN2
FB2
RUN2
LTM8060 FB3
FB4
VIN34 CLKOUT12
SYNC34
RUN3
4.7µF
×4 RUN4 VOUT3
100k
RT34
fSW34 = 400kHz VOUT
VOUT4
1V
100µF 12A
PINS NOT USED: ×4
AUX1, AUX2, AUX3, AUX4, GND
BIAS12, BIAS34,
SHARE1
SHARE2
SHARE3
SHARE4
PG1, PG2, PG3, PG4,

CLKOUT34
8060 F19
Figure 19. 3V to 40V Input to Paralleled 1V at 12A
Rev. C

LTM8060
TYPICAL APPLICATION
C4
VIN1 VIN1 4.7nF
TRSS1
TRSS2
TRSS3
TRSS4
TRSS1
TRSS2
TRSS3
TRSS4
VIN
3V TO RUN1 RUN1
40V
VOUT1 VOUT1
100k 100k
RT12 RT12
fSW12 = 400kHz fSW12 = 400kHz
SYNC12
VOUT2 VOUT2
SYNC12 249k
CLKOUT34
FB1
VIN2 249k VIN2
FB1 FB2
RUN2 LTM8060 RUN2 LTM8060
FB2 FB3
FB3 FB4
FB4 CLKOUT12
VIN34 VIN34
CLKOUT12 SYNC34
RUN3 SYNC34 RUN3
4.7µF
VOUT3 4.7µF VOUT3
×4 RUN4 RUN4
×4
100k 100k
RT34 RT34
fSW34 = 400kHz fSW34 = 400kHz
VOUT4 VOUT4
VOUT
100µF 100µF 1V
×4 ×4 24A
GND GND
SHARE1
SHARE2
SHARE3
SHARE4
SHARE1
SHARE2
SHARE3
SHARE4
PINS NOT USED:
8060 F20
AUX, AUX2, AUX3, AUX4,
BIAS12, BIAS34
PG1, PG2, PG3, PG4
Figure 20. Two LTM8060 are Paralleled to Supply 1V/24A Output in Forced Continuous Mode
Rev. C

LTM8060
TYPICAL APPLICATION
C4
VIN1 VIN1 4.7nF
TRSS1
TRSS2
TRSS3
TRSS4
TRSS1
TRSS2
TRSS3
TRSS4
VIN
3V TO 40V RUN1 RUN1
VOUT1 VOUT1
100k 100k
RT12 RT12
VOUT2 VOUT2
VIN2 VIN2
249k 249k
RUN2 FB1 RUN2 FB1
LTM8060 LTM8060
FB2 FB2
FB3 FB3
VIN34 FB4 VIN34 FB4
LTC6909 fSW = 400kHz RUN3 RUN3

4.7µF 4.7µF
OUT1 ×4 RUN4 VOUT3 RUN4 VOUT3
×4
OUT2
OUT3 100k 100k
RT34 RT34
OUT4
OUT5 VOUT4 VOUT4
VOUT
OUT6 100µF 100µF 1V
×4 ×4 24A
OUT7 GND GND
OUT8
SHARE1
SHARE2
SHARE3
SHARE4
SHARE1
SHARE2
SHARE3
SHARE4
SYNC12 SYNC12
SYNC34 SYNC34
8060 F16
PINS NOT USED:

AUX1, AUX2. AUX3, AUX4,
BIAS12, BIAS34,
PG1, PG2, PG3, PG4,
CLKOUT12, CLKOUT34
Figure 21. Two LTM8060 are Paralleled to Supply 1V/24A Output with 45° Phase Shift Interleaving through All Eight Channels
Rev. C

LTM8060
PACKAGE DESCRIPTION
Table 6. LTM8060 Pinout (Sorted by Pin Number)
PIN PIN PIN PIN PIN
PIN NAME PIN NAME PIN PIN NAME PIN NAME PIN PIN NAME PIN PIN NAME PIN NAME PIN NAME
A1 VOUT3 B1 VOUT3 C1 TRSS3 D1 TRSS4 E1 RT34 F1 FB3 G1 VIN34 H1 VIN34
A2 VOUT3 B2 VOUT3 C2 AUX3 D2 BIAS34 E2 AUX4 F2 FB4 G2 VIN34 H2 VIN34
A3 VOUT3 B3 VOUT3 C3 GND D3 GND E3 GND F3 SHARE4 G3 GND H3 GND
A4 VOUT3 B4 VOUT3 C4 GND D4 GND E4 GND F4 SHARE3 G4 GND H4 GND
A5 GND B5 GND C5 GND D5 GND E5 GND F5 GND G5 GND H5 GND
A8 VOUT2 B8 VOUT2 C8 GND D8 GND E8 GND F8 GND G8 GND H8 GND
A9 VOUT2 B9 VOUT2 C9 GND D9 GND E9 PG1 F9 GND G9 GND H9 GND
A10 VOUT2 B10 VOUT2 C10 CLKOUT12 D10 PG2 E10 DNC F10 VIN2 G10 VIN2 H10 VIN1
A11 VOUT2 B11 VOUT2 C11 SYNC12 D11 RUN2 E11 RUN1 F11 VIN2 G11 VIN2 H11 VIN1
PIN PIN PIN PIN
PIN NAME PIN NAME PIN PIN NAME PIN NAME PIN PIN NAME PIN PIN NAME PIN NAME
J1 VIN34 K1 VIN34 L1 RUN3 M1 RUN4 N1 SYNC34 P1 VOUT4 R1 VOUT4
J2 VIN34 K2 VIN34 L2 DNC M2 PG4 N2 CLKOUT34 P2 VOUT4 R2 VOUT4
J3 GND K3 GND L3 PG3 M3 GND N3 GND P3 VOUT4 R3 VOUT4
J4 GND K4 GND L4 GND M4 GND N4 GND P4 VOUT4 R4 VOUT4
J5 GND K5 GND L5 GND M5 GND N5 GND P5 GND R5 GND
J8 GND K8 SHARE1 L8 GND M8 GND N8 GND P8 VOUT1 R8 VOUT1
J9 GND K9 SHARE2 L9 GND M9 GND N9 GND P9 VOUT1 R9 VOUT1
J10 VIN1 K10 FB2 L10 AUX2 M10 BIAS12 N10 AUX1 P10 VOUT1 R10 VOUT1
J11 VIN1 K11 FB1 L11 RT12 M11 TRSS2 N11 TRSS1 P11 VOUT1 R11 VOUT1
Rev. C

BGA Package
165-Lead (16mm × 11.9mm × 3.32mm)
(Reference LTC DWG# 05-08-1605 Rev B)
28
A SEE NOTES
DETAIL A
2× aaa Z 6
E Y
X A2 SEE NOTES 11 10 9 8 7 6 5 4 3 2 1
3
Z
A
A1
LTM8060
PIN 1 ccc Z B PIN 1

CORNER
4 C
b D
b1
MOLD E
CAP
SUBSTRATE F
H1
G
H2
D F H
DETAIL B
// bbb Z
J
PACKAGE DESCRIPTION
Øb (165 PLACES) L
e
ddd M Z X Y
M
eee M Z
R
2× aaa Z
e b
PACKAGE TOP VIEW DETAIL A G
DETAIL B
PACKAGE BOTTOM VIEW
PACKAGE SIDE VIEW
5.000
4.000
3.000
2.000
1.000
0.000
1.000
2.000
3.000
4.000
5.000
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
7.000 2. ALL DIMENSIONS ARE IN MILLIMETERS
For more information www.analog.com

DIMENSIONS
6.000 3 BALL DESIGNATION PER JEP95
SYMBOL MIN NOM MAX NOTES
5.000 A 3.13 3.32 3.51 4 DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL,
A1 0.40 0.50 0.60 BALL HT BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
0.500 REF Ø 165x 4.000 THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR
A2 2.73 2.82 2.91 MARKED FEATURE
3.000 b 0.50 0.60 0.70 BALL DIMENSION
5. PRIMARY DATUM -Z- IS SEATING PLANE
b1 0.47 0.50 0.53 PAD DIMENSION
2.000
D 16.00 6 PACKAGE ROW AND COLUMN LABELING MAY VARY
1.000
! AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
E 11.90
LAYOUT CAREFULLY
e 1.00
0.000
F 14.00
1.000 G 10.00
2.000
H1 0.32 REF SUBSTRATE THK
H2 2.50 REF MOLD CAP HT
3.000
aaa 0.15
4.000 bbb 0.10 LTMXXXX
ccc 0.20 µModule
5.000
ddd 0.25
COMPONENT
6.000 eee 0.10 PIN 1
TOTAL NUMBER OF BALLS: 165
7.000
TRAY PIN 1
BEVEL
SUGGESTED PCB LAYOUT PACKAGE IN TRAY LOADING ORIENTATION BGA 165 0120 REV B
Rev. C
TOP VIEW
LTM8060
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 05/21 Updated thermal resistance. 1, 2
Updated MSL rating. 2
Updated graph G45. 36
B 4/23 Fixed major formatting issues (updated cross references, re-paginated, added Part # to schematics). All
Removed SnPb mention in Description section. 1
Removed ordering information for SnPb option. 2
Changed 165-lead to 165-pin in the Pin Configuration drawing. 3
Moved some Derating and Power Loss curves to the Applications Information section (Figure 3 through Figure 13). 15, 16
Rearranged Pin Functions section alphanumerically. 9, 10
Added ink marking statement to package photos. 30
C 5/23 Added FB resistor tolerance 11
Corrected equation numbers 13, 17
Corrected SYNC34 connection 23
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For more by
is granted information www.analog.com
implication or otherwise under any patent or patent rights of Analog Devices. 29
LTM8060
PACKAGE PHOTOS Part marking is either ink mark or laser mark
DESIGN RESOURCES
SUBJECT DESCRIPTION
µModule Design and Manufacturing Resources Design: Manufacturing:
• Selector Guides • Quick Start Guide
• Demo Boards and Gerber Files • PCB Design, Assembly and Manufacturing Guidelines
• Free Simulation Tools • Package and Board Level Reliability
µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
Digital Power System Management Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTM4613 36V, 8A Low EMI Step-Down µModule Regulator 5V ≤ VIN ≤ 36V, 3.3V ≤ VOUT ≤ 15V, EN55022B Compliant, 15mm × 15mm ×
4.32mm LGA, 15mm × 15mm × 4.92mm BGA Packages
LTM8063 40V, 2A Step-Down Silent Switcher µModule Regulator 3.2V ≤ VIN ≤ 40V, 0.8V ≤ VOUT ≤ 15V, 4mm × 6.25mm × 2.22mm BGA Package
LTM8065 40V, 2.5A Step-Down Silent Switcher 3.4V ≤ VIN ≤ 40V, 0.97V ≤ VOUT ≤ 18V, 6.25mm × 6.25mm × 2.32mm
µModule Regulator BGA Package
LTM8053 40V, 3.5A Step-Down Silent Switcher 3.4V ≤ VIN ≤ 40V, 0.97V ≤ VOUT ≤ 15V, 6.25mm × 9mm × 3.32mm
LTM8078 40V, Dual 1.4A Step-Down Silent Switcher 3V ≤ VIN ≤ 40V, 0.8V ≤ VOUT ≤ 10V, 6.25mm × 6.25mm × 2.32mm
LTM8024 40V, Dual 3.5A Step-Down Silent Switcher 3V ≤ VIN ≤ 40V, 0.8V ≤ VOUT ≤ 8V, 9mm × 11.25mm × 3.32mm BGA Package
µModule Regulator
LTM8073 60V, 3A Step-Down µModule Regulator 3.4V ≤ VIN ≤ 60V, 0.85V ≤ VOUT ≤ 15V, 6.25mm × 9mm × 3.32mm
BGA Package
LTM8071 60V, 5A Step-Down Silent Switcher µModule Regulator 3.6V ≤ VIN ≤ 60V, 0.97V ≤ VOUT ≤ 15V, 9mm × 11.25mm × 3.32mm
BGA Package
LTM8051 40V, Quad 1.2A Step-Down Silent Switcher 3V ≤ VIN ≤ 40V, 0.8V ≤ VOUT ≤ 8V, 6.25mm × 11.25mm × 2.32mm
LTM4643 Quad 3A, 20V Step-Down µModule Regulator 4V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 3.3V, 9mm × 15mm × 1.82mm LGA,
9mm × 15mm × 2.42mm BGA Packages
LTM4644 Quad 4A, 14V Step-Down µModule Regulator 4V ≤ VIN ≤ 14V, 0.6V ≤ VOUT ≤ 5.5V, 9mm × 15mm × 5.01mm BGA Package
Rev. C
30
5/23
www.analog.com
For more information www.analog.com  ANALOG DEVICES, INC. 2021-2023

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LTM8060

Quad 40VIN, Silent Switcher μModule Regulator

Document Feedback For more information www.analog.com 1

SYNC12 RUN2 RUN1 FB1 RT12 TRSS2 TRSS1

TRSS3 TRSS4 RT34 FB3 BANK5 VIN34 RUN3 RUN4 SYNC34

2 For more information www.analog.com

For more information www.analog.com 3

POWER LOSS (W)

POWER LOSS (W)

POWER LOSS (W)

POWER LOSS POWER LOSS POWER LOSS

POWER LOSS (W)

POWER LOSS POWER LOSS POWER LOSS

POWER LOSS (W)

POWER LOSS POWER LOSS

4 For more information www.analog.com

INPUT CURRENT (A)

INPUT CURRENT (A)

POWER LOSS (W)

INPUT CURRENT (A)

INPUT CURRENT (A)

INPUT CURRENT (A)

0.4 0.6 0.8

0.2 0.3 0.4

For more information www.analog.com 5

MAXIMUM TOTAL LOAD CURRENT (A)

INPUT CURRENT (A)

Derating, VOUT = 1V Derating, VOUT = 1.2V Derating, VOUT = 1.5V

16.0 0LFM 16.0 0LFM 16.0 0LFM

MAXIMUM TOTAL LOAD CURRENT (A)

MAXIMUM TOTAL LOAD CURRENT (A)

14.0 14.0 14.0

12.0 12.0 12.0

10.0 10.0 10.0

8.0 8.0 8.0

6.0 6.0 6.0

4.0 12VIN 4.0 12VIN 4.0 12VIN

Derating, VOUT = 1.8V Derating, VOUT = 2V Derating, VOUT = 2.5V

16.0 0LFM 16.0 0LFM 16.0 0LFM

MAXIMUM TOTAL LOAD CURRENT (A)

14.0 14.0 14.0

12.0 12.0 12.0

10.0 10.0 10.0

8.0 8.0 8.0

6.0 6.0 6.0

4.0 12VIN 4.0 12VIN 4.0 12VIN

6 For more information www.analog.com

16.0 0LFM 16.0 0LFM 16.0 0LFM

MAXIMUM TOTAL LOAD CURRENT (A)

MAXIMUM TOTAL LOAD CURRENT (A)

12.0 12.0 12.0

10.0 10.0 10.0

8.0 8.0 8.0

6.0 6.0 6.0

4.0 12VIN 4.0 12VIN 4.0 12VIN

16.0 0LFM 16.0 0LFM

MAXIMUM TOTAL LOAD CURRENT (A)

4.0 12VIN 4.0 12VIN NOISE FLOOR

10 8060 G35 –40