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Asynchronous Serial Data Transfer Asynchronous Communication Interface

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39 views17 pages

Asynchronous Serial Data Transfer Asynchronous Communication Interface

Uploaded by

mohitgora1008
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Asynchronous

serial data transfer


&

Asynchronous
Communication
Interface
Intro

Group
Members
1.Manish Bisht (2k22/SE/112)
2.Mohit(2K22/SE/115)
3.Muaviz Khan(2K22/SE/116)
4.Rajat Kumar(2K22/SE/134)
5.Ritik Pal(2K22/SE/138)
Data Transfer basically divided into two parts:
Serial data transfer
Parallel data transfer

Serial data transfer is further divided into Two parts:


synchronous serial data transfer
Asynchronous serial data transfer
data transfer
Parallel 01 Serial 02
In serial data transmission, each bit in
In parallel data transmission, each bit of
the message has its own path and the the message is sent in sequence one at
total message is transmitted at the same a time. This method requires the use of
time. This means that an n-bit message one pair of conductors or one conductor
must be transmitted through n separate
and a common ground
conductor paths

NOTE:-Parallel transmission is faster but requires many wires. It is used for short distances and where speed is
important. Serial transmission is slower but is less expensive since it requires only one pair of conductors.
SERIAL DATA TRANSFER
Synchronous : Asynchronous:
01 02

In synchronous transmission, the In asynchronous transmission,


two units share a common clock binary information is sent only when
frequency and bits are transmitted it is available and the line remains
continuously at the rate dictated by idle when there is no information to
the clock pulses be transmitted.
Asynchronous serial data transmission
technique
With this technique, each character consists of three parts: a
start bit, the character bits, and stop bits. The convention is
that the transmitter rests at the 1-state when no characters are
transmitted. The first bit, called the start bit, is always a 0 and is
used to indicate the beginning of a character. The last bit
called the stop bit is always a 1.
Transmission rules

1. When a character is not being sent, the line is kept in the 1-state.
2. The initiation of a character transmission is detected from the start bit, which is
always 0.
3. The character bits always follow the start bit.
4. After the last bit of the character is transmitted, a stop bit is detected when the
line returns to the 1-state for at least one bit time.
Baud Rate
Baud rate denotes the rate of serial information transmission, measured in
bits per second. It is calculated by determining the time required to transmit
each bit.
For example, in a format comprising a start bit, eight data bits, and two stop
bits (totaling 11 bits per character), if ten characters are transmitted per
second, each character takes 0.1 seconds for transfer. With 11 bits per
character, the resulting baud rate is calculated as 110 baud. Accurate baud
rate calculation is essential for establishing communication parameters and
ensuring reliable data transmission.
Asynchronous Communication Interface
The asynchronous communication interface serves as both a transmitter and
a receiver, depicted in the block diagram.

Initialization of the interface for a particular transfer mode is achieved by


loading a control byte into its control register.

Data transmission from the CPU begins with the transmission of a data byte
via the data bus to the transmitter register.

The transmitted byte is then transferred to a shift register for serial


transmission.
Asynchronous Communication Interface
The CPU can access the received byte by selecting the receiver register through the data bus.

The status register contains bits used for input and output flags and error recording during
transmission.

Communication with the CPU is managed through chip select, read, and write control lines.

The chip select (CS) input selects the interface through the address bus.

Register selection is determined by the register select (RS) in conjunction with the read (RD)
and write (WR) controls.

Two registers are write-only, and two are read-only, with the selection being a function of the
RS value and the RD and WR status as specified in the accompanying table.
Transmitter
The operation of the transmitter portion of the interface is as follows. The CPU reads
the status register and checks the flag to see if the transmitter register is empty. If it
is empty, the CPU transfers a character to the transmitter register and the interface
clears the flag to mark the register full. The first bit in the transmitter shift register is
set to 0 to generate a start bit. The character is transferred in parallel from the
transmitter register to the shift register and the appropriate number of stop bits are
appended into the shift register. The transmitter register is then marked empty. The
character can now be transmitted one bit at a time by shifting the data in the shift
register at the specified baud rate. The CPU can transfer another character to the
transmitter register after checking the flag in the status register. The interface is said
to be double buffered because a new character can be loaded as soon as the
previous one starts transmission.
Reciever
The operation of the receiver portion of the interface is similar. The FIFO receive
data input is in the 1-state when the line is idle. The receiver control monitors the
receive-data line for a 0 signal to detect the occurrence of a start bit. Once a start bit
has been detected, the incoming bits of the character are shifted into the shift
register at the prescribed baud rate. After receiving the data bits, the interface
checks for the parity and stop bits. The character without the start and stop bits is
then transferred in parallel from the shift register to the receiver register. The flag in
the status register is set to indicate that the receiver register is full. The CPU reads
the status register
Transmission Error
The interface checks for any possible errors during
transmission and sets appropriate bits in the status register.
The CPU can read the status register at any time to check if
any errors have occurred. Three possible errors that the
interface checks during transmission are parity error,
framing error, and overrun error.
Transmission Error
A Parity error occurs if the number of l's in the received
data is not the correct parity.

A framing error occurs if the right number of stop bits is


not detected at the end of the received character.

An overrun error occurs if the CPU does not read the


character from the receiver register before the next one
becomes available in the shift register
Overrun error results in a loss of characters in the received
data stream.
Thank You

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