Module 4

Q1 Draw Symbol and write truth table of D & T Flip Flop?

Q2 Describe the working of JK FlipFlop with its truth table & Logic diagram:
Solution: Logic diagram:

Working:
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry
that prevents the illegal or invalid output condition that can occur when both inputs S and R
are equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has four
possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”.
Both the S and the R inputs of the previous SR bistable have now been replaced by two
inputs called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates
to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-
input NAND gates with the third input of each gate connected to the outputs at Q and Q.
This cross coupling of the SR flip-flop allows the previously invalid condition of S = “1”
and R = “1” state to be used to produce a “toggle action” as the two inputs are now
interlocked.
If the circuit is now “SET” the J input is inhibited by the “0” status
Of Q through the lower NAND gate. If the circuit is “RESET” the K input is inhibited by
the “0” status of Q through the upper NAND gate. As Q and Q are always different we can
use them to control the input. When both
inputs J and K are equal to logic “1”, the JK flip flop toggles

Q3 Describe the operation of R-S flip flop using NAND gates only.
Solution:

Description/explanation-
When clock = 0, the outputs of NAND gates 3 and 4 will be forced to be 1 irrespective of
thevalues of S and R. That means R’= S’ = 1.Hence the outputs of basic SR/F/F i.e. Q n+1
andwill not change. Thus if clock = 0, then there is no change in the output of the
clocked SR flip-flop.
Case I : S = R = 0, clock = 1: No change
If S=R=0 then outputs of NAND gate 3 and 4 are forced to become 1.
Hence R' and S' both will be equal to 1. Since R' and S' are the inputs of the basic S – R flip-
flop using NAND gates. There will be no change in the state of outputs.
Case II : S =1, R = 0, clock = 1: Set
Now S=0, R=1 and a positive going edge is applied to the clock
Output of NAND 3 i.e. R’ = 0 and output of NAND 4 i.e. S’ = 1.
Hence output of SR flip-flop is Q n+1 = 1 and = 0.
This is the set condition.
Case III : S =0, R = 1, clock = 1: Reset
Now S=0, R=1 and a positive edge is applied to the clock input.
Since S=0, output of NAND – 3 i.e. R ́= 1. And as R’ = 1 and clock = 1 the output of NAND-
4 i.e. S ́ = 0. Hence output of SR flip-flop is Q n+1 = 0 and = 1.
This is the reset condition.
Case IV : S =1, R = 1, clock = 1: Undefined/ forbidden
As S=1, R=1 and clock = 1, the outputs of NAND gates 3 and 4 both are 0 i.e. S' = R'=0.
Soboth the outputs Q n+1 = 1 and
Hence output is Undefined/ forbidden.
Q4 Explain 3 bit Asynchronous UP Counter with Output waveform?
Solution:
Q5 Describe the operation of 4 bit serial in serial out shift register?
Solution:

Working:
Explaination :-
If a logic “1” is connected to the DATA input pin of FFA then on the first
clock pulse the output of FFA and therefore the resulting QA will be set HIGH
to logic “1” with all the other outputs still remaining LOW at logic “0”.
Assume now that the DATA input pin of FFA has returned LOW again to logic
“0” giving us one data pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic “0” and the
output of FFBand QB HIGH to logic “1” as its input D has the logic “1” level
on it from QA. The logic “1” has now moved or been “shifted” one place along
the register to the right as it is now at QA.
When the third clock pulse arrives this logic “1” value moves to the output
of FFC ( QC ) and so on until the arrival of the fifth clock pulse which sets all
the outputs QA to QD back again to logic level “0” because the input
to FFA has remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one
place to the right, and this is shown in the following table until the complete
data value of 0-0-0-1 is stored in the register. This data value can now be read
directly from the outputs of QA to QD.
Then the data has been converted from a serial data input signal to a parallel
data output. The truth table and following waveforms show the propagation of
the logic “1” through the register from left to right as follows.

module 5
Q1 Compare the following :
Weighted resistor DAC & R2R Ladder DAC
Solution:
Q2 Draw Block diagram of dual slope ADC and Explain its working?
Solution:
Q3 Draw block diagram of Programmable Logic array(PLA)?
Solution:

Q4 compare the Following

i) Volatile and Non volatile memory

Working:
The successive approximation A/D converter is as shown in fig. An analog voltage (Va) is
constantly compared with voltage Vi, using a comparator. The output produced by
comparator (Vo) is applied to an electronic Programmer. If Va=Vi, then Vo=0 & then no
conversion is required. The programmer displays the value of Vi in the form of digital O/P.
But if Va Vi, then the O/P is changed by the programmer. If Va> Vi, then value of Vi is
increased by 50% of earlier value. But if Va< Vi, then value of Vi is decreased by 50% of
earlier value.
This new value is converted into analog form, by D/A converter so as to compare it with Va
again. This procedure is repeated till we get Va=Vi. As the value of Vi is changed
successively, this method is called as successive-approximation A/D converter.
When the starts signal goes low the successive approximation register SAR is cleared and
output voltage of DAC will be 0v. When start goes high the conversion starts.
After starts, during first clock pulse the control circuit set MSB bit so SAR output wiil be
1000 0000. This is connected as input to DAC so output of DAC is compared with Vin
input voltage. If VDAC is more than Vin the comparator output –Vsat, if VDAC is less than
Vin, the comparator output is +Vsat.
If output of DAC i.e. VDAC is +Vsat (i.e. unknown analog input voltage Vin> VDAC) then
MSB bit is kept set, otherwise it is reset.
Consider MSB is set so SAR will contain 1000 0000.
The next clock pulse will set next bit i.e. D6 bit is kept as it is, but if it –Vsat the D6 bit
reset. The process of checking and taking decision to keep bit set or to reset is continued
upto D0. Then the DAC input will be digital data equal to analog input.
When the conversion is finished the control circuits sends out an end of conversion signal
and data is locked in buffer register.