UNIT-II

Synchronous Sequential logic circuits: Introduction to Sequential circuits, latches,flip-flops, RS,

D, T, JK, M/S JK-flipflops, truth tables, excitation tables and characteristic equations, clocked
and edgetriggeredflipflops, Registers- Definition, serial, parallel, shift left/right registers,
Johnson counter, asynchronous and synchronous counters.

3.1 INTRODUCTION TO SEQUENTIAL CIRCUITS:

Sequential logic circuits are those, whose output depends not only on the present value of the
input but also on previous values of the input signal (history of values) which is in contrast to
combinational circuits where output depends only on the present values of the input, at any
instant of time. Sequential circuit can be considered as combinational circuit with feedback
circuit. Sequential circuit uses a memory element like flip – flops as feedback circuit in order
to store past values. The block diagram of a sequential logic is shown below.

Fig 3.1 Block Diagram of Sequential Logic

3.2 FLIP-FLOPS:
A flip flop is a basic data storage element. A NAND or NOR gate individually act as a storage
element when they are cross coupled with feedback. Such cross coupled NAND or NOR gates
with feedback are known as flip flops. A flip flop is a bistable (output will remain permanently
either 0 or 1 until it is forced to change the state by an external trigger) circuit. A flip flop have
two outputs Q and Q’, and are complement to each other.

(a) R-S (RESET-SET)FLIP FLOP USING NOR GATES:

R Truth Table:
Q S R Q (output)
0 0 No Change
1 0 1 (SET)
S Q’ 0 1 0 (RESET)
Figure 3.2.1 RS Flip Flop using NOR Gate 1 1 Invalid
The truth table shown for NOR gate flip flop is similar to that of transistor flip flop.
(b) R-S (RESET-SET) FLIP FLOP USING NAND GATES:
S Truth Table:
Q
S R Q (output)
0 0 Invalid
1 0 0 (RESET)
Q’ 0 1 1 (SET)
R
Figure 3.2.2 RS Flip Flop using NAND Gate 1 1 No Change

The truth table shown for NAND gate flip flop is inverted to that of NOR gate flip flop, hence
inverters gates are used to drive the inputs to the gates as shown:

S’ Truth Table:
S Q S R Q (output)
0 0 No Change
1 0 1 (SET)
0 1 0 (RESET)
Q’
R 1 1 Invalid
R’
Figure 3.2.3 RS Flip Flop

The truth table for NAND gate flip flop with inverters is similar to that of transistor flip flop,
hence this flip flop is used to realize the desired flip flop.

(c) CLOCKED R-S FLIP FLOP:

S S’ Truth Table:
Q Clock S R Q (output)
1 0 0 No Change
Clock 1 1 0 1 (SET)
1 0 1 0 (RESET)
Q’
1 1 1 Invalid
R R’
Figure 3.2.4Clocked RS Flip Flop

The clock signal or the enabling signal which makes the circuit to perform the required
operation. If clock = 0, the circuit output will remain unchanged. If clock = 1, the flip flop is
enabled and respond to the applied input signal.

(d) J-K FLIP FLOP:

In order to overcome the invalid condition in R-S Flip Flop, the J-K Flip Flop is used.
S
S’
J Q
Clock

K Q’
R’
R
Figure 3.2.5JK Flip Flop
Truth Table of J-K Flip Flop:

CLK J K Qn S R Qn+1 Remarks

(output)
1 0 0 0 0 0 0
Qn (No change)
1 0 0 1 0 0 1
1 0 1 0 0 0 0
0 (RESET)
1 0 1 1 0 1 0
1 1 0 0 1 0 1
1 (SET)
1 1 0 1 0 0 1
1 1 1 0 1 0 1
Toggle or complement
1 1 1 1 0 1 0

Qn represent the past state; Qn+1 represent the present state i.e. the state of the output
after the clock pulse is applied.
The J-input is analogous to the S input and K to the R input. So, when J=1 and K=0, the J-K flip
flop is in SET state and when, J = 0 and K = 1, the flip flop is in RESET state. When J=K=1, the
flip flop will complement its output condition, with high clock signal. This is the RACE around
condition and it is aproblem in JK flip flop. To overcome the problem of race around condition,
Master-Slave JK flip flop is used.

(e) Master-Slave JK Flip-flop

The master-slave flip-flop eliminates all the timing problems by using two SR flip-flops
connected together in a series configuration. One flip-flop acts as the “Master” circuit, which
triggers on the leading edge of the clock pulse while the other acts as the “Slave” circuit,
which triggers on the falling edge of the clock pulse. This results in the two sections, the
master section and the slave section being enabled during opposite half-cycles of the clock
signal.
The TTL 74LS73 is a Dual JK flip-flop IC, which contains two individual JK type bistable’s within
a single chip enabling single or master-slave toggle flip-flops to be made. Other JK flip flop IC’s
include the 74LS107 Dual JK flip-flop with clear, the 74LS109 Dual positive-edge triggered JK
flip flop and the 74LS112 Dual negative-edge triggered flip-flop with both preset and clear
inputs.
Dual JK Flip-flop 74LS73

Figure 3.2.6 DualJK Flip Flop

The Master-Slave JK Flip-flop
The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series
configuration with the slave having an inverted clock pulse. The outputs from Q and Q from
the “Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the
“Master” flip flop being connected to the two inputs of the “Slave” flip flop. This feedback
configuration from the slave’s output to the master’s input gives the characteristic toggle of
the JK flip flop as shown below.

The Master-Slave JK Flip Flop

Figure 3.2.7 Dual JK Flip Flop

The input signals J and K are connected to the gated “master” SR flip flop which “locks” the
input condition while the clock (Clk) input is “HIGH” at logic level “1”. As the clock input of
the “slave” flip flop is the inverse (complement) of the “master” clock input, the “slave” SR
flip flop does not toggle. The outputs from the “master” flip flop are only “seen” by the gated
“slave” flip flop when the clock input goes “LOW” to logic level “0”.
When the clock is “LOW”, the outputs from the “master” flip flop are latched and any
additional changes to its inputs are ignored. The gated “slave” flip flop now responds to the
state of its inputs passed over by the “master” section.
Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop are
fed through to the gated inputs of the “slave” flip flop and on the “High-to-Low” transition the
same inputs are reflected on the output of the “slave” making this type of flip flop edge or
pulse-triggered.
Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data to
the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip
flop is a “Synchronous” device as it only passes data with the timing of the clock signal.

(f) T- Flip Flop (Toggle or change state):

T- flip flop is a single input version of the JK flip flop. T flip flop is obtained if both the inputs of
JK flip flop are tied together.
 Truth Table:
S
S’ Clock T Qn+1
J Q (output)
T Clock 1 0 Qn
1 1 Qn’
K Q’
R’
R
Figure 3.2.8JK Flip Flop
(g) D-Flip Flop:
The SR or JK flip flop can be converted into a delay (D) flip flop. The D flip flop receives the
designation from its ability to transfer data into a flip flop i.e when clock is high the output Q
follows the state of the input line D.

Truth Table:
D S
S’ Clock D Qn+1
J Q (output)
Clock 1 0 0
1 1 1
K Q’
R’
R
Figure 3.2.9D Flip Flop

3.3 EDGE & LEVEL TRIGGERED CIRCUITS:

Triggering is very important in the sequential circuits. The circuits operates with the clock
waveforms. The circuit can be made to work on either level or edge triggering.

Level Triggered Circuits:

We know that the clock pulse is having the two levels. Therefore if the output is changing
during the positive or negative levels of the clock pulse, then the triggering is called the Level
Triggered Circuits. In level triggering the circuit gets activated when the clock waveform
reaches certain level i.e. either 1 or 0. Clock waveform for level triggering is shown in figure
3.3.1 (a).

Figure 3.3.1 Level and Edge Triggering

Edge Triggered Circuits:
If the output of any sequential circuits is changing during the transition period of the clock
waveform then the triggering is called the Edge Triggering. This can be seen in figure 3.3.1 (b)
and (c).
Edge triggered circuits are those circuits which reads the data available at the input pins i.e.
gets activated only on the edge of the clock cycle. The edge may be positive or negative
depending on that the circuits are called Positive Edge Triggered Circuits and Negative Edge
Triggered Circuits.
In positive edge triggered circuts the circuit gets activated when the clock pulse is moving
from level 0 to level 1, whereas in negative edge triggered circuits the circuit gets activated
when the clock amplitude is moving towards 0 from 1.

3.4 SHIFT REGISTERS:

The register capable of shifting itsbinary information either to the right or to the left is called
shift register. Shift register consists of array of flio flops connected in cascade. All flip flops
receive a common clock pulse which causes the shift from one stage to the next stage.
Shift registers are classified depending upon the way data are loaded and retrieved.
Classified as- 1.Serial Input Serial Output Shift Register 2.Serial Input Parallel Output Shift
Register 3.Parallel Input Serial Output Shift Register 4.Parallel Input Parallel Output Shift
Register.

1. Serial Input Serial Output Shift Register (SISO):

Serial I/P
D Q D Q D Q D Q
F1 F2 F3 F4 Serial Output

Q’ Q’ Q’ Q’
Clock
Figure 3.4.1Serial Input Serial Output Shift Register

From the above diagram of SISO shift register, output of eah flip flop is connected to the input
of the next flip flop at its right. Each clock pulse shifts the contents of the register one bit to
the right.

Operation:
Serial loading of Information or data: Serial retriving of Information or data:

Input F1 F2 F3 F4 Clock Clock Pulse F1 F2 F3 F4 Output

Sequence Pulse Sequence
1101 0 0 0 0 Initial After 4 CP 1 1 0 1 -----
state After 5 CP X 1 1 0 1
1 0 0 0 After 1 CP After 6 CP X X 1 1 01
0 1 0 0 After 2 CP After 7 CP X X X 1 101
1 0 1 0 After 3 CP After 8 CP X X X X 1101
1 1 0 1 After 4 CP Serial retriving of data
Serial Loading of data

2. Serial Input Parallel Output Shift Register (SIPO):

In SIPO, data is loaded serially, one bit at a time but data can be read simultaneously.Clock
pulse stop at the movement the binary information is stored. Each output is available on a
separate line, and they may be read simultaneously.
 Parallel Output

Q1 Q2 Q3 Q4
Serial I/P
D Q D Q D Q D Q
F1 F2 F3 F4
Q’ Q’ Q’ Q’
Clock
Figure 3.4.2 Serial Input Parallel Output Shift Register

3. Parallel Input Parallel Output Shift Register (PIPO):

D1 D2 D3 D4

Q1 Q2 Q3 Q4

D Q D Q D Q D Q
F1 F2 F3 F4
Q’ Q’ Q’ Q’
Clock
Figure 3.4.3 Parallel Input Parallel Output Shift Register
In PIPO shift register, input data D1,D2,D3 and D4 can be loaded into the flip flop
simultaneously through enable pulse and can be retrived simultaneously also from outputs
Q1,Q2,Q3 and Q4.

4. Parallel Input Serial Output Shift Register (PISO):

In PISO shift register, all flip flops are preset and the input binary information is written into
the register, all bits in parallel, by the preset enable pulse. The stored information may be read
serially by applying clock pulses. Since the data can be loaded into the flip flop simultaneously
and can be read from the register one bit at a time by clock pulse, this shift register is a
parallel to serial converter.

D1 D2 D3
Enable

D1 D2 D3 Serial
O/P
Q Q
Q
D Q D Q D Q
F1 F2 F3
Q’ Q’ Q’
Clock

Figure 3.4.4 Parallel Input Serial Output Shift Register

From the above figure of PISO shift register, data input D1,D2 and D3 are loaded
simultaneously, when Enable = 1. When Enable = 0, loaded data is taken out serially from Q3
output of F3 flip flop. On application of clock pulse.

APPLICATIONS OF SHIFT REGISTERS:

1. TheSISO shift register is used to provide a time delay from input to output. If N is the
number of flip flop and fc is the clock frequency, then the time delay is-
Td = N x 1 / fc

2. RING COUNTER:Ring counter is a shift register, in which output of last stage is feedback to
the input of first stage.

Q1 Q2 Q3 Q4

D1 Q D2 Q D3 Q D4 Q
F1 F2 F3 F4
Q’ Q’ Q’ Q’
Clock
Figure3.4.5: 4-bit Ring Counter

Q1 Q2 Q3 Q4 Clock pulse
Reference State 1 0 0 1
1 1 0 0 1
0 1 1 0 2
0 0 1 1 3
1 0 0 1 4
Count Sequence

Above table shows the count sequence of 4-bit

ring counter. Assuming the starting state as 1001
Q1=1,Q2=0,Q3=0 and Q4=1. After a clock pulse 1,
Q1 bit is shifted to Q2, Q2 to Q3, Q3 to Q4 and
from Q4 to Q1 and counter is in 1100 state. The 1001 1001
second and third clock pulse produces 0110
and 0011 respectively. Further clock pulses
causes the sequence to repeat. Since it has 4- 1001
different states before the sequence repeats,
therefore it is also called MOD-4 counter. Figure 3.4.6: State Diagram of Ring Counter
3.5JOHNSON COUNTER (Twisted Ring Counter or Moebius Counter):
In johnson counter, the complement output of last stage flip flop is feedback to input of first
stage.

Q1 Q2 Q3 Q4

D1 Q D2 Q D3 Q D4 Q
F1 F2 F3 F4
Q’ Q’ Q’ Q’
Clock
Figure3.5.1: 4-bit Johnson Counter
 Q1 Q2 Q3 Q4 Clock pulse
Reference State 0 0 0 0
1 0 0 0 1
1 1 0 0 2
1 1 1 0 3
1 1 1 1 4
0 1 1 1 5
0 0 1 1 6
0 0 0 1 7
0 0 0 0 8
Table: Johnson Counter Count Sequence

3.6 ASYNCHRONOUS AND SYNCHRONOUS COUNTERS:

Counters are digital circuit which is used to count the clock pulses or to generate the sequence
of states. Science clock pulses occur at known intervals, the counter can be used for
measuring time and therefore period or frequency.
Asynchronous Counter or Serial Counter:
1.Each flip flop is triggered by the previous flip flop. Except the first flip flop.
2.Counter is simple and straight forward in operation.
3.Construction usually requires a minimum number of hardware.
4.Counters has a cumulative settling time.
Synchronous Counter or Parallel Counter:
1.Every flip flop is triggered by the clock (in synchronism).
2.Increase in speed of operation.
3. Construction- Increased in hardware.
4. Settling time is equal to the delay time of a single flip flop.

Modulus of Counter(MOD): Modulus of counter is the number of different states before the
sequence repeats. Example- 3-bit binary counter has 8 different states, so MOD-8 counter.

ASYNCHRONOUS UP- COUNTER (BINARY RIPPLE COUNTER):

+Vcc

Q1 Q2 Q3
T Q T Q T Q
A B C
Q’ Q’ Q’
Clock Figure 3.6.01: 3-Bit Binary Ripple Counter
3-bit binary ripple counter using T-Flip flop is shown above. From the figure, negative edge
triggered clock drives the flip flop “A”. Output Q1 of flip flop “A” drives the flip flop “B” and
output Q2 of flip flop “B” drives flip flop “C”. Flip flop “A” change state before it can trigger the
flip flop “B” and flip flop “B” has to change state before it can trigger the flip flop “C”. The
trigger moves through the flip flop like a ripple in water, hence the name Ripple Counter.
Operation: Let assume all flip flop are reset to produce “0”. Consider flip flop “A” as least
significant bit (LSB) and flip flop “C” as most significant bit (MSB), so the content of counter is
CBA = 0 0 0.
 Cloc Q Q Q Coun a b c d e f g h
Time
0 0 0 0
a 0 0 1 1
Clock
b 0 1 0 2
c 0 1 1 3
Q1
d 1 0 0 4
e 1 0 1 5
f 1 1 0 6 Q2
g 1 1 1 7
h 0 0 0 0 Q3
TRUTH TABLE
Figure 3.6.02: Waveforms
From the waveform, for every negative clock transition, output Q1 of flip flop A will change
the state. Since flip flop A output Q1, act as a clock for flip flop B, each time the waveform at
Q1 goes low, output Q2 of flip flop B will toggle (change the state). Each time the output Q2 of
flip flop B goes low, output Q3 of flip flop C will toggle (change the state).

ASYNCHRONOUS DOWN COUNTER:

+Vcc

A B C
T A T B T C
FF1 FF2 FF3
A’ B’ C’
Clock Figure3.6.03: 3-bit Asynchronous down Counter

System clock is used to drive flip flop 1, but the complement A’ of flip flop-1, is used to drive
the flip flop-2 and complement B’ of flip flop-2, is used to drive the flip flop-3. Output A of flip
flop-1 toggles with every negative clock transition. But flip flop 2 will toggle each time A goes
high i.e. A’ goes low and it is this negative transition that triggers flip flop-2. On the time line,
flip flop-2 toggles at point a,c,e,g and i. similarly, flip flop-3 is triggered by B’ and so flip flop-3
will toggle each time flip flop-2 goes high. Thus flip flop-3 toggles high at point a on time line
and toggles back at point e and high at point i. Notice that the counter content are reduced by
one count with each clock transition i.e in count down mode.
TRUTH TABLE a b c d e f g h
Clock C B A Count Time
1 1 1 7
a 1 1 0 6 Clock
b 1 0 1 5
c 1 0 0 4 A
d 0 1 1 3
e 0 1 0 2 B
f 0 0 1 1
g 0 0 0 0 C
h 1 1 1 7
Figure 3.6.04: Waveforms
SYNCHRONOUS COUNTER OR PARALLEL COUNTER:
In a ripple counter (asynchronous counter) flip flop delay times are additive and the total
settling time for the counter is approximate the delay times the total number of flip flops.
These problem is overcome by the use of a synchronous counter or parallel counter. Here
every flip flop is triggered in synchronism with the clock.

SYNCHRONOUS 3-BIT BINARY UP COUNTER OR MOD-8 PARALLEL COUNTER:

A3 A2 A1
Q’ Q Q’ Q Q’ Q

T T T

To next Clock
stage
Count Enable
Figure 3.6.05: 3- Bit Synchronous Up Counter

Truth Table:
Count Clock A3 A2 A1 count a b c d e f g h
Enable pulse Time
0 0 0 0
1 1 0 0 1 1 Clock
1 1 0 1 0 2
1 1 0 1 1 3 A1
1 1 1 0 0 4
1 1 1 0 1 5 A2
1 1 1 1 0 6
1 1 1 1 1 7
1 1 0 0 0 0 A3
Figure 3.6.06: Waveforms

The truth table and waveforms of 3-bit synchronous up counter is shown above.

SYNCHRONOUS 3-BIT BINARY DOWN COUNTER :

A3 A2 A1

Q’ Q Q’ Q Q’ Q

T T T

To next
Clock
stage
Count Enable
Figure 3.6.07: 3- Bit Synchronous down Counter
 TRUTH TABLE
Clock A3 A2 A1 Count Time
a b c d e f g h
a 1 1 1 7
b 1 1 0 6
Clock
c 1 0 1 5
d 1 0 0 4
A1
e 0 1 1 3
f 0 1 0 2
g 0 0 1 1 A2
h 0 0 0 0
1 1 1 7 A3

Waveforms
Figure 3.6.08: Waveform and truth table of 3-bit binary down counter

Since memory elements in sequential circuits are usually flip-flops, it is worth

summarizing the behavior of various flip-flop types before proceeding further.

Summary of Characteristics Table & Excitation table

All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of
inputs and in the response invoked by different value of input signals. The four types of flip-
flops are defined in Table 1.

FLIP-FLOP FLIP-FLOP CHARACTERISTIC CHARACTERISTIC

EXCITATION TABLE
NAME SYMBOL TABLE EQUATION
S R Q(next) Q Q(next) S R
0 0 Q Q(next) = S + 0 0 0 X
R'Q
SR 0 1 0 0 1 1 0
1 0 1 SR = 0 1 0 0 1
1 1 ? 1 1 X 0

J K Q(next) Q Q(next) J K
0 0 Q 0 0 0 X
Q(next) = JQ' +
JK 0 1 0 0 1 1 X
K'Q
1 0 1 1 0 X 1
1 1 Q' 1 1 X 0
D Q(next) Q Q(next) D

0 0 0
D 0 0 Q(next) = D 0 1 1
1 1 1 0 0
1 1 1
 Q Q(next) T
T Q(next) 0 0 0
0 Q Q(next) = TQ' + 0 1 1
T
1 Q' T'Q
1 0 1
1 1 0

Each of these flip-flops can be uniquely described by its graphical symbol, its characteristic
table, its characteristic equation or excitation table. All flip-flops have output signals Q and Q'.

The characteristic table in the third column of Table 1 defines the state of each flip-flop as a
function of its inputs and previous state. Q refers to the present state and Q(next) refers to
the next state after the occurrence of the clock pulse. The characteristic table for the RS flip-
flop shows that the next state is equal to the present state when both inputs S and R are
equal to 0. When R=1, the next clock pulse clears the flip-flop. When S=1, the flip-flop output
Q is set to 1. The equation mark (?) for the next state when S and R are both equal to 1
designates an indeterminate next state.

The characteristic table for the JK flip-flop is the same as that of the RS when J and K are
replaced by S and R respectively, except for the indeterminate case. When both J and K are
equal to 1, the next state is equal to the complement of the present state, that is, Q(next) =
Q'.

The next state of the D flip-flop is completely dependent on the input D and independent of
the present state.

The next state for the T flip-flop is the same as the present state Q if T=0 and complemented
if T=1.

The characteristic table is useful during the analysis of sequential circuits when the value of
flip-flop inputs are known and we want to find the value of the flip-flop output Q after the
rising edge of the clock signal. As with any other truth table, we can use the map method to
derive the characteristic equation for each flip-flop, which are shown in the third column of
Table 1.

During the design process we usually know the transition from present state to the next state
and wish to find the flip-flop input conditions that will cause the required transition. For this
reason we will need a table that lists the required inputs for a given change of state. Such a
list is called the excitation table, which is shown in the fourth column of Table 1. There are
four possible transitions from present state to the next state. The required input conditions
are derived from the information available in the characteristic table. The symbol X in the
table represents a "don't care" condition, that is, it does not matter whether the input is 1 or
0.