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MAX25203 Dual-Phase Synchronous Boost Controller with

Programmable Gate Drive and I2C

General Description Benefits and Features

The MAX25203 automotive dual-phase synchronous ● Meets Stringent OEM Module Power Consumption
boost controller enables infotainment systems to stay in and Performance Specifications
regulation during cold-crank or start-stop operation all the • ±1.5% Output-Voltage Accuracy at FB
way down to a battery input of 1.8V. It can also be used • Output Voltage Adjustable Between 12V and 65V
to generate backlight voltage and Class D audio amplifier (70V Abs Max)
voltages. This device can start with an input voltage sup- • 5µA Shutdown Supply Current
ply from 4.5V to 42V and can operate down to 1.8V after ● High Efficiency and Current Sharing
start-up, and has a low 5µA shutdown supply current. • Pass-Through for >98% Efficiency
The MAX25203 operates at up to 2.1MHz frequency to al- • OTP Gate Drive Voltage from 6.5V to 10V Allows
low small external components and reduced output ripple, User to Optimize External MOSFETs and Improve
and to guarantee no AM band interference. The switching Efficiency
frequency is resistor adjustable (220kHz to 2100kHz) or it • Current Sharing Accuracy of ±5% Between Phases
can be synchronized on-the-fly to an external clock. to Improve System Efficiency
The MAX25203 has a spread-spectrum option for fre- • Programmable Current-Limit Blanking Handles High
quency modulation to minimize EMI interference. A 90° Peak Loads without Oversizing Inductor
out-of-phase clock output enables synchronizing a second ● EMI-Reduction Features Reduce Interference with
MAX25203 for quad-phase operation. Sensitive Radio Bands without Sacrificing Wide Input
Pass-through operation has over 98% efficiency when the Voltage Range
supply voltage exceeds the output regulation voltage. Pro- • Spread-Spectrum Option
grammable current-limit blanking handles high peak loads • On-the-Fly Frequency-Synchronization Input
without oversizing the inductor. • Resistor-Programmable Frequency between
220kHz and 2.1MHz
The MAX25203 features a power-OK monitor and under- • Synchronization Output Provides 90° Out-of-Phase
voltage lockout. Protection features include cycle-by-cycle Clock for Quad-Phase Operation
current limit and thermal shutdown. It operates over the
-40°C to +125°C automotive temperature range. ● Integration and Thermally Enhanced Package Saves
Board Space and Cost
• Current-Mode Controllers with Forced-Continuous
Applications and Skip Modes
● Infotainment Systems • Side-Wettable, 32-Pin TQFN-EP Package
● Automotive Audio Amplifier
● Protection Features and I2C Diagnostics for Improved
System Reliability
• Supply Undervoltage Lockout
• Die Temperature Monitoring through I2C
• Short-Circuit Protection with True ShutdownTM
• Individual Phase Current Monitoring through I2C

Ordering Information appears at end of data sheet.

True Shutdown is a trademark of Maxim Integrated Products, Inc.

19-101004; Rev 1; 8/21

MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Simplified Block Diagram

BATT
CSUP

SUP
EN
CS1P
PWM CS1N
SYNCOUT
FSYNC DH1
L1 RCS1
PGOOD/IRQ LX1

SDA DL1
SCL
BST1
OPTIONAL OUTPUT
FOSC DISCONNECT
OUTS
SS DRV OUT
RFOSC
CSS COUTS COUT
MAX25203
BIAS BST2

OUT DH2 BATT

OUTS OUTS L2 RCS2
LX2
0.1µF BIAS FB DL2

COMP
CS2P
CS2N

PGATE
RC
CF EP GND PGND

CC

www.maximintegrated.com Maxim Integrated | 2

MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SW-TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics—MAX25203Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current-Mode Control Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Fixed 5V Linear Regulator (BIAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Gate Drive LDO (DRV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Start-Up Operation/UVLO/EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Oscillator Frequency/External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pass-Through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MOSFET Drivers (DH and DL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
High-Side Gate-Driver Supply (BST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
p-Channel MOSFET Output Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Current Limiting and Current-Sense Inputs (SUP and CS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output Voltage Monitor (PGOOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Interrupt Request Output (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I2C Fault Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Thermal-Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

TABLE OF CONTENTS (CONTINUED)

Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I2C Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MAX25203 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Setting and Controlling the Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
External Feedback Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
I2C Voltage Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PWM Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Current-Sense Resistor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Current-Sense Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Inductor DCR Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Boost Converter Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MOSFET Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Threshold Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Maximum Drain-to-Source Voltage (VDS(MAX)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Current Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Low-Voltage Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Quad-Phase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Typical Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Bootstrap Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

www.maximintegrated.com Maxim Integrated | 4

MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

LIST OF FIGURES
Figure 1. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 2. I2C Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3. External Feedback Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 4. Current-Sense Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

www.maximintegrated.com Maxim Integrated | 5

MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Absolute Maximum Ratings

SUP, CS_P, EN to GND ........................................... -0.3V to 42V Package Thermal Characteristics
OUT, OUTS, LX_ to GND......................................... -0.3V to 70V T3255Y+4C
PGATE to OUTS ........................................................ -0.3V to 6V Continuous Power Dissipation
CS_P to CS_N ........................................................ -0.3V to 0.3V TQFN (derate 34.5mW/°C (Note 1) above
BIAS, FOSC, PWM, SDA, SCL, PGOOD, SS, FB to GND ..-0.3V +70°C) ...............................................................2758.6mW
to 6V Junction-to-Case Thermal Resistance (θJC) ........... 1.7°C/W
SYNCOUT, FSYNC, COMP to GND ........... -0.3V to BIAS + 0.3V Junction-to-Ambient Thermal Resistance (θJA) ........ 29°C/W
BST_ to LX_ ............................................................. -0.3V to 12V Operating Temperature Range ....................-40°C to +125°C
DH_ to LX_ ................................................. -0.3V to BST_ + 0.3V Junction Temperature ................................................ +150°C
DRV to GND ............................................................. -0.3V to 12V Storage Temperature Range .......................-65°C to +150°C
DL_ to PGND ...............................................-0.3V to DRV + 0.3V Soldering Temperature (reflow) ................................. +260°C
PGND to GND ......................................................... -0.3V to 0.3V Lead Temperature (soldering, 10s) ...........................+300°C
ESD Rating Human Body Model ..................................2.5kV
ESD Rating Charged Device Model ............................1000V
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a 4-layer
board. For detailed information on package thermal consideration see www.maxim-ic.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Recommended Operating Conditions

TYPICAL
PARAMETER SYMBOL CONDITION UNIT
RANGE
-40 to
Ambient Temperature Range °C
+125

Note: These limits are not guaranteed.

Package Information
SW-TQFN
Package Code T3255Y+4C
Outline Number 21-100214
Land Pattern Number 90-100082
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 29°C/W
Junction to Case (θJC) 1.7°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal
considerations, refer to www.maximintegrated.com/thermal-tutorial.

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MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Electrical Characteristics
(VSUP = 14V, VEN = 14V, VDRV = 10V (MAX25203ATJA), 6.5V (MAX25203BATJA), CBIAS = 2.2μF, CBST = 0.1μF, TJ = -40°C to
+150°C, unless otherwise noted (Note 2, Note 3), typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SYNCHRONOUS STEP-UP CONTROLLER
Initial startup, VSUP voltage 4.5 36
Supply Voltage Range VSUP Bootstrap mode after initial startup V
1.8 36
condition is satisfied, VBAT voltage
Output Overvoltage
Detected with respect to VFB rising 104 108 111 %
Threshold
VEN = VSUP, VSUP > VOUT, no load (not
600
including the FB divider current)
Supply Current ISUP µA
VEN = 0V, shutdown (not including FB
5 10
divider current)
Output Voltage
3.5 65 V
Adjustable Range
Regulated Feedback
VFB TA = -40°C to +125°C 0.987 1 1.012 V
Voltage
Feedback Leakage
IFB TA = +25°C 0.01 0.5 μA
Current
Feedback Line
VIN = 3.5V to 36V, VFB = 1V 0.01 %/V
Regulation Error
Transconductance (from
gm_boost VFB = 1V, VBIAS = 5V (Note 2) 170 260 370 µS
FB to COMP)
DL low to DH rising 40
Dead Time ns
DH low to DL rising 30
DH and DL Rise Time CLOAD = 3nF 20 ns
DH and DL Fall Time CLOAD = 3nF 10 ns
MAX25203ATJA 200
Minimum Off Time tOFFBST ns
MAX25203BATJA/VY+ 85
Switching Frequency
fSW Forced-PWM, resistor programmable 0.22 2.1 MHz
Range
Switching Frequency
RFOSC = 17.5kΩ, VBIAS = 5V, 3.8V 360 400 440 kHz
Accuracy
CS Current-Limit Averaged VCSP_ - VCSN_; VBIAS = 5V,
VLIMIT 40 50 60 mV
Voltage Threshold VBATT > 2.5V
Current Sharing
VCSP_- VCSN_ > 25mV, tON > 300ns -5 5 %
Accuracy
Cycle-by-Cycle CS
Peak VCSP_ - VCSN_; VBIAS = 5V,
Current-Limit Voltage VLIMIT2 90 mV
VBATT > 2.5V
Threshold
Soft-Start Current ISS 8 10 12 μA
LX Leakage Current VLX_ = VPGND or VSUP, TA = +25°C 0.001 5 μA
PGOOD_H % of FB, rising 93 95 97
PGOOD Threshold %
PGOOD_F % of FB, falling 91 93 95
PGOOD Leakage
VPGOOD = 5V, TA = +25°C 1 μA
Current

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MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Electrical Characteristics (continued)

(VSUP = 14V, VEN = 14V, VDRV = 10V (MAX25203ATJA), 6.5V (MAX25203BATJA), CBIAS = 2.2μF, CBST = 0.1μF, TJ = -40°C to
+150°C, unless otherwise noted (Note 2, Note 3), typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PGOOD Output Low
ISINK = 1mA 0.2 V
Voltage
PGOOD Debounce
Fault detection, rising and falling 150 µs
Time
PGOOD Timeout Output in regulation to PGOOD high 1 ms
FSYNC INPUT
Minimum sync pulse of 100ns,
1.8 2.6 MHz
FSYNC Input Frequency fOSC = 2.1MHz
Range Minimum sync pulse of 100ns,
250 550 kHz
fOSC = 400kHz
FSYNC Switching High threshold 1.4
V
Thresholds Low threshold 0.4
INTERNAL LDO BIAS
Internal BIAS Voltage VIN > 6V 5 V
VBIAS rising 4.5
BIAS UVLO Threshold V
VBIAS falling 3 3.3
BIAS Current Capability VBIAS = 5V 10 mA
GATE DRIVE LDO
Factory programmable 6.5
DRV Voltage Options Factory programmable 8 V
Factory programmable 10
MAX25203ATJA, VSUP = 14V,
9.6 10 10.3
IDRV = 1mA
DRV Output Voltage VDRV V
MAX25203BATJA, VSUP = 14V,
6 6.5 7
IDRV = 150mA
DRV Dropout Voltage VSUP = 6V, IDRV = 100mA 1 V
UVLO Threshold DRV rising 4.5 V
Hysteresis 0.85 V
PGATE DRIVER
PGATE Turn-On Time From turn-on to 500mA current 15 µs
PGATE Turn-Off Time From turn-off to less than 1mA 0.1 ms
PGATE VGS Drive
VBIAS > 4V 5 V
Voltage
PWM VOLTAGE POSITIONING
PWM Switching
Low threshold 0.4 V
Threshold
PWM Switching
High threshold 1.4 V
Thresholds
PWM Input Frequency
Minimum PWM pulse of 100ns 200 800 kHz
Range

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MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Electrical Characteristics (continued)

(VSUP = 14V, VEN = 14V, VDRV = 10V (MAX25203ATJA), 6.5V (MAX25203BATJA), CBIAS = 2.2μF, CBST = 0.1μF, TJ = -40°C to
+150°C, unless otherwise noted (Note 2, Note 3), typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I2C-COMPATIBLE INTERFACE TIMING CHARACTERISTICS (SCL, SDA)
SCL Clock Frequency fSCL 0 400 kHz
Bus-Free Time Between
a STOP and START tBUF 1.3 μs
Condition
Hold Time for a
tHD;STA 0.6 μs
Repeated START
SCL Pulse Width Low tLOW 1.3 μs
SCL Pulse Width High tHIGH 0.6 μs
Setup Time for a
Repeated START tSU;STA 0.6 μs
Condition
Data Hold Time tHD;DAT 0 ns
Data Setup Time tSU;DAT 100 ns
Data Valid Time tVD,DAT 900 ns
SDA and SCL Receiving 20 +
tR Incoming signals (from master) 300 ns
Rise Time CB/10
SDA and SCL Receiving 20 +
tF Incoming signals (from master) 300 ns
Fall Time CB/10
SDA Transmitting Fall 20 +
tF 250 ns
Time CB/10
Setup Time for STOP
tSU;STO 0.6 μs
Condition
Bus Capacitance
CB 2.5V ≤ VDDIO ≤ 5.5V 0 900 pF
Allowed
Width of spikes that must be suppressed
Pulse Width of a
by the input filter of both the SDA and 50 ns
Suppressed Spike
SCL signals
Input High Voltage VIH 1.2 V
Input Low Voltage VIL 0.5 V
Output Low Voltage VOL ISINK = 4mA 0.2 V
THERMAL OVERLOAD
Thermal Shutdown
170 °C
Temperature
Thermal Shutdown
20 °C
Hysteresis
EN LOGIC INPUT
High Threshold EN 1.8 V
Low Threshold EN 0.8 V
EN Input Bias Current EN logic inputs only, TA = +25°C 0.01 1 µA
SPREAD SPECTRUM
fOSC ±
Spread Spectrum SPS_EN = 0b1; SPS_RANGE = 0b1
6%

www.maximintegrated.com Maxim Integrated | 9

MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Electrical Characteristics—MAX25203Q
(VSUP = 14V, VEN = 14V, VDRV = 10V, CBIAS = 2.2μF, CBST = 0.1μF, TJ = -40°C to +150°C, unless otherwise noted (Note 2, Note 3),
typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SYNCHRONOUS STEP-UP CONTROLLER
Initial startup, VSUP voltage 4.5 36
Supply Voltage Range VSUP Bootstrap mode after initial startup V
1.8 36
condition is satisfied, VBAT voltage
VEN = 0V, shutdown (not including FB
Supply Current ISUP 5 10 µA
divider current)
DL low to DH rising 40
Dead Time ns
DH low to DL rising 30
DH and DL Rise Time CLOAD = 3nF 20 ns
DH and DL Fall Time CLOAD = 3nF 10 ns
Minimum Off-Time tOFFBST 200 ns
CS Current-Limit Averaged VCSP_ - VCSN_; VBIAS = 5V,
VLIMIT 40 50 60 mV
Voltage Threshold VBATT > 2.5V
Current Sharing
VCSP_- VCSN_ > 25mV, tON > 300ns -5 5 %
Accuracy
Cycle-by-Cycle CS
Peak VCSP_ -VCSN_; VBIAS = 5V,
Current Limit Voltage VLIMIT2 90 mV
VBATT > 2.5V
Threshold
LX Leakage Current VLX_ = VPGND or VSUP, TA = +25°C 0.001 5 μA
FSYNC INPUT
Minimum sync pulse of 100ns,
1.8 2.6 MHz
FSYNC Input Frequency fOSC = 2.1MHz
Range Minimum sync pulse of 100ns,
250 550 kHz
fOSC = 400kHz
FSYNC Switching High threshold 1.4
V
Thresholds Low threshold 0.4
INTERNAL LDO BIAS
Internal BIAS Voltage VIN > 6V 5 V
VBIAS rising 4.5
BIAS UVLO Threshold V
VBIAS falling 3 3.3
BIAS Current Capability VBIAS = 5V 10 mA
GATE DRIVE LDO
Factory programmable 6.5
DRV Voltage Options Factory programmable 8 V
Factory programmable 10
DRV Output Voltage VDRV VSUP = 14V, IDRV = 1mA 9.6 10 10.3 V
DRV Dropout Voltage VSUP = 6V, IDRV = 100mA 1 V
UVLO Threshold DRV rising 4.5 V
Hysteresis 0.85 V
I2C-COMPATIBLE INTERFACE TIMING CHARACTERISTICS (SCL, SDA)
SCL Clock Frequency fSCL 0 400 kHz

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MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Electrical Characteristics—MAX25203Q (continued)

(VSUP = 14V, VEN = 14V, VDRV = 10V, CBIAS = 2.2μF, CBST = 0.1μF, TJ = -40°C to +150°C, unless otherwise noted (Note 2, Note 3),
typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Bus-Free Time Between
a STOP and START tBUF 1.3 μs
Condition
Hold Time for a
tHD;STA 0.6 μs
Repeated START
SCL Pulse Width Low tLOW 1.3 μs
SCL Pulse Width High tHIGH 0.6 μs
Setup Time for a
Repeated START tSU;STA 0.6 μs
Condition
Data Hold Time tHD;DAT 0 ns
Data Setup Time tSU;DAT 100 ns
Data Valid Time tVD;DAT 900 ns
SDA and SCL Receiving 20 +
tR Incoming signals (from master) 300 ns
Rise Time CB/10
SDA and SCL Receiving 20 +
tF Incoming signals (from master) 300 ns
Fall Time CB/10
SDA Transmitting Fall 20 +
tF 250 ns
Time CB/10
Setup Time for STOP
tSU;STO 0.6 μs
Condition
Bus Capacitance
CB 2.5V ≤ VDDIO ≤ 5.5V 0 900 pF
Allowed
Width of spikes that must be suppressed
Pulse Width of a
by the input filter of both the SDA and 50 ns
Suppressed Spike
SCL signals
Input High Voltage VIH 1.2 V
Input Low Voltage VIL 0.5 V
Output Low Voltage VOL ISINK = 4mA 0.2 V
THERMAL OVERLOAD
Thermal Shutdown
170 °C
Temperature
Thermal Shutdown
20 °C
Hysteresis
EN LOGIC INPUT
High Threshold EN 1.8 V
Low Threshold EN 0.8 V
EN Input Bias Current EN logic inputs only, TA = +25°C 0.01 1 µA

Note 2: All units are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltages are
guaranteed by design and characterization.
Note 3: The device is designed for continuous operation up to TJ = +125°C for 95,000 hours and TJ = +150°C for 5,000 hours.

www.maximintegrated.com Maxim Integrated | 11

MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Typical Operating Characteristics

(VSUP = 14V; VEN = 14V; TA = +25°C unless otherwise noted.)

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MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Typical Operating Characteristics (continued)

(VSUP = 14V; VEN = 14V; TA = +25°C unless otherwise noted.)

Pin Configuration
SYNCOUT
FSYNC

TOP VIEW
CS2N

CS2P
BST2

PWM

SDA
SCL

24 23 22 21 20 19 18 17

DH2 25 16 FOSC

LX2 26 15 PGOOD /IRQ

DL2 27 14 SS

PGND 28 MAX25203 13 COMP

DRV 29 12 NC

DL1 30 11 GND

LX1 31 10 BIAS
+
DH1 32 9 FB

1 2 3 4 5 6 7 8
BST1

CS1P
CS1N
EN

SUP

OUT
OUTS

PGATE

SW TQFN
5mm x 5mm

Pin Description
PIN NAME FUNCTION
Boost Flying Capacitor Connection for High-Side Gate Voltage. Connect a high-voltage diode
1 BST1 between DRV and BST1. Connect a ceramic capacitor between BST1 and LX1. See the High-Side
Gate-Driver Supply (BST) section.
High-Voltage Tolerant, Active-High Digital Enable Input for Controller. Driving EN low disables the
boost controller. EN also has a very accurate threshold of ±3% for both rising and falling voltages.
2 EN A resistor-divider can be used to control the turn ON and OFF of the boost controller in hardware
by using a resistor-divider. When EN is low, the MAX25203 is powered off, including BIAS and I2C
interface. Bring EN high to enable the MAX25203 and power up into the default state.

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MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Pin Description (continued)

PIN NAME FUNCTION
Negative Current-Sense Input for Phase 1. Connect CS1N to the negative side of the current-
3 CS1N
sense element. See the Current Limiting and Current-Sense Inputs (SUP and CS) section.
Positive Current-Sense Input for Phase 1. Connect CS1P to the positive side of the current-sense
4 CS1P
element. See the Current Limiting and Current-Sense Inputs (SUP and CS) section.
5 SUP Supply Input. Connect SUP to the main battery.
6 OUTS True Shutdown PFET's Source Connection.
External p-Channel MOSFET Gate Connection. Connect PGATE to the gate of the external p-
7 PGATE
channel output disconnect switch. Connect PGATE to GND if not used.
8 OUT Output Voltage Sense for Internal Feedback Divider. Connect OUT to the boost output.
Boost Converter Feedback Input. Connect FB to BIAS to use the I2C programmed output voltage
or PWM voltage control. For external feedback, connect FB to the center tap of a resistor-divider
9 FB
between the boost regulator output. FB regulates to 1V (typ). See the Setting and Controlling the
Output Voltage section.
5V Internal Linear Regulator Output. Bypass BIAS to GND with a low-ESR ceramic capacitor of
10 BIAS 1µF minimum value. BIAS provides the power to the internal circuitry and external loads. See the
Fixed 5V Linear Regulator (BIAS) section.
11 GND Ground.
12 NC Leave this pin unconnected.
Boost Controller Error Amplifier Output. Connect an RC network to COMP to compensate the
13 COMP
boost converter.
Soft-Start. Connect a capacitor from SS to GND to set the soft-start time. See the Soft-Start
14 SS
section.
Open-Drain Power-Good Output or Interrupt Request. This pin is configured as either a power-
good (PGOOD) output or interrupt request (IRQ) output (see the Ordering Information table). To
obtain a logic signal, pull up PGOOD/IRQ with an external resistor connected to a positive voltage
lower than 5.5V.

PGOOD pulls low when OUT is more than 93% (typ) below the normal regulation point. PGOOD is
low during soft-start and in shutdown. PGOOD becomes high impedance when OUT is in
regulation.
15 PGOOD/IRQ
IRQ pulls low when OUT is more than 93% (typ) below the normal regulation point and when a
fault is reported in the FAULT register. IRQ is low during shutdown, and remains low after startup
until the FAULT register has been read. IRQ becomes high impedance after reading the
FAULT_STAT register when OUT is in regulation. If there is a persistent fault, IRQ pulls low again
after reading FAULT, otherwise IRQ remains high until a fault occurs.

See the Output Voltage Monitor (PGOOD) and Interrupt Request Output (IRQ) sections for details.
Frequency Setting Input. Connect a resistor to FOSC to set the switching frequency of the DC-DC
16 FOSC
converters.
Synchronization Clock Output. SYNCOUT outputs a clock that is 90° out-of-phase with the internal
17 SYNCOUT oscillator or the external FSYNC input. For the quad-phase configuration, connect SYNCOUT of
the master to FSYNC of the slave.
External Clock Synchronization Input. To synchronize with an external clock, connect the clock to
FSYNC. See the Oscillator Frequency/External Synchronization section. When not using external
18 FSYNC
synchronization, connect FSYNC to BIAS for forced-PWM operation with the internal clock, or
connect FSYNC to GND for skip-mode operation.
19 SDA I2C Data Input/Output.
20 SCL I2C Clock Input.

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MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Pin Description (continued)

PIN NAME FUNCTION
PWM Positioning Control Input. Controls the output voltage, allowing it to track a digital duty cycle
21 PWM (PWM) signal. Connect PWM to GND when using an external resistor-divider to set the output
voltage or if PWM is not used.
Positive Current-Sense Input for Phase 2. Connect CS2P to the positive side of the current-sense
22 CS2P
element. See the Current Limiting and Current-Sense Inputs (SUP and CS) section.
Negative Current-Sense Input for Phase 2. Connect CS2N to the negative side of the current-
23 CS2N
sense element. See the Current Limiting and Current-Sense Inputs (SUP and CS) section.
Boost Flying Capacitor Connection for High-Side Gate Voltage. Connect a high-voltage diode
24 BST2 between DRV and BST2. Connect a ceramic capacitor between BST2 and LX2. See the High-Side
Gate-Driver Supply (BST) section.
25 DH2 High-Side MOSFET Gate Driver Output. The DH2 output voltage swings from VLX2 to VBST2.
Inductor Connection for Phase 2. Connect LX2 to the switched side of the inductor. LX2 serves as
26 LX2
the lower supply rail for the DH2 high-side gate driver.
27 DL2 Low-Side n-Channel MOSFET Gate Driver Output for Phase 2.
28 PGND Power Ground.
6.5V to 10V Preset Low-Dropout Voltage-Regulator Output. Bypass DRV to GND with a 4.7μF or
29 DRV greater ceramic capacitor. This voltage is used as the gate drive voltage for external MOSFETs.
See the Ordering Information table for the factory-set DRV voltage.
30 DL1 Low-Side n-Channel MOSFET Gate Driver Output for Phase 1.
Inductor Connection for Phase 1. Connect LX1 to the switched side of the inductor. LX1 serves as
31 LX1
the lower supply rail for the DH1 high-side gate driver.
32 DH1 High-Side MOSFET Gate Driver Output. The DH1 output voltage swings from VLX1 to VBST1.
Exposed Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does
EP EP not remove the requirement for proper ground connections to GND. The exposed pad is attached
with epoxy to the substrate of the die, making it an excellent path to remove heat from the IC.

www.maximintegrated.com Maxim Integrated | 15

MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Functional Diagram

OUT SS PGOOD COMP SUP SDA SCL

VBIAS
EN
BATUV
VCS
USER MODE I2C
PGOOD EN AON AND IMON ADC
COMP VBIAS
OTP
IBIAS1
FB FEEDBACK EAMP BG IBIAS SUP
SELECT IBIAS2
LOGIC
PWM SS VREF<1:N>
REF DRV
GDRVCC
HVLDO_10V
VREF 1V THERMAL
FSYNC SHDN
FSYNC
SELECT
LOGIC
PHASE MASTER AND SLAVE
EXTERNAL EN BST1,2
CLOCK INPUT
FOSC
SLOPE STEP-UP DC-DC
OSCILLATOR
SPS_EN COMP LOGIC DH1,2
PWM LOGIC
PWM
SYNC CSA
OFFSET GATE DRIVE LX1,2
OUT CLK
CLK REG LOOP
SLAVE
ONLY VREF<2> ILIM/ZX DL1,2
CLK 180° VCS
OUT-OF-PHASE
SKIP GND
CLK (FOR SLAVE) CURRENT-
LIMIT
THRESHOLD
MODE SKIP ZERO
SELECT CROSS
COMP
OUTS

CSP1,2
PGATE
CSN1,2

SHORT SUP
PROTECTION
VBIAS BIAS
HVLDO_5V
BIASUV

www.maximintegrated.com Maxim Integrated | 16

MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Detailed Description
The MAX25203 automotive dual-phase synchronous boost controller enables infotainment systems to stay in regulation
during cold-crank or start-stop operation all the way down to a battery input of 1.8V. It can also be used to generate
backlight voltage and Class D audio amplifier voltages. This device can start with an input voltage supply from 4.5V to
42V and can operate down to 1.8V after start-up, and has a low 5µA shutdown supply current.
The MAX25203 operates at up to 2.1MHz frequency to allow small external components and reduced output ripple, and
to guarantee no AM band interference. The switching frequency is resistor adjustable (220kHz to 2100kHz) or it can be
synchronized on-the-fly to an external clock.
The MAX25203 has a spread-spectrum option for frequency modulation to minimize EMI interference. A 90° out-of-phase
clock output enables synchronizing a second MAX25203 for quad-phase operation.
Pass-through operation has over 98% efficiency when the supply voltage exceeds the output regulation voltage.
Programmable current-limit blanking handles high peak loads without oversizing the inductor.
The MAX25203 features a power-OK monitor and undervoltage lockout. Protection features include cycle-by-cycle
current limit and thermal shutdown. It operates over the -40°C to +125°C automotive temperature range.

Current-Mode Control Loop

Peak current-mode control operation provides excellent load step performance and simple compensation. The inherent
feed-forward characteristic is useful especially in automotive applications where the input voltage changes quickly during
cold-crank and load-dump conditions. To avoid premature turn-off at the beginning of the on-cycle, the current-limit and
PWM comparator inputs have leading-edge blanking.

Fixed 5V Linear Regulator (BIAS)

An internal 5V linear regulator (BIAS) is used to power the controller's internal circuitry. Connect a 1μF or greater ceramic
capacitor from BIAS to GND as close to the IC pins as possible to guarantee stability under the full-load condition. If
the BIAS voltage drops below the undervoltage (UVLO) threshold, the controller will shut down and all I2C register value
reset to their default values.

Gate Drive LDO (DRV)

DRV is a low-dropout voltage regulator (LDO) used to supply the gate drive for external MOSFETs. The gate drive LDO
output voltage is factory preset to 6.5V, 8V, or 10V; see the Ordering Information table for each part number's drive
voltage. DRV can provide up to 150mA (typ) total. The gate drive current requirements can be estimated as follows:
IDRV= fSW (QG1DL + QG1DH + QG2DL + QG2DH)
where fSW is the switching frequency (per phase), and QG_ is the low- and high-side MOSFET total gate charge
(MOSFET specification at VGS = VDRV). To reduce the internal power dissipation, DRV can optionally be connected to
an external 6.5V to 10V rail, bypassing the internal linear regulator.
If the DRV voltage drops below the undervoltage (UVLO) threshold switching stops, the controller is shutdown, and I2C
register values are reset to default. When DRV rises above its UVLO rising threshold, the controller will begin soft-start.

Start-Up Operation/UVLO/EN
The BIAS input undervoltage lockout (UVLO) circuitry inhibits switching if the 5V bias supply (BIAS) is below its UVLO
falling threshold (see the Electrical Characteristics table). Once the 5V bias supply (BIAS) rises above its UVLO rising
threshold and EN is high, the boost controller starts switching and the output voltage begins to ramp up using soft-start.
Driving EN low disables the device and reduces the standby current to less than 10μA.

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MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Soft-Start
Soft-start ramps up the internal reference during start-up to reduce input surge current. Soft-start begins when EN is logic-
high and VBIAS and VDRV are above the undervoltage lockout threshold. The soft-start time (tSS) is set by connecting a
resistor from SS to GND.
CSS = tSS × 10 µ A / V

Oscillator Frequency/External Synchronization

The MAX25203 internal oscillator is set by a resistor connected from FOSC to GND with an adjustment range of
220kHz to 2.1MHz. High-frequency operation optimizes the application for the smallest component size, trading off
efficiency to higher switching losses. Low-frequency operation offers the best overall efficiency at the expense of
component size and board space. See the Typical Operating Characteristics section to determine the relationship
between switching frequency and RFOSC. For forced-PWM operation where the switching frequency matches the internal
oscillator frequency, connect FSYNC to BIAS. Connect FSYNC to GND to allow skip-mode operation at light loads. With
skip-mode, the output switches only as needed to supply the load, improving light-load efficiency.
The devices can also be synchronized to an external clock by connecting the external clock signal to FSYNC. For
dual-phase/master controllers (see the Ordering Information table), the per-phase frequency is 1/4 of the applied
external clock frequency. For slave controllers, FSYNC connects to SYNCOUT of the master (frequency equal to the
phase frequency). The internal oscillator is synchronized on the rising edge of the external clock. See the Electrical
Characteristics table for the FSYNC frequency range and voltage levels.

Pass-Through
When the supply voltage is higher than the output regulation voltage, switching is reduced to a 16µs period. During this
period, the high-side MOSFETs are turned on in order to maximize efficiency, and the output voltage will follow the supply
voltage. At the end of the 16µs period, a short switching cycle keeps the BST capacitors charged in order to maintain the
high-side gate drive voltage.

Spread Spectrum
Spread spectrum is used to reduce peak emission noise at the clock frequency and its harmonics, making it easier
to meet stringent EMI limits. This is done by dithering the switching frequency by a programmable percentage of the
switching frequency. The amount of dithering is programmable by I2C to between 0% (disabled), ±6%, or ±9%. See the
Ordering Information table for the default power-on spread spectrum setting. When using an external clock source (i.e.,
driving the FSYNC input with an external clock), spread spectrum is disabled.

MOSFET Drivers (DH and DL)

The DH high-side n-channel MOSFET driver is powered from BST while the low-side driver (DL) is powered from BIAS.
Each driver has shoot-through protection that monitors the gate-to-source voltage of the external MOSFETs to prevent a
MOSFET from turning on until the complementary switch is fully off. This requires a low-resistance, low-inductance path
from DL and DH to the MOSFET gates for the protection circuits to work properly.

High-Side Gate-Driver Supply (BST)

The high-side MOSFET is turned on by closing an internal switch between BST and DH and transferring the bootstrap
capacitor’s charge (at BST) to the gate of the high-side MOSFET. This charge refreshes when the high-side MOSFET
turns off and the LX voltage drops down to ground potential, taking the negative terminal of the capacitor to the same
potential. At this time, the bootstrap diode recharges the positive terminal of the bootstrap capacitor.
The selected n-channel, high-side MOSFET determines the appropriate boost capacitance values according to the
following equation:
CBST = QG/ΔVBST
where QG is the total gate charge of the high-side MOSFET and ΔVBST is the voltage variation allowed on the high-
side MOSFET driver after turn-on. Choose ΔVBST such that the available gate-drive voltage is not significantly degraded

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MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

(e.g., ΔVBST = 100mV to 300mV) when determining CBST. The boost capacitor should be a low-ESR ceramic capacitor.
A minimum value of 0.1μF works well in most cases. Choose a diode with low reverse current (<1µA) at maximum
temperature and voltage.

p-Channel MOSFET Output Disconnect

An optional p-channel MOSFET disconnects the output from the supply when shut down and provides short-circuit
protection. See the Typical Operating Circuit for the p-channel MOSFET connections. When this feature is not used,
connect PGATE to GND.

Current Limiting and Current-Sense Inputs (SUP and CS)

The current-limit circuit uses differential current-sense inputs (CS_P and CS_N) to limit the peak inductor current. If the
magnitude of the current-sense signal exceeds the current-limit threshold (VLIMIT > 50mV (typ)), the PWM controller
turns off the high-side MOSFET.
For the most accurate current sensing, use a current-sense resistor between the inductor and the input capacitor.
Connect CS_N to the inductor side of RCS and CS_P to the capacitor side. See the Current-Sense Resistor Selection
section to determine the resistor value.
To improve efficiency, the current can also be measured directly across the inductor, eliminating the power loss from
the sense resistor. However, this method is significantly less accurate and requires a filter network in the current-sense
circuit. See the Inductor DCR Current Sense section for more information.

Output Voltage Monitor (PGOOD)

PGOOD is an open-drain output used to monitor the output voltage. PGOOD pulls low when the output voltage drops
below the PGOOD threshold (see the Electrical Characteristics table). PGOOD is high impedance when the output
voltage is in regulation. Typically a pullup resistor is connected from PGOOD to the relevant logic rail to provide a logic-
level output.
Typically when changing the output voltage by I2C or PWM control, PGOOD does not pull low due to undervoltage during
the transition. This is done by blanking the PGOOD output during the ramp up/down time plus the PGOOD timeout (see
the Electrical Characteristics table). In some cases where a large output capacitance is used, the output voltage may not
be able to reach the final value during blanking time. In this case, it is possible for PGOOD to briefly pull low during the
transition.

Interrupt Request Output (IRQ)

IRQ is the open-drain interrupt request output. This is a factory option that replaces the PGOOD output; see the Ordering
Information table for supported parts.
IRQ pulls low when the output voltage drops below the PGOOD threshold (see the Electrical Characteristics table) and
when a fault is flagged in the FAULT_STAT register. IRQ is high impedance when the output voltage is in regulation
and no faults are flagged. Typically a pullup resistor is connected from IRQ to the relevant logic rail to provide a logic-
level output. IRQ is low when disabled and during start-up remains low until soft-start is complete and the FAULT_STAT
register has been read.
When a fault occurs, it it is latched in the FAULT_STAT register, so IRQ remains low until the FAULT register is read.
Reading the fault register clears the flagged faults; however, if the fault persists it is immediately flagged again, and IRQ
pulls low again.

Protection Features
I2C Fault Flags
The FAULT register indicates if any faults have occurred since the last time the register was read. Reading the register
clears all fault flags; however, if the fault condition persists, the corresponding flag will be set again. The fault conditions
reported in the FAULT register are output overvoltage, output undervoltage, input undervoltage, and overcurrent for
phase 1 and phase 2. See the Register Map for more information.
Initially after power-up, all fault bits are set. This indicates that a reset has occurred, not that the fault corresponding to

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MAX25203 Dual-Phase Synchronous Boost Controller with
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each flag has occurred. The FAULT register should be read after power-up to clear the fault flags.

Overvoltage Protection
The devices limit the output voltage by turning off the high-side gate driver if the output voltage exceeds 105% (typ) of
the nominal output voltage. The output voltage needs to come back into regulation before the device resumes switching.

Overcurrent Protection
If the inductor current exceeds the maximum current limit set by RCS or inductor DCR sensing, the respective MOSFET
driver turns off. If the output current is increased further, this results in shorter and shorter high-side pulses. A hard short
results in a minimum on-time pulse every clock cycle. Choose the components so they can withstand the short-circuit
current, if required. If an overcurrent conditions persists for the current-limit blanking time, hiccup protection is activated
and the BST1_OC or BST2_OC bit in the FAULT register will be set. The hiccup protection stops switching for 100ms
then attempts to soft-start. This is repeated until start-up is successful. If the sensed current exceeds the current-limit
threshold by 50% or more, hiccup protection does not wait for the current-limit blanking time.

Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the devices. When the junction temperature exceeds +170°C
(typ), an internal thermal sensor shuts down the device, allowing it to cool down. The thermal sensor turns on the devices
again after the junction temperature cools by 20°C (typ).

I2C Interface
The MAX25203 feature an I2C-/SMBus-compatible, 2-wire slave serial interface consisting of a serial data line (SDA) and
a serial clock line (SCL).

I2C Timing Diagram

tf tr tSU;DAT

...
70%
SDA CONT.
30%

tf tHD;DAT tHIGH tVD;DAT

tr

SCL 70% ...

30% CONT.

9TH CLOCK
tHD;STA tLOW
S 1 / fSCL
1ST CLOCK CYCLE
tBUF

. . . SDA

tSU;STA tHD;STA tSP tVD;ACK tSU;STO

. . . SCL

Sr P S
9TH CLOCK

VIL = 0.3VDD
VIH = 0.7VDD

Figure 1. I2C Timing Diagram

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MAX25203 Dual-Phase Synchronous Boost Controller with
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Bit Transfer
One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the
SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA
and SCL idle high when the I2C bus is not busy.

START and STOP Conditions

SDA and SCL idle high when the bus is not in use. One data bit is transferred during each SCL cycle. The data on
SDA must remain stable during the high period of the SCL pulse. Changing SDA while SCL is high will result in control
conditions being issued. A high-to-low transition on the SDA line while SCL is high defines a START (S) condition. A
low-to-high transition on the SDA line while SCL is high defines a STOP (P) condition. START and STOP conditions are
always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to
be free again a certain time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead
of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical.

Clock Stretching
In general, the clock signal generation for the I2C bus is the responsibility of the master device. The I2C specification
allows slow slave devices to alter the clock signal by holding down the clock line. The process in which a slave device
holds down the clock line is typically called clock stretching. The MAX25203 do not use any form of clock stretching to
hold down the clock line.

Slave Address
The slave address consists of 7 address bits followed by the R/W bit. Set the R/W bit to 1 to configure the devices to read
mode. Set the R/W bit to 0 to configure the device to write mode. The address is the first byte of information sent to the
devices after the START condition. See the Ordering Information table for the slave address value.

Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the device uses to handshake receipt each byte of data. The device
pulls down SDA during the master-generated 9th clock pulse. The SDA line must remain stable and low during the
high period of the acknowledge clock pulse. Monitoring ACK allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an
unsuccessful data transfer, the bus master can reattempt communication.

Write Data Format

A write to the device includes transmission of a START condition, the slave address with the R/W bit set to 0, one byte
of data to the register address, one byte of data to the command register, and a STOP condition.

Read Data Format

A read from the device includes transmission of a START condition, the slave address with the R/W bit set to 0, one
byte of data to the register address, a restart condition, the slave address with R/W bit set to 1, one byte of data to the
command register, and a STOP condition.

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MAX25203 Dual-Phase Synchronous Boost Controller with
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I2C Data Format

WRITE BYTE

SLAVE
S 0 A REGISTER ADDRESS A DATA A P
ADDRESS

READ BYTE

SLAVE SLAVE N
S 0 A REGISTER ADDRESS A SR 1 A DATA BYTE P
ADDRESS ADDRESS A

Figure 2. I2C Data Format

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MAX25203 Dual-Phase Synchronous Boost Controller with
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Register Map
MAX25203
ADDRESS NAME MSB LSB
USR_REGS
0x00 CHIP_ID_REG[7:0] DIE_TYPE[7:0]
BST_CTRL_0_REG[7:0
0x01 RSVD EN_PH2 ILIM_BLANK[1:0] RAMP_RATE[1:0] VIN_UV_TH[1:0]
]
BST_CTRL_1_REG[7:0 SPS_RA
0x02 SPS_EN – – – – – –
] NGE
BST_CTRL_2_REG[7:0
0x03 – – VOUT_THR[5:0]
]
0x05 BST1_IMON_REG[7:0] BST1_IMON[7:0]
0x06 BST2_IMON_REG[7:0] BST2_IMON[7:0]
0x07 DIE_TEMP_REG[7:0] DIE_TEMP[7:0]
FAULT_STAT_REG[7:0 VOUT_O VOUT_U BST1_O BST2_O
0x08 VIN_UV – – –
] V V C C
SW_RESET
0x0F SW_RESET_REG[7:0] SW_RST – – – – – – –

Register Details

CHIP_ID_REG (0x00)

BIT 7 6 5 4 3 2 1 0
Field DIE_TYPE[7:0]
Reset
Access
Read Only
Type

BITFIELD BITS DESCRIPTION

Read Only. See the Ordering Information table for the fixed value of this
DIE_TYPE 7:0
register. This can be used to identify the IC on the I2C bus.

BST_CTRL_0_REG (0x01)

BIT 7 6 5 4 3 2 1 0
Field RSVD EN_PH2 ILIM_BLANK[1:0] RAMP_RATE[1:0] VIN_UV_TH[1:0]
Reset 0x1 0x1 0x01 0x0 0x0
Access
Write, Read Write, Read Write, Read Write, Read Write, Read
Type

BITFIELD BITS DESCRIPTION DECODE

Reserved. Set this bit to 1 when writing
RSVD 7
BST_CTRL0_REG.
0x0: Disable phase 2 controller
EN_PH2 6 Phase 2 Controller Enable.
0x1: Enable phase 2 controller

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MAX25203 Dual-Phase Synchronous Boost Controller with
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BITFIELD BITS DESCRIPTION DECODE

Current-Limit Blanking Time. An overcurrent
condition that persists for the blanking time
triggers hiccup overcurrent protection and 0x0: 0ms
flags in the FAULT register. 0x1: 50ms
ILIM_BLANK 5:4
0x2: 100ms
Note: If the current exceeds the current limit 0x3: 20ms
by more than 50%, the protection is activated
immediately.
0x0: 8ms
RAMP_RAT Sets the ramp time when changing the output 0x1: 500µs
3:2
E voltage from 12V to 65V. 0x2: 1ms
0x3: 2ms
0x0: 5V
0x1: 6V
VIN_UV_TH 1:0 Input Undervoltage Threshold.
0x2: 7V
0x3: 8V

BST_CTRL_1_REG (0x02)

BIT 7 6 5 4 3 2 1 0
SPS_RANG
Field SPS_EN – – – – – –
E
Reset OTP OTP – – – – – –
Access
Write, Read Write, Read – – – – – –
Type

BITFIELD BITS DESCRIPTION DECODE

Spread Spectrum. See the Ordering 0x0: Spread spectrum disabled
SPS_EN 7
Information table for the reset value. 0x1: Spread spectrum enabled
SPS_RANG Spread Spectrum Clock Setting. See the 0x0: ±9%
6
E Ordering Information table for the reset value. 0x1: ±6%

BST_CTRL_2_REG (0x03)

BIT 7 6 5 4 3 2 1 0
Field – – VOUT_THR[5:0]
Reset – – OTP
Access
– – Write, Read
Type

BITFIELD BITS DESCRIPTION

Output Voltage Setting. Sets the output feedback threshold of the OUT pin
between 12V and 65V.

VOUT = 12 + VOUT_THR[5:0].
VOUT_THR 5:0
Any code that is greater than the decimal 53 is reserved. See the Ordering
Information table for the default voltage setting.

Do not write to this register when using the PWM output voltage control.

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MAX25203 Dual-Phase Synchronous Boost Controller with
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BST1_IMON_REG (0x05)

BIT 7 6 5 4 3 2 1 0
Field BST1_IMON[7:0]
Reset 0x0
Access
Read Only
Type

BITFIELD BITS DESCRIPTION

Current-Sense Resistor Voltage ADC Measurement for Phase 1.
BST1_IMON 7:0
VCS1 = 0.5415 x BST1_IMON - 19.0

BST2_IMON_REG (0x06)

BIT 7 6 5 4 3 2 1 0
Field BST2_IMON[7:0]
Reset 0x0
Access
Read Only
Type

BITFIELD BITS DESCRIPTION

Current-Sense Resistor Voltage ADC Measurement for Phase 2.
BST2_IMON 7:0
VCS2 = 0.5415 x BST1_IMON - 19.0

DIE_TEMP_REG (0x07)

BIT 7 6 5 4 3 2 1 0
Field DIE_TEMP[7:0]
Reset 0x0
Access
Read Only
Type

BITFIELD BITS DESCRIPTION

DIE_TEMP 7:0 Die Temperature ADC Measurement. TJ (°C) = 2.04 x DIE_TEMP - 273

FAULT_STAT_REG (0x08)

When a fault occurs, a 1 is latched into the corresponding bit. All fault bits are cleared after reading this register. On
power-up, all fault bits are set to indicate reset.
BIT 7 6 5 4 3 2 1 0
Field VOUT_OV VOUT_UV BST1_OC BST2_OC VIN_UV – – –
Reset 0x1 0x1 0x1 0x1 0x1 – – –
Access Read Read Read Read Read
– – –
Type Clears All Clears All Clears All Clears All Clears All

BITFIELD BITS DESCRIPTION DECODE

0x0: No fault.
VOUT_OV 7 Output Overvoltage Flag. 0x1: Output exceded overvoltage threshold 108%
of target.
0x0: No fault.
VOUT_UV 6 Output Undervoltage Fault. 0x1: Output dropped below the undervoltage
threshold 93% of target (2% hysteresis).

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MAX25203 Dual-Phase Synchronous Boost Controller with
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BITFIELD BITS DESCRIPTION DECODE

0x0: No fault.
BST1_OC 5 Phase 1 Overcurrent Fault. 0x1: Phase 1 current exceeded the overcurrent
threshold.
0x0: No fault.
BST2_OC 4 Phase 2 Overcurrent Fault.
0x1: Phase 2 exceeded the overcurrent threshold.
Supply Voltage Undervoltage Fault.
0x0: No fault.
VIN_UV 3 VIN_UV is asserted when the supply voltage 0x1: The supply voltage dropped below the
is below the value specified in undervoltage threshold.
VIN_UV_TH[1:0].

SW_RESET_REG (0x0F)

BIT 7 6 5 4 3 2 1 0
Field SW_RST – – – – – – –
Reset 0x0 – – – – – – –
Access Write,
– – – – – – –
Type Read, Ext

BITFIELD BITS DESCRIPTION

Write 1 to Force Software Reset. This sets all registers to their power-on
SW_RST 7
default values and soft-starts the controller. Reads back 0.

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MAX25203 Dual-Phase Synchronous Boost Controller with
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Applications Information
Setting and Controlling the Output Voltage
The MAX25203 provides three methods of setting the output voltage: an external resistor-divider, I2C, and PWM input.
Any one of these methods may be used to control the output voltage; however, do not change methods during operation.

External Feedback Divider

To use an external resistor-divider to set the output voltage, connect FB to the center tap of two resistors connected from
the output to ground, as shown in Figure 3. When using the external divider, the output voltage range is 3.5V to 65V. The
PWM input and I2C voltage setting are ignored in this configuration. PWM should be connected to GND.
Calculate the divider resistor values as follows:

[ ]
VOUT
R1 = R2 V −1
FB
where VFB is the regulated feedback voltage (see the Electrical Characteristics table).

OUT
OUT

R1

FB

R2

Figure 3. External Feedback Divider

I2C Voltage Setting

When using I2C to control the output voltage, connect FB to BIAS and connect PWM to GND. If FB is connected to an
external divider, the register value will be ignored and the output voltage will correspond to the value set by the divider.
With configured for I2C voltage control, the MAX25203 initially powers on to the default output voltage (see the Ordering
Information table). The output voltage can then be changed to any voltage from 12V to 65V in 1V steps by writing to
VOUT_THR[5:0] in the BST_CTRL_2_REG register. Writing 0 corresponds to 12V, and decimal 53 or higher corresponds
to 65V.
VOUT = 12 + VOUT_THR[5 : 0] for VOUT_THR[5 : 0] ≤ 53
VOUT = 65V for VOUT_THR[5 : 0] > 53
When the voltage setting is changed, the output voltage changes in 1V steps until it reaches the new value. The total
time to change to the new target voltage is set in RAMP_RATE[1:0]. If VOUT_THR[5:0] is changed before reaching the
previous target voltage, the output will step towards the new target voltage.
On initial power-on, the output completes soft-start to the factory default setting. If VOUT_THR[5:0] is changed during
soft-start, the output will continue to the factory default setting and complete soft-start before starting to step to the new
target voltage.

PWM Voltage Control

To use the PWM input to control the output voltage, FB must connect to BIAS. The PWM input does not function when

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MAX25203 Dual-Phase Synchronous Boost Controller with
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using an external resistor-divider to set the voltage.

To control the output voltage with the PWM input, apply a 400kHz (typ) PWM signal to PWM. See the Electrical
Characteristics table for the PWM frequency range. The output can change from 12V to 65V in 1V steps, with each 1V
step corresponding to a 0.8% change in duty cycle in the range 25% to 67%. A duty cycle of less than or equal to 25%
corresponds to 12V output, and greater or equal to 67% corresponds to 65V output. For ICs with the maximum output
limited to less than 65V, contact the factory.
The output voltage target only changes when a 0.8% or greater change in duty cycle (in the 25% to 67% range) is
detected on PWM. Duty-cycle changes outside this range are ignored. If this change occurs during soft-start, the PWM
setting is ignored until the PWM duty cycle changes again by at least 0.8%.
If the PWM input is low at startup, the output will go to the default output voltage (see the Ordering Information table).
Once there is a transition on the PWM input, the PWM control takes affect. If the PWM signal is present at startup
(including 100% duty cycle), the output starts up to the voltage determined by the PWM signal.

Inductor Selection
Duty cycle and frequency are important to calculate the inductor size, as the inductor current ramps up during the on-time
of the switch and ramps down during its off-time. A higher switching frequency generally improves transient response
and reduces component size; however, if the boost components are to be used as the input filter components during
non-boost operation, a low frequency is advantageous.
The duty-cycle range of the boost converter depends on the effective input-to-output voltage ratio. In the following
calculations, the duty cycle refers to the on-time of the boost MOSFET:
VOUT(MAX) − VSUP(MIN)
DMAX = VOUT(MAX)

The ratio of the inductor peak-to-peak AC current to DC average current must be selected first. A good initial value is
a 30% peak-to-peak ripple current to average current ratio. The switching frequency, input voltage, output voltage, and
selected LIR determine the inductor value as follows:
VSUP × D
L[μH] = f
SW[MHz] × LIR
where:
D = (VOUT - VSUP)/VOUT
VSUP = typical input voltage
VOUT = typical output voltage
LIR = 0.3 x IOUT/(1 - D)
Select the inductor with a saturation current rating higher than the peak switch current limit of the converter:
∆ IL_RIP_MAX
IL_PEAK > IL_MAX + 2
Running a boost converter in continuous-conduction mode introduces a right-half plane zero into the transfer function. To
avoid the effect of this right-half plane zero, the crossover frequency for the control loop should be ≤ 1/3 x fRHP_ZERO. If
a faster bandwidth is required, a smaller inductor and higher switching frequency are recommended.

Input Capacitor Selection

The input current for the boost converter is continuous and the RMS ripple current at the input capacitor is low. Calculate
the minimum input capacitor value and the maximum ESR using the following equations:
∆ IL × D
CSUP = 4 × f
SW × ∆ VQ
∆ VESR
ESR = ∆ IL

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MAX25203 Dual-Phase Synchronous Boost Controller with
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where:

∆ IL =
(VSUP − VDS) × D
L × fSW

VDS is the total voltage drop across the external MOSFET plus the voltage drop across the inductor ESR. ΔIL is
the peak-to-peak inductor ripple current as calculated above. ΔVQ is the portion of input ripple due to the capacitor
discharge and ΔVESR is the contribution due to ESR of the capacitor. Assume the input capacitor ripple contribution
due to ESR (ΔVESR) and capacitor discharge, (ΔVQ) are equal when using a combination of ceramic and aluminum
capacitors. During the converter turn-on, a large current is drawn from the input source, especially at a high output-to-
input differential.

Output Capacitor Selection

In a boost converter, the output capacitor supplies the load current when the boost MOSFET is on. The required output
capacitance is high, especially at higher duty cycles. Also, the output capacitor ESR needs to be low enough to minimize
the voltage drop while supporting the load current. Use the following equations to calculate the output capacitor for a
specified output ripple. All ripple values are peak to peak:
∆ VESR
ESR = I
OUT
IOUT × DMAX
C = ∆V ×f
Q SW
where:
IOUT = load current in A
fSW is in MHz
COUT is in μF
ΔVQ = portion of ripple due to capacitor discharge
ΔVESR = contribution due to capacitor ESR
DMAX = maximum duty cycle at the minimum input voltage.
Use a combination of low-ESR ceramic and high-value, low-cost aluminum capacitors for lower output ripple and noise.

Current-Sense Resistor Selection

The current-sense resistor (RCS_) connected between the battery and the inductor sets the current limit. The CS_ input
has a voltage trip level (VCS_) of 50mV (typ).
Set the current-limit threshold high enough to accommodate the component variations. Use the following equation to
calculate the value of RCS_:
VCS
RCS = I
SUP(MAX)
where IIN(MAX) is the peak current that flows through the MOSFET at full load and a minimum VIN.
ILOAD(MAX)
ISUP(MAX) = 1 − D
MAX
When the voltage produced by this current (through the current-sense resistor) exceeds the current-limit comparator
threshold, the MOSFET driver (DL) quickly terminates the on-cycle.

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MAX25203 Dual-Phase Synchronous Boost Controller with
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Current-Sense Configurations

RCS L
BATTERY

CS_N
CS_P
CURRENT-SENSE RESISTOR

RDC L
BATTERY

R2 R1

CEQ
CS_N
CS_P
INDUCTOR DCR CURRENT SENSE

Figure 4. Current-Sense Configurations

Inductor DCR Current Sense

High-power applications that do not require accurate current sense can use the inductor's DC resistance as the current-
sense element instead of the current-sense resistor. This is done by with an RC network across the inductor. The
equivalent sense resistance of the network is:

( R2
RCS_EQ = R1 + R2 × RDC )
where RDC is the DC resistance of the inductor, R1 is connected from the switch side of the inductor to CS_N, and R2 is
connected from the battery side of the inductor to CS_N (see Figure 4). The capacitor CEQ (connected parallel to R2) is
calculated as follows:

CEQ = R
L
DC R1
(1
+ R2
1
)
Boost Converter Compensation
The basic regulator loop is modeled as a power modulator, output feedback-divider, and error amplifier, as shown in
Figure 4. The power modulator has a DC gain set by gmc x RLOAD, with a pole and zero pair set by RLOAD, the output
capacitor (COUT), and its ESR. The loop response is set by the following equation:

( )
f
1+j

( )
fzMOD
1−D
GMOD = gMC × RLOAD × 2 × ( ) 1+j
f
× 1 − jf
Rph_zMOD
f

fpMOD

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MAX25203 Dual-Phase Synchronous Boost Controller with
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where RLOAD = VOUT/ILOUT(MAX) in Ω, and gmc =1/(AV_CS x RDC) in S. AV_CS is the voltage gain of the current-sense
amplifier and is typically 12V/V. RDC is the DC resistance of the inductor or the current-sense resistor in Ω.
In a current-mode step-down converter, the output capacitor and the load resistance introduce a pole at the following
frequency:
1
fpMOD = π × R
LOAD × COUT
The output capacitor and its ESR also introduce a zero at:
1
fzMOD = 2π × ESR × C
OUT
The right-half plane zero is at:
RLOAD
fRph_zMOD = 2π × L × (1 − D) × (1 − D)
When COUT is composed of “n” identical capacitors in parallel, the resulting COUT = n x COUT(EACH), and ESR =
ESR(EACH)/n. Note that the capacitor zero for a parallel combination of similar capacitors is the same as for an individual
capacitor.
The feedback voltage-divider has a gain of GAINFB = VFB/VOUT, where VFB is 1.0V (typ).
The transconductance error amplifier has a DC gain of GAINEA(DC) = gm,EA x ROUT,EA, where gm,EA is the error-
amplifier transconductance, which is 370μS (max), and ROUT,EA is the output resistance of the error amplifier, which is
10MΩ (typ) See the Electrical Characteristics table for details.
A dominant pole (fdpEA) is set by the compensation capacitor (CC) and the amplifier output resistance (ROUT,EA). A zero
(fZEA) is set by the compensation resistor (RC) and the compensation capacitor (CC). There is an optional pole (fPEA)
set by CF and RC to cancel the output capacitor ESR zero if it occurs near the crossover frequency (fC), where the loop
gain equals 1 (0dB). Thus:
1
fpEA =
(
2π × ROUTEA + RC × CC )
1
fzEA = 2π × R × C
C C
1
fp2EA = 2π × R × C
C F
The loop gain crossover frequency (fC) should be ≤ 1/3 of right-half plane zero frequency.
fRph_zMOD
fC ≤ 3
At the crossover frequency, the total loop gain must be equal to 1. So:
VFB
GAINMOD(f ) × V × GAINEA(f ) = 1
C OUT C
GAINEA(f ) = gm, EA × RC
C
fpMOD
GAINMOD(f ) = GAINMOD(dc) × fC
C
Therefore:
VFB
GAINMOD(f ) × V × gm, EA × RC = 1
C OUT
Solving for RC:
VOUT
RC = g
m, EA × VFB × GAINMOD(fC)

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MAX25203 Dual-Phase Synchronous Boost Controller with
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Set the error-amplifier compensation zero formed by RC and CC at the fpMOD. Calculate the value of CC as follows:
1
CC = 2π × f
pMOD × RC
If fzMOD is less than 5 x fC, add a second capacitor (CF) from COMP to GND. The value of CF is:
1
CF = 2π × f
zMOD × RC

MOSFET Selection
The key selection parameters to choose the n-channel MOSFET used in the boost converter are as follows.

Threshold Voltage
The boost n-channel MOSFETs are driven with gate voltage of VDRV. Make sure the on-resistance of the selected
MOSFETs is specified at this gate voltage.

Maximum Drain-to-Source Voltage (VDS(MAX))

The MOSFET must be chosen with an appropriate VDS rating to handle all VIN voltage conditions.

Current Capability
The n-channel MOSFET must deliver the input current (IIN(MAX)):
DMAX
IIN(MAX) = ILOAD(MAX) × 1 − D
MAX
Choose MOSFETs suitable for the appropriate average current at VGS = VDRV.

Low-Voltage Operation
The devices operate down to a voltage of 4.5V or less on their SUP pins. If the system input voltage is lower than this
the circuit can be operated from its own output as shown in the Bootstrap Application Circuit. At very low input voltages,
it is important to remember that the input current will be high and the power components (inductor, MOSFET, and diode)
must be specified for this higher input current.
In addition, the current-limit of the devices must be set high enough so that the limit is not reached during the on-time of
the MOSFET, which would result in output power limitation and eventually entering hiccup mode. Estimate the maximum
input current using the following equation:

( )/
VOUT × IOUT VOUT − VSUPMIN VSUPMIN
ISUPMAX = η
VSUPMIN + 0.5 × VOUT
× f
SW × L

where:
IINMAX = maximum input current
VOUT = output voltage
IOUT = output current
η = estimated efficiency (lower at low input voltages due to higher resistive losses)
VINMIN = minimum value of the input voltage
fSW = switching frequency
L = minimum value of the chosen inductor

Quad-Phase Operation
Two MAX25203 devices can operate together in a quad-phase master/slave configuration in order to double the output
power capability. In the quad-phase configuration, each phase operates 90° out-of-phase so as to minimize the input and
output ripple. Connections between the master and slave are as follows: SYNCOUT of the master connects to FSYNC
of the slave, and COMP pins connect together (one COMP network shared between the two).

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MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Layout Recommendations
Careful PCB layout is critical to achieve low switching losses and clean, stable operation. Layout of the switching power
components requires particular attention. Follow these guidelines for good PCB layout:
● Keep high-current paths short, especially at the ground terminals.
● Minimize resistance in high-current paths by keeping the traces short and wide. Using thick (2oz vs. 1oz copper) can
improve full load efficiency.
● Connect the CS and SUP connections used for current sensing directly across the sense resistor using a Kelvin sense
connection.
● Route noisy switching and clock traces away from sensitive analog areas (FB, CS).

Typical Application Circuits

Typical Operating Circuit

BATT
CSUP

SUP
EN CS1P
PWM CS1N
SYNCOUT
FSYNC DH1

LX1 L1 RCS1
PGOOD/IRQ
DL1
SDA
SCL BST1
OPTIONAL OUTPUT
FOSC DISCONNECT
OUTS
SS DRV OUT
RFOSC
CSS COUTS COUT
MAX25203
BIAS BST2

OUT DH2 BATT

OUTS OUTS L2 RCS2
LX2
0.1µF
BIAS FB DL2

COMP
CS2N
CS2P

PGATE

RC
CF EP GND PGND

CC

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MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Typical Application Circuits (continued)

Bootstrap Application Circuit

BATT OUTS
CSUP
OPTIONAL
SUP
EN BATT
CS1P
PWM
CS1N
SYNCOUT
FSYNC DH1

LX1 L1 RCS1
PGOOD/IRQ
DL1
SDA
SCL
BST1
OPTIONAL OUTPUT
FOSC DISCONNECT
OUTS
SS DRV OUT
RFOSC
CSS MAX25203 COUTS COUT
BIAS BST2

OUTS
OUT DH2 BATT
OUTS L2 RCS2
LX2
R1 0.1µF
FB DL2

R2 COMP
CS2N
CS2P

PGATE

RC
EP GND PGND
CF
CC

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MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Ordering Information
SLAVE
PIN- DEFAULT SPREAD DEFAULT CHIP PGOOD
PART ADDRESS W/ VDRV PHASES
PACKAGE SPECTRUM VOUT _ID /IRQ
R***
MAX25203ATJA/ 32 SW Dual-phase/
Off 24V 0xA8/0xA9 0x08 PGOOD 10V
VY+ TQFN-EP* quad master
MAX25203ATJB/ 32 SW Dual-phase/
Off 24V 0xA8/0xA9 0x08 PGOOD 8V
VY+** TQFN-EP* quad master
MAX25203ATJC/ 32 SW Dual-phase/
Off 24V 0xAC/0xAD 0x08 PGOOD 10V
VY+** TQFN-EP* quad master
MAX25203ATJD/ 32 SW Dual-phase/
Off 12V 0xA8/0xA9 0x08 PGOOD 10V
VY+** TQFN-EP* quad master
MAX25203ATJE/ 32 SW Dual-phase/
Off 12V 0xAC/0xAD 0x08 PGOOD 10V
VY+** TQFN-EP* quad master
MAX25203BATJA/ 32 SW Dual-phase/
Off 24V 0xA8/0xA9 0x09 PGOOD 6.5V
VY+ TQFN-EP* quad master
MAX25203QATJA/ 32 SW Quad-phase
N/A N/A 0xAA/0xAB 0x08 N/A 10V
VY+ TQFN-EP* slave
All parts are available in the -40°C to +125°C automotive temperature range.
*EP = Exposed pad.
**Future product—contact factory for availability.
***8-bit device address including R/W bit.
/VY Denotes side-wettable automotive qualified parts.
+Denotes a lead (Pb) free/RoHS compliant package.

www.maximintegrated.com Maxim Integrated | 35

MAX25203 Dual-Phase Synchronous Boost Controller with
Programmable Gate Drive and I2C

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 8/21 Initial release —
1 8/21 Updated Ordering Information 35

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Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

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