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Resume - 2023

The document provides a resume for Vaibhav Solanki. It details his work experience as a Design Verification Engineer and ASIC Verification Trainee. It also lists his education, skills, interests and hobbies.

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Divyesh Makwana
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87 views1 page

Resume - 2023

The document provides a resume for Vaibhav Solanki. It details his work experience as a Design Verification Engineer and ASIC Verification Trainee. It also lists his education, skills, interests and hobbies.

Uploaded by

Divyesh Makwana
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VAIBHAV SOLANKI

DESIGN VERIFICATION ENGINEER


11, Satyanarayana Marg near Sindhi Colony [email protected]
Pali, Rajasthan (306401)

+91 9116861261 https://www.linkedin.com/in/vaibhavsolanki2408/

CARRER OBJECTIVE
To secure a challenging position as a Design Verification Engineer in a dynamic organization where I can utilize my
skills and experience in the field of ASIC/FPGA Design Verification.

WORK EXPERIENCE
Design Verification Engineer, eInfochips AUG 2022 – PRESENT • 1 year 3 mos
Project (US-based Client) – IP Verification
Project Description: Verification of IP responsible for proper operation of the sensors and providing the sensor
data at the desired Output Data Rate (ODR).
• Implemented feature based functional coverage.
• Developed Reference Model for mimicking the sensor Turn ON/OFF commands based on different power
mode and ODRs.
• Testcase development to test a specific feature of the IP.
• Assertions based verification of clock generation block.
• Enhanced Testbench by optimizing several components.

ASIC Verification Trainee, eInfochips JAN 2022 – JULY 2022 • 7 mos


Project (Internal) – UART VIP Development
• Developed a UART VIP employing Autoflow Control and verified Full, Half Duplex & Simplex modes along
with basic features of UART using SV and converted it to UVM Methodology.
• Created planning documents (Verification, Assertion & Testcase plan etc) and executed them in time.

Project (Internal) – UART Design & Verification using Verilog.


• Developed a synthesizable UART Protocol DUT using Verilog.
• Developed Testbench to generate different stimulus and checked the expected output.

EDUCATION
MARWADI UNIVERSITY - Rajkot (Guj.), India ST. PAUL’S SR. SEC. SCHOOL - Pali (Raj.), India
Bachelor of Technology - (2018-2022) CBSE Higher Secondary Certificate - (2017-2018)
Electronics & Communication Science & Mathematics
CPI - 9.44 CGPA – 7.12

SKILLS
Programming Languages: System Verilog, Verilog, C, Python, Perl
Verification Methodology: UVM
EDA Tools: Cadence Xcellium, Synopsys VCS & DVE
Protocols Known: UART, AXI, AHB, APB, I2C, SPI
Communication: English, Hindi & Gujrati

INTEREST AND HOBBIES


Sports: Volleyball, Badminton, Table Tennis, Gymnastics
Recreational: Origami, Mimicry

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