8-Channel Fault-Protected

Analog Multiplexer
ADG528F
FEATURES FUNCTIONAL BLOCK DIAGRAM
Low on resistance (300 Ω typical)
ADG528F
Fast switching times
tON: 250 ns maximum S1
tOFF: 250 ns maximum
Low power dissipation (3.3 mW maximum)
Fault and overvoltage protection (−40 V to +55 V) D
All switches off with power supply off
Analog output of on channel clamped within power
supplies if an overvoltage occurs S8
Latch-up proof construction
WR 1 OF 8
Break-before-make construction RS DECODER
TTL and CMOS compatible inputs

09655-001
APPLICATIONS A0 A1 A2 EN
Figure 1.
Existing multiplexer applications (both fault-protected and
nonfault-protected)
New designs requiring multiplexer functions

GENERAL DESCRIPTION PRODUCT HIGHLIGHTS

1
The ADG528F is a CMOS analog multiplexer, with the 1. Fault protection.
comprising eight single channels. This multiplexer provides The ADG528F can withstand continuous voltage inputs
fault protection. Using a series n-channel, p-channel, n-channel from −40 V to +55 V. When a fault occurs due to the
MOSFET structure, both device and signal source protection is power supplies being turned off, all the channels are turned
provided in the event of an overvoltage or power loss. The off and only a leakage current of a few nanoamperes flows.
multiplexer can withstand continuous overvoltage inputs 2. On channel turns off while fault exists.
from −40 V to +55 V. During fault conditions, the multiplexer 3. Low RON.
input (or output) appears as an open circuit and only a few 4. Fast switching times.
nanoamperes of leakage current will flow. This protects not 5. Break-before-make switching.
only the multiplexer and the circuitry driven by the multiplexer, Switches are guaranteed break-before-make so that input
but also protects the sensors or signal sources that drive the signals are protected against momentary shorting.
multiplexer. 6. Trench isolation eliminates latch-up.
The ADG528F switches one of eight inputs to a common output A dielectric trench separates the p-channel and n-channel
as determined by the 3-bit binary address lines A0, A1, and A2. MOSFETs thereby preventing latch-up.
The ADG528F has on-chip address and control latches that
facilitate microprocessor interfacing. An EN input on the device
is used to enable or disable the device. When disabled, all channels
are switched off.

Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2001–2011 Analog Devices, Inc. All rights reserved.
ADG528F

TABLE OF CONTENTS
Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................6
Applications ....................................................................................... 1 ESD Caution...................................................................................6
Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions..............................7
General Description ......................................................................... 1 Typical Performance Characteristics ..............................................8
Product Highlights ........................................................................... 1 Terminology .................................................................................... 10
Revision History ............................................................................... 2 Theory of Operation ...................................................................... 11
Specifications..................................................................................... 3 Test Circuits ..................................................................................... 12
Dual Supply ................................................................................... 3 Outline Dimensions ....................................................................... 15
Truth Table .................................................................................... 4 Ordering Guide .......................................................................... 15
Timing Diagrams.......................................................................... 5

REVISION HISTORY
7/11—Rev. E to Rev. F
Deleted ADG508F/ADG509F .......................................... Universal
Changes to Table 3 ............................................................................ 6
Added Table 4.................................................................................... 7
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 15
7/09—Rev. D to Rev. E
Updated Format .................................................................. Universal
Added TSSOP ..................................................................... Universal
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 18
4/01—Data Sheet Changed from Rev. C to Rev. D.
Changes to Ordering Guide ............................................................ 1
Changes to Specifications Table ...................................................... 2
Max Ratings Changed ...................................................................... 4
Deleted 16-Lead Cerdip from Outline Dimensions .................. 11
Deleted 18-Lead Cerdip from Outline Dimensions .................. 12

Rev. F | Page 2 of 16
 ADG528F

SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.
B Version
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS + 3 V min
VDD − 1.5 V max
RON 300 350 Ω typ −10 V ≤ VS ≤ +10 V, IS = 1 mA;
VDD = +15 V ± 10%, VSS = −15 V ± 10%
400 Ω max −10 V ≤ VS ≤ +10 V, IS = 1 mA;
VDD = +15 V ± 5%, VSS = −15 V ± 5%
RON Drift 0.6 %/°C typ VS = 0 V, IS = 1 mA
RON Match 5 % max VS = 0 V, IS = 1 mA
LEAKAGE CURRENTS
Source Off Leakage IS (Off ) ±0.02 nA typ VD = ±10 V, VS = +10 V;
±1 ±50 nA max See Figure 19
Drain Off Leakage ID (Off ) ±0.04 nA typ VD = ±10 V, VS = +10 V;
±1 ±60 nA max See Figure 20
Channel On Leakage ID, IS (On) ±0.04 nA typ VS = VD = ± 10 V;
±1 ±60 nA max See Figure 21
FAULT
Output Leakage Current ±0.02 nA typ VS = ±33 V, VD = 0 V, see Figure 20
(With Overvoltage) ±2 ±2 μA max
Input Leakage Current ±0.005 μA typ VS = ±25 V, VD = +10 V, see Figure 22
(With Overvoltage) ±2 μA max
Input Leakage Current ±0.001 μA typ VS = ±25 V, VD = VEN = A0, A1, A2 = 0 V
(With Power Supplies Off ) ±2 μA max See Figure 23
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH ±1 μA max VIN = 0 or VDD
CIN, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS 1
tTRANSITION 200 ns typ RL = 1 MΩ, CL = 35 pF;
300 400 ns max VS1 = ±10 V, VS8 = +10 V; see Figure 24
tOPEN 50 ns typ RL = 1 kΩ, CL = 35 pF;
25 10 ns min VS = 5 V; see Figure 25
tON (EN, WR) 200 ns typ RL = 1 kΩ, CL = 35 pF;
250 400 ns max VS = 5 V; see Figure 26
tOFF (EN, RS) 200 ns typ RL = 1 kΩ, CL = 35 pF;
tSETT, Settling Time 250 400 ns max VS = 5 V; see Figure 26
0.1% 1 μs typ RL = 1 kΩ, CL = 35 pF;
0.01% 2.5 μs typ VS = 5 V
tW, Write Pulse Width 100 120 ns min
tS, Address, Enable Setup Time 100 ns min
tH, Address, Enable Hold Time 10 ns min
tRS, Reset Pulse Width 100 ns min

Rev. F | Page 3 of 16
ADG528F
B Version
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
Charge Injection 4 pC typ VS = 0 V, RS = 0 Ω, CL= 1 nF; see Figure 29
Off Isolation 68 dB typ RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
50 dB min VS = 7 V rms; see Figure 30
CS (Off ) 5 pF typ
CD (Off ) 50 pF typ
POWER REQUIREMENTS
IDD 0.1 0.2 mA max VIN = 0 V or 5 V
ISS 0.1 0.1 mA max
1
Guaranteed by design, not subject to production test.

TRUTH TABLE
Table 2. ADG528F Truth Table 1
A2 A1 A0 EN WR RS On Switch
X X X X 1 Retains previous switch condition
X X X X X 0 None (address and enable latches cleared)
X X X 0 0 1 None
0 0 0 1 0 1 1
0 0 1 1 0 1 2
0 1 0 1 0 1 3
0 1 1 1 0 1 4
1 0 0 1 0 1 5
1 0 1 1 0 1 6
1 1 0 1 0 1 7
1 1 1 1 0 1 8
1
X = don’t care.

Rev. F | Page 4 of 16
 ADG528F
TIMING DIAGRAMS
Figure 2 shows the timing sequence for latching the switch This input data is latched on the rising edge of WR. Figure 3
address and enable inputs. The latches are level sensitive; shows the reset pulse width, tRS, and the reset turnoff time, tOFF
therefore, while WR is held low, the latches are transparent (RS). Note that all digital input signals rise and fall times are
and the switches respond to the address and enable inputs. measured from 10% to 90% of 3 V. tR = tF = 20 ns.

3V
WR 50% 50%

0V
tW
tS
tH
3V
2V
A0, A1, A2

09655-002
EN 0.8V
0V

Figure 2. Timing Sequence for Latching the Switch Address and Enable Inputs

3V

RS 50% 50%

0V
tRS
tOFF (RS)
VOUT
SWITCH 0.8VOUT

09655-003
OUTPUT
0V

Figure 3. Reset Pulse Width

Rev. F | Page 5 of 16
ADG528F

ABSOLUTE MAXIMUM RATINGS

TA = 25°C unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
Table 3. rating only; functional operation of the device at these or any
Parameter Rating other conditions above those indicated in the operational
VDD to VSS 44 V section of this specification is not implied. Exposure to absolute
VDD to GND −0.3 V to +25 V maximum rating conditions for extended periods may affect
VSS to GND +0.3 V to −25 V device reliability.
Digital Input, EN, Ax −0.3 V to VDD + 2 V or 20 mA,
whichever occurs first
VS, Analog Input Overvoltage with VSS − 25 V to VDD + 40 V ESD CAUTION
Power On (VDD = +15 V, VSS = −15 V)
VS, Analog Input Overvoltage with −40 V to +55 V
Power Off (VDD = 0 V, VSS = 0 V)
Continuous Current, S or D 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) 40 mA
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA, Thermal Impedance 90°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

Rev. F | Page 6 of 16
 ADG528F

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

WR
NC
RS
A0

A1
3 2 1 20 19

EN 4 PIN 1 18 A2
INDENTFIER
VSS 5 17 GND
S1 6
ADG528F 16 VDD
TOP VIEW
S2 7 (Not to Scale) 15 S5
S3 8 14 S6

9 10 11 12 13

D
S4

S8
S7
NC

09655-007
NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1 NC No Connect. This pin is open.
2 WR Write. The WR signal latches the state of the address control lines and the enable line.
3 A0 Logic Control Input.
4 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
5 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
6 S1 Source Terminal 1. This pin can be an input or an output.
7 S2 Source Terminal 2. This pin can be an input or an output.
8 S3 Source Terminal 3. This pin can be an input or an output.
9 S4 Source Terminal 4. This pin can be an input or an output.
10 D Drain Terminal. This pin can be an input or an output.
11 NC No Connect. This pin is open.
12 S8 Source Terminal 8. This pin can be an input or an output.
13 S7 Source Terminal 7. This pin can be an input or an output.
14 S6 Source Terminal 6. This pin can be an input or an output.
15 S5 Source Terminal 5. This pin can be an input or an output.
16 VDD Most Positive Power Supply Potential.
17 GND Ground (0 V) Reference.
18 A2 Logic Control Input.
19 A1 Logic Control Input.
20 RS Reset. The RS signal clears both the address and enable data in the latches resulting in no
output (all switches off ).

Rev. F | Page 7 of 16
ADG528F

TYPICAL PERFORMANCE CHARACTERISTICS

2000 2000

TA = 25°C VDD = +15V

1750 1750 VSS = –15V

1500 1500

1250 1250
VDD = +5V
RON (Ω)

RON (Ω)
1000 VSS = –5V 1000

750 750
TA = 85°C TA = 125°C
VDD = +10V
500 500
VSS = –10V

250 250
VDD = +15V TA = 25°C
VSS = –15V
0 0

09655-008

09655-011
–15 –10 –5 0 5 10 15 –15 –10 –5 0 5 10 15
VD, VS (V) VD, VS (V)

Figure 5. On Resistance as a Function of VD (VS) Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures

1m 1m

100µ VDD = 0V 100µ VDD = +15V

VSS = 0V VSS = –15V
10µ VD = 0V 10µ VD = 0V
IS INPUT LEAKAGE (A)

IS INPUT LEAKAGE (A)

1µ 1µ

100n 100n

10n 10n
OPERATING RANGE OPERATING RANGE
1n 1n

100p 100p

10p 10p

1p 1p
09655-009

09655-012
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60
VIN INPUT VOLTAGE (V) INPUT VOLTAGE (V)

Figure 6. Input Leakage Current as a Function of VS (Power Supplies Off) Figure 9. Input Leakage Current as a Function of VS (Power Supplies On)
During Overvoltage Conditions During Overvoltage Conditions

1m 0.3

100µ VDD = +15V VDD = +15V

VSS = –15V 0.2 VSS = –15V
10µ VD = 0V TA = 25°C
LEAKAGE CURRENTS (nA)
ID INPUT LEAKAGE (A)

IS (OFF)
1µ
0.1
100n IS (OFF)

10n
0
1n IS (ON)
OPERATING RANGE
100p –0.1

10p

1p –0.2
09655-010

09655-013

–50 –40 –30 –20 –10 0 10 20 30 40 50 60 –14 –10 –6 –2 2 6 10 14

VIN INPUT VOLTAGE (V) VS, VD (V)

Figure 7. Output Leakage Current as a Function of VS (Power Supplies On) Figure 10. Leakage Currents as a Function of VD (VS)
During Overvoltage Conditions

Rev. F | Page 8 of 16
 ADG528F

100 280
VDD = +15V
VDD = +15V 260 VSS = –15V
VSS = –15V VIN = +5V
VD = +10V 240
tON (EN)
10
LEAKAGE CURRENTS (nA)

VS = –10V
ID (OFF)

SWITCHING TIME (ns)

220

200 tTRANSITION
1
IS (OFF) 180

160
0.1
ID (ON) 140

120 tOFF (EN)

0.01 100

09655-014

09655-016
25 35 45 55 65 75 85 95 105 115 125 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 11. Leakage Currents as a Function of Temperature Figure 13. Switching Time vs. Temperature

260
VIN = 2V
240

220
SWITCHING TIME (ns)

tON (EN)
200

180

160 tTRANSITION

140
tOFF (EN)
120

100
09655-015

10 11 12 13 14 15
POWER SUPPLY (V)

Figure 12. Switching Time vs. Power Supply

Rev. F | Page 9 of 16
ADG528F

TERMINOLOGY
VDD tON (EN)
Most positive power supply potential. Delay time between the 50% and 90% points of the digital input
and switch on condition.
VSS
Most negative power supply potential. tOFF (EN)
Delay time between the 50% and 90% points of the digital input
GND and switch off condition.
Ground (0 V) reference.
tTRANSITION
RON Delay time between the 50% and 90% points of the digital
Ohmic resistance between D and S. inputs and the switch on condition when switching from one
RON Drift address state to another.
Change in RON when temperature changes by one degree tOPEN
Celsius. Off time measured between 80% points of both switches when
RON Match switching from one address state to another.
Difference between the RON of any two channels. VINL
IS (Off) Maximum input voltage for Logic 0.
Source leakage current when the switch is off. VINH
ID (Off) Minimum input voltage for Logic 1.
Drain leakage current when the switch is off. IINL (IINH)
ID, IS (On) Input current of the digital input.
Channel leakage current when the switch is on. Off Isolation
VD (VS) A measure of unwanted signal coupling through an off channel.
Analog Voltage on Terminal D and Terminal S. Charge Injection
CS (Off) A measure of the glitch impulse transferred from the digital
Channel input capacitance for off condition. input to the analog output during switching.
CD (Off) IDD
Channel output capacitance for off condition. Positive supply current.
CD, CS (On) ISS
On switch capacitance. Negative supply current.
CIN
Digital input capacitance.

Rev. F | Page 10 of 16
 ADG528F

THEORY OF OPERATION
The ADG528F multiplexer is capable of withstanding overvoltages During fault conditions, the leakage current into and out of
from −40 V to +55 V, irrespective of whether the power supplies the ADG528F is limited to a few microamps. This protects the
are present or not. Each channel of the multiplexer consists of an multiplexer and succeeding circuitry from over stresses as well
n-channel MOSFET, a p-channel MOSFET, and an n-channel as protecting the signal sources, which drive the multiplexer.
MOSFET, connected in series. When the analog input exceeds the Also, the other channels of the multiplexer will be undisturbed
power supplies, one of the MOSFETs will switch off, limiting the by the overvoltage and will continue to operate normally.
current to submicroamp levels, thereby preventing the overvoltage Q1 Q2 Q3
+55V
from damaging any circuitry following the multiplexer. Figure 14 OVERVOLTAGE

illustrates the channel architecture that enables these multiplexers n-CHANNEL

MOSFET IS
to withstand continuous overvoltages.

09655-017
OFF
VDD VSS
When an analog input of VSS + 3 V to VDD − 1.5 V is applied
to the ADG528F, the multiplexer behaves as a standard multi- Figure 14. +55 V Overvoltage Input to the On Channel

plexer, with specifications similar to a standard multiplexer,

for example, the on-resistance is 400 Ω maximum. However, Q1 Q2 Q3
–40V
when an overvoltage is applied to the device, one of the three OVERVOLTAGE
MOSFETs will turn off. n-CHANNEL
MOSFET IS
p-CHANNEL

09655-018
Figure 14 to Figure 17 show the conditions of the three MOSFETs ON
MOSFET IS
VSS VDD OFF
for the various overvoltage situations. When the analog input
applied to an on channel approaches the positive power supply Figure 15. −40 V Overvoltage on an Off Channel with
Multiplexer Power On
line, the n-channel MOSFET turns off because the voltage on
the analog input exceeds the difference between VDD and the
n-channel threshold voltage (VTN). When a voltage more nega- Q1 Q2 Q3
+55V
OVERVOLTAGE
tive than VSS is applied to the multiplexer, the p-channel
n-CHANNEL
MOSFET will turn off because the analog input is more

09655-019
MOSFET IS
negative than the difference between VSS and the p-channel OFF

threshold voltage (VTP). Because VTN is nominally 1.5 V and Figure 16. +55 V Overvoltage with Power Off
VTP is typically 3 V, the analog input range to the multiplexer is
limited to −12 V to +13.5 V when a ±15 V power supply is used.
Q1 Q2 Q3
–40V
When the power supplies are present but the channel is off, OVERVOLTAGE
again either the p-channel MOSFET or one of the n-channel n-CHANNEL
MOSFETs will turn off when an overvoltage occurs. MOSFET IS
p-CHANNEL

09655-020
ON
MOSFET IS
Finally, when the power supplies are off, the gate of each OFF

MOSFET will be at ground. A negative overvoltage switches Figure 17. −40 V Overvoltage with Power Off
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the series
will remain off because the gate to source voltage applied to this
MOSFET is negative.

Rev. F | Page 11 of 16
ADG528F

TEST CIRCUITS
IDS

VDD VSS

V1
VDD VSS ID (ON)
S1 D
A
S2 VD
S D
S8
VS EN 2.4V

09655-021

09655-025
VS
RON = V1/IDS

Figure 18. On Resistance Figure 21. ID (On)

VDD VSS VDD VSS

IS (OFF) VDD VSS VDD VSS

S1 S1
A A
S2 D S2 D

VS S8 S8
EN 0.8V EN 0.8V
09655-022

09655-026
VD VS

Figure 19. IS (Off) Figure 22. Input Leakage Current (with Overvoltage)

0V 0V

VDD VSS
VDD VSS
0V A2 S1 A VS
VDD VSS
S1 A1
ADG528F
ID (OFF) A0
S2 D S8
A EN
S8 VD RS D
EN 0.8V
GND WR
09655-023

VS

09655-027
Figure 20. ID (Off) Figure 23. Input Leakage Current (with Power Supplies Off)

Rev. F | Page 12 of 16
 ADG528F

VDD VSS

VDD VSS 3V
A2 S1 VS1 ADDRESS
50% 50%
VIN 50Ω A1 DRIVE (VIN)
S2 TO S7
A0
S8 VS8
ADG528F
2.4V EN
RS D VOUT
RL CL 90%
GND WR
1MΩ 35pF
VOUT

90%

09655-024
tTRANSITION tTRANSITION

Figure 24. Switching Time of Multiplexer, tTRANSITION

VDD VSS 3V

ADDRESS
VDD VSS DRIVE (VIN)
A2 S1 VS
VIN 50Ω A1
S2 TO S7
A0
ADG528F S8
RS
D VOUT 80%
2.4V EN VOUT 80%
RL CL
GND WR
1kΩ 35pF

09655-029
tOPEN

Figure 25. Break-Before-Make Delay, tOPEN

VDD VSS 3V

ENABLE
VDD VSS DRIVE (VIN) 50% 50%
A2 S1 VS
A1 0V
S2 TO S8
A0 tOFF (EN)
ADG528F VOUT
RS 0.9VOUT
D VOUT
EN OUTPUT
RL CL
GND WR
VIN VRS 1kΩ 35pF
09655-030

0V
tON (EN)

Figure 26. Enable Delay, tON (EN), tOFF (EN)

VDD VSS 3V

VDD VSS WR 50%

A2 S1 VS
A1 0V
S2 TO S8
A0 tON (WR)
ADG528F
2.4V EN VOUT

RS D VOUT
OUTPUT
WR RL CL
GND 0.2VOUT
1kΩ 35pF
VRS VWR
09655-031

0V

Figure 27. Write Turn-On Time, tON (WR)

Rev. F | Page 13 of 16
ADG528F
VDD VSS 3V

VDD VSS RS 50% 50%

A2 S1 VS
A1 0V
S2 TO S8 tRS
A0
tOFF (RS)
ADG528F VOUT
2.4V EN
D VOUT 0.8VOUT
RS SWITCH
RL CL OUTPUT
GND WR
VIN 1kΩ 35pF

09655-032
0V

Figure 28. Reset Turn-Off Time, tOFF (RS)

VDD VSS

3V
VDD VSS
A2 RS LOGIC
2.4V
A1 INPUT (VIN)
A0
ADG528
0V
RS S D
VOUT
EN CL
VS
1nF
VOUT ∆VOUT
VIN GND WR

09655-033
QINJ = CL × ∆VOUT

Figure 29. Charge Injection

VDD

VDD
A2 S1
A1
S8
A0 VIN
ADG528F
2.4V RS
D VOUT
EN
RL
GND WR VSS
1kΩ
09655-034

VSS

Figure 30. Off Isolation

Rev. F | Page 14 of 16
 ADG528F

OUTLINE DIMENSIONS
0.180 (4.57)
0.048 (1.22 ) 0.165 (4.19)
0.042 (1.07) 0.056 (1.42)
0.20 (0.51) 0.020 (0.50)
0.042 (1.07) MIN R
3 19
0.021 (0.53)
0.048 (1.22) 4 18
PIN 1 0.050 0.013 (0.33)
0.042 (1.07) IDENTIFIER 0.330 (8.38) BOTTOM
(1.27)
TOP VIEW BSC VIEW
0.032 (0.81) 0.290 (7.37) (PINS UP)
(PINS DOWN) 0.026 (0.66)
8 14
9 13
0.020 0.045 (1.14)
(0.51) 0.356 (9.04) R
R SQ 0.025 (0.64)
0.350 (8.89)
0.120 (3.04)
0.395 (10.03) 0.090 (2.29)
SQ
0.385 (9.78)

COMPLIANT TO JEDEC STANDARDS MO-047-AA

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 31. 20-Lead Plastic Leaded Chip Carrier [PLCC]

(P-20)
Dimensions shown in inches and (millimeters)

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
ADG528FBP −40°C to +85°C 20-Lead PLCC P-20
ADG528FBPZ −40°C to +85°C 20-Lead PLCC P-20
1
Z = RoHS Compliant Part.

Rev. F | Page 15 of 16
ADG528F

NOTES

©2001–2011 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D09655-0-7/11(F)

Rev. F | Page 16 of 16