Microelectronic System Lab.

1 Report
Name Matr. Nr : Norma Hermawan : 728799

1. 1 Bit Full Adder a) VHDL Code Including library

library ieee; use ieee.std_logic_1164.all;

Entity declaration
entity adder is port( adder_in end adder ; : in bit_vector(2 downto 0); -- three input signals are bit_vector type. F, Cout : out bit);

if statement implementation
architecture if_statement of adder is begin process (adder_in) is begin if adder_in = "001" then F <= '1'; Cout <= '0'; elsif adder_in = "010" then F <= '1'; Cout <= '0'; elsif adder_in = "011" then F <= '0'; Cout <= '1'; elsif adder_in = "100" then F <= '1'; Cout <= '0'; elsif adder_in = "101" then F <= '0'; Cout <= '1'; elsif adder_in = "110" then F <= '0'; Cout <= '1'; elsif adder_in = "111" then F <= '1'; Cout <= '1'; else -if adder_in = "000" then F <= '0'; Cout <= '0'; end if; end process; end if_statement;

b) Simulation Result

Description of the result Clock with different frequency is applied in the input of adder instead of forced signal. That will make sure that all case are tested. The result is exactly same as truth table. When input 000 is applied, f output give '0' and cout output give '0' and so on as seems on picture. It is said that simulation is successful.

c) Stimulus Only Tesbench Including Library

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

Entity declaration
entity adder_tb is end adder_tb ;

Component declaration
component adder is port( adder_in : in bit_vector(2 downto 0); F, Cout : out bit); end component;

Internal Signals
signal signal data_input : bit_vector(2 downto 0); -- set initial value outF, Cout : bit;

Device Under Test instantiation

component adder is port( adder_in : in bit_vector(2 downto 0); F, Cout : out bit); end component;

Stimuli
data_input (0)<= '0','1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns; data_input (1)<= '0','1' after 20 ns, '0' after 40 ns, '1' after 60 ns; data_input (2)<= '0','1' after 40 ns, '0' after 80 ns;

Simulation using testbench

Simulation using testbench gives same result as if manually apply signal to the gate. data_input (2 downto 0) is set to different value every 10 ns to test all cases. 2. 4x1Multiplexer a) VHDL-code
-- mux4x1.vhd --------------------------entity MUX4X1 port( S : in E : in Y : out end MUX4X1; is bit_vector(1 downto 0); bit_vector(3 downto 0); bit);

architecture Behaviour of MUX4X1 is signal enabled_signal : bit; begin -- standard mux4x1 with S select Y <= E(0) E(1) E(2) E(3) end Behaviour;

when when when when

"00", "01", "10", "11";

b) Stimuli Testbench
-- mux4x1_tb.vhd -- testbench 4x1 multiplexer --------------------------------entity Testbench is end Testbench; architecture TestbenchArch of Testbench is signal S_in : bit_vector(1 downto 0); signal E_in : bit_vector(3 downto 0); signal Y_out: bit; begin DUT: entity work.MUX4X1 port map(S_in, E_in, en_in, Y_out); E_in <= "1011", "0100" after 400 ns; S_in <= "00","01" after 100 ns,"10" after 200 ns, "11" after 300 ns, "00" after 400 ns,"01" after 500 ns, "10" after 600 ns, "11" after 700 ns; end architecture TestbenchArch;

c) Simulation Result

Simulation result verify that the given VHDL code is correct. y_out pin logic is dependent to s_in. If s_in = 0, than y_out logic is same as e_in(0), if s_in = 1, than y_out logic is same as e_in(1) and so on. That is exactly how a multiplexer works. d) Selected Signal Assignment Multiplexer with Enable Signal
with S select enabled_signal <= E(0) when "00", E(1) when "01", E(2) when "10", E(3) when "11"; with en select Y <= enabled_signal when '0', '0' when '1';

e) Conditional Signal Assignment Multiplexer with Enable Signal

enabled_signal <= E(0) when S = "00" E(1) when S = "01" E(2) when S = "10" E(3) ; -- when S = Y <= enabled_signal when en='0' else else else else "11"; '0';

f) Extended Testbench
-- mux4x1_tb.vhd -- testbench 4x1 multiplexer --------------------------------entity Testbench is end Testbench; architecture TestbenchArch of Testbench is signal S_in : bit_vector(1 downto 0); signal E_in : bit_vector(3 downto 0); signal en_in: bit; signal Y_out: bit; begin DUT: entity work.MUX4X1 port map(S_in, E_in, en_in, Y_out); E_in <= "1011", "0100" after 400 ns; S_in <= "00","01" after 100 ns,"10" after 200 ns, "11" after 300 ns, "00" after 400 ns,"01" after 500 ns, "10" after 600 ns, "11" after 700 ns; en_in <= '1','0' after 400 ns; end architecture TestbenchArch;

g) Simulation Result Both (d) and (e) are giving same result

If the en_in pin is '1', then y_out will go '0' ignoring any other input conditions. If en_in is '0', than multiplexer works normally as descibed in (c). 3. XOR Gate Implementation Homework a) if-elsif-else Code
--import std_logic from the IEEE library library ieee; use ieee.std_logic_1164.all; --ENTITY DECLARATION: name, inputs, outputs entity xor_ifelsif_gate is port( A, B : in std_logic; F : out std_logic); end xor_ifelsif_gate; --FUNCTIONAL DESCRIPTION architecture ifelsif of xor_ifelsif_gate is begin xor_process: process(A,B) begin if (A = B) then F <= '0'; else F <= '1'; end if; end process; end ifelsif;

Result

b) Logical operator XOR Code

--import std_logic from the IEEE library library ieee;

use ieee.std_logic_1164.all; --ENTITY DECLARATION: name, inputs, outputs entity xor_logic_gate is port( A, B : in std_logic; F : out std_logic); end xor_logic_gate ; --FUNCTIONAL DESCRIPTION architecture logical of xor_logic_gate is begin F <= A xor B; end logical;

Result

c) Conditional signal assignment Code

--import std_logic from the IEEE library library ieee; use ieee.std_logic_1164.all; --ENTITY DECLARATION: name, inputs, outputs entity xor_cond_gate is port( A, B : in std_logic; F : out std_logic); end xor_cond_gate ; --FUNCTIONAL DESCRIPTION architecture conditional of xor_cond_gate is begin F <= '0' WHEN (A = B) ELSE '1'; end conditional;

Result