Exploring Neuromorphic Computing Based on Spiking

Neural Networks: Algorithms to Hardware

NITIN RATHI, INDRANIL CHAKRABORTY, and ADARSH KOSTA, School of Electrical and
Computer Engineering, Purdue University, USA
ABHRONIL SENGUPTA, School of Electrical Engineering and Computer Science, Pennsylvania State
University, USA
AAYUSH ANKIT, School of Electrical and Computer Engineering, Purdue University, USA
PRIYADARSHINI PANDA, Electrical Engineering, Yale University, USA
KAUSHIK ROY, School of Electrical and Computer Engineering, Purdue University, USA
243
Neuromorphic Computing, a concept pioneered in the late 1980s, is receiving a lot of attention lately due to
its promise of reducing the computational energy, latency, as well as learning complexity in artificial neural
networks. Taking inspiration from neuroscience, this interdisciplinary field performs a multi-stack optimiza-
tion across devices, circuits, and algorithms by providing an end-to-end approach to achieving brain-like
efficiency in machine intelligence. On one side, neuromorphic computing introduces a new algorithmic para-
digm, known as Spiking Neural Networks (SNNs), which is a significant shift from standard deep learning and
transmits information as spikes (“1” or “0”) rather than analog values. This has opened up novel algorithmic
research directions to formulate methods to represent data in spike-trains, develop neuron models that can
process information over time, design learning algorithms for event-driven dynamical systems, and engineer
network architectures amenable to sparse, asynchronous, event-driven computing to achieve lower power
consumption. On the other side, a parallel research thrust focuses on development of efficient computing
platforms for new algorithms. Standard accelerators that are amenable to deep learning workloads are not
particularly suitable to handle processing across multiple timesteps efficiently. To that effect, researchers have
designed neuromorphic hardware that rely on event-driven sparse computations as well as efficient matrix
operations. While most large-scale neuromorphic systems have been explored based on CMOS technology,
recently, Non-Volatile Memory (NVM) technologies show promise toward implementing bio-mimetic func-
tionalities on single devices. In this article, we outline several strides that neuromorphic computing based on
spiking neural networks (SNNs) has taken over the recent past, and we present our outlook on the challenges
that this field needs to overcome to make the bio-plausibility route a successful one.

CCS Concepts: • Theory of computation → Design and analysis of algorithms; • Computing method-
ologies → Bio-inspired approaches;

N. Rathi and I. Chakraborty contributed equally to this research.

This work was supported in part by the Center for Brain-inspired Computing Enabling Autonomous Intelligence (C-BRIC),
one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA, in part by the
National Science Foundation, in part by Intel, in part by the ONR-MURI program, and in part by the Vannevar Bush Faculty
Fellowship.
Authors’ addresses: N. Rathi, I. Chakraborty, A. Kosta, A. Ankit, and K. Roy, School of Electrical and Computer Engineering,
Purdue University, West Lafayette, IN, 47906; emails: {rathi2, ichakra, akosta, aankit, kaushik}@purdue.edu; A. Sengupta,
School of Electrical Engineering and Computer Science, Pennsylvania State University, State College, PA, 16801; email:
[email protected]; P. Panda, Electrical Engineering, Yale University, New Haven, CT, 06511; email: [email protected].
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243:2 N. Rathi et al.

Additional Key Words and Phrases: Neuromorphic Computing, Spiking Neural Networks, bio-plausible learn-
ing, spike-based backpropagation, event cameras, In-Memory Computing, Non-Volatile Memories, asynchro-
nous communication
ACM Reference format:
Nitin Rathi, Indranil Chakraborty, Adarsh Kosta, Abhronil Sengupta, Aayush Ankit, Priyadarshini Panda,
and Kaushik Roy. 2023. Exploring Neuromorphic Computing Based on Spiking Neural Networks: Algorithms
to Hardware. ACM Comput. Surv. 55, 12, Article 243 (March 2023), 49 pages.
https://doi.org/10.1145/3571155

1 INTRODUCTION
In the seminal book “The Computer and the Brain” [241], John von Neumann discussed how the
brain can be viewed as a computing machine. Since then, there have been multitude of works
trying to perform brain-like functions with brain-like architectures. Neural networks, specifically
Deep Learning, have powered the current era of ubiquitous artificial intelligence, demonstrating
unprecedented success, even surpassing humans in several cognitive tasks [116, 214]. But at what
cost?
While our fastest parallel computers have enabled deep learning, they are primarily limited by
their ability to move data between the compute and memory, which is in stark contrast to the mas-
sively parallel, sparse, event-driven, distributed processing capabilities of the brain. Consequently,
there is a substantial energy-efficiency gap between the brain and deep learning architectures.
With increasing complexity of tasks in the era of in-sensor analytics and Internet of Things (IoT)
and with the ever-growing size of networks deployed for such tasks, implementing and training
such deep neural networks in edge devices with constrained power, energy and computational
budgets have become a daunting task [257].
The underlying computational paradigm for Neuromorphic Computing is an emerging disci-
pline of artificial neural networks that attempts to mimic neuronal and synaptic functionalities tem-
porally and in a distributed fashion based on neuron “spikes” or firing events in the brain [47, 70].
Termed as Spiking Neural Networks (SNNs) [133], these networks lead to possibilities of sparse,
event-driven neuronal computations and temporal encoding–a shift from standard deep learning
networks, termed as Analog Neural Networks (ANNs), which process and transmit logically
analog information rather than all-or-nothing spikes.
Owing to the unique features of SNNs, there is a need to explore new algorithmic directions that
are more amenable to its implicit recurrence, event-driven, and sparse nature of computing. SNNs,
by their design, are dynamical recurrent systems; the internal state of the spiking neuron integrates
temporal information and maintains a history of previous inputs. Training recurrent networks
with binary signals exacerbates the issue of exploding and vanishing gradients. While the event-
driven nature of SNNs offers a promising route for achieving lower energy and power consumption
for intelligent hardware, it also poses a critical limitation on their learning capability. Integrating
temporally encoded statistics of spiking neurons/synapses with standard gradient-descent-based
learning algorithms (catered for ANNs that do not encode information in time) presents several
challenges [123, 265]. It is difficult to train the layers of a deep SNN architecture globally in an
end-to-end manner [181]. Bio-plausible unsupervised [52] and supervised [99] learning have been
explored as a viable solution that allows localized learning, and has proven to be computationally
more efficient than backpropagation-based algorithms. Although SNNs trained with unsupervised
learning algorithms are not yet suitable for challenging cognitive tasks, they find applications in
clustering and extracting low-level features from images for recognition. There has also been a
significant thrust towards developing scalable gradient-based algorithms that can be adapted to

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Exploring Neuromorphic Computing Based on Spiking Neural Networks 243:3

event-driven, sparse activity in SNNs [16, 166]. Overall, these algorithmic drives promises to scale
up the performance of SNNs to levels currently offered by ANNs, while preserving the benefits
of sparse event-based computations. Also, current algorithms do not take full advantage of the
quintessential “time” parameter, future research can explore these opportunities along with imple-
menting additional bio-plausible functions to further the performance of SNNs.
A parallel research thrust focuses on the development of efficient computing platforms for
the evolving SNN algorithms and workloads. Hardware for SNN workloads derives certain
motivation from the broad field of Neuromorphic Engineering. The concept of Neuromorphic
Engineering was first proposed by Carver Mead in his seminal book [144, 145], where he explored
the notion of analog circuits to mimic complex neuronal and synaptic functionalities in the brain.
This was later demonstrated in groundbreaking work of implementing a Silicon Neuron [139]
and then a Silicon Retina by Mahowald et al. [138]. Various neuromorphic chips have hence been
implemented such as ROLLS [187], Dynap-SEL [154], Neurogrid [21], SpiNNaker [171] and so
on. These implementations target emulation of the biophysics of neurons and synapses of the
brain through CMOS circuits. SNN workloads tend to use simpler neuro-synaptic models, and can
potentially take inspiration from aforementioned works that have delved deeper into emulating
brain-like characteristics on chip. Besides neuro-synaptic models, another key component of
SNN hardware is acceleration of the computations in SNN workloads. The requirements of
such SNN accelerators have evolved significantly over the last few years, particularly toward
designing large-scale systems effectively leveraging key features of SNN algorithms. The accel-
erators targeted toward executing standard ANN workloads more efficiently such as General
Purpose Graphics Processing Units (GPGPUs) and Tensor Processing Units (TPUs) [98]
are not designed to optimize processing across multiple timesteps. Neuromorphic hardware
architectures draw inspiration from two basic principles of SNNs: (i) event-driven sparse com-
putations and (ii) efficient and parallel matrix operations. While ANN accelerators are designed
to efficiently perform matrix operations, they fail to leverage temporal sparsity in SNNs. The
temporal sparsity has inspired various architectures such as T rueNorth [6] and Loihi [46], which
deploy asynchronous computing systems to reduce compute and communication of data. The
second feature is more generic to neural networks, and have overseen significant developments
of domain-specific accelerators [5, 163] with intertwined memory and compute elements to
overcome the von-Neumann bottleneck. While most large-scale SNN accelerators are based
on CMOS technology, several Non-Volatile Memory (NVM) technologies have emerged as a
promising candidate for building bio-mimetic devices [31, 37, 269]. Such devices can emulate neu-
ronal [172, 206, 234] and synaptic functionalities [28, 84, 97, 111, 185, 224, 226] at a one-to-one level
while simultaneously enabling a novel paradigm of “In-Memory” computing, i.e., in situ synaptic
computations [262] for acceleration of SNN workloads [11, 216]. Thus, there is a need to co-design
neuromorphic algorithms and the underlying computing architectures in a multi-disciplinary
research [88].
This article outlines recent developments in the domain of Spiking Neural Networks under the
umbrella of neuromorphic engineering in terms of driving research directions in algorithms as
well as hardware. Whether we will be able to achieve the much eluded energy-efficiency in ma-
chine intelligence platforms is a question that is difficult to answer currently. However, we be-
lieve a rethinking of brain-inspired computing with a unified hardware-software perspective is
essential to enable computationally efficient learning. Combining outlooks from varying fields—
computational neuroscience, machine learning, materials, devices, circuits, and architectures—will
help outline the challenges posed by these different outlooks and provide a future direction for in-
telligent platforms with power and energy-efficiency akin to the brain.

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2 ALGORITHMS
In this section, we delve into the algorithmic foundations for SNNs. Significant developments in
neuron modeling, input encoding, learning algorithms, and network architectures have shaped
the progress of neuromorphic computing. Due to the representation of inputs with time domain
information, considerable rethinking of the training algorithms, currently in place for ANNs, is
required.

2.1 Neuron Models

Neuron models with varying degrees of bio-fidelity have been proposed to mimic the dynamics
of biological neurons [69]. Some of the simpler and popular models are integrate-and-fire (IF),
leaky-integrate-and-fire (LIF), and spike response model (SRM) that are widely used in deep
SNNs for image-recognition tasks [52, 96, 199, 209, 213]. The more detailed and complex Hodgin-
Huxley model considers the dynamics of different ion channels observed in biological neurons [83].
The IF/LIF and SRM neuron models can be derived from the Hodgin-Huxley model [69]. Although
Hodgin-Huxley model is more biologically realistic, current optimization algorithms (such as ANN-
to-SNN conversion and surrogate gradient-based learning) perform better with simpler IF/LIF neu-
ron models. Most of the spiking neuron models have few things in common: They have an internal
state that accumulates the input stimuli; the neuron generates an output (or fires) when the inter-
nal state crosses a threshold value; and sometimes the firing event is followed by a refractory
time-period, during which the neuron is dormant and does not respond to input stimuli. Here, we
discuss the prevalent IF/LIF model that shows competitive performance on complex tasks and the
stochastic neuron model that does not have an internal state. We refer to Reference [69] for details
on other spiking neuron models.

2.1.1 LIF/IF Neuron Model. The dynamics of the IF/LIF model is described by the differential
equation
du (t )
τ = −[u (t ) − ur est ] + RI (t ), (1)
dt
where u is the internal state known as the
membrane potential, ur est is the resting value
of the membrane potential, R(I ) is the input
resistance (current), and τ is the time con-
stant [69]. The equation represents the behav-
ior of the neuron when the membrane poten-
tial (u) is below the threshold potential (v). The
membrane potential integrates the input cur-
rent over time and the neuron fires when the
potential crosses the threshold voltage. IF/LIF
is a very simple model and does not reflect the Fig. 1. Dynamics of a leaky-integrate-and-fire (LIF)
overall complex dynamics of a biological neu- model in response to input spikes.
ron. However, its simplicity makes it attractive
to optimize in deep learning frameworks. For LIF neuron, the integration is leaky and the mem-
brane potential decays over time in the absence of input stimuli (Figure 1). The firing event is
sometimes followed by a refractory period during which the membrane potential does not inte-
grate the input current. This avoids excessive firing of a particular neuron and allows other neurons
to participate in the learning [52]. The membrane potential is reset after firing and returns to its
rest value after the refractory period (Figure 1).

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The continuous time domain differential equation (Equation (1)) is solved to get an iterative
update rule [254] where τ is mapped to λ through integration as

uit = λuit −1 + w i j otj − voit −1 , (2)
j
⎧
⎪ 1, if uit −1 > v
oit −1 = ⎨
⎪ 0, otherwise , (3)
⎩
where u is the membrane potential, subscript i and j represent the post- and pre-neuron, respec-
tively, superscript t is the timestep, λ is a constant (<1) responsible for the leak in membrane
potential, w is the weight connecting the pre- and post-neuron, o is the output spike, and v is
the threshold potential. The second term in Equation (2) integrates the inputs and the last term
resets the membrane potential after firing. The reset mechanism reduces the membrane potential
by the threshold value instead of resetting it to the reset potential. This reduces information
loss and leads to better performance in image classification tasks [77]. Most of the hardware
implementations of LIF models employ the reset to ground, however, few of them provide the
functionality of reset by subtraction [4].
2.1.2 Stochastic Neuron Model. The deterministic IF/LIF neuron model, discussed above, emits
a spike as soon the membrane potential crosses the threshold voltage. If the membrane potential
is below the threshold at any timestep, then the computation in next timestep begins with the
previous membrane potential. In contrast, a probabilistic neuron model, fires stochastically and the
probability of firing at a particular time is a non-linear function of the instantaneous magnitude
of the weighted input [19, 206, 242]. The probability of firing of a post-neuron is defined as
1
P (oi = 1) = 
− j wi j o j
, (4)
1+e
where o j is the spike input (1 or 0) from pre-neurons and w i j is the synaptic weight connecting pre-

and post-neuron. In the absence of any input activity and bias ( j o j = 0) the firing probability is
0.5. A network with stochastic neurons is evaluated over multiple iterations and the output of a
layer is computed as the average number of spikes over all iterations. The average analog value
can then be rate-coded (more on this in Section 2.2.1) as a Poisson spike train to act as input to the
next layer. These stochastic models are difficult to implement in hardware.

2.2 Input Encoding

SNNs compute and communicate information through binary signals (spikes). Therefore, analog
inputs such as image pixels or real numbers need to be encoded in binary signals. A single spike is
a discrete event represented as “+1” or “−1” and an analog value is encoded in a set of spikes. The
encoding mechanism determines the quantization or conversion error in representing the analog
value with spikes. The analog value is represented by one or more spikes distributed over a time
period. The popular coding methods are rate coding [52, 209], temporal coding [155], and explicitly
training an encoding layer [193, 255]. The encoding methods are depicted in Figure 2.
2.2.1 Rate Coding. In rate coding, the information is represented in the mean firing rate of
the neuron within a time period. The timing of the individual spikes has no relevance. In Pois-
son encoding, a type of rate coding, at each timestep the normalized analog value is compared
with a random number. The neuron fires (output “1”) if the analog value is greater, otherwise
stays inactive (output “0”). The number of timesteps1 determines the discretization error in the
1 Wall-clocktime for 1 “timestep” is dependent on the number of computations performed and the underlying hardware.
In simulation, 1 timestep is the time taken to perform 1 forward pass.

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Fig. 2. Different input encoding methods for SNNs. In rate coding, the information is represented in the
average number of spikes in a given duration. In Poisson rate coding, at every timestep (t  ) a random number
[0, 1] is generated for each neuron and compared with the corresponding pixel value; the neuron fires if the
pixel value is greater than the random number. In Temporal Switch Coding, a form of temporal coding, the
time difference between two spikes (ts+ and ts− ) encodes the input data; p ∗ is proportional to the value being
encoded. Event cameras capture the asynchronous changes in log intensity as discrete spikes over time [158].

representation of the analog value by spike-train. This leads to adopting a large number of
timesteps for high accuracy at the expense of high inference latency [209]. Rate coding is inef-
ficient due to minimal information content in each spike.
2.2.2 Temporal Coding. Unlike rate coding, in temporal coding, the timing of individual spikes
is crucial, as the information is encoded in the timing instances. The Logarithmic Temporal Cod-
ing [267] encodes the analog value as a binary number with a predefined number of bits. The
number of bits serves as a proxy for time and a spike is generated for each active bit in the binary
number. For sparser representations, the spike is generated only for the most significant bit. Rank
Order Coding [48] represents the information as the order of firing instances instead of using the
precise timing of the spike. The input neurons encoding larger analog values fire earlier compared
to neurons encoding smaller values. Time-to-First-Spike [156, 198], a form of Rank Order Coding,
restricts each neuron to spike only once. The order or time of spike is inversely proportional to the
analog value being encoded. In Temporal Switch Coding [76], the analog value is encoded using
two spikes, and the time difference between the spikes is proportional to the encoded value. It
achieves better energy-efficiency, since at most two memory accesses and two addition computa-
tions are performed for each synapse. Although temporal coding methods can encode information
with less number of spikes, the lack of appropriate training algorithms for temporally coded SNNs
results in sub-optimal performance compared to rate-coded SNNs [198].
2.2.3 Encoding Layer. Rate and temporal coding, discussed earlier, are fixed formula-based, non-
parameterized coding methods. Alternatively, the input encoding can be made part of the training
process and, therefore, the encoding function can have parameters that are trained with the input
data. The encoding function is modelled as a neural network that receives the analog values and
generates a spike train. In some cases, this network is as simple as one convolution layer [132,
193, 199]. The encoding layer is appended to the front of the SNN and trained end-to-end with
the entire SNN. The encoding layer consists of IF/LIF neuron that integrates the weighted analog
values and generates a spike-train. The input to the encoding layer at every timestep is the same
analog value.
2.2.4 Event-based Sensors. All the above discussed encoding methods are designed with the aim
to encode the original image frames captured by standard cameras into pixel-wise temporal spikes
to construct the inputs for the SNN. However, since the original input had no time information
to begin with, this spatio-temporal representation is not very well justified. Standard cameras
that are typically used to capture image as well as video information fall victim to a variety of
drawbacks for real-world and edge-applications. Their low and fixed sampling rate makes them

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prone to motion blur when capturing high-speed motion. Their low dynamic range of operation
renders them unable to capture meaningful information in challenging lighting conditions such
as low light and high dynamic range (HDR) environments. In addition, sampling the entire
image frame at regular intervals makes them capture redundant information over and over in
nearly static scenes leading to a high power consumption. These shortcomings motivate the need
for specialized sensing modalities for efficient operation in challenging real-world environments
while being significantly energy-efficient.
Event-based sensors (such as DVS128 [129], DAVIS240 [29], Samsung DVS [217], etc.) aim to
address these concerns by offering asynchronous sensing of change in visual information from the
environment. Also known as bio-inspired silicon retinas, event cameras detect the log-intensity (I )
changes at each pixel element asynchronously and independently and generate a spike event if
the change exceeds a threshold (C):
 log(It +1 ) − log(It ) ≥ C. (5)
These cameras employ a threshold-variation-insensitive algorithm over the standard asynchro-
nous sigma-delta modulation when handling the input intensity signal. This results in idle output
for no change in input intensity. Since only the log intensity changes are monitored and recorded,
a very low power consumption can be achieved. Due to the fundamentally different working prin-
ciple compared to standard cameras, event-cameras provide exceptionally high temporal resolu-
tion (10μs vs. 3ms), high dynamic range (120dB vs. 74dB), and low power consumption (∼10mW vs.
3W ). Event-cameras offer advantages compared to standard cameras in scenarios such as real-time
human-machine interface systems, robotics, wearable electronics, or vision-based edge-devices in
general, where efficient operation in challenging lighting conditions, low latency, and power con-
sumption [130] are paramount. They also find applications in computer vision and robotics tasks
such as object detection and tracking [151], gesture recognition [10], optical flow/depth, egomo-
tion estimation [260, 270, 272], and so on.
Event-based encoding results in asynchronous and sparse spatio-temporal data containing both
structural and temporal information in the form of a voxel. This type of input representation can
be naturally handled by asynchronous event-driven models such as SNNs, as will be discussed in
later sections. Nevertheless, most of the research using event cameras has been carried out either
in conjunction with traditional computer vision methods or with ANNs. This requires construct-
ing event frames in place of image frames (as with standard cameras) by accumulating events
over a certain time interval and subsequently considering them equivalent to image frames there-
after. For example, works such as References [260, 270, 272] utilize these event frames as channels
serving as input to an ANN. This leads to the loss of essential temporal information within the
accumulation interval as well as the temporal ordering of individual frames. Although, they show
promising potential when compared with approaches using standard cameras, they still do not
completely utilize the fundamental benefits of event cameras. This is because the asynchronous
and discrete nature of event camera data makes it incompatible to work with with traditional ANNs
in their native form that rely on frame-based information. In addition, ANN-based methods are
typically designed for pixel-based images following the photo-consistency assumption (color and
brightness of an object remains the same over image sequences). Certain works such as References
[22] and [23] explore using events directly for estimating visual-flow, however, they are limited in
terms of scalability to more complex problems. In light of this, SNNs inspired by the biological neu-
ron model, offer direct handling of event data providing asynchronous computations while also
exploiting the rich spatio-temporal dynamics and inherent input sparsity. Moreover, using event
data with SNNs eliminates the need for having any complicated spike encoding stage required for

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ANN-based methods. The working principle of spiking neurons naturally offers compatibility for
event-based asynchronous processing distributed across SNN layers and, combined with compu-
tation on specialized neuromorphic hardware such as IBM’s TrueNorth [6] or Intel’s Loihi [46],
provides high energy-efficiency. Section 3.4 discusses some works combining event cameras with
SNNs along with the benefits as well as challenges associated with them.

2.3 Feedforward Networks

Feedforward networks comprise multiple convolutional and/or fully connected layers, where in-
formation flows from the input to the output layer, and connections between the neurons do not
form a cycle. In this section, we discuss various unsupervised, supervised, and bio-plausible local
learning rules for feedforward SNNs.
2.3.1 Unsupervised Learning. Unsupervised learning refers to algorithms that identify patterns
from unlabelled data. The data consists of inputs (image, audio, text, etc.) and no corresponding
label or targets. Unsupervised learning is desirable to find clusters in raw and unknown data.
Spike Timing Dependent Plasticity: Spike Timing Dependent Plasticity (STDP) [25, 69, 101],
an unsupervised learning technique, is a biologically plausible mechanism for synaptic learning
in SNNs. STDP-based learning rules [218] modify the weight of a synapse interconnecting a pair
of pre- and post-synaptic neurons based on the degree of correlation between the respective spike
times as specified by
⎧
⎪ A+ e − τ+ , if Δt = tpost − tpr e > 0
Δt

Δw = ⎪⎨ Δt , (6)
⎩ −A− e − , if Δt = tpost − tpr e < 0
τ

where tpr e and tpost are the time instant of a pair of pre- and post-spikes, A+ , A− , τ+ , and τ− are
the learning rates and time constants governing the change, Δw, in the synaptic weight. Another
variant of the STDP rule performs both potentiation2 and depression based on the positive values
of Δt (Figure 3(d)) [52, 192]. The weight update is computed as
  tpr e −tpos t  
Δw = η × e τ
− o f f set × [wmax − w]μ , (7)

where Δw is the change in weight, η is the learning rate, tpr e and tpost are the time instant of pre-
and post-synaptic spikes, τ is the time constant, o f f set is a constant used for depression, wmax is
the maximum constrained imposed on the synaptic weight, w is the previous weight value, μ is a
constant that governs the exponential dependence on previous weight value. The weight update
is positive (potentiation) if the post-neuron spikes immediately after the pre-neuron and negative
(depression) if the spikes are far apart (Figure 3(d)). There are many other variants of STDP curves
in response to spike pair stimulation, including spike triplets and quadruplets [73]. STDP modu-
lates the strength of each synapse independently; while this is very powerful, it also introduces
stability problems. Therefore, mechanisms to maintain an appropriate level of distributed activity
throughout the network are explored in Reference [3]. In STDP, effective synapses are strength-
ened and ineffective synapses are weakened, which creates a positive feedback loop and leads to
stability issues.
In addition to non-volatile STDP, which is non-adaptive to different learning scenarios (due to
the absence of any forgetting mechanism in absence of a spike stimulus), synaptic learning mech-
anisms such as Short-Term Plasticity (STP) and Long-Term Potentiation (LTP) [140, 274]

2 Inneuroscience, the increase in synaptic strength (positive change in weight) is called potentiation, and the reverse (neg-
ative change in weight) is termed depression.

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Fig. 3. Unsupervised learning in SNN based on STDP learning rule; (a) the input image is converted to spike-
train, where the probability of spiking is proportional to the pixel intensity; (b) a 2-layer fully connected net-
work with inhibitory connections receives spike inputs and the weights are trained based on STDP learning
rule. The input-to-excitatory layer weights are trained, whereas the excitatory-to-inhibitory and inhibitory-
to-excitatory layer connections are fixed before training [52]; (c) visualization of input-to-excitatory layer
weights show that each excitatory neuron learns a unique class; (d) STDP learning rule (Equation (7)) based
on temporal correlation between pre- and post-synaptic spikes (η = 0.002, τ = 20ms, o f f set = 0.4, wmax =
1, w = 0.5, μ = 0.9).

bearing resemblance to the concepts of Short-Term and Long-Term Memory [13, 113] have also
been explored for online learning that can adapt synaptic weights to dynamically changing envi-
ronments. Catastrophic forgetting, a phenomena observed in continual learning where knowledge
about old tasks is lost when new tasks are learned, is a prevalent issue in neural networks, and
SNNs trained with STDP also suffer from it [173]. An adaptive weight decay mechanism [173] that
gradually forgets less important weights and learns new information in its place can effectively
learn new data and avoid catastrophic forgetting.
SNNs are being actively explored for unsupervised pattern recognition due to their ability to
learn input representations using STDP-based localized learning rules. The unsupervised feature
learning capability of SNNs was initially demonstrated using two-layer SNN consisting of an in-
put layer fully connected to neurons in the excitatory (or output) layer followed by an inhibitory
layer (Figure 3) [52, 74]. However, the performance of such two-layer SNNs is still limited to sim-
ple tasks like handwritten digit recognition. Convolutional SNNs, similar in architecture to their
deep learning counterparts [107], were proposed to address the limited scalability of two-layer
SNNs [63, 103, 121, 141, 221, 223, 230, 232]. The convolutional layers can be trained using STDP for
learning hierarchical input representations in an unsupervised manner, which are then fed to the
classifiers trained using supervised learning rules for inference. While STDP-trained convolutional
SNNs yield improvement over fully connected two-layered SNNs, the accuracy is still lower than
state-of-the-art performance on popular benchmark datasets. The challenge for STDP-trained con-
volutional SNNs is two-fold. First, it remains to be seen how deep these SNNs can be scaled, since
the current networks are limited to few convolutional layers. Second, it is inconclusive if STDP
alone can enable the deeper layers to learn complex input representations. STDP is powerful at
clustering and extracting low-level features from images but fails to generalize on composing high-
level features and, therefore, two or more layers of STDP learning do not provide much benefit [63].
In hierarchical learning with convolutional layers, it is necessary to combine learned features into
high-order features that can perform recognition. Some algorithms that can supplement the fea-
ture extraction of STDP can address these shortcomings. However, if these grand challenges are

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243:10 N. Rathi et al.

met, then STDP would enable a new generation of low-cost (area/power/resource requirement),
local, and unsupervised learning framework, as opposed to their non-spiking counterparts (ANNs)
relying on global and supervised learning techniques. The advantages are multitude; unsupervised
learning enables the network to adapt to changing environments while local learning assists in im-
plementation of low-power learning circuit primitives. Local learning would remove the need for a
global error distribution that is essential for supervised learning, which, in turn, requires hardware
expensive circuitry.
Stochastic STDP: The STDP algorithm, de-
scribed earlier, works well for shallow net-
works (2–3 layers) with full precision weights.
However, networks with low precision, for ex-
ample binary weights, require a probabilistic
learning rule for efficient training and to avoid
rapid switching of weights between allowed
levels. The difference between the spike times
of post- and pre-neuron (tpost −tpr e ) is mapped
to the switching probability of the connecting
binary weight (Figure 4) [222]. The synaptic
weight switches from low to high state (Heb-
bian potentiation) with a constant probability Fig. 4. Stochastic STDP learning rule for binary
if the time difference is positive and below a synapse where the probability of the synapse switch-
certain threshold. If the time difference is neg- ing from high to low state (H→L) is a function of the
ative and above a fixed threshold, then the difference between the spike times of post- and pre-
weight switches from high to low state (Heb- neuron (tpost − tpr e ).
bian depression) with a constant probability.
Additionally, if the time difference is positive and above a certain value, then the synapse is de-
pressed (anti-Hebbian depression) due to low causality. The authors in Reference [222] mention
that anti-Hebbian learning enables the synapses to unlearn features lying outside the receptive
field like noisy background in images. The stochastic STDP learning rule enables training of SNNs
with binary weights [188] and can achieve similar accuracy as full-precision SNNs trained with
STDP [52] but with lower memory requirements [222]. Additionally, Reference [119] proposes a
semi-supervised training mechanism with STDP. The network is initialized with pre-trained STDP
weights trained in an unsupervised manner. Next, supervised gradient-based learning is employed
to fine-tune the weights and improve the accuracy with faster convergence. Even though STDP-
based local learning rules are not yet applicable for large-scale problems (like ImageNet), they
perform relatively well for energy-efficient clustering tasks.
2.3.2 Supervised Learning. Unlike unsupervised learning that does not require labelled exam-
ples for training, supervised learning derives its strength from large corpus of labelled examples.
In supervised learning, the network receives an input (image, text, or audio) and produces a
prediction score for all possible labels that the input can belong to, i.e., number of classes in the
datasets. The prediction is compared with the true label (one-hot vector with “1” for the correct
class and “0” for everything else) to determine the error/loss, and the network parameters (weights,
bias, etc.) are updated based on the gradients of the loss function with respect to the parameters.
Generally, in ANNs the supervised methods perform extremely well if a large number of labelled
samples are available. However, direct implementation of gradient-based methods in SNNs is
challenging because of the discontinuous and non-differentiable nature of the spiking neuron.

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Exploring Neuromorphic Computing Based on Spiking Neural Networks 243:11

To circumvent this problem, researchers pro-

posed methods to convert a trained ANN to
an SNN for inference [34, 53, 199, 209]. In ad-
dition, surrogate gradients that approximate
the discontinuous derivative as a continuous
function are used to train SNNs with end-to-
end backpropagation [16, 166, 213]. Recently,
a combination of ANN-to-SNN conversion
and surrogate gradient-based learning was
employed to train deep SNNs for image-
recognition tasks [193, 194]. Additionally, bio- Fig. 5. Mapping a ReLU neuron to IF neuron during
plausible methods that learn from local infor- ANN-to-SNN conversion.
mation present at a synapse are also proposed
for efficient training [165, 202].
ANN-to-SNN conversion: Although SNNs trained with local learning rules are hardware-
friendly and energy-efficient, they suffer from sub-optimal accuracy on challenging datasets [63,
174]; whereas, SNNs trained with conversion frameworks achieve accuracy similar to that of
ANNs [34, 53, 85, 199, 209]. In ANN-to-SNN conversion, first an ANN with ReLU neurons is trained
with state-of-the-art supervised algorithms with some restrictions (no bias, average pooling, no
batch normalization), although some works have shown that some of the restrictions can be re-
laxed [199]. Next, an SNN with IF neurons and iso-architecture as ANN is initialized with the
weights of the trained ANN. The underlying principle of this process is that a ReLU neuron can be
mapped to an IF neuron with minimum conversion loss. The mapping is performed by adjusting
the firing threshold of the IF neuron so its average firing rate is similar to the activation of the
ReLU neuron (Figure 5). The major bottleneck of this method is to determine the firing threshold
of the IF neurons that can balance the accuracy-latency tradeoff. Generally, the threshold is com-
puted as the maximum pre-activation of the IF neuron resulting in high inference accuracy at the
cost of high inference latency (∼1,000 timesteps) [209]. In recent work, the authors showed that in-
stead of using the maximum pre-activation, a certain percentile of the pre-activation distribution
reduces the inference latency (60–80 timesteps) with minimal accuracy drop [132]. Researchers
in References [199, 209] have demonstrated deep SNNs trained with conversion methods on stan-
dard deep learning architectures such as VGG [215], ResNet [79], and Inception [228], exhibit-
ing state-of-the-art performances on complex datasets like ImageNet [200]. A “soft reset” mecha-
nism (Section 2.1) that retains the residual membrane potential at spike-events was proposed to
further reduce the conversion loss in ANN-to-SNN conversion frameworks [77]. Deep architec-
tures with sparse, event-driven computations can potentially yield energy reductions compared
to their ANN counterparts, since the neuron spiking sparsity increases drastically with network
depth [209]. While conversion frameworks establish the effectiveness of spike-based inference and
show as proof-of-concept that SNNs bear comparable computational power as their ANN counter-
parts, it has a major drawback: the absence of the timing information. The quintessential param-
eter “time” is not utilized in the conversion process, which leads to higher inference latency. The
spike-based gradient descent methods, described next, perform credit assignment with backprop-
agation through time (BPTT) and achieve lower inference latency by incorporating temporal
information.
Spike-based backpropagation: ANNs are primarily trained with gradient-descent-based
methods that update the network parameters (weights, biases, etc.) based on the partial derivative
of the loss function with respect to the parameter ( ∂L/∂W ). In SNNs, the spike activation function

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243:12 N. Rathi et al.

of the IF/LIF neuron does not have a continu-

ous derivative. The derivative of the spike func-
tion (Dirac-delta) is not defined at the time of
spike and “0” otherwise. To overcome this is-
sue, surrogate gradients or pseudo-derivatives
(Figure 6) of the spike function are proposed
that approximate the real gradient as a contin-
uous function [16, 166, 213]. Since SNNs com-
pute over multiple timesteps in the forward
pass, the gradients are computed by unrolling
the network in time and performing BPTT.
Several recent works have employed spike-
based gradient-descent learning on SNNs to
perform various classification tasks [16, 96,
119, 120, 123, 155, 165, 166, 254]. SNNs trained
with spike-based gradient-descent can achieve
lower inference latency compared to ANN-to-
SNN converted networks (Figure 7). The pri-
mary reason is the integration of temporal in- Fig. 6. Discontinuous gradient of spike function
formation in training that is lacking in the approximated as a continuous pseudo derivative. x 1
ANN-to-SNN conversion process. Thus, gradi- and x 2 represents the Poisson spike-train of two input
neurons connected with weights w 1,1 and w 1,2 to a LIF
ent descent-based training achieves better la-
neuron, u is the membrane potential, λ is the leak co-
tency but requires more training effort (both efficient, and o is spike output of the LIF neuron. The
computations and memory). A single feed- derivative of the LIF output o with respect to its input
forward pass in ANN corresponds to multiple x is discontinuous and is approximated by a pseudo-
forward passes in SNN that is proportional to derivative to enable credit assignment through
the number of timesteps. Also, the backward backpropagation.
pass requires the gradients to be integrated
over the total number of timesteps, which increases the computation and memory complexity.
The multiple-iteration training effort with exploding memory requirement has limited the appli-
cability of spike-based backpropagation methods to small datasets (such as MNIST and CIFAR10)
on simple few-layered convolutional architectures.
Researchers in Reference [16] showed that damping the surrogate gradient enhanced the per-
formance of gradient descent during larger time spans. Furthermore, Reference [166] provides a
comparative study of employing various surrogate gradients as an approximation for the discon-
tinuous real gradients for performing gradient descent in SNNs.
Hybrid learning: The efficacy of the gradient descent algorithms have thus far been validated
on MNIST [117] and CIFAR datasets [106] for SNNs with few layers. The scalability of the super-
vised algorithms and their ability to achieve training convergence for much deeper SNNs remain
a challenge (since this requires error backpropagation with neurons generating outputs as a
temporal spike sequence). Additionally, the memory requirement for performing gradient descent
in SNNs is higher compared to the conversion frameworks, because the number of computations
linearly increase with time. To address the scalability of gradient descent methods, Reference [194]
proposed a hybrid training mechanism (Figure 8) that solves both the issue of high latency (conver-
sion frameworks) and high training cost (gradient descent in SNN). They first perform an ANN-to-
SNN conversion using the framework from Reference [209] followed by a gradient descent-based
training in SNN with surrogate gradient (Algorithm 1). The conversion framework acts as a good

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Exploring Neuromorphic Computing Based on Spiking Neural Networks 243:13

ALGORITHM 1: Supervised learning in SNNs: ANN-to-SNN conversion, and spike-based

backpropagation
ANN training
Input : Dataset (D), ANN model (Na ), initial weights (Wa )
while stopping criterion not met do
sample mini-batch of input (X ) - target (Y ) pairs from D Ŷ = Na (X ) // Forward propagation
Loss = CrossEntropy(Y , Ŷ )
Wa ← Wa − ϵ ddW Loss // Weight update
a
end
ANN-to-SNN conversion
Input : Trained ANN weights (Wa ), mini-batch input (X ) - target (Y ) pairs from D, SNN model (Ns ),
Timesteps (T )
// Initialize SNN weights with trained ANN weights
Ws ← Wa
V : threshold voltage
// compute the threshold for all layers sequentially
for l in Ns do
for t = 1 to T do
// pre-activation of layer l
Al = Ns (X )
// K is generally chosen between 90–100
if K t h percentile of Al > Vl then
Vl = K t h percentile of Al
end
end
end
Spike-based backpropagation on converted SNN
Input : Dataset (D), Converted SNN (Ns ), SNN weights (Ws )
while stopping criterion not met do
sample mini-batch of input (X ) - target (Y ) pairs from D, U : membrane potential, O: spike output, λ:
membrane leak
for t = 1 to T do
O 0 = X // direct input encoding
for l = 1 to L–1 do
// accumulate the output of previous layer in U , soft reset when spike occurs
Ult = λl Ult −1 + Wsl Olt−1 − Vl Olt −1
// generate spike if U exceeds V
if Ul > Vl then
Ol = 1
end
end
// only accumulation in the final layer
ULt = ULt −1 + Ws L O L−1
t

end
Loss = CrossEntropy(Y , ULT )
Wa ← Wa − ϵ ddW Loss // Weight update
a
V ← V − ϵ d Loss
dV // Threshold update
λ ← λ − ϵ d Loss
d λ // Leak update
end

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243:14 N. Rathi et al.

initialization and the gradient descent con-

verges to a good setting within few epochs.
The inference latency and accuracy on im-
age classification tasks can be improved by
training the leak and threshold along with
the weights of the network [193].
Bio-plausible local learning: Spike-
based gradient methods, described ear-
lier, achieve good accuracy, but the back-
propagation of global loss from output
to input layer results in significant mem-
ory overhead. However, STDP-based un-
supervised learning rules (Section 2.3.1)
Fig. 7. Comparing classification accuracy vs. timesteps
are compute- and memory-efficient but do
for SNNs trained with ANN-to-SNN conversion and
not achieve competitive accuracy. In addi- spike-based backpropagation on VGG9 for CIFAR10
tion, local learning rules are more compat- dataset [120]. For ANN-to-SNN conversion the threshold
ible with event-driven neuromorphic hard- is computed as the maximum pre-activation of that layer.
ware (more on this in Section 4). Thus, The timesteps for ANN-to-SNN conversion can be reduced
researchers have explored gradient-based by setting the threshold as a certain percentile of the pre-
methods that do not require end-to-end activation values [132, 193, 199].
backpropagation and perform weight up-
dates based on local information. Generally, the global error (E) is the function of the output of
the final layer (O L ) and the target (Y )
E = f (O L , Y ). (8)
To update the weights of a hidden layer (Wl ) the gradient is computed as
∂E ∂E ∂Ol ∂Ul
= , (9)
∂Wl ∂Ol ∂Ul ∂Wl
where Ul is the membrane potential. The term ∂E/∂Ol is the backpropagated error and is computed
from all downstream synaptic weights; the other two terms are based on local information. The
works based on bio-plausible local learning eliminate the dependence on this backpropagated term
to perform weight updates. Hebbian three-factor learning rules [66] describe a method to update
parameters locally based on pre-synaptic activity, post-synaptic variables, and neuromodulators. In
the context of SNNs, neuromodulators are replaced with a local error signal [17, 99, 157, 264]. These
learning rules can be implemented in hardware by designing eligibility traces for each synapse [49].
DECOLLE, an SNN equipped with local error functions to perform deep continuous local learning,
is one such example [99]. A random readout layer is attached to each layer of the network, and an
auxiliary cost function is defined over the readout. The random readout is obtained by multiplying
the activations with a random and fixed matrix. Instead of minimizing a global objective function,
the training process minimizes many local cost functions [157]. The weight update in each layer
depends only on the information available locally, and thus all layers in the network can be trained
in parallel.

2.4 Recurrent Networks

In feedforward networks, discussed earlier, a neuron is always connected to a different neuron
and does not have any self-connection or loops. Additionally, there are no connections between
neurons in the same layer; the neurons in one layer are connected to the neurons in other layers. In

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Exploring Neuromorphic Computing Based on Spiking Neural Networks 243:15

ALGORITHM 2: Training in Spike-FlowNet (adapted from Reference [118])

Input: Spike inputs (inputs), #spike-frames in former/latter groups (N ), #SNN layers (L S ),
#ANN layers (L A ), SNN/ANN output (o/o A ), neuronal membrane potential (V ), neuronal
firing threshold (Vt h ), ANN non-linear activation (h)
Initialize: V l [n] = 0, ∀l = 1, . . . , L S
// Forward-pass in SNN-block
for n ← 1 to N do
o 1 [n] = inputs[n]
for l ← 2 to L S − 1 do
// weighted spike-inputs are integrated into V
V l [n] = V l [n − 1] + w l ol −1 [n]
// check if V exceeds Vt h
if V l [n] > Vt h then
// emit a spike and reset V
ol [n] = 1
V l [n] = 0
// accumulate output at the final SNN layer
oALS
= V LS [n] = V LS [n − 1] + w LS o LS −1 [n]
// Forward-pass in ANN-block
for l ← L S + 1 to L S + L A do
olA = h(w l olA−1 )
// Compute loss: photometric + smoothness
L = photo(o A(LS +LA ) ) + smooth(o A(LS +LA ) )
// Backward-pass in ANN-blocks
for l ← L S + L A to L S do
∂ L ∂o A
l
Δw l = l ∂w l
∂o A
// Backward-pass in SNN-blocks
for n ← N to 1 do
for l ← L S − 1 to 1 do
// evaluate partial derivatives of loss w.r.t. w S by unrolling the SNN over time
∂o l [n] ∂V l [n]
Δw l [n] = ∂o∂lL[n] ∂V l [n] ∂w l [n]

contrast, recurrent networks have feedback connections where the output of the neuron is routed
back as input with a time delay. Hence, the output is a function of current input and the previous
state of the neuron. SNNs implicitly have this relation, as the membrane potential depends on
the input and the potential at previous timestep (Equation (2)). Thus, SNNs have implicit recur-
rence through its internal state [166, 252], as shown in Figure 9. Note, however, in this section, we
discuss recurrent networks of spiking neurons (RSNNs) that have explicit recurrent connec-
tions on top of the intrinsic recurrent dynamics. In ANNs, recurrent connections are particularly
important to learn and generate sequences with long-range structure such as text, video, or au-
dio data. RNNs contain feedback loops in their connectivity structure, which allows the network
to remember prior computations or history of the input [57, 116, 179, 227]. The computation in
RNNs occur by unrolling the network over discrete timesteps. Once unrolled, RNNs can be viewed
as deep feedforward networks with shared weights capable of establishing long-range temporal

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243:16 N. Rathi et al.

Fig. 8. Hybrid learning algorithm combining ANN-to-SNN conversion and spike-based backpropaga-
tion [194]. A trained ANN is converted to SNN by replacing ReLU neurons with IF neurons and threshold
balancing, where the threshold for each layer is determined sequentially. The converted SNN is incrementally
trained for few epochs (∼20) with spike-based gradient backpropagation to reduce the inference latency. The
trained SNN demonstrates better accuracy as well as lower inference latency (100–200 timesteps) on image
classification tasks. The inference latency can be reduced (5–10 timesteps) by replacing the Poisson spike
generator with an encoding layer that accepts analog values and outputs spike-trains [193].

dependencies. However, training RNNs has proven to be very difficult than their deep feedforward
counterparts due to exploding or vanishing gradients that deteriorate the overall learning [20, 81].
Today, Recurrent Neural Networks (RNNs), specifically Long Short-term Memory (LSTM)
networks [82], are widely used to process sequential inputs such as language or speech.
The biological brain is known to be composed of a network of several millions of neurons con-
nected via billions of recurrent synaptic links. These neuronal links are not randomly determined
but are optimized for specific tasks and have developed through long-term evolution. RSNNs at-
tempt to realize this neuronal model of the brain. This includes exploring connectivity in the model
as well as learning the synaptic weights. RSNNs aim to offer high energy-efficiency compared to
RNNs due to the computations being sparse and discrete in nature in the form of spikes. However,
the research in this field has been highly limited due to the challenges associated with training.
RSNNs generally have sub-optimal performance compared to equivalently trained RNNs, thereby
limiting their application to only simplistic tasks.
Research on developing algorithms to enable bio-plausible learning in RSNNs has been an open
problem for quite a few years with little success. There have been several works over the past
years that aim to train RSNN models in a bio-plausible manner [7, 71, 148, 235]. These aim at
learning the non-linear dynamics of RSNNs through feedback-based local learning rules. Authors

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Exploring Neuromorphic Computing Based on Spiking Neural Networks 243:17

Fig. 9. Implicit recurrence in SNNs is similar to the recurrence relation in traditional RNNs. In RNNs, the
hidden state h(t ) retains the history of all previous inputs through explicit feedback connections, whereas,
in SNNs, the equivalent membrane potential V (t ) acts as a memory of past inputs. The output in RNNs is
a non-linear function of the hidden state, and in SNNs, the neurons fire based on their membrane potential.
Note, however, the inputs and outputs in SNNs are binary, whereas, in RNNs, they are continuous values.

in Reference [71] present FOLLOW (Feedback-based Online Local Learning Of Weights), a

local-learning algorithm in which the weights changes depend on the presynaptic activity and
the projected error on the postsynaptic neuron. Reference [235] proposes to incorporate a third
factor of local dendritic potential besides pre- and postsynaptic activity to modulated plasiticity.
They utilize a functional rule seeking to minimize the descrepancies between somatic firings and
the local dendritic potential. However, Reference [148] introduces a learning method called Deep
Feedback Control (DFC), which uses a feedback controller to drive a neural network towards a
desired target output while its control signal is used for credit assignment. Researchers in Refer-
ence [51] explore using appropriate “firing-rate” models to train RSNNs for generating complex
temporal outputs by utilizing continuous-variable networks to identify training targets. In addi-
tion, authors in References [100, 149, 150] explore event-based solutions related to neuro-circuit
design for visual-motion perception and scene understanding.
In contrast to surrogate gradient-based BPTT, authors in Reference [18] propose “e-prop,” a
biologically realistic method based on minimizing a spike-dependent loss function (E) that mea-
sures the difference between the actual neuron output and a target output. It is shown that the
loss-derivative with respect to the synaptic weights can be represented as the sum of products
over the timesteps of RSNN computation with the help of a suitable pseudo-derivative offering
an adequately powerful function to enable learning in RSNN models. The results show that “e-
prop” can learn nearly as well as BPTT-based methods for tasks such as phenome recognition and
reinforcement learning on Atari games compared with A3C [152] algorithm.
2.4.1 Spiking LSTMs. Like traditional LSTMs, spiking LSTM, too, finds applications in sequence
modelling tasks such as natural language and speech processing, time-series predictions, and so
on. However, training these spiking LSTMs again suffers drawbacks associated with SNNs, as dis-
cussed previously. To mitigate these and enable training, ingenious methods need to be developed.
Authors in Reference [131] explore approximate loss functions to compute gradients and enable
backpropagation through time (BPTT) in spiking LSTMs. They evaluate the performance on
sequential versions of MNIST [117] and extended MNIST datasets while providing comparison
with other feedforward SNNs. The authors in Reference [182], however, propose a hybrid analog

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243:18 N. Rathi et al.

Fig. 10. Algorithmic and architectural optimization approaches for improving learning in liquid state ma-
chines (LSMs). (a) Vanilla LSM taking spike stream corresponding to each pixel in the image frame as input
and predicting outputs at the readout layer trained using backpropagation. (b) Learning alternate liquid
connections [175] to improve performance. Fast connections (having a high decay rate) are fixed, while the
slow connections (having a low decay rate) are learned using STDP-based local learning rules. (c) Ensem-
ble of smaller liquids with local classifiers followed by a global classifier for predicting final output leading
to better performance at smaller overall liquid size [220]. (d) Deep Hierarchical LSM with attention modu-
lated readout. Each hidden reservoir captures different sets of features that are selectively analyzed at the
attention layer [219].

and spiking LSTM where the compute-intensive parts of LSTM are converted to SNN for better
energy-efficiency on edge devices. The results showcase significantly lower energy consumption
while having a negligible drop in performance for sequential image classification on MNIST [117]
dataset and sequence-to-sequence translation on the IWSLT14 [36] dataset.

2.4.2 Liquid State Machines. Liquid state machines (LSM) have been explored as lightweight
architectures to handle spatio-temporal inputs in a bio-plausible manner [134, 136]. LSM is an
RSNN consisting of a sparsely connected reservoir (liquid) of excitatory and inhibitory spiking neu-
rons. The synaptic connections and their weights are randomly initialized and fixed a priori. This
leads to a simplistic lightweight structure while still inherently capturing the spatio-temporal input
information. The liquid essentially projects the inputs to a higher dimensional space while also re-
taining temporal information through recurrent connections. Given a large enough reservoir with
random and sparse interconnects, the high-dimensional representation generated can be linearly
classified using a fully connected readout layer. The work by Maass and Markram in 2004 [135]
investigates on the computational power of LSMs for real-time computing. Figure 10(a) shows a
vanilla LSM consisting of a reservoir of spiking neurons (excitatory and inhibitory) with random
connections. Several works have successfully employed LSMs for a variety of applications ranging
from gesture recognition [175], video activity recognition [219], reinforcement learning [124, 183],

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Exploring Neuromorphic Computing Based on Spiking Neural Networks 243:19

and so on, with low compute costs. The major challenge with LSM lies in its inability to scale well
for real-life complex computing tasks without drastically increasing the reservoir size. Various ef-
forts have been made towards improving the learning capability of LSMs without increasing their
size significantly. One approach involves exploring mechanisms for training the liquid connections
to improve application accuracy at the cost of added complexity. Authors in Reference [258] ex-
plore using heterogeneous neurons with different behaviors and degree of excitability in the liquid
to aid learning. Reference [175] employs a Driven/Autonomous model approach [2] coupled with
Recursive Least Squares (RLS) rule and FORCE training [167] to train the liquid connections.
This approach consists of two different types of synaptic connections, namely, fixed fast connec-
tions (τf ast ) and learnable slow connections (τslow = 10 ∗ τf ast . This is shown in Figure 10(b).
Other efforts focus on optimizing the network architecture itself. Authors in Reference [220] pro-
pose to adopt a “divide and learn” strategy by utilizing multiple small liquids, each learning charac-
teristic patterns corresponding to a segment of input patterns. In addition, the input-to-ensemble
connections are trained using STDP-based learning rules. The intermediate outputs from the en-
semble of liquids are combined using a global classifier to generate the final output. This approach
is shown in Figure 10(c). However, authors in Reference [219] propose an architecture involving
multiple layers of liquids to form a deep hierarchical LSM. The hidden layers (liquids) are con-
nected using spiking winner-take-all encoders that extract and propagate the temporal features.
The representations generated by the different hidden layers (liquids) are condensed using an at-
tention function before final classification at the readout. Figure 10(d) demonstrates this method.
These approaches offer competitive accuracy and faster training time compared to a large single
liquid. Similar to these, Reference [162] presents an efficient partitioning method for hierarchical
mapping of large SNNs on reconfigurable neuromorphic hardware.
Recurrent networks of spiking neurons in the form of spiking LSTMs and LSMs thus show
promise for realizing energy-efficient implementations for real-world applications on resource-
constrained edge-devices. However, advancement in this field is not well paced when compared
to ANNs due to their limited learning ability.

2.5 Neuromorphic APIs and Libraries

Neuromorphic systems involving different spiking neuron models and architectures demand a par-
adigm shift in the standard softwares and libraries that are originally optimized for ANNs, such as
Pytorch, Tensorflow, Caffe, and so on. This is due to the fact that the asynchronous event-driven
processing required by SNN architectures can not be directly realized using the above software
APIs on traditional Graphical Processing Units (GPUs). This not only requires a complete re-
work at the hardware end to develop neuromorphic hardware such as Intel’s Loihi [46], IBM’s
TrueNorth [6], SpiNNaker [171], and so on, as will be discussed in more detail in Section 4, but
also requires developing specialized software that can handle these event-driven computations.
Towards this direction, Intel with the introduction of its new and updated Loihi-2 also unveiled its
LAVA software framework [45]. LAVA addresses the need for a common neuromorphic software
framework allowing researchers and developers to utilize a common set of tools, methods, and li-
braries and run neural network models seamlessly on heterogeneous architectures across conven-
tional and neuromorphic hardware. In addition, it enables development of applications without
accessing specialized neuromprphic hardware. The kind of applications targeted by these neuro-
morphic systems are discussed next.

3 APPLICATIONS
SNNs are well suited to process both static as well as sequential data due to their inherent recur-
rence. Also, SNNs can naturally process discrete spatiotemporal data from event sensors. In this

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243:20 N. Rathi et al.
Table 1. Performance of SNNs on Different Image-recognition Datasets
Paper Neuron model Input coding Learning rule Network architecture Accuracy Timesteps
MNIST
[52] LIF Rate STDP 2 FC 95% 700
[156] IF Temporal Backprop 784FC-600FC-10FC 96.98% 167
[222] LIF Rate Stochastic STDP 36C3-2P-128FC-10FC 66.23%% 100
[268] LIF Encoding layer Backprop 15C5-P2-40C5-P2-300FC 99.53% 5
[267] IF Temporal ANN-to-SNN 32C5-P2-64C5-P2-1024FC-10FC 99.41% 8
[198] IF Temporal ANN-to-SNN LeNet-5 98.53% -
CIFAR10
[76] IF Temporal ANN-to-SNN VGG16 93.63% 2,048
[209] IF Rate ANN-to-SNN VGG16 91.55% 1,000
[199] IF Rate ANN-to-SNN 4 Conv, 2 FC 90.85% 400
[194] LIF Rate Hybrid VGG16 92.02% 200
[120] LIF Rate Backprop VGG9 90.45% 100
[222] LIF Rate Stochastic STDP 256C3-2P-1024FC-10FC 98.54% 100
[255] LIF Encoding layer Backprop CIFARNet 90.53% 12
[268] LIF Encoding layer Backprop CIFARNet 91.41% 5
[193] LIF Encoding layer Hybrid VGG16 92.70% 5
ImageNet
[76] IF Temporal ANN-to-SNN VGG16 73.46% 2,560
[77] IF Rate ANN-SNN VGG16 71.34% 768
[199] IF Rate ANN-SNN VGG16 49.61% 400
[209] IF Rate ANN-SNN VGG16 69.96% 300
[194] LIF Rate Hybrid VGG16 65.19% 250
[132] IF Encoding layer ANN-SNN VGG15 66.56% 64
[193] LIF Encoding layer Hybrid VGG16 69.00% 5
NMNIST
[123] LIF Event sensor Backprop 2 FC 98.74% 350 ms
[254] LIF Event sensor Backprop 3 FC 98.78% 300 ms
[213] SRM Event sensor Backprop 12C5-2P-64C5-2P-10FC 99.20% 300 ms
[96] SRM Event sensor Backprop 2 FC 98.88% 0.6 ms
DVS CIFAR10
[108] IF Event sensor ANN-to-SNN 4 Conv, 2 FC 65.61% 60
[255] LIF Event sensor Backprop 128C3-2P-128C3-256C3-2P-1024FC 60.5% 5
[253] IF Event sensor Backprop VGG7 62.5% 5

section, we discuss the application of SNNs in image classification, gesture recognition, sentiment
analysis, biomedical applications, and motion estimation. Additionally, we review the relevance of
SNNs as a defense mechanism against adversarial attacks.

3.1 Image Classification

Table 1 compares the performance of various SNN models on image classification tasks from
frame-based image datasets (MNIST [117], CIFAR10 [106], ImageNet [50]) as well as neuromor-
phic datasets (N-MNIST [170], CIFAR10-DVS [127]). The pixel-based images are converted to
spike-train based on the encoding methods discussed in Section 2.2. The learning algorithm is
among the variants described in Section 2.3. In SNNs, the challenge is to achieve competitive
accuracy with the minimum number of timesteps for better energy-efficiency. To that effect, net-
works employing pixel values directly as input and training with gradient-based backpropagation
methods achieve the best overall performance. Neuromorphic-MNIST (N-MNIST) [170] and
CIFAR10-DVS [127] are the spiking versions of the MNIST and CIFAR10 dataset, respectively,
recorded with a dynamic vision sensor.

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3.2 Gesture Recognition and Sentiment Analysis

Sequential classification tasks have inputs that have some temporal dependence between them.
Thus, they require models that can keep this dependence into account when generating predictions.
The ability of SNNs to inherently capture temporal information makes them directly compatible
with such temporal inputs and suitable for sequence classification tasks. Works such as References
[10, 213, 256] explore gesture recognition using deep SNNs on the IBM DVS gesture dataset [10].
Their results show that SNNs demonstrate comparable performance to corresponding state-of-
the-art ANN implementations. Reference [213] also performs audio classification on the TIDIGITS
dataset [125]. However, Reference [4] performs the task of sentiment analysis on movies reviews
from the IMDB dataset. This implementation shows that the neuronal membrane potential tracks
the positive/negative nature of the sentiment as the review is presented to the SNN as a sequence.

3.3 Bio-medical Applications

Real-world biological signals and patterns are generally time-varying signals, which are a natu-
ral fit for SNN-based processing. To that effect, researchers have proposed several solutions for
analyzing and classifying these biological patterns. These include works analyzing and decod-
ing signals such as Electroencephalogram (EEG) [54, 105, 109, 168, 229], Electrocardiogram
(ECG) [259, 261], Electromyography (EMG) [55, 68], and so on. In addition, authors in Refer-
ences [30, 67, 275] show that high frequency oscillations (HFO) generated by the epileptogenic
tissue in Electrocorticography (ECoG) recordings can also be efficiently processed and analyzed
using SNNs.

3.4 Motion Estimation

The emergence of event-based sensors, as discussed previously (Section 2.2.4), have induced
promising opportunities for SNNs owing to inherent input compatibility. Edge-devices such as
small ground and flying robots incur huge benefits from event-based processing in terms of per-
ception and planning tasks. Authors in Reference [44] demonstrate the importance of using event
cameras to efficiently accomplish tasks such as obstacle detection and avoidance while moving at
high speeds as well as awareness-based sensing of the environment. While there have been works
that utilize ANNs along with event-cameras for such tasks [270], they are inefficient in retaining
the rich temporal information held by the events. In contrast, SNNs show inherent compatibility
by naturally capturing the temporal nature of event camera data. Authors in Reference [169]
demonstrate visual motion estimation using SNNs by accounting for synaptic delays when
generating motion-sensitive receptive fields. Reference [75] presented real-time model-based
optical flow estimation on IBM’s TrueNorth [6] for simple patterns of rotating spirals and pipes. In
addition, authors in Reference [177] carried out optical flow estimation using convolutional SNNs
trained using STDP-based learning. The main limitations of these works involve the usage of
small-scale learning that does not scale well for dynamic and complex inputs. Training deep SNNs
using end-to-end backpropagation brings forward new challenges. Deep SNNs suffer from the
“spike vanishing” phenomenon, where the number of spikes propagating to the later layers reduce
drastically, hindering learning and leading to poor performance. To that effect, a hybrid SNN-ANN
architecture, where the SNN layers enable effortless handling of event data while the ANN layers
enable end-to-end learning along with maintaining application performance, seems to be a promis-
ing alternative. Authors in Spike-FlowNet [118] utilize such a deep encoder-decoder architecture
based on the U-Net [196] model for optical flow estimation on the Multi-Vehicle Stereo Event
Camera (MVSEC) [271] dataset. This dataset consists of various sequences (indoor _f lyinд1/2/3,
outdoor _day1/2) recorded using a stereo pair of event cameras. The model is trained end-to-end

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243:22 N. Rathi et al.

Fig. 11. (a) Input Event Representation. (Top) Continuous raw events and discrete grayscale images from
a DAVIS camera. (Bottom) Accumulated event frames between two consecutive grayscale images to form
the former and latter event groups. (b) Spike-FlowNet Architecture [118]. The 4-channeled input images,
as groups of former and latter events, are sequentially passed through the hybrid network. The SNN-block
contains the encoder layers of the network, while the ANN-block contains the residual and decoder layers.
The loss is evaluated after forward-propagating all consecutive input event frames within the time window.
(c) The predicted optical flow compared with the provided ground truth and EV-FlowNet [270].

using surrogate gradient-based Backpropagation through-time (BPTT), as highlighted in

Algorithm 2. Figure 11 highlights the input representation, hybrid SNN-ANN architecture and
qualitative results, while Table 2 compares the Average Endpoint Error (AEE) with the state-of-
the-art ANN implementation Ev-Flownet [270]. Usage of SNNs lead to lower energy consumption
due to the accumulate (AC) operations in SNNs compared to multiply-accumulate (MAC) op-
erations in ANNs. These works establish SNNs as prime candidates for real-world perception and
planning tasks, making SNN and event-camera-based computer vision an active area of research.
However, there are traditional computer vision-based works that are again, highly efficient for
small-scale inputs but do not offer similar performance or scale well to larger inputs. One such
recent work is Reference [142], where the authors propose to estimate optical flow by modelling
the temporal events from an event-sensor as a three-dimensional probability distribution param-
eterized by the pixel address and timestamp. The Fisher-Rao matrix for each parameter value
is used to compute the optical flow given by the eigen vector corresponding to the least eigen
value. This work demonstrates respectable performance compared to Ev-FlowNet [270] and Spike-
Flownet [118], as shown in Table 2. These suggest that learning-based methods inspired by fun-
damental concepts from the field of traditional computer vision seem to hold a lot of potential
towards realizing high-performance perception and planning while maintaining efficiency.

3.5 Adversarial Robustness

Several machine learning models, including neural networks, are vulnerable to adversarial at-
tacks [110]. An adversarial example is an input sample perturbed with carefully crafted noise to

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Exploring Neuromorphic Computing Based on Spiking Neural Networks 243:23
Table 2. Average Endpoint Error (AEE) Comparisons between EV-FlowNet [270], Spike-FlowNet [118], and
Fisher-Rao Metric-based Method [142] on the MVSEC Dataset
dt=1 frame dt=4 frame
indoor1 indoor2 indoor3 outdoor1 indoor1 indoor2 indoor3 outdoor1
EV-FlowNet [270] 1.03 1.72 1.53 0.49 2.25 4.05 3.45 1.23
Spike-FlowNet [118] 0.84 1.28 1.11 0.49 2.24 3.83 3.18 1.09
Fisher-Rao Metric [142] 1.88 - - - 2.95 - - -
Lower is better.

cause the neural network to misclassify the input sample. The modified samples are subtle and
undetectable by a human observer. Such systems can seriously undermine the security of neural
networks for mission-critical applications. For example, a slightly modified image of the “Stop sign”
is classified as a speed limit sign [60]. The defense mechanisms include activation pruning, input
discretization, and non-linear transfer functions. SNNs inherently possess most of these features
and are better suitable to handle adversarial attacks [14, 212]. The input to SNNs is binary, the dy-
namics of the LIF neuron are non-linear, and the activations are sparse. Also, SNNs can exploit the
time and leak parameter to improve the resiliency of the network. The authors in Reference [212]
showed that SNN trained with spike-based backpropagation, employing LIF neurons, and lower
number of timesteps perform better under adversarial attack compared to ANN as well as ANN-to-
SNN-converted networks that generally use IF neuron and require a larger number of timesteps.
The authors in Reference [14] studied the robustness of SNNs under different input coding meth-
ods with random and adversarial perturbations. Networks trained with rate coding performed
better compared to temporally coded network. The reason may be the particular form of temporal
coding, first-to-spike, which allows only one spike per neuron, thereby reducing redundancy. To
generate an adversarial sample, the gradient of the loss with respect to input is added to the input.
In SNNs, the gradient is continuous, whereas the input is binary. The authors in Reference [128]
proposed a method to convert continuous gradient to spike-compatible ternary gradients with
probabilistic sampling. Adversarial robustness is an active area of research, and SNNs with their
unique properties can potentially provide a low-power defense mechanism.

4 NEUROMORPHIC HARDWARE
We have described how neuromorphic computing presents a novel paradigm with diverse neuronal
functionalities as well as synaptic learning algorithms. In this section, we delve into the design of
neuromorphic hardware [41, 231] that can faithfully emulate the algorithmic functionalities and
leverage the inherent computational efficiency offered by SNNs.

4.1 Motivation for Neuromorphic Hardware Design

Neuromorphic hardware design was initially inspired by building electronic equivalent of the hu-
man brain to mimic its computational capabilities [143]. This was demonstrated by Mahowald and
Douglas in 1991 [139] with an analog integrated circuit for silicon neuron followed by a silicon
retina for stereoscopic vision [137].
Over the recent years, growing interest in artificial intelligence and machine learning systems
has led to domain-specific acceleration of such workloads in systems such as GPUs, TPUs, and so
on, due to the data-intensive nature of the workloads. However, designing efficient neuromorphic
hardware presents further challenges that need to be addressed. Neuromorphic computing work-
loads such as SNNs are inherently temporal in nature, i.e., it evaluates the neural network model
over a number of timesteps. Furthermore, due to the time-dependent processing of the spiking
neurons, there exists little to no temporal parallelism that can be exploited without breaking the
pipeline of the processing. Thus, the data-level parallelism is confined within a single timestep of

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243:24 N. Rathi et al.

processing, which of course can be leveraged through GPU or TPU acceleration. However, SNN
workloads tend to show event-driven characteristics, i.e., the neurons process data asynchronously,
leading to considerable sparsity in its activations at a given time. Moreover, spiking activity of the
neurons can diminish in deeper layers in a deep SNN. Hardware systems such as GPUs and TPUs
are designed to efficiently leverage data-parallelism, but they fail to exploit the high temporal spar-
sity as well as spatial sparsity of activations in SNNs. Additionally, SNNs have memory-intensive
data-structures such as membrane potential that need to be processed across timesteps, an over-
head that is not entirely mitigated by today’s digital accelerators. There have been some proposals
on using analog capacitors as memory elements in neurons [89] for “state-ful” processing, which
could serve as a good design choice for mixed-signal SNN accelerators. Finally, the training algo-
rithms of SNNs could involve both global as well as local weight updates across time, as described
in Section 2, which can introduce further bottlenecks in efficient execution of such operations.
Considering the limitations of hardware systems designed to accelerate machine learning work-
loads, researchers have explored several avenues [6, 11, 21, 31, 46, 89, 208, 231, 262] across the
design stack from devices and circuits to architectural solutions to address the unique challenges
presented by neuromorphic computing workloads such as SNNs. In the next subsection, we will
discuss how intelligent design of basic compute primitives forms the platform for acceleration of
SNN workloads.

4.2 Neuromorphic Architecture

The key facets of designing Neuromorphic architectures involve techniques that effectively utilize
the temporal and spatial activation sparsity in SNNs, as well as optimize the basic computing ar-
chitecture, such as building efficient functional primitives and coordinating the communication of
various data-structures. The first challenge can be tackled through sparsity-driven optimizations,
which include conditional activation of memory and processing units along with asynchronous
communication [6, 46].

4.2.1 Sparsity-driven Solutions – Asynchronous Systems. We have discussed in Section 2 how

SNNs have abundant temporal and spatial sparsity in neuron activity. One common way to lever-
age such sparsity is to use hierarchical mesh architecture and asynchronous communication as
adopted by various researchers [6, 46, 154]. An example mesh operation, implemented in the Loihi
chip, is shown in Figure 12(a). It is a fully asynchronous many-core chip where each core has its
own sense of frequency and timing. Interaction between cores is also asynchronous, and not timed,
and the operation of one neuron in the system is entirely independent of another. The operation
of a core in the system commences at a local time t, and through iteration of the neuron com-
partments in each core, firing events are monitored. In the event of firing, the network-on-chip
(NOC) broadcasts a spike message to only the cores that contain the synaptic fan-out of the firing
core. Once the slowest core finishes processing, a synchronization mechanism between neighbor-
ing cores ensures that all spikes are safely delivered and received before proceeding to timestep
t +1. A unique property of Loihi is that it deploys an entirely asynchronous system where different
modes of operation within the core microarchitecture can operate at different frequencies, in addi-
tion to the event-driven communication system through the mesh network. The authors suggest
that this local dataflow control suffices the necessity of varying workload-dependent timescales
for spiking neuron processes as well as facilitates back-end timing closure.
An alternative way of realizing asynchronous systems is adopted by T rueNorth, where the com-
puting cores are synchronous in nature, whereas the communication protocol between the cores
through the NOC routers is asynchronous. This ensures that all cores operate in parallel and an
asynchronous control circuitry enables only the cores in case of a need for synaptic integration and

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Exploring Neuromorphic Computing Based on Spiking Neural Networks 243:25

Fig. 12. (a) Mesh architecture adopted in Loihi for transmitting spikes across various neurons [46], (b) Multi-
core implementation of neuromorphic processors connected to a common router [171] and (c) Near-memory
processing architecture with a 2-D array of processing elements, with each PE consisting of internal storage
for neuronal functionalities as well as computing elements for synaptic computations [5].

membrane potential update. The local synchronous digital circuit design facilitates low complexity
design for complex neuron functionality.
Some extensions of mesh-based architectures involved hierarchical mixed-mode routing sys-
tems where various distinct levels of routers are deployed. For example, in Reference [154], three
levels of routers are deployed: one responsible for local traffic, a second responsible for non-local
events for nearby cores, whereas a third level router is responsible for long-distance communica-
tion. This chip, also knows as DYNAPs, demonstrates the efficacy of the novel digital communica-
tion scheme along with emulation of neuro-synaptic functionalities on CMOS analog circuits.
Event-driven systems can also be incorporated using 2-D processing arrays connected to a com-
mon packet router, as adopted by the SpiNNaker Project [171], shown in Figure 12(b). Events are
communicated by maintaining routing tables for event sources. The processing elements simply
emit a spiking event in form of a packet with the address of the spiking neuron and the router
communicates the packets to any of the other processing cores where the selected routes are de-
termined by the routing table.
In addition to the aforementioned approaches to building large-scale neuromorphic systems, re-
searchers have explored scalable implementations that faithfully realize complex neuronal and
synaptic functions using analog circuits. For example, the BrainScaleS system [203] performs
wafer-scale integration of multiple instances of the HICANN ASIC, which implements the Adap-
tive Exponential Integrate-and-Fire Model using analog circuit along with synapses capable of
performing STDP-based learning. Neurogrid [21] is a mixed-signal large-scale system to perform
brain simulations and visualization. It used a combination of highly bio-plausible neural and synap-
tic sub-threshold analog circuits with detailed modeling of soma, dendritic trees, axons, and so
on. Multiple cores communicate with each other using digital Address Event Representation
(AER) protocol. The basic skeleton of neuromorphic systems with AER architecture containing
an Integrate-and-Fire Array Transceiver (IFAT), a look-up table (LUT) to store synaptic

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Fig. 13. (a) RESPARC as a pool of NeuroCells (b) Macro Processing Engine - The mPE receives input spikes
over the bus and the switch network, which is processed by the crossbars to produce output currents: C1, C2,
C3, C4. The crossbar currents get integrated into the neurons to produce output spikes that are then sent to
the target neurons over the network.

connections, and AER protocol for communication between neurons is also used as a popular
approach. Variants of IFAT systems have been explored using different kinds of neuronal cir-
cuits [239, 240]. A reconfigurable mixed-signal design called ROLLS, targeting both emulation
of complex neuronal and synaptic learning functionalities, and image classification tasks, have
been proposed [187]. Although this design derives motivation from various previous designs, it
performs a holistic integration and performs complex tasks in a fully on-chip format.
Large-scale reconfigurable systems [244] have been explored to overcome the Liebig’s law for
neuromorphic hardware, where the performance can be limited by the component with short-
est supply. Such reconfigurable systems consist of arrays of identical components, which can be
configured as LIF neurons, a learning synapse with STDP-based rules, as well as an axon with
trainable delay. Efficacy of such a system has been prototyped using a field programmable gate
array (FPGA)-based design and later demonstrated on Silicon.
4.2.2 Efficient Computing Architectures. However, researchers have also explored tiled architec-
tures to reduce data movements over the network. SPARE [5] and RESPARC [11] are examples of
tiled architectures built with CMOS and post-CMOS primitives, respectively, that achieve signifi-
cant improvements in efficiency for SNN execution. As shown in Figure 12(c) Each tile in SPARE is
composed of ROM-Embedded RAM-based arrays, where RAM stores the weights for a small par-
tition of the SNN, and ROM stores lookup tables for executing transcendental operations that can
perform complex neuron functions. During an SNN execution, each tile performs multiply-and-
accumulate and transcendental operations on its portion of weight data (weights remain station-
ary), thereby enabling near-memory computing. Typical SNN execution on SPARE is performed
in a time-multiplexed manner, where each layer is mapped on the tiled architecture, one at a time.
The currently mapped layer computes its outputs before the next layer is mapped.
RESPARC further extends the tiled architecture by leveraging the high storage density of hlmem-
ristive crossbars to enable large number of on-chip tiles. However, expensive crossbar writes limit
the applicability of a time-multiplexed architecture, where the crossbars are reused across layers by
re-programming weight matrices and executing the corresponding dot-product operations. Con-
sequently, a spatial architecture where the weight data of an entire SNN are pinned to crossbars
located across multiple tiles is more efficient, as it leverages the benefits of high storage density
while alleviating the costly writes. Figure 13 illustrates a tiled architecture built with post-CMOS

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Exploring Neuromorphic Computing Based on Spiking Neural Networks 243:27

primitives (memristive crossbars). It is worth noting that while such a spatial architecture is ef-
fective for SNN inference, it may still suffer from costly writes in SNN training where weight
data is updated frequently. Recent explorations on hybrid ANN-SNN architectures by partitioning
the network into non-spiking and spiking counterparts have also shown promise to mitigate the
algorithmic inference latency disadvantage of SNNs [216].
Alternatively, an SNN accelerator such as Spinal − Flow [163] has explored techniques to tackle
the iterative memory access overhead over multiple timesteps for updating membrane potential
and weight read. They propose a novel dataflow that leverages the temporal re-use patterns in
SNN workloads. By creating a compact sorted list of spikes, Spinal − Flow sequentially walks
through the spikes of all timesteps in a layer to yield significant speedups due to activation sparsity.
The architecture uses an output stationary dataflow to map neurons to the processing elements
across all timesteps. This allows the membrane potential to accumulate for an input across all the
timesteps in a layer, before proceeding to next layer, thereby eliminating additional storage and
data-movement costs for the membrane potential data-structure. Such a dataflow maximizes re-
use of membrane potential, in contrast to dataflows followed in ANN accelerators, which aim to
maximize re-use of data-structures such as inputs, weights, and outputs.

4.3 Asynchronous Communication

The communication between different neurons in a large-scale neuromorphic chip requires
high speed, time-multiplexed asynchronous circuits. Typically, such circuits are serviced by a
transceiver to read and write spikes in parallel and an on-chip router for transmission of neu-
ronal events or spike. The most commonly used asynchronous communication protocol is address-
event representation (AER) [27, 137]. The signals in the AER protocol carry analog information
in form of “inter-spike intervals” using the digital medium, where addresses of the nodes responsi-
ble for events are represented in binary. In the most primitive case, a look-up table with source and
destination pairs of addresses is maintained to determine connectivity between different nodes.
The primary obstacle of interconnected SNN hardware implementation is the high memory
requirement for the look-up table that stores the network connectivity information. To accommo-
date arbitrary connectivity among n neurons, the routing table requires O (n) entries, which can
be mostly redundant. Instead, if the neurons, have preferential connectivity to local neighboring
neurons, then routing protocols can be designed to trade off network configuration flexibility with
routing memory. To that effect, multi-stage [153] and hierarchical [35] routing schemes have been
explored to reduce memory requirements for implementing reconfigurable large-scale SNNs.
In addition to routing schemes, asynchronous communication in large-scale neuromorphic sys-
tems also require efficient on-chip routers. Typically, on-chip routers for neuromorphic systems
need to have unique features such as low latency multi-cast routing to support high connectivity.
Researchers have proposed tree-based routers [147] which uses recursive branching to broadcast
packets to corresponding subtrees. By reducing the number of nodes to navigate, this approach
reduces memory look-ups and also the size of the header of the data packets.
The delays in aforementioned asynchronous communication systems become critical since neu-
romorphic systems use accelerated timescales where circuits operate much faster than biological
systems. The latency and performance of any AER-based neuromorphic system is hence funda-
mentally limited by communication latency as well as its memory requirements.

4.4 CMOS-based Neuromorphic Compute Primitives

The computing primitives for efficient neuromorphic systems have two design facets: (a) imple-
menting complex neuronal [90] and synaptic learning functionalities [15] and (b) deploying low-
power synaptic integration functions. We first describe how these design facets are realized in

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243:28 N. Rathi et al.

Fig. 14. Illustration of CMOS-based neuronal circuits. (a) Circuit shows basic comparison and firing behavior
of an IF neuron [87] (b) Circuit shows more complex functionalities of an IF neuron, such as spike frequency
adaptation, leak as well as refractory period [236].

CMOS technology, which has been a popular thrust of research in neuromorphic circuit design.
Next, we will delineate how novel memory technologies can be effectively used to accelerate the
aforementioned computation and realize the basic processing units in a compact fashion.
4.4.1 Neuronal Circuits. The classical case of representing neuronal circuits on silicon was
based on equivalence between ion transportation in biological neurons and electron transport in
transistors. Researchers have shown that the ionic channel transport in biological neurons can
be modeled using very few transistors, operating in the sub-threshold domain [61]. Such sub-
threshold transistors have been also leveraged to implement Hodgkin-Huxley-based neuron mod-
els [263] using programmable kinetics of the gating variables.
However, the more widely popular neuronal functionality is IF or LIF, which we have described
in detail in Section 2. The abstract view of such a neuron primarily consists of a capacitive unit
that holds and updates the membrane potential, a comparison unit, and a thresholding unit. The
most primitive form of IF neuron was conceptualized back in the late ’80s [143] with a simple
feedback circuit that could produce fixed width, fixed height voltage pulses, where the rate of the
pulses was proportional to the input injection current (arriving from synapses), and the temporal
characteristics of the pulses represented the shape of the input current waveform. A subsequent
design of IF neuron circuits in the analog domain involved incorporation of a comparator unit,
as shown in Figure 14(a) [145, 236]. In this design, the injected current is integrated using the
membrane capacitance, Cmem , and then fed to a comparator circuit to compare the resulting Vmem
against the threshold voltage Vt hr . The capacitive feedback, C f b , in both circuits ensures that small
fluctuations of Vmem around Vt hr do not affect firing activity. The updated circuit also has a control
for the refractory period of the neuron. Initially, after firing, Vmem decreases linearly, but once it
falls below Vt hr , the output of the first inverter sets high, leading to discharge of capacitor Cr at a
controlled rate using Vr f r . This ensures Vmem does not start to increase, as long as voltage at Cr is
above a certain value.
Analog IF neuron circuits have evolved significantly over time by incorporating more features,
such as reset, leak, as well as spike frequency adaptation, and so on. Figure 14(b) shows a fairly
complex and generalized IF neuron circuitry [89]. Such a neuron circuit consists of an input dif-
ferential pair integrator (DPI). The integration is performed by the membrane capacitor, Cmem ,
and the spike generation scheme is implemented using an inverting amplifier with positive feed-
back. The reset behavior is implemented using transistor M13, and together with transistor M21,
refractory-period behavior is implemented. Transistors M5–M10 produce the current proportional

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Exploring Neuromorphic Computing Based on Spiking Neural Networks 243:29

Fig. 15. Illustration of a fully digital IF neuron. Fig. 16. Illustration of three different kinds of CMOS-
based synaptic circuits.

to the neuron’s firing rate, and hence lead to spike frequency adaptation mechanism. The modified
equation of the implemented LIF neuron is:
d
Cmem Vmem = (Idpi − Iτ ) − Iahp + I f b . (10)
dt
This generalized neuron realizes an adaptive, exponential IF neuron.
Other types of analog neuron implementations based on CMOS have also been explored, such as
the log-domain LPF neuron [12], which implements a reconfigurable IF circuit. Yet another type of
IF neuron circuit is called the “Tau-Cell neuron” [191, 237], which uses current-mode circuits, and
the membrane potential is represented as a current. More compact IF neuron circuits have been
proposed using above-threshold transistors, such as the quadratic IF neuron [249]. Such a neu-
ron is loosely based on the Izhikevich neuron model [92] where two state variables are maintained
across two separate capacitors instead of one. Leaky IF neurons have been also implemented using
switched capacitor circuits where the switches are used to implement leak behavior between the
membrane potential and resting potential [64]. The switch capacitance technique motivates more
digitally inspired neuron designs. One such design involves weighted current mirror circuits acti-
vated by a binary coded digital weight [211]. After, the neuron generates a positive and negative
spike based on the excitatory/inhibitory nature of the synapses.
Leading from digital inspiration of the previous neuron design, IF neurons have also been
explored in fully digital mode [33]. A digital adder and accumulator along with comparator circuits
can be used to implement integration and spike-generation behavior of IF neurons, shown in
Figure 15. Leak in such a neuron is implemented by a fixed weight synapse driven by a global clock.
4.4.2 CMOS-based Synaptic Circuits. Synaptic circuits were first conceived by Carver
Mead [145] as pulsed current-sources with transistors operating in the subthreshold domain, as
shown in Figure 16. The output of the circuit is simply a synaptic current, Isyn , which is a pulse with
width proportional to the width of the input spike. An extension to the aforementioned scheme
involves exponential decay of the post-synaptic spike using the mechanism of charging and dis-
charging of the node Vsyn [12, 115]. When an input pulse is applied, the node Vsyn decreases
linearly, where the rate of decrease is governed by the difference in current through the transis-
tors biased using Vt au and Vw , respectively. Consequently, the synaptic current Isyn exponentially
increases. When there is no input spike, Isyn discharges exponentially at the rate governed by
current through the transistor biased using Vt au . An alternative synaptic circuit can be imple-
mented using a differential pair, more commonly known as a differential pair integrator (DPI)
circuit [89]. During the charging phase, current through one branch of the differential pair repre-
sents the input current to the synapse. This DPI synapse has more independent control of the time-
constant of charge and discharge of the synaptic voltage node. Implementation of plasticity, both

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243:30 N. Rathi et al.

Fig. 17. Illustration of CMOS circuits consisting of subthreshold transistors exhibiting various complex
synaptic functionalities such as STDP, short-term depression (STD), as well as integration [89].

short-term and long-term, in synapses requires additional circuitry. Unsupervised learning neces-
sitates automatic update of weights based on internal signals rather than providing the update
signals externally for individual synapses. Figure 17 shows an excitatory synaptic circuit [89] that
implements both short-term plasticity (STP) as well as long-term plasticity (STDP) while us-
ing a current mirror integrator circuit (CMI) to enable the integrating behavior of a synapse.
The CMI circuit operates similar to the integrating circuits we have discussed before. On arrival
of a spike on the “pre” node, the CMI’s integrating capacitor gets charged, while in absence of the
spike, the charge decays through the diode connected transistor.
The STP in Figure 17 operates on the synaptic weight voltage Vw 0 . When spikes are applied
to the “pre” node, the synaptic weight reduces at a rate controlled by the bias voltage. Thus, the
synaptic weight goes through a short-term depression, i.e., it is maximum at onset of the spikes and
reduces gradually on consecutive application of spikes at the “pre” node. The STDP mechanism,
described in Section 2, is implemented using the STDP circuit shown in Figure 17. Specifically,
the circuit modulates the analog voltage Vw 0 based on the relative difference between the pre-
and post-spike times. Two waveforms, Vpot and Vdep , are generated based on the presynaptic and
postsynaptic pulses, respectively. The pre- and post-spikes activate two transistors that control the
current that cause increase and decrease in the Vw 0 node. The bias voltages Vp and Vd set a limit
on the current injection and removal from the capacitance at the node Vw 0 . The transistors in the
middle branch that carry currents Ipot and Idep operate in the subthreshold region to enable an
exponential relationship required for STDP. The bistability circuit shown in Figure 17 is required
to hold the analog value of synaptic weight, since CMOS capacitors are prone to leakage of charge.
In absence of spiking activity, the bistability circuit generates a constant leak current, which pulls
the weight node Vw 0 towards one of the two stable states. The voltage Vt hr that is fed to the
comparator is set externally. If STDP circuits cause the synaptic weight to fall below the threshold,
then the bistability circuits allow a negative current to flow to drive the weight towards an analog
value representing the depressed state. When synaptic weight increases above the threshold, a
positive current flows to drive the weight to a high state. Similar approach has been followed in
other works with different variants of plastic synapses. For example, one chip called ROLLS [187]
uses separate synaptic arrays for short-term plasticity and long-term plasticity along with custom
neuronal circuits based on a variant of the adaptive exponential IF neuron circuit described earlier.

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Exploring Neuromorphic Computing Based on Spiking Neural Networks 243:31

Researchers have also explored CMOS floating-gate (FG)-based devices to represent

synapses [78, 190] due to their ability to hold on to the synaptic weights indefinitely. To implement
plasticity, the synaptic weights are updated considering the injection and tunneling currents in FG
transistors. The currents exponentially depend on the gate and tunneling voltages as shown below:
Iinj ∝ exp(−ΔVд /V0 ), (11)
Itun ∝ exp(−ΔVtun /Vox )exp(−ΔVд /V0 ). (12)
The change in weight is directly proportional to the currents. For long-term potentiation, the
change in weight exponentially decays with increasing spike timing difference if a linear depen-
dence exists between the gate voltage, Vд with the time difference. The injection current governs
the long-term potentiation and the tunneling current causes long-term depression. When both
currents are combined, it results in STDP behavior. When a post-spike arrives, an injection pulse
and then a tunnel input is applied. When the input spike is delayed, it occurs during the tunneling
phase, which causes a negative change in weight. When input spike occurs before post-spike,
the gate voltage goes down, and during the subsequent tunneling phase, it increases, resulting in
exponential reduction of tunneling current, and hence a positive change in weight.

4.5 ROM-embedded RAM as Neuronal Function Storage

We have previously mentioned how efficient computing architectures can be composed of tiled
near memory processing (NMP) systems to reduce data movement. A key factor of implement-
ing such NMP systems is high on-chip storage density, which would alleviate the need for costly
DRAM accesses. Improvements in storage densities can be achieved through recent proposals of
placing Read-Only Memory (ROM) into Static Random Access Memory (SRAM) caches to
obtain a ROM-embedded cache (R-cache) [122] architecture without incurring degradation in
area or performance. Standard storage units in caches are 6-transistor (6T) SRAM cells that usu-
ally consist of 2 access transistors and 2 cross-coupled inverters. The new memory cell involves
adding an extra word-line to the standard 6T SRAM cell, as shown in Figure 18.
This standard cell design can be operated to achieve the functionality of both SRAM
and a ROM. In the RAM mode, the wordlines WL1 and WL2 are connected together.
They are turned ON and OFF together to operate the cell as a conventional 6T-SRAM for
memory read and write. There is no performance degradation compared to a standard 6T-
SRAM cell. The ROM functionality can be realized through a number of sequential steps.
Step 1: “1”s are written to an en-
tire row of bit-cells by activating
both WL1 and WL2. Step 2: “0”s
are written to the bit-cells con-
nected to WL2 by turning on WL2
and keeping WL1 off. Note, only
bit-cells connected to WL2 stores
“0,” while others store “1.” Now, if Fig. 18. Standard 6T-SRAM embedded with ROM. An additional
word-line is used to retrieve the ROM data. This primitive can
consecutive bit-cells have different
work both in RAM and ROM mode. In RAM mode, the WLs are
ROM data, then this step would shorted and the primitive operates as standard SRAM. In ROM
end up performing a 5T write mode, the WL connections enable writing of ROM data into the
operation on the SRAM cell using SRAM cells.
the connnected access transistor.
The ROM data is now accessible through conventional RAM read. The initial ROM retrieval
process destroys RAM contents, so the RAM data should be backed up to use the design in
the ROM mode. The ROM-embedded RAM structure thus bypasses the need to access external

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243:32 N. Rathi et al.

Fig. 19. Neuron devices and circuits based on various NVM technologies, such as PCM, RRAM, Spintronics,
exhibiting IF characteristics.

memory to read necessary data such as look-up tables, and so on. These look-up tables can
be used to store transcendental functions, as well as complex neuronal functions required for
SNNs [5].

4.6 Non-volatile Memory-based Compute Primitives

In spite of significant advances in CMOS technology to emulate the logical adjacency of processing
and storage elements in SNNs, there is a need to explore alternative technologies for two particular
reasons. First, to improve efficiency of NMP systems, there is a need for higher on-chip storage den-
sity. Second, emulating complex neuronal and synaptic functionalities in CMOS technologies can
lead to high area consumption. To that effect, non-volatile memory (NVM) technologies such as
Resistive RAMs (RRAM), Phase Change Memories (PCM), and Spintronics offer significant
promise [37]. They allow component-wise direct emulation of neuronal/synaptic functionality at
a one-to-one level by the underlying device characteristics. Such a feature along with their high
on-chip storage density and ability to perform massively parallel in-memory computations make
NVM technologies particularly suitable for neuromorphic systems.
Originally conceptualized by L. Chua [42] in 1971, the fundamental component in NVM tech-
nologies, the memristor, was materialized by HP Labs in 2008 [225]. The main deviation in the
basic functionality between memristors (memory+resistor) and conventional CMOS transistors
(Boolean switches) arise from the fact that they are non-volatile programmable analog resistors.
This enables us to mimic the computational units of neurons and synapses directly in the underly-
ing device resistance state. Following naturally through principles of physics, these NVM devices
can be arranged in array structures to realize highly compact and energy-efficient “In-Memory”
dot-product computing kernels essential for neuromorphic computations. Each NVM device con-
ductance state encodes the corresponding synaptic weight. Input spikes are applied as voltages
along the rows of the crossbar array. The currents flowing through each device are weighted by
the device conductance and get summed up along the column of each array to realize the dot-
product operation. The crossbar array can be also interfaced with resistive neuronal devices to
implement the neuronal processing operation. Important metrics for neural/synaptic devices are

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Exploring Neuromorphic Computing Based on Spiking Neural Networks 243:33

the bit resolution available for programming, programming energy and speed, ratio of the maxi-
mum to minimum device conductance, reliability, and endurance [112, 201, 251, 273].

4.6.1 Neuronal Circuits. The rich device physics of NVM technologies can enable efficient emu-
lation of neuronal and synaptic functionalities in single devices. Various material stacks are being
actively investigated as synaptic and neuronal elements. For instance, phase change materials
(PCM) are being currently investigated where a chalcogenide material sandwiched between two
electrodes can be switched between amorphous and crystalline states due to the heating effect in-
duced by current flowing through the electrodes [24, 250]. The variable current through the device
in different states can be used to implement integrate and fire neurons, where the membrane po-
tential is temporally integrated by successive crystallization pulses. The device changes its state to
crystalline beyond a threshold, and it is reset to the amorphous state subsequently. The reset mech-
anism introduces stochasticity in the IF neuron, since each individual amorphous state is different.
Researchers have explored applications such as temporal correlation between data streams using
such stochastic IF neurons [233]. PCM-based neurons have been experimentally demonstrated in
both electrical [234] and photonic domains [39].
Metal oxides such as SrTiO3 [248],
as well as HfOx [72], TiOx [195],
have been explored as an alternative
material for constituting a class of
device, known as RRAMs. Alike
PCM, RRAM devices can also be
used as LIF neurons by connecting
it parallel to an external capacitance,
as shown in Figure 19. The internal
membrane potential is encoded
in the conductance of the RRAM
device. When the RRAM is in its
ON conductance state, the current
through the circuit suddenly in-
creases, which leads to an analog
spike. The voltage across the RRAM
device represents the LIF character-
istics. Other types of RRAM-based Fig. 20. (a) STDP characteristics can be emulated in RRAM
neurons involve controlling the synapses using repeated pulsing schemes [©2014 IEEE. Reprinted,
with permission, from Wang IT et al. In 2014 IEEE International
migration of oxygen vacancies using
Electron Devices Meeting 2014 Dec. 15 (pp. 28.5.1–28.5.4). IEEE].
post-synaptic pulses [114, 146]. (b) STDP learning in PCM synapses [111] emulates neuroscientic
RRAM and PCM devices are often experiments [186] (right) using series of pulses of increasing
characterized with high switching amplitude [Reprinted (adapted) with permission from Nano
times and power over the years. Letters 2012 May 9;12(5):2179–86. Copyright (2012) American
Although, more recently, through Chemical Society].
extensive material research, the
switching times of RRAM devices have been brought down a few ns timescale [1]. As an
alternative technology, researchers have explored Spintronic devices such as Magnetic Tunnel
Junctions [65] as LIF [93] as well as stochastic neurons [205]. MTJs are formed using two
ferromagnetic (FM) nanomagnets with a spacer layer (MgO) sandwiched between them. MTJ
can exist in two different resistance states based on the relative direction of magnetization
of the two FM layers. The spin dynamics of an FM can be expressed effectively using the

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243:34 N. Rathi et al.

stochastic-Landau-Lifshitz-Gilbert-Slonchewski (s-LLGS) equation:

 
∂m̂ ∂m̂ 1
= −|γ |(m̂ × H E F F ) + α m̂ × + (m̂ × Is × m̂), (13)
∂t ∂t qNs
where m̂ is the unit vector of free layer magnetization, H E F F is the effective magnetic field
including the shape anisotropy field, external field, and thermal field, γ is the gyromagnetic ratio
for electron, α is Gilbert’s damping ratio. The first two terms of the LLG equations is often used
to represent the “leak” behavior, while the last term encodes the integrating behavior. This makes
spin devices particularly amenable to be used as LIF neurons. Alternate spin dynamics such as the
magneto-electric (ME) switching has also been explored as LIF neurons [93], where a ME oxide
layer is used a capacitance to induce leaky behavior. IF neurons can also be implemented using
larger magnets, more commonly known as domain-wall magnets (DWM) [207], as shown
in Figure 19. The membrane potential is integrated through motion of the domain-wall, and it
reaches a threshold value when the domain-wall reaches the extremity of the magnet.
Furthermore, the switching dynamics on Spintronic devices is a strong function of a thermal
field, which leads to stochastic behavior. Such stochastic behavior can be leveraged to design
stochastically switching binary neurons, described in Section 2.1.2. Since such neurons require fre-
quent switching, they are often based on Spin-Orbit-Torque (SOT) MTJs for reduced power con-
sumption [205]. SOT-MTJs consist of a heavy metal at the bottom of the MTJ stack and leverages
the principle of Spin Hall Effect (SHE) to produce magnetization switching at lower currents.
Besides the RRAM, PCM and Spintronic technologies, recent interest in Ferro-electric Field
Effect Transistors (FEFETs) have led to exploration of neuromorphic devices based on it. The
abrupt switching of FEFET on application of repeated pulses can be leveraged to mimic function-
ality of IF neurons [159, 160]. The firing dynamics is a function of the amplitude and duration of
the pulses. The leak behavior in a FEFET-based neuron has been experimentally demonstrated in
an HZO thin film [56].
4.6.2 NVM devices for Synaptic Learning. The variable states in NVM devices can also be used
to perform synaptic learning using both unsupervised and supervised weight update mechanisms,
described earlier. Unsupervised learning schemes such as STDP have been experimentally demon-
strated using PCM synapses [8, 111]. The conductance of synapses can be gradually increased or
decreased through successive pulses to perform both long term potentiation (LTP) and long
term depression (LTD). The pre-spikes consist of pulses of gradually changing amplitude, and
post-spike is a negative pulse, as shown in Figure 20(a). The overlap of pulses is a function of the
spike time difference, and the change in conductance is proportional to the overlap. Other kinds
of schemes involve usage of two PCM devices [26], one each for LTP and LTD. PCM devices based
on photonics have also been demonstrated to perform on-chip STDP learning [40, 62]. In this tech-
nology, the change in optical response through refractive index modulation is used to change the
state of the devices.
The state modulation in RRAM devices can also be used to perform STDP through differential
pulse shaping of pre-synaptic and post-synaptic voltages [184, 189]. Like PCM device, gradual
increase/decrease of conductance is also be achieved through a series of identical pulses [210, 243].
Since controlled pulses maybe difficult to generate, STDP has also been explored with an additional
transistor, i.e., with a 2T/1R synapse [246] to enable more precise control.
We have discussed earlier how Spintronic devices can be programmed to have multi-level states
using multi-domain magnets. Such multi-level states enable synaptic behavior whose weight can
be encoded by the position of the domain wall in the device. Through the use of extra transis-
tors [204], STDP learning is enabled by leveraging the exponential characteristics of the transistors

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Exploring Neuromorphic Computing Based on Spiking Neural Networks 243:35

Fig. 21. STDP learning scheme in DWM-based spin Fig. 22. Illustration of a typical NVM
synapse [204] using peripheral transistors. [Reproduced with crossbar with necessary peripheral
permission Physical Review Applied 2016 Dec. 8;6(6):064003., circuits.
Copyright 2017 American Physical Society].

in sub-threshold regime, as shown in Figure 21. The transistor M ST DP operates in the sub-threshold
regime, and a linearly increasing gate voltage is applied at the time when pre-spike arrives. When
the post-spike arrives, a programming current, exponentially dependent on the time difference of
the spikes, flows through the heavy metal layer. The transistors MA2 and MA4 in Figure 21 can
be removed when connecting multiple such synaptic devices in a crossbar fashion [204]. Due to
the low resistance range of Spintronic devices, encoding multiple states can hurt functionality. To
that effect, regular MTJs encoding binary information can also be used as synapses. A variant of
STDP learning, namely, stochastic STDP, has been explored in binary synapses, which can lead
to significant energy-efficiency [224, 238] due to low operating currents. To achieve multi-level
stochastic STDP, researchers have explored multiple MTJs to represent a single synapse [266].
The switching behavior in FEFETs produces bi-stability that makes them suitable for synaptic
operations. FEFET-based synapses can also achieve multiple levels and have been experimentally
demonstrated [43, 94, 161]. STDP-based learning scheme has been achieved through conductance
potentiation and depression using gradual threshold voltage turning.

4.6.3 NVM Crossbars. We have discussed briefly how NVM devices can be arranged in a matrix
formation to form a crossbar to constitute ultra-dense memories as well as serve as primitives for
highly parallel “In-Memory Computing.” More specifically, such crossbars based on NVM devices
can perform matrix-vector multiplication (MVM) operations efficiently. The conductance of
the NVM devices stores the values of the matrix elements while the vector is provided as voltages
to the word-lines of the crossbar, as shown in Figure 22. The multiplication occurs in the NVM
device itself, and the product, which is the current through each device Ii j = Vi ∗ G i j , is summed
up in the bit-line.
In addition to performing efficient MVM synaptic computations, learning mechanisms such as
STDP have been demonstrated in NVM crossbars based on all the aforementioned technologies.
For example, in PCM technology, small-scale arrays of size 10 × 10 consisting 1T-1R PCM cells
have been used to perform on-chip STDP [58, 59]. With an additional transistor, the arrays could
be further scaled [104]. PCM-based crossbars have also been explored [38] and even experimentally
demonstrated [62] in the photonic domain. Crossbars based on RRAM devices have distinct simi-
larity to PCM crossbars. As a result, in situ learning has been proposed in RRAM crossbar arrays for
single layer neural networks [180, 245]. RRAM and PCM-based crossbars have been further scaled
for supervised learning to demonstrate deeper networks [9, 32, 102, 126, 176, 247]. Although such

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243:36 N. Rathi et al.

demonstrations have been limited to ANN workloads, it can be used to map SNNs trained using
supervised learning algorithms. Spintronic/magnetic tunnel junction-based crossbars, however,
have not been widely demonstrated due to very low ON/OFF resistance ratios due to fabrication
challenges. A lower ON/OFF ratio can pose limitations on application accuracy. Simulation stud-
ies have explored STDP-based learning [204] at an array level based on higher predictive ON/OFF
ratios [80], which has been closely matched through experimental demonstration [86].

4.7 Hardware-software Co-design Approaches

In this section, we have described different methodologies for designing custom SNN hardware
at various levels of the hardware stack such as architectures, communications, and finally com-
pute primitives. Researchers have also explored effective hardware-software co-optimization tech-
niques to efficiently map SNNs to the hardware systems. One of the approaches include Bayesian
hyper-parameter optimization [178], where the authors have performed a grid search on hardware-
specific hyperparameters. The authors of Reference [163] explored an architectural solution that
we have described earlier, which required each layer of the SNN model to be computed through all
the timesteps before progressing to the next layer—a prime example of hardware-aware optimiza-
tion of SNN models for achieving compute efficiency. Transforming SNN models to achieve better
amenability to neuromorphic hardware constraints has also been explored [95] to achieve high
resource utilization. Efficient mapping of SNN models on the non-volatile memory-based SNN ac-
celerators has been explored in Reference [11]. Hardware-Software co-optimization is at a fairly
nascent stage in the neuromorphic domain. Researchers can draw motivation from corresponding
deep learning hardware-software co-optimization techniques such as utilizing pruning, quantiza-
tion as well as exploring models that can enable parameter re-use. In addition, as we scale SNN
models, we should continue addressing unique challenges faced by neuromorphic systems as well
such as additional overhead of the membrane potential storage and how re-use and quantization
can help in that regard.

5 DISCUSSION
Artificial intelligence has become ubiquitous in diverse fields and is transforming the world around
us. The current powerful machine learning models are mostly deployed on large cloud-computing
systems. To enable large-scale adoption of edge intelligence or TinyML on IoT devices, there is
a need to rethink the prevailing solutions. To that effect, techniques such as model compression,
pruning, and quantization in ANNs have shown significant promise, but to achieve brain-like ef-
ficiency that may not be enough. Brain-inspired neuromorphic computing, specifically SNNs, can
assist in bridging the energy gap. SNNs operate as dynamical systems with temporally evolving
quantities that define the dynamics of the neurons and synapses. Although recent gradient-based
methods consider the spike times for parameter updates, the backpropagation through time is
memory-intensive. Therefore, further research is needed to develop learning algorithms that can
efficiently employ the rich timing information to achieve faster learning with fewer resources.
As discussed in Section 2.4 and Figure 9, SNNs can behave as RNNs due to their inherent re-
currence. This provides a unique opportunity to employ SNNs for both static and sequential tasks.
Research, so far, is mainly focused on using SNNs for static image classification. Other tasks such
as language modeling, speech recognition, machine translation, and so on, where RNNs have per-
formed well, may be explored for SNNs. In Section 2.1, we discussed the IF/LIF neuron model
whose simplicity is its strength, but further research in neuron modeling, structural plasticity, and
the role of dendrites in efficient learning is required to mimic the complex dynamics of the brain.
Also, the individual advancement in neuron modeling and learning algorithms may not result
in a compatible solution. The focus should be on the co-design of neuron models and learning

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Exploring Neuromorphic Computing Based on Spiking Neural Networks 243:37

algorithms that can achieve an optimal tradeoff between complexity and trainability. Similarly,
the backpropagation-based algorithms may not be very suitable for deep SNNs, and the various
hardware-friendly local learning methods may be more apt for performing computations on edge.
Unsupervised STDP-based methods work well on shallow networks for simple tasks but fail to opti-
mize deep networks. Other variants of STDP learning in combination with homeostasis and local
gradient-based techniques may be explored to discover better learning mechanisms. Batch Nor-
malization [91] has proven to be a successful technique in training deep ANNs, but its application
in SNNs is limited and has not resulted in significant improvements. Moreover, edge applications
require real-time online learning (batch size = 1), which raises the question of whether batch nor-
malization can be done. SNNs are highly successful in handling spatiotemporal data from event
sensors. They perform relatively better than ANNs at tasks such as motion estimation and classi-
fying images from neuromorphic datasets. Therefore, further research is needed to identify more
such tasks or efficiently convert other tasks in a discrete form that is more suitable for SNNs.
In Section 4, we have described the fundamental requirements as well as recent explorations to-
ward building neuromorphic emulators and accelerators. The advancements in the field of neuro-
morphic hardware has closed the gap that exists between the algorithm space and their amenability
in today’s general-purpose as well as domain-specific accelerators. Further, the research in neu-
romorphic hardware leverages the unique features of SNN workloads that can potentially lead
to low computational complexity as well as energy-efficiency. Despite the development in the
space of neuromorphic hardware, significant evolution is required to truly realize the potential of
energy-efficiency offered by SNN workloads. Neuromorphic algorithms are constantly evolving,
as new features are being incorporated in the workloads, necessitating neuromorphic hardware
to evolve as well. Over the past two decades, we have overseen massive leaps in building analog
neuromorphic circuits in CMOS as well mapping such functionalities directly in single NVM de-
vices. The primary challenge toward building efficient neuromorphic systems is scalability. We
have delved into large-scale CMOS neuromorhic systems, which include wafer-scale integration
as well as multi-chip modules. However, scaling NVM-based neuromorphic systems remains a
challenge. First, the device variability and reliability poses a big challenge in realizing scalable sys-
tems using NVM-based neural primitives. Second, NVM-based compute primitives perform the
synaptic computations in the analog domain. Analog computing in NVM-based primitives [37] is
erroneous in nature and requires modeling and sufficient mitigation [210] for reasonably accurate
operation. Various algorithmic strategies have been explored to mitigate and potentially leverage
device mismatch and variability in a beneficial sense. For example, stochasticity in synapses [222]
and neurons [197] have been shown to be beneficial towards generalization in SNNs.
In spite of significant efforts on building large-scale neuromorphic systems in CMOS, one critical
aspect of such systems is implementing neuro-synaptic functions using analog circuits. Analog
circuits are prone to threshold voltage variations across transistors. Although various electrical
engineering techniques can be used to minimize device variations, analog design of silicon neurons
and synapses requires additional circuitry for incorporating various kinds adaptation and feedback
mechanisms. There have been explorations in devising techniques to counteract such variations in
analog circuits [164]. Researchers also argue that a certain degree of imprecision is often beneficial
to neural computing, drawing analogies with imprecise and diverse computing patterns in the
biological brain [136]. Further, device mismatch has also been demonstrated [149] to enable stable
receptive fields and balanced network activity in recurrent SNNs. Although there is significant
merit to such arguments, it is also necessary to devise engineering solutions to circumvent the
effect of device variations in large-scale neuromorphic systems, especially as CMOS technology
has scaled down to below 10 nm.

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Last, architecting neuromorphic hardware has to consider workload-related overheads. While

there have been significant developments in designing event-driven hardware, SNN workloads are
associated with additional data movements and storage due to an extra data-structure, which is the
membrane potential, unlike ANN workloads. Architectures exploring non-volatile memory-based
neurons can also allow in situ membrane potential storage and update [216], thereby reducing
movement of membrane potential. Further optimizations can be considered to minimize the cost
of fetching and updating membrane potential at every timestep. One such technique can involve
quantization of membrane potential to lower than full-precision. This would reduce the storage
requirements as well as data movement costs. Alternatively, one could explore stationarity options
between inputs, weights, partial sums, and membrane potential and design a dataflow that reduces
the movement of the most critical data structure. Overall, reducing membrane potential overhead
remains a key design challenge in future neuromorphic hardware.
Neuromorphic computing has evolved significantly since its inception in the ’90s, aided by de-
velopments in the field of neuroscience as well as semiconductor technology. With our current
understanding of the functionalities of the biological brain, we have harnessed some key features
such as event-based computation and communication, localized learning, as well as co-location of
memory and processing capabilities. In addition, we have drawn inspiration from the development
of AI algorithms to scale up the networks and achieve comparable performance in state-of-the-art
recognition tasks compared to conventional ANNs while potentially reducing the power consump-
tion. Along with the momentous progress, neuromorphic computing presents us with numerous
challenges mentioned above that will shape the way for future research. Such efforts across the
stack of sensors, hardware, and algorithms can truly help achieve efficient intelligent systems
based on neuromorphic computing.

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Received 30 October 2021; revised 29 August 2022; accepted 25 October 2022

ACM Computing Surveys, Vol. 55, No. 12, Article 243. Publication date: March 2023.