Cell-Based IC Physical Design and Verification

- Encounter Digital Implementation

 Class Schedule

• Day1  Power Analysis

– Design Flow Over View  SRoute
– Prepare Data  NanoRoute
– Getting Started
 Fill Filler
– Importing Design
 Output Data
– Specify Floorplan
 Day3
– Power Planning
– Placement  DRC
• Day2  LVS
– Synthesize Clock Tree  extraction/nanosim
– Timing Analysis  Foundation flow
– Trial Route

2
Chapter1- SOC Encounter

Cell-Based Physical Design

– EDI 14.24
– EXT 10.13.065 (fire & Ice)

3
 Cell-Based Design Flow
Implenentation Verification
RTL code
always @ (posedge clk) RTL Simulation
if (in1==1) Lint check
a=c+d code coverage analysis
else
a=c-d
Logic synthesis
Formal
Gate-Level netlist
Gate level Simulation
Static Timing Analysis
Power Analysis

Formal
Post layout Gate level Simulation
Place&Route
Gate-Level netlist Static Timing Analysis
Power Analysis

transistor netlist
LVS
GDS layout
Extraction

DRC Transistor-level Simulation

Transistor-level STA
Tape out 4
Power Analysis
 Cell Library
function NAND NOR XOR INV ADD FF

schematic

layout

symble

timing A1àO 0.1ns A1àO 0.1ns

A2àO 0.2ns A2àO 0.2ns

power A1àO 0.1pw A1àO 0.1pw

A2àO 0.2pw A2àO 0.2pw

abstract
5
 SOC Encounter P&R flow

high
rough
Netlist (verilog) IO,P/G Placement IO constraints

Timing constraints (sdc)

Specify floorplan

Power Planning

Power Analysis

sdc defined
Amoeba Placement

Optimize capability
RC delay data
Timing Analysis

Pre-CTS Optimization

rough
Clock Tree Synthesis

Timing Analysis

Clock data
Post-CTS Optimization

SI Driven Route
Output GDS,
Timing/SI Analysis Netlist

detail

detail

low
Post-Route Optimization
6
 IO, P/G Placement

I1 VDD O1 Corner2
Corner1

I2 O2

IOVDD IOVSS

I3 O3

Corner3 Corner4
I4 VSS O4

7
Specify Floorplan

Hight

Width

8
 Floorplan

I1 VDD O1

I2 O2
M2
IOVDD IOVSS
M1 M3
I3 O3

I4 VSS O4

9
Power Planning

VDD

VSS

10
Power Route

11
Add IO Filler

12
Placement

13
 Clock Tree Synthesis

D D D D
Q Q Q Q
D D D D
Q Q Q Q
D D
Q Q
D D
Q Q
D D D D
Q Q Q Q
D D
Q Q
D D D D
Q Q Q Q

CLK CLK
D D D D
Q Q Q Q

14
Routing

15
 Prepare Data
• Library
– Physical Library (LEF)
– Timing Library (LIB)
– Capacitance Table
– Celtic Library
• User Data
– Gate-Level netlist (verilog)
– SDC constraints
– IO constraint
– scan def
16
 LEF Format
-- Process Technology

Layers Design Rule Parasitic

POLY Net width Resistance

Net spacing Capacitance
Contact Area
Metal1 Enclosure
Wide metal
Via1
slot
Metal2 Antenna
Current density

17
 LEF Format
-- Process Technology : Layer define

Wide metal spacing

Layer Metal1 width
TYPE ROUTING ;
WIDTH 0.28 ;
MAXWIDTH 8 ;
AREA 0.202 ; Wide metal
SPACING 0.28 ;
SPACING 0.6 RANGE 10.0 10000.0 ; spacing
PITCH 0.66 ;
DIRECTION VERTICAL ;
THICKNESS 0.26 ;
ANTENNACUMDIFFAREARATIO 5496 ;
RESISTANCE RPERSQ 1.0e-01 ;
CAPACITANCE CPERSQDIST 1.11e-04 ;
EDGECAPACITANCE 9.1e-05 ;
END Metal1

18
 LEF Format
-- APR technology

• Site
• Routing pitch
• Default direction
• Via rule

19
 LEF Format
-- APR technology : SITE

The Placement site give the placement grid of

a family of macros

a row a site

20
Row Based PR

VDD

VSS

VDD

VSS

21
 LEF Format
-- APR technology : routing pitch , default direction

metal1 routing pitch

via
Horizontal Vertical
routing routing
metal2 routing pitch
Metal1 Metal2
Metal3 Metal4
Metal5 Metal6
22
Grid Based Routing

metal2 grid

metal1 grid

23
 LEF Format
-- APR technology : Physical Macros
• Define physical data for
– Standard cells
– I/O pads
– Memories
– other hard macros
• describe abstract shape
– Size
– Class
– Pins
– Obstructions

24
 LEF Format
-- APR technology : Physical Macros cont.

MACRO XNOR
CLASS CORE ;
FOREIGN ADD1 0.0 0.0 ;
ORIGEN 0.0 0.0 ;
VDD LEQ ADD ;
SIZE 19.8 BY 6.4 ;
SYMMETRY x y ;
SITE coresite ;
A PIN A
B DIRECTION INPUT ;
A PORT
LAYER Metal1 ;
B Y RECT 19.2 8.2 19.5 10.3 ;
……
END
END A
PIN B
VSS …..
END B
OBS
……
END
END ADD1

25
Layout vs. Abstraction

Layout Abstraction

VDD VDD

A
B B
A A
Y B Y

VSS VSS
pdiff contact pin

ndiff nwell blockage

metal1 poly prboundary
prboundary
26
 LIB Format
• Operating condition type: input type: output
D Q
– slow, fast, typical setup/hold time max_cap/max_fanout
internal power internal power
output transition
• Pin type
– input/output/inout CLKàQ delay

– function
type: clock type: output
– data/clock mpwh/mpwl
max transition
CLK QN max_cap/max_fanout
internal power

– capacitance internal power CLKàQN delay output transition

• Path delay/transition function: ff

footprint
• Internal power area
leakage power

• Timing constraint
– setup, hold, mpwh, mpwl, recovery,
removal …

27
 Capacitance Table
• CapTable
– cap_value = f(configuration, width, spacing)
• CapModel
– CapTable contains the area, fringe and lateral coupling capacitance coefficients organized
per layer

Metal2 Metal2
L2
Fc A Fu Fd

Metal1 Metal1
L1

28
 CeltIC Library
cdB model
• Noise Model

29
 QRC layermap

Integrated QRC
#lefdef lef icecaps layer_ict
layer METAL1 icecaps METAL_1
layer METAL2 icecaps METAL_2
layer METAL3 icecaps METAL_3
layer VIA12 icecaps VIA_1
layer VIA23 icecaps VIA_2

Stand Alone QRC

extraction_setup \
-technology_layer_map \
METAL1 METAL_1\
METAL2 METAL_2\
METAL3 METAL_3\
VIA12 VIA_1\
VIA23 VIA_2\

30
 gate-level netlist
• If designing a chip , IO pads should be added before the netlist is
imported.
• Remove “assign” statement before APR.
A B
– The assign statement can be removed in Encounter
Encounter> setDoAssign -buffer buf_name on assign B=A ;

• Make sure that there is no “ *cell*” net name in the netlist.

– Use the synthesis commands (DC) below to remove “*cell*” cell name
dc_shell> define_name_rules name_rule –map {{\\*cell\\* cell”}}
dc_shell> change_names –hierarchy –rules name_rule

• Ensure the names of all instantiated cell types are unique

unix> uniquifyNetlist –top TOP output_netlist input_netlist

31
 Static Timing Analysis
 Main steps of STA
 Break the design into sets of timing paths
 Calculate the delay of each path
 Check all path delays to see if the given timing constraints are met
 STA paths
PI PATH PO
PATH
PATH D
SET
Q D
SET
Q PATH PO

CLK CLR
RN
CLR

ENCLK PATH
RESET PATH

32
 Static Timing Analysis

SET Tn1
D Q Tn2 Tn4 D SET
Tc1 Tc2 Tn3 Tc3 Q

CLR Q
CLR Q

33
 Static Timing Analysis
Cell Delay
Cell Delay Dcell(I2) = f(Dtransition(I1), Ceq)

Transition Delay Dtransistion(I2) = g(Dtransition(I1), Ceq)

Output Input Transition

Capacitance 0 0.5 1
0.1 0.123 0.234 0.456
0.2 0.222 0.432 0.801

Vin Dc Vout Dtransition(I2)

I1
I2
Dtransition(I1) I3
Req
Dcell(I2) Ceq
34
Static Timing Analysis
setup time and hold time

DFF1 DFF2
PATH
D Q D Q

clk1 clk2

clk1

setup
hold
clk2 time
time

35
 SDC constraint basic

create_clock set_input_delay
set_clock_latency set_output_delay
set_clock_uncertainty set_drive
set_load
input drive
current design

input delay
CK
output load
create latency uncertainty
clock output delay
CK

latency

36
 Basic sdc file

create_clock [get_ports {CLK}] -name CLK -period 8 -waveform {0 4}

set_clock_latency 2 [get_clocks {CLK}]
set_clock_uncertainty 1 [get_clocks {CLK}]
set_input_delay 2 [remove_from_collection [all_inputs] [get_ports CLK]]
set_output_delay 2 –clock CLK [all_outputs]
set_drive 0.1 [all_inputs]
set_load -pin_load 20 [all_outputs]
 SDC constraint others

set_generated_clock set_min_delay
set_clock_transition set_max_delay
set_input_transition set_false_path
set_propagate_clock set_multicycle_path
set_case_analysis set_max_capacitance
set_clock_gating_check set_max_fanout
set_data_check set_max_transition
set_disable_timing set_max_time_borrow
set_dont_touch set_min_pulse_width
set_dont_use …..
…..

38
 IO constraint
(globals
version = 3
io_order = default
)
toplef top topright (iopad
(top

P_HALT
P_CLK

(inst name=“P_CLK”)
CORNER0 (inst name=“P_HALT”)
CORNER1
)
(right
(inst name =“P_VDD1” cell=“PVDD1DGZ”)
(inst name =“P_VSS1” cell=“PVSS1DGZ”)
P_X2 P_VSS1 )
(left
left

right
(inst name=“P_X1”)
(inst name=“P_X2”)
)
P_X1 P_VDD1 (bottom
(inst name=“P_IOVDD1” cell=“PVDD2DGZ”)
(inst name=“P_IOVSS1” cell=“PVSS2DGZ”)
)
(topright
P_IOVSS1
P_IOVDD1

(inst name=“CORNER0” cell=“PCORNER”)

CORNER2
CORNER3 )
(topright/topleft/bottomrignt/bottomleft
bottomright
……...
bottomlef bottom )
)
39
 IO constraint
• globals
(globals
version = 3
io_order = default/clockwise/counterclockwise
space=5
)
(iopad
……
)
counterclockwise
(iopin
……
)
space

40
 IO constraint

• side/corner
(iopad/iopin
( top / right / left / bottom /
topright / topleft /bottomright / bottomleft/
(inst name=“inst1” ……)
(inst name=“inst2” ……)
(inst name=“inst3” ……)
(inst name=“inst4” ……)
)
)

41
 IO constraint

• iopad

P_CLK
CORNER0
(iopad CORNER1

(right endspace gap

(locals
space = 5 P_X2 P_VSS1
)
(inst name=“P_VDD1”
skip=5
P_X1 P_VDD1
offset= 300
orientation=R90 skip offset
cell=“PVDD1DGZ”

P_IOVSS1
P_IOVDD1
)
CORNER2
(keepclear begin=200 end=400) CORNER3
(inst name=“P_VSS1” cell=“PVSS1DGZ”)
(endspace gap =5)
)
)
42
 Orientation

R90 R270
R0 R180

MY90 MX90
MX MY

43
 IO constraint
• iopin
(iopin
(top/right/left/bottom
(locals
io_order=default/clockwise/counterclockwise
space = 5
)
(pin name=“pin_x”
layer=2 pin_x
width=0.14 width
depth=0.5
depth
skip=5
)
(pin name =……)
)
)

44
 IO constraint version2

Create an I/O assignment file manualy using the following template:

Version: 2
MicronPerUserUnit: value
Pin: pinName side [layer width [depth]]
Pad: padInstanceName side|corner [cellName]
Offset: length
Skip: length
Spacing: length
Keepclear: side offset1 offset2
Orient: orientation

45
 IO constraint version2 cont.

PAD_HALT
PAD_CLK
Version: 2
Pad: CORNER0 NW PCORNER
Pad: PAD_CLK N
Pad: PAD_HALT N CORNER0
N CORNER1
Pad: CORNER1 NE PCORNER
Pad: PAD_X1 W
Pad: PAD_X2 W PAD_X2 PAD_VSS1
W E
Pad: CORNER2 SW PCORNER
Pad: PAD_IOVDD1 S PVDD2DGZ PAD_VDD1
Pad: PAD_IOVSS1 S PVSS2DGZ PAD_X1
S

PAD_IOVDD1

PAD_IOVSS1
Pad: CORNER3 SE PCORNER
Pad: PAD_VDD1 E PVDD1DGZ
Pad: PAD_VSS1 E PVSS2DGZ
CORNER2 CORNER3

46
 SSO Consideration
• SSO
– Simultaneously Switch Outputs
• SSN
– The noise produced by SSO buffers
• DI
– maximum number of copies of an I/O cell switching from high to low
simultaneously without making the voltage on the quiet output “0”
higher than a threshold value “Vil” when a single ground cell is
applied.
• DF Ground Output Ground
– Drive Factor, DF = 1/DI pad pad bounce
1 DI < Vil
• SDF
– Sum of Drive Factor DF 1 < Vil
47
 SSO Consideration cont.
• Parameter of DF
– operating condition
– package inductance
– slew-rate control IO
– IO type with different drive strength
• In SSO case
– Required number of ground pads = SDF
– Required number of power pads = SDF/1.1
• Non SSO case (suggest)
– Required number of ground pads = SDF/1.5
– Required number of power pads = SDF/1.6
48
 SDF Example
IO Type 2mA 4mA 8mA 12mA 16mA 24mA

DF Value 0.02 0.03 0.09 0.18 0.3 0.56

• If a design has 20 PDB02DGZ(2mA), 10

PDD16DGZ(16mA). then
• SDF = 20 x 0.02 + 10 x 0.3 = 3.4
• In SSO case,
– number of VSS pad = 3.4  4
– number of VDD pad = 3.4/1.1 = 3.09  4
49
Tips to Reduce the Power/Ground Bounce
• Don’t use stronger output buffers than are necessary
• Use slew-rate controlled outputs cells
• Insert as many power and ground cells for I/O as possible.
• Place power pad near the middle of the output pads
• Place noise sensitive I/O pads away from SSO I/Os
• Consider using double bonding on the same power pad to
reduce inductance

50
Cadence On-Line document : cdnshelp
/usr/cad/cadence/EDI/cur/tools/bin/cdnshelp

51
 Getting Started
• Source the encounter environment:
unix% source /usr/cad/cadence/CIC/edi.cshrc
• Invoke soc encounter :
unix% encounter
• Do not run in background mode. Because the terminal become the
interface of command input while running soc encounter.
• The Encounter reads the following initialization files:
– enc.tcl
• Log file:
– encounter.log*
– encounter.cmd*

52
 GUI
menus design views
tool widgets

display control

design display area

name of
selected
object
cursor coordinates

auto query 53
 Tool Wedgits

Clear query
attribute highlight hierarchy violation all design
Design Import editor selected Down/Up browser rulers density
Fit

Undo/Redo highlight Zoom Zoom Redraw design Clear Summary

Selected In/Out Previous browser Violation Report

ruler cut add polygon

select rectilinear edit wire cut wire

move wire point to point route

move query stretch wire
add blockage
resize area
reshape density
54
 Design Views

 FloorplanView
 displays the hierarchical module and block
guides,connection flight lines and floorplan objects
 Amoeba View
 display the outline of modules after placement
 Physical View
 display the detailed placements of cells, blocks.

55
Display Control

56
ALL Colors
 Common Used Bindkeys
Key Action Key Action
q Edit attribute space Select Next
f Fits display e popup Edit
z Zoom in T editTrim
Z Zoom out 0-9 toggle layer[0-9] visibility
Arrows pans design area in the h/H hierarchy up/down
direction of the arrow
x clear Drc
Escape Cancel
N next via
K Removes all rulers
Looking for more bindkey:
OptionsàSet Preference, Binding Key

58
 import floorplan powerplan placement CTS routing

Import Design

FileàDesign Import…
 Import LEF in the order: 
 technology first 
 geometry lef for cell/block
 antenna lef for cell/block

 IO Assignment File:
 get a IO assignment template: 
DesignàSaveàI/O File…



59
 MMMC Browser
FileàDesign Import

60
 Traditional Timing Analysis
• One sdc file
– Fit all operation mode in one sdc file
• Max Timing Libraries
– worst-case conditions for setup-time analysis
• Min Timing Libraries
– best-case conditions for hold-time analysis

61
 Why MMMC
Case1

module A

CLK module B

Operation Mode1： moduleA runs on 100MHz

moduleB not use
Operation Mode2： moduleA runs on 50MHz
moduleB runs on 50MHz

62
 Why MMMC
Case2

• design is required to meet 3 operating corner

– Corner1： 1.1V ， 0°C
– Corner2： 0.9V ， 100°C
– Corner3： 1.1V ， 100°C

63
Traditional Timing Analysis to MMMC

Mode Corner Max Library Sets

SDC Max Delay Corner

RC Corner

Min Delay Corner

Min Library Sets

Max Analysis View Min Analysis View

Active Analysis View

set_analysis_view
-setup max_analysis_view
-hold min_analysis_view

64
 Multi-Mode Multi Corner
expand view

Corner
Mode Library Sets 1

Delay Corner 1
SDC 1 RC Corner 1

Library Sets 2
SDC 2 Delay Corner 2

RC Corner 2
SDC 3
Library Sets 3
Delay Corner 3

RC Corner 3

Analysis View V1 V2 V3 V4 V5 V6 V7 V8 V9

Active Analysis View

set_analysis_view
-setup V1 V2 V4 V5 V7 V8
-hold V3 V6 V9

65
 Multi-Mode Multi Corner

Library Sets
- group of librarys
-cdb librarys

Operating
Condition
- PVT

SDC Delay Corner

- clock Power Mode
Constraint Mode - one(or two) libray set
RC Corner
- io timing - Captable
- -one
each
sdcdoamin@nominal - one RC corner
- case analysis - one sdc - res/cap factor
- one(or two) op cond.
- false path - qx tech file
- multi-cycle path
……

Analysis View Active Analysis View

- one constraint mode set_analysis_view
- one delay corner -setup views_for_setup_analysis
-hold views_for_hold_analysis

66
import floorplan powerplan placement CTS routing

Global Net Connection

Powerà Connections Gloval Nets …

VDD

1'b1

 VSS

tie high net

INV inv1(.I(1’b1), .O(o));




67
import floorplan powerplan placement CTS routing

Check Design
• checkDesign
– Checks for missing or inconsistent library and design
data and writes the results to a text and HTML report.
– checkDesign checks the following data:
• I/Os
• Netlist
• Physical library
• Timing library
• Power and ground pins
• Tie-high and tie-low pins
• Floorplan
• Placement
import floorplan powerplan placement CTS routing

Specify Floorplan

FloorplanàSpecify Floorplan …




Hight

 
 

Width

69
 import floorplan powerplan placement CTS routing

Specify Floorplan-core utilization

core utilization = standard cell + macro cell

core area

70
import floorplan powerplan placement CTS routing

Floorplan Purposes

 Develop early physical layout to ensure design objective can be

archived
 Minimum area for low cost
 Minimum congestion for design routable
 Estimate parasitic for delay calculation
 Analysis power for reliability

71
import floorplan powerplan placement CTS routing

Difference Floorplan Difference Performance

72
import floorplan powerplan placement CTS routing

Module Constraint

• Soft Guide
• Guide
Soft Guide Guide
• Region
• Fence
Region Fence

73
 import floorplan powerplan placement CTS routing

Guide , Region, Fence

• Placement constraint
• Create guide for timing issue
• A critical path should not
through two different modules
• The more region, the more
complicated floorplanning

74
import floorplan powerplan placement CTS routing

Soft Module & Hard Macro

75
 import floorplan powerplan placement CTS routing

Place Block

 FloorplanàAutomatic FllorplanàPlan Design…

 Automatic generate a quick, initial floorplan.
 Move/Resize/Reshape floorplan object.
 edit floorplan by functions in :
FloorplanàEdit Floorplan

76
 import floorplan powerplan placement CTS routing

Block Placement

• Block place issue

– power issue
– noise issue
– route issue

77
import floorplan powerplan placement CTS routing

Tip for Memory Place

78
 import floorplan powerplan placement CTS routing

Blockage
• Placement Blockage
– Hard
– Soft
• The initial placement should not use the area, but later phases, such as
optimization of CTS can use the blockage area.
– Partial
• The initial placement should not use more than maxDensity percentage
of the blockage area.
• Routing Blockage
– Blockage on given routing layers

79
 import floorplan powerplan placement CTS routing

Add Halo To Block

FloorplanàEdit FloorplanàEdit Halos…

• Prevent the placement of blocks and standard cells in order to reduce

congestion around a block.

halo


hot spot

hard route
halo  
 
metal2
power ring
80
import floorplan powerplan placement CTS routing

Placement
PlaceàPlace Standard Cells …

D Q d1 D Q

CLK CLK

d2
D Q D Q
O
B
CLK CLK

D Q D Q
d3

CLK CLK
clk

81
import floorplan powerplan placement CTS routing

Mode Setup -- placement

OptionsàSet ModeàMode Setup…

82
 Scan Chain
scan_in
Inputs
11110000 outputs
A Reg
11001100 Z scan_out
00110000
B Reg Reg
10101010
C Reg

Scan Flip-Flop
hard to observe
TI
1 TO hard to assign value
DI 0 Q
Reg
TE QN
Tester Cycles
CK Clock
Measure PO’s

Scan Enable

83
 import floorplan powerplan placement CTS routing

Specify Scan Chain with scan def

FileàLoadàDEF…
SOUT
scan_def D
SI
Q D
SI
Q D
SI
Q D
SI
Q
SIN
SCANCHAINS 1 ; CK CK CK CK
SE SE SE SE
- scan1
ORDERED
+ START SIN
+ FLOATING
DCT_tposemem_Bisted_RF_2P_ADV64x16_BistCtrl_i0/S44/State_reg[2] ( IN SI ) ( OUT QN )
DCT_tposemem_Bisted_RF_2P_ADV64x16_BistCtrl_i0/S44/State_reg[1] ( IN SI ) ( OUT Q )
DCT_tposemem_Bisted_RF_2P_ADV64x16_BistCtrl_i0/S44/State_reg[3] ( IN SI ) ( OUT Q )
DCT_tposemem_Bisted_RF_2P_ADV64x16_BistCtrl_i0/S44/State_reg[0] ( IN SI ) ( OUT QN )
…………
+ ORDERED
DCT/tposemem_Bisted_RF2SH64x16_BistCtrl_i0_ST_MAL_i0_S17_reg ( IN SI ) ( OUT QN )
DFT_shared_out_mux_3 ( IN B ) ( OUT Y )
+ STOP SOUT
;
END SCANCHAINS
END DESIGN
84
 Generate Scan Def
• Design Vision
– write_scan_def –o scan.def
• RTL compiler
– write_scandef > scan.def

85
import floorplan powerplan placement CTS routing

Specify Scan Chain with specifyScanChain command

encounter > specifyScanChain scanChainName
–start {ftname | instPinName}
– stop {ftname | instPinName}
• specifyScanChain
– ftname
• The design input/output pin name
– instPinName
• The design instance input/output pin name
• Specifies a scan chain in a design. The actual tracing of the scan chain is
performed by the scanTrace or scanReorder command
• enables scanTrace trace through multiple input logic gates in scan path
– setScanReorderMode -compLogic

86
import floorplan powerplan placement CTS routing

Scan Chain Reorder

SCAN IN SCAN OUT SCAN IN SCAN OUT

D D D D
Q Q Q Q
D D D D
Q Q Q Q
D D
Q Q
D D
Q Q
D D D D
Q Q Q Q
D D
Q Q
D D D D
Q Q Q Q
D D D D
Q Q Q Q

87
 import floorplan powerplan placement CTS routing

Add Tiehi/Tielo cell

 Tiehi/Tielo cell connect tiehi/tielo net to supply voltage or

ground with resister VDD
VDD

 Tiehi/Tielo cell is added for ESD protection. 1'b1

Y
1'b1

VSS
A tie high cell

 PlaceàTie Hi/Lo CellàAdd

88
import floorplan powerplan placement CTS routing

Power Planning: Add Rings

PoweràPower PlanningàAddRings

89
 import floorplan powerplan placement CTS routing

Power Planning: Add Rings

Use wire group to avoid slot DRC error
VDD
VDD
GND
GND

metal slot





90
import floorplan powerplan placement CTS routing

Power Planning: Wire Group

Use wire group Use wire group
no interleaving interleaving
number of bits = 2 number of bits = 2

VDD VDD
VDD GND
GND VDD
GND GND

91
 import floorplan powerplan placement CTS routing

Max Density Rule

• Max density violation usually happened on power ring
• Max density rule : metal area coverage must < 70%
2x
density = = 66%
2x+x
2x
x
2x
x
2x
x
2x

92
import floorplan powerplan placement CTS routing

Power Planning: Block Ring

VDD
VDD
GND
GND

93
import floorplan powerplan placement CTS routing

Power Planning: Block Ring cont.

VDD
VDD
GND
GND

94
 Block power pin
ring type: ping type: rail type:
VDD VDD
VDD VDD
GND GND
GND GND

Add Stripes SRoute Add stripes

- set to set distance - block - over p/g pins

95
import floorplan powerplan placement CTS routing

Power Planning: Add Stripes

VDD
VDD
GND
GND

I3 I2 I1

IR drop

96
import floorplan powerplan placement CTS routing

Power Planning: Add Stripes

97
import floorplan powerplan placement CTS routing

Power Planning: Add Stripes

VDD
VDD
VSS
VSS

blockage

98
 Stripes

horizontal
horizontal stripe
stripe VDD

VSS
VSS
vertical
stripe
vertical
stripe
VDD VSS
power rail

99
 import floorplan powerplan placement CTS routing

SRoute
• RouteàSpecial Route
• Route Special Net (power/ground net)
– Block pins
– Pad pins
– Pad rings
– Follow pins
– Floating Stripes
– Secondary Power Pins

100
 import floorplan powerplan placement CTS routing

PowerPlan Order
hint: connect wider nets prior then narrow ones.
1. create power ring
2. connect pad pin
3. create block ring
4. connect block pin
5. create stripe
6. connect follow pin

101
 import floorplan powerplan placement CTS routing

Add IO filler
addIoFiller –cell <fillerCellName>
[ –prefix <prdfix> ]
[ -side { n|w|s|e } ]
[ -fillAnyGap ]

• Connect io pad power bus by inserting IO filler.

• Add from wider filler to narrower filler.

ADD IO FILLER

102
 import floorplan powerplan placement CTS routing

Add IO filler cont.

• In order to avoid DRC error
– The sequence of placing fillers must be from
wider fillers to narrower ones.
– Only the smallest filler can use -fillAnyGap option.
• Use addIoFiller.cmd provided in CIC design kit
– source addIoFiller.cmd A gap that unable to place any filler

addIoFiller -cell PADFILLER20 -prefix IOFILLER

addIoFiller -cell PADFILLER10 -prefix IOFILLER
addIoFiller -cell PADFILLER5 -prefix IOFILLER
addIoFiller -cell PADFILLER1 -prefix IOFILLER
addIoFiller -cell PADFILLER05 -prefix IOFILLER fill any gap
addIoFiller -cell PADFILLER0005 -prefix IOFILLER -fillAnyGap 103
 import floorplan powerplan placement CTS routing

Edit Route
hotkey : e 




Duplicate wire

Fix Wire Wider than Max Width

Change layer Split wire Trim wire Clear DRC markers
Change width Merge wire Delete wire
104
import floorplan powerplan placement CTS routing

Edit Route cont.

Trim wire
(hotkey : T)

Fix wire wider

than max width

105
import floorplan powerplan placement CTS routing

Edit Route cont.

Move Wire
Add Wire

Cut Wire

Stretch Wire

106
import floorplan powerplan placement CTS routing

Edit Route cont.

• Edit Route Form

107
 import floorplan powerplan placement CTS routing

Edit Power Via

• PowerPower PlanningEdit Power Via…
import floorplan powerplan placement CTS routing

Clock Problem
• Clock problem
– Heavy clock net loading
– Long clock insertion delay
– Clock skew
– Skew across clocks
– Clock to signal coupling effect
– Clock is power hungry

109
import floorplan powerplan placement CTS routing

Clock Tree Topology

CLK
110
import floorplan powerplan placement CTS routing

Clock Concurrent Optimization

import floorplan powerplan placement CTS routing

CCOpt/CCOpt-CTS Flow
import floorplan powerplan placement CTS routing

Configure CCOpt/CCOpt-CTS
 Configure Route Type
create_route_type -name leaf_rule -non_default_rule CTS_2W1S
-top_preferred_layer M5 -bottom_preferred_layer M4

create_route_type -name trunk_rule -non_default_rule CTS_2W2S

-top_preferred_layer M7 -bottom_preferred_layer M6
-shield_net VSS -bottom_shield_layer M6

create_route_type -name top_rule -non_default_rule CTS_2W2S

-top_preferred_layer M9 -bottom_preferred_layer M8
-shield_net VSS -bottom_shield_layer M8

set_ccopt_property -net_type leaf route_type leaf_rule

set_ccopt_property -net_type trunk route_type trunk_rule
set_ccopt_property -net_type top route_type top_rule

set_ccopt_property routing_top_min_fanout 10000

 NON DEFAULT RULE

LEF NONDEFAULTRULE CTS2W2S

LAYER M1
WIDTH 0.24 ;
SPACING 0.2 ;
END M1
LAYER M2
WIDTH 0.28 ;
SPACING 0.3 ;
END M2
LAYER M3
WIDTH 0.28 ;
SPACING 0.3 ;
END M3
MINCUTS VIA1 4 ;
MINCUTS VIA2 4 ;
END CTS2W2S

115
 Configure Library Cells
set_ccopt_property buffer_cells { BUFX12 BUFX8 BUFX6 BUFX4 BUFX2 }

set_ccopt_property inverter_cells { INVX12 INVX8 INVX6 INVX4 INVX2 }

set_ccopt_property clock_gating_cells { PREICGX12 PREICG8 PREICGX6 PREICGX4 }

set_ccopt_property use_inverters true

116
 Configure Target Transition
1. Configure the maximum transition target.
set_ccopt_property target_max_trans 100ps

2. CCOpt translate target_max_trans_sdc property form sdc

set_max_transition constraints.
If target_max_trans is not set, the target_max_trans_sdc will be inspected.

117
 Configure Target Skew
• Configure a skew target for CCOpt-CTS (ccopt_design -cts).
• This is ignored by CCOpt (ccopt_design).

set_ccopt_property target_skew 50ps

118
 Create CCOpt clock tree spec
Create a clock tree specification by analyzing the timing graph structure of all
active setup and hold analysis views
create_ccopt_clock_tree_spec
or written to a file for inspection and then loaded
create_ccopt_clock_tree_spec -file ccopt.spec
source ccopt.spec
A clock tree specification contains clock_tree, skew_group, and property settings.

119
 CCOpt clock tree spec
• A clock tree specification contains clock_tree,
skew_group, and property settings.

120
 Source Latency Update
• CCOpt and CCOpt-CTS update sdc constraint automatically
1. switch clocks to propagated mode
2. update source latencies of clock root
• To disable source latency update，use：
set_ccopt_property update_io_latency false

121
 Outer CCOpt commnad
set_ccopt_property
get_ccopt_property
delete_ccopt_clock_tree_spec
reset_ccopt_config
report_ccopt_clock_trees
report_ccopt_skew_groups
……

122
 CCOpt Clock Tree Debugger
ClockàCCOpt Clock Tree Debugger..

123
import floorplan powerplan placement CTS routing

Trial Route
• perform quick routing for congestion and
parasitics estimation
• Prototyping:
 Quickly to gauge the feasibility
of netlist.
 components in design might not
routed at legal location

124
 import floorplan powerplan placement CTS routing

Trial Route Congestion Marker

• visually check the congestion statistics.

25/20

The vertical (V) overflow is 25/20

(25 tracks are required , but only 20 tracks are
available) .

125
import floorplan powerplan placement CTS routing

Trial Route Congestion Marker cont.

• Set Congection Map Stype
– RouteàNanoRouteà Analysis Congection…

Level Color Overflow Value

0 Black <-2
1 Blue -1
2  Green 0
3  Yellow 1
4  Red 2
5  Magenta 3
6 and higher  Grey to White >4
126
 import floorplan powerplan placement CTS routing

Timing Analysis

TimingàReport Timing …
placement

Routing

Extract RC

Delay calculation

Timing analysis

127
import floorplan powerplan placement CTS routing

Timing Debug
TimingàDebug Timing
import floorplan powerplan placement CTS routing

Timing Debug
TimingàDebug Timing

129
 import floorplan powerplan placement CTS routing

Timing Path Analyzer set drive

input delay
D

CK

Data Path CLK

clock latency

setup uncertainty
drive adjustment

negative slack

130
import floorplan powerplan placement CTS routing

Timing Path Analyzer

Clock Path

131
 import floorplan powerplan placement CTS routing

Timing Path Analyzer

Path SDC

setup uncertainty
drive adjustment

negative slack

132
import floorplan powerplan placement CTS routing

Timing Path Analyzer

Timing Interpretation

133
import floorplan powerplan placement CTS routing

Timing Path Analyzer

Schematic

134
import floorplan powerplan placement CTS routing

Timing Path Analyzer reg2reg D D

latency CK CK
CLK latency

135
import floorplan powerplan placement CTS routing

Timing Path Analyzer reg2out set output load

D
set output delay
latency CK

CLK

136
import floorplan powerplan placement CTS routing

Debug Hold Time

137
 import floorplan powerplan placement CTS routing

Optimization

Optimizeà Optimize Design…

• Optimization
– setup time
– hold time
– DRV (Design Rule
Violation)

138
import floorplan powerplan placement CTS routing

Mode Setup -- Optimization

139
 import floorplan powerplan placement CTS routing

Useful Skew

11ns 9ns

After CTS
1ns
10ns

balanced clock

9ns 11ns 10ns

Before CTS

-1ns

10ns
schedule clock
140
import floorplan powerplan placement CTS routing

Power Analysis

SET SET
D Q D Q

CLR Q CLR Q

SET SET
D Q D Q

CLR Q CLR Q

SET SET
D Q D Q

CLR Q CLR Q

141
 Power Component
• dynamic power
– switching power switching power

• P=f*1/2CV2
– internal power
Internal power

• static power DFF

– leakage power rst

Q
clk

D
reverse bias

142
import floorplan powerplan placement CTS routing

Internal Power Model

I1
I2
I3
Req
Ceq

143
143
import floorplan powerplan placement CTS routing

Power Analysis

simulation SDF gate-level Power

pattern netlist model

simulation toggle
Simulation TCF/VCD Power Analysis Power
model probability
report

144
 Switching Activity Information
setAnalysisMode -analysisType bcwc
write_sdf
• Get VCD file by simulation -max_view av_func_mode_max \
-typ_view av_func_mode_typ \
– save netlist for simulation -min_view av_func_mode_min \
• FileàSaveàNetlist… -edges noedge \
-splitsetuphold \
– save sdf for simulation -remashold \
• TimingàWrite SDF… -splitrecrem \
-min_period_edges none \
CHIP.sdf

– simulation and dump vcd file. (CELL

• $dumpvars; (CELLTYPE "INVXL")
(INSTANCE DFT_shared_out_mux_6)
• $dumpfile(“wave.vcd”); (DELAY
(ABSOLUTE
– Input vcd file for power analysis (IOPATH A Y (0.14:0.29:0.32) (0.08:0.17:0.23))
)
)
) 145
 import floorplan powerplan placement CTS routing

Power Analysis

• Create power grid library ( required by dynamic power analysis mode)

– Setup library mode:
• PoweràRail Analysisà Set PG Library Mode
– Create library
• PoweràRail Analysisà Generate PG Library

• Run Power Analysis

– Set power analysis mode
• PoweràPower AnalysisàSetup…
– run power analysis
• PoweràPower AnalysisàRun …

146
import floorplan powerplan placement CTS routing

Power Grid Library Mode

PoweràRail AnalysisàSet PG Library Mode…

147
import floorplan powerplan placement CTS routing

Create Power Library

PoweràRail AnalysisàGenerate PG Library

 power grid view contain

 tap location
 tap capacitance
 tap current
 internal resistor grid
 device decoupling

148
import floorplan powerplan placement CTS routing

Power Analysis
PoweràPower AnalysisàSetup…

149
import floorplan powerplan placement CTS routing

Power Analysis
PoweràPower AnalysisàRun…

150
 import floorplan powerplan placement CTS routing

Power Analysis result

• Power report
Group Internal Switching Leakage Total Percentage
Power Power Power Power (%)
----------------------------------------------------------------------------------------------------
Sequential 22.07 2.88 0.00354 24.96 30.61
Macro 3.228 0.03977 0.01 3.278 4.02
IO 17.96 14.97 0.003231 32.93 40.39
Combinational 9.817 6.712 0.005406 16.53 20.28
Clock (Combinational) 1.493 2.341 0.000202 3.835 4.703
Clock (Sequential) 0 0 0 0 0
----------------------------------------------------------------------------------------------------
Total 54.57 26.95 0.02238 81.54 100

• Power DB
• Instance current file

151
import floorplan powerplan placement CTS routing

Power Histograms…
PoweràReportàPower Histograms…

152
 import floorplan powerplan placement CTS routing

Power & Rail Results

PoweràReportà
Power&Rail Results… 

153
import floorplan powerplan placement CTS routing

Power Graph – Instance Total Power

154
import floorplan powerplan placement CTS routing

Power Graph – Instance transistion Density

155
import floorplan powerplan placement CTS routing

Rail Analysis

simulation

VCD/SAIF

power analysis

instance current

rail analysis

156
 import floorplan powerplan placement CTS routing

Rail Analysis

• Create power grid library ( required by dynamic rail analysis)

– Setup:
• PoweràRail Analysisà Set PG Library Mode
– Generate:
• PoweràRail Analysisà Generate PG Library
• Run Rail Analysis
– Set rail analysis mode
• PoweràRail AnalysisàSet Rail Analysis Mode…
– run rail analysis
• PoweràRail AnalysisàRun Rail Analysis…

157
import floorplan powerplan placement CTS routing

Rail Analysis
PoweràRail AnalysisàSet Rail Analysis Mode…

158
import floorplan powerplan placement CTS routing

Rail Analysis
PoweràRail AnalysisàRun Rail Analysis…

159
import floorplan powerplan placement CTS routing

Pad Location File



160
 import floorplan powerplan placement CTS routing

Power & Rail Results


PoweràReportà
Power&Rail Results… 

161
import floorplan powerplan placement CTS routing

Power Graph – IR drop

I3 I2 I1

162
import floorplan powerplan placement CTS routing

Power Graph – Electromigration

163
import floorplan powerplan placement CTS routing

Dynamic Waveforms
PoweràReportàDynamic Waveforms…

164
import floorplan powerplan placement CTS routing

NanoRoute
RouteàNanoRouteàRoute



 Optimize Via

Optimize Wire

165
 Crosstalk

Crosstalk problem are getting more serious in 0.25um and below

for:
 Smaller pitches
 Greater height/width ratio
 Higher design frequency

166
 SI Problem

Aggressor
 Delay problem
original signal

impacted signal

 Noise problem Aggressor

original signal

impacted signal

167
 SI Prevention

 Placement solution
 Insert buffer in lines Add buffer
 Upsize driver
 Congestion optimization Upsize

 Routing solution
 Limit length of parallel nets
 Wider routing grid
 Shield special nets

168
import floorplan powerplan placement CTS routing

SI Analysis

TimingàReport Timing …

169
 import floorplan powerplan placement CTS routing

Verify Gemoetry

VerifyàVerify Geometry

170
 import floorplan powerplan placement CTS routing

Verify Connectivity

VerifyàVerify Connectivity
D Q D Q

CLK CLK

connectivity D Q D Q

database CLK CLK

D Q D Q

CLK CLK

layout
database

171
import floorplan powerplan placement CTS routing

Verify process Antenna

VerifyàVerify Process Antenna…

172
import floorplan powerplan placement CTS routing

Antenna Effect

 In a chip manufacturing process, Metal is initially deposited so

it covers the entire chip.
 Then, the unneeded portions of the metal are removed by
etching, typically in plasma(charged particles).
 The exposed metal collect charge from plasma and form voltage
potential.
 If the voltage potential across the gate oxide becomes large
enough, the current can damage the gate oxide.

173
 import floorplan powerplan placement CTS routing

Antenna Ratio

Plasma
metal2 metal2 Plasma
via2 + + + + + ++ + + + metal1 + + +
via1

poly gate oxide

Area of process antennas on a node

Antenna Ratio =
Area of gates to the node

174
 import floorplan powerplan placement CTS routing

Antenna Problem Repair

• Add jumper
• Add antenna cell (diode)
metal2
• Add buffer

via1 metal1
poly
gate oxide

175
 Add Core Filler
import floorplan powerplan placement CTS routing export

PlaceàFilleràAdd Filler…
• Connect the NWELL/PWELL layer in core rows.
• Insert Well contact.
• Add from wider filler to narrower filler.
gap
core filler

well

176
 Add bonding pads
import floorplan powerplan placement CTS routing export

Linear IO pad Stagger IO pad

Abutted Stagger IO
PIN

Logic and driver

PR boundary

Bonding matel

Inner Bonding

Outer Bonding
177
 Circuit Under Pad

traditional bonding pad CUP bonding pad

200 um

178
 Add bonding pads
import floorplan powerplan placement CTS routing export

• For the limitation of bonding wire technique , the

stagger IO pads are used in order to reduce IO pad
width.
• We have to add the bonding pads after APR is finished if
stagger IO pads is used. But Encounter does not provide
a built-in function for add bonding pads, CIC reaches
this purpose by the way of importing DEF.
• CIC provides a perl script to calculate the bonding pad
location. The full flow is described in next page

179
Add bonding pads flow (stagger IO pads only)
import floorplan powerplan placement CTS routing export

A placed and routed Export DEF routed.def

design in encounter (In encounter)

addbonding_v3.pl addbonding_v3.pl routed.def

(In unix terminal) addbond.cmd

io.list

source addbond.cmd
(In encounter terminal)

finish
180
 Add Dummy Metal
• Why add dummy
– meet minimize metal density rule
– prevent over etching
– prevent sagging in local area
– improve yield
– reduce on chip variation
• better connect dummy metal to VSS
• Side effect
– introduce parasitic to signal line

181
Add Dummy Metal
RouteàMetal FillàSetup…

182
Add Dummy Metal
RouteàMetal FillàAdd…

183
 Add text IOVDD & IOVSS
import floorplan powerplan placement CTS routing export

add_text -layer METAL5 -label IOVSS -pt 1365 1095 -height 10

add text location

184
 Output Data
import floorplan powerplan placement CTS routing export

DesignàSaveàGDS…
DesignàSaveàNetlist…
write_sdf
DesignàSaveàDEF

• Export GDS for DRC,LVS,LPE,and tape out.

• Export Netlist for LVS and simulation.
• Export Netlist and sdf for post layout simulation
• Export DEF for reordered scan chain.

185
 Export sdf

 source savesdf.cmd
savesdf.cmd
setAnalysisMode -analysisType bcwc
write_sdf -max_view av_func_mode_max \
-typ_view av_func_mode_typ \
-min_view av_func_mode_min \
CHIP.sdf
-edges noedge \ (CELL
-splitsetuphold \ (CELLTYPE "INVXL")
(INSTANCE DFT_shared_out_mux_6)
-remashold \ (DELAY
(ABSOLUTE
-splitrecrem \ (IOPATH A Y (0.14:0.29:0.32) (0.08:0.17:0.23))
)
-min_period_edges none \ )
)
CHIP.sdf
186
 Stream Out
EditàSaveàGDS/OASIS…

• source savegds.cmd savegds.cmd

streamOut CHIP.gds \
 -mapFile streamOut.map \
 -merge { gds/RF2SH64x16.gds \
gds/tpb973gv.gds \
gds/tsmc18_core.gds \
gds/tsmc18_io.gds } \
-stripes 1 -units 1000 -mode ALL

187
 Stream Out

• Merge gds
only cell name and location full cell layout information

cell gds

188
 import floorplan
Stream Out map
powerplan placement CTS routing export

 Layer/object name layer/object type layer number data type

METAL1 ALL 16 0
NAME METAL1/NET 16 0
NAME METAL1/SPNET 40 0
NAME METAL1/PIN 40 0
NAME METAL1/LEFPIN 16 0
VIA12 ALL 17 0
METAL2 ALL 18 0
…
…

189
 Chapter 2

Encounter Foundation Flow

190
 Flow feature
• The recommended flow to implement a block of
flat chip from a completed floorplan.
• A single source of all data required to run design
• A flow environment that is both structured and
flexible

191
Flow Step

192
 Create Flow Environment
1. Create Flow template
– FlowsàCreate Foundation Flow TemplateàSave
– writeFlowTemplate or
2. Prepare setup file
– FlowsàFoundation Flow Wizard…
– SCRIPTS/gen_edi_setup.tcl or
3. Generate script
– SCRIPTS/gen_edi_flow.tcl
 Foundation Flow Wizard
• FlowsàFoundation Flow Wizard…
Library
Design
Timing
Power
Tool Setup
User Plug-in
 Environment setup
• setup file (by Foundation Flow Wizard)
– setup.tcl
– edi_config.tcl
– lp_config.tcl
• Create Flow script
– SCRIPTS/gen_edi_flow.tcl
• Generate tcl script
• Generae Makefile

• Execution
– make make_target

201
 Flow Environment Structure
file or directory description
setup.tcl design data setup
edi_config.tcl
lp_config.tcl
Makefile make file
FF/ flow script
RPT/ timing/clock/verification report
DBS/ encounter data save
LOG/ command log and message log
make/ makefile flow control
PLUG/ user custom plugin
202
 Data Prepare
• EDI System configuration file (setup.tcl)
– Timing libraries
– Lef libraries
– timing constraints
– capacitane table or QRC technology file
– SI libraries
• Verilog netlist
• Floorplan file
• clock Tree Specification file
• Scan Chain information
• GDS Layer map file

203
 Flow control
make target Script DBS condition

init run_init.tcl Init.enc make/init

place run_place.tcl place.enc make/place

prects run_prects.tcl prects.enc make/prects

cts run_cts.tcl cts.enc make/cts

postcts run_postcts.tcl postcts.enc make/postcts

postcts_hold run_postcts_hold.tcl postcts_hold.enc make/postcts_hold

route run_route.tcl route.enc make/route

postroute run_postroute.tcl postroute.enc make/postroute

postroute_hold run_postroute_hold.tcl postroute_hold.enc make/postroute_hold

signoff run_signoff.tcl signoff.enc make/signoff

204
 Files in Plug directory

always_source.tcl pre_postcts_hold.tcl
pre_init.tcl post_postcts_hold.tcl
post_init.tcl pre_route.tcl
pre_partition.tcl post_route.tcl
pre_place.tcl pre_postroute.tcl
post_place.tcl post_postroute.tcl
pre_place_checks.tcl pre_postroute_hold.tcl
pre_prects.tcl post_postroute_hold.tcl
post_prects.tcl pre_postroute_si_hold.tcl
pre_cts.tcl post_postroute_si_hold.tcl
pre_postroute_si.tcl
post_cts.tcl
post_postroute_si.tcl
pre_postcts.tcl pre_signoff.tcl
post_postcts.tcl post_signoff.tcl

205
 Chapter3

Post-Layout Verification –
DRC/ERC/LVS/LPE
 Post-Layout Verification Overview

• Post-Layout Verification do the following

things :
– DRC ( Design Rule Check )
– ERC (Electrical Rule Check )
– LVS (Layout versus Schematic )
– LPE/PRE (Layout Parasitic Extraction / Parasitic
Resistance Extraction) and Post-Layout Simulation.

207
 Post-Layout Verification Overview cont.

DRC LVS
vdd!

i zn compare with i zn

0 1 2 3 VSS!

ERC LPE/PRE
vdd! clk
vdd!
short
extract
i zn i zn

VSS! 208
 DRC flow

• Prepare Layout
• Prepare command file
• run DRC
• View DRC error (DRC summary/RVE)

209
 Prepare Layout

• stream out with cell gds merged

• be sure to use layer map file
provided by CIC

210
 Prepare command file

• Prepare DRC Command file:

– TSMC 90nm (CBDK_TSMC90G_Arm) Calibre
• CLN90S_3XTM_9M.22a1
– TSMC 0.18 (CBDK018_TSMC_Artisan) Calibre
• CLM18_LM16_6M.28a_m.drc

211
 Prepare Calibre Command file
• Edit runset file
LAYOUT PATH “CHIP.gds2”
LAYOUT PRIMARY “CHIP”
LAYOUT SYSTEM GDSII
…
…
…
DRC SELECT CHECK
NW.W.1
NW.W.2
…
DRC UNSELECT CHECK
NW.S.1Y
NW.S.2Y
…
DRC ICSTATION YES
INCLUDE “Calibre-drc-cur”

212
 Submit Calibre Job

• Submit Calibre Job

– unix% calibre –drc CLM18_LM16_6M.28a_m.drc
– Result log
– DRC.sum (ASCII result)
– DRC.db (Graphic result)

213
 View Calibre result in SOC Encounter

ToolsàViolation Browser…

214
 Calibre Interactive In Encounter
• STEP1
– source calibre.cshrc
– source edi.cshrc
– exec encounter
– In encounter terminal:
source /usr/cad/mentor/calibre/cur/lib/cal_enc.tcl
Calibre menu in Encounter
 Setup streamout options
• STEP2 : calibreàSetupàGDS Export

streamOut CHIP.gds \
-mapFile streamOut.map \
-merge { gds/RF2SH64x16.gds \
gds/tpb973gv.gds \
gds/tsmc18_core.gds \
gds/tsmc18_io.gds } \
-stripes 1 -units 1000 -mode ALL
 Calibre Interactive
• STEP3: calibreàRun nmDRC
Calibre RVE
 LVS Overview
Layout Data Schematic Netlist

VDD clk rst cin sel VSS VDD

a<0> b<0>
a<1> b<1> a<5:0>

a<2> b<2> b<5:0>

s<5:0>
a<3> b<3> clk

a<4> b<4> rst

carry
a<5> b<5> cin

VDD VSS! sel

VSS s<0> s<1>. . . . . VSS

220
 Initial Correspondence Points

• Initial correspondence points establish a

starting place for layout and schematic
comparison.
• Create initial correspondence node pairs by
– adding text strings on layout database.
– all pins in the top of schematic netlist
VDD
will be
global pin : VDD and VSS

treated as .an
..
initial corresponding a<0>
node if calibre ...
finds
a<0>
b<0>
a text string in layout
initial corresponding
which
b<0>
matches the
node name innode schematic.
pairs
...

221
 Black-Box LVS
Calibre black-box LVS
– One type of hierarchical LVS.
– Black-box LVS treats every library cell as a black box.
– Black-box LVS checks only the interconnections between
library cells in your design, but not cell inside.
– You need not know the detail layout of every library cells.
– Reduce CPU time.

222
Black-Box LVS vs. Transistor-Level LVS

Transistor Level LVS

VDD

i1 z
i1 z
i2 vs.
i2
VSS

Black-Box LVS
inv0d1
VDD nd02d1
inv0d1 nd02d1 i1
i1 z z
vs.
i2
VSS

i2 223
 LVS flow
• Prepare Layout
– The same as DRC Prepare Layout
• Prepare Netlist
– v2lvs
• Prepare calibre command file
• run calibre LVS
• View LVS error (LVS summary/RVE)

224
 Prepare Netlist for Calibre LVS

Prepare Netlist
Verilog
tsmc_18lvs.v
CHIP.v
tpz973gv_lvs.v

v2lvs
tsmc_18lvs.spi
tpz973gv_lvs.spi
source.spi

• v2lvs –v CHIP.v –l tsmc18_lvs.v –l tpz973gv_lvs.v –s tsmc18_lvs.spi –s tpz973gv_lvs.spi –o

source.spi –s1 VDD –s0 VSS
If a macro DRAM64x16 is used
• v2lvs –v CHIP.v –l tsmc18_lvs.v –l tpz973gv_lvs.v –l DRAM64x16.v –s tsmc18_lvs.spi –s
tpz973gv_lvs.spi –s DRAM64x16.spi –o source.spi –s1 VDD –s0 VSS

225
 CIC Supported Files (tsmc0.18)

 CIC supports the following files in our cell library design kit.
 Calibre LVS rule file
Calibre.lvs
 Black-box LVS relative files
 pseudo spice file
tsmc18_lvs.spi
tpz973gv_lvs.spi
 pseudo verilog file
tsmc18_lvs.v
tpz973gv_lvs.v

226
 Black Box related file
• Pseudo spice file
.GLOBAL VDD VSS
.SUBCKT AN2D1 Z A1 A2 VDD VSS
.ENDS
…

• Pseudo verilog file

module AN2D1 (Z, A1, A2);
output Z;
input A1;
input A2;
endmodule
…

227
 Generate Pseudo Verilog file
module RF2SH64x16 (
• gen pseudo verilog for from simulation model, but leaving QA,
only header definition. AA,
CLKA,
• gen pseudo spice by run v2lvs on pseudo verilog CENA,
AB,
unix% v2lvs –v RF2SH64x16.v DB,
CLKB,
CENB
.SUBCKT RF2SH64x16 QA[15] QA[14] QA[13] QA[12] QA[11] QA[10] QA[9] QA[8] QA[7] );
+ QA[6] QA[5] QA[4] QA[3] QA[2] QA[1] QA[0] AA[5] AA[4] AA[3] AA[2] AA[1] AA[0] output [15:0] QA;
+ CLKA CENA AB[5] AB[4] AB[3] AB[2] AB[1] AB[0] DB[15] DB[14] DB[13] DB[12] input [5:0] AA;
+ DB[11] DB[10] DB[9] DB[8] DB[7] DB[6] DB[5] DB[4] DB[3] DB[2] DB[1] DB[0] input CLKA;
+ CLKB CENB input CENA;
.ENDS input [5:0] AB;
input [15:0] DB;
• ADD VDD VSS port on pseudo spice input CLKB;
input CENB;
.SUBCKT RF2SH64x16 QA[15] QA[14] QA[13] QA[12] QA[11] QA[10] QA[9] QA[8] QA[7]
+ QA[6] QA[5] QA[4] QA[3] QA[2] QA[1] QA[0] AA[5] AA[4] AA[3] AA[2] AA[1] AA[0] endmodule
+ CLKA CENA AB[5] AB[4] AB[3] AB[2] AB[1] AB[0] DB[15] DB[14] DB[13] DB[12]
+ DB[11] DB[10] DB[9] DB[8] DB[7] DB[6] DB[5] DB[4] DB[3] DB[2] DB[1] DB[0]
+ CLKB CENB VDD VSS
.ENDS
228
Prepare command file for Calibre LVS

• Edit Calibre LVS runset

LAYOUT PATH “CHIP.calibre.gds”
LAYOUT PIMARY “CHIP”
LAYOUT SYSTEM GDSII
SOURCE PATH “source.spi”
SOURCE PRIMARY “CHIP”
…
…
INCLUDE “/calibre/LVS/Calibre-lvs-cur”

 Edit Calibre LVS rule file

…
…
LVS BOX PVSSC
LVS BOX PVSSR
LVS BOX DRAM64x4s

229
 Submit Calibre LVS

• calibre –lvs –spice layout.spi –hier –auto Calibre.lvs > lvs.log

layout verilog

extract v2lvs

layout.spi source.spi

230
 Check Calibre LVS Summary

• OVERALL COMPAISON RESULTS

• CELL SUMMARY
• INFORMATION AND WARNINGS
• Initial Correspondence Points

231
 Check Calibre LVS Summary
OVERALL COMPAISON RESULTS

OVERALL COMPARISON RESULTS

# ################### _ _
# # # * *
# # # CORRECT # |
# # # # \___/
# ###################

232
 Check Calibre LVS Summary
CELL SUMMARY

*************************************************
CELL SUMMARY
*************************************************

Result Layout Source

----------- ----------- --------------
CORRECT CHIP CHIP

233
 Check Calibre LVS Summary
INFORMATION AND WARNINGS

******************************************************************
INFORMATION AND WARNINGS
******************************************************************

Matched Matched Unmatched Unmatched Component

Layout Source Layout Source Type
----------- ----------- -------------- --------------- --------------
Nets: 11525 11525 0 0

Instances: 1 1 0 0 ADDFHX1
54 54 0 0 ADDFHX4
79 79 0 0 ADDFX2
542 542 0 0 AND2X1
…… …… .. .. ………….
8 8 0 0 XOR3X2
----------- ----------- -------------- --------------- --------------
Total Inst: 10682 10682 0 0

234
 Check Calibre LVS Summary
Initial Correspondence Points

Initial Correspondence Points:

Nets: VDD VSS I_X[2] I_X[3] I_X[4] I_X[5] I_X[6] I_X[7] I_X[8] I_X[9] I_X[10]
I_X[11] O_SCAN_OUT O_Z[0] O_Z[1] O_Z[2] O_Z[3] I_HALT I_RESET_ I_DoDCT
I_RamBistE I_CLK I_SCAN_IN I_SCAN_EN I_X[0] O_Z[4] I_X[1] O_Z[5] O_Z[6]
O_Z[7] O_Z[8] O_Z[9] O_Z[10] O_Z[11]

235
 Check Calibre LVS Log
• TEXT OBJECT FOR CONNECTIVITY EXTRACTION
• PORTS
• Extraction Errors and Warnings for cell “CHIP”

236
 Check Calibre LVS Log
TEXT OBJECT FOR CONNECTIVITY EXTRACTION

--------------------------------------------------------------------------------
TEXT OBJECTS FOR CONNECTIVITY EXTRACTION
--------------------------------------------------------------------------------
O_Z[0] (523.447,31.68) 105 CHIP O_Z[1] (598.068,31.68) 105 CHIP
O_Z[2] (821.931,31.68) 105 CHIP O_Z[3] (896.553,31.68) 105 CHIP
O_Z[4] (971.175,31.68) 105 CHIP O_Z[5] (1164.455,372.964) 105 CHIP
O_Z[6] (1164.455,446.966) 105 CHIP O_Z[7] (1164.455,520.968) 105 CHIP
O_Z[8] (1164.455,594.97) 105 CHIP O_Z[9] (1164.455,668.972) 105 CHIP
O_Z[10] (1164.455,742.974) 105 CHIP O_Z[11] (1164.455,816.976) 105 CHIP
……
……

237
 Check Calibre LVS Log
PORTS

--------------------------------------------------------------------------------
PORTS
--------------------------------------------------------------------------------
O_Z[0] (523.447,31.68) 105 CHIP O_Z[1] (598.068,31.68) 105 CHIP
O_Z[2] (821.931,31.68) 105 CHIP O_Z[3] (896.553,31.68) 105 CHIP
O_Z[4] (971.175,31.68) 105 CHIP O_Z[5] (1164.455,372.964) 105 CHIP
……
……

238
 Check Calibre LVS Log
Extraction Errors and Warnings for cell “CHIP”

Extraction Errors and Warnings for cell "CHIP"

----------------------------------------------

WARNING: Short circuit - Different names on one net:

Net Id: 18
(1) name “VSS" at location (330.301,216.95) on layer 102 "M2_TEXT"
(2) name “VSS" at location (673.2,29.1) on layer 101 "M1_TEXT"
(3) name "VDD" at location (748.1,31.5) on layer 101 "M1_TEXT"
(4) name "VDD" at location (208.93,274.56) on layer 101 "M1_TEXT"
The name "VDD" was assigned to the net.

239
Chapter4

Post-Layout Timing Analysis

-- Nanosim
What Introduce After Place&Route?
• Interconnection wire’s parasitic capacitance.
M1 to substrate
M2 capacitance

M1 to M1
capacitance
M1

M1 to M2
capacitance
vdd! vdd!

VSS! VSS!
241
What Introduce After Place&Route?
• Interconnection wires’ parasitic resistance.
M2 M1 parasitic resistance

VIA

M1 VIA parasitic resistance

vdd! vdd! M2 parasitic resistance

VSS! VSS!

242
 Pre-Layout And Post-Layout Design
• A pre-layout design (before P&R) and a post-
layout design (after P&R)
pre-layout

post-layout

243
 Post-layout Timing Analysis Flow

Gate-level
Netlist

Gate-level
Analysis

Tr.-level post-layout
timing analysis Layout
Delay
Calculation
Extraction

Tr. Netlist
RC Network
RC Network Gate-level post-layout
timing analysis

Tr-level
Analysis
244
 Transistor-level Post-layout Simulation

layout

netlist/parasitic
Calibre LPE/PRE
extraction

SPICE netlist

simulation Post-layout
stimulus simulation
VCS-Nanosim

simulation
result
245
 What is Nanosim
• Nanosim is a transistor- level timing simulation tool for
digital and mixed signal CMOS and BiCMOS designs.
• Nanosim handles voltage simulation and timing check.
• Simulation is event driven, targeting between SPICE
( circuit simulator ) and Verilog ( logic simulator ).

246
 Prepare for Post-Layout Simulation
• Apply for a CIC account
– http://www.cic.org.tw  工作站帳號申請.
– fill in your personal data and your request.
• Connect to CIC queue server
– ssh -l your_account queue.cic.org.tw
• Put gds file to your account via ftp

247
 Replace Layout / LPE
Qentry -M DRC -tech TSMC18 -help
Qentry -M [DRC|LPE] -tech TSMC18 Available process technology:
-f gds_file TN40LP
-T top_module TSMC90GUTM
[ -c TSMC18 ]
TN65GP
[ -i TSMC18 ]
[ -s ram_spec_file -t t18ra1shd ] TN40G
[ -s ram_spec_file -t t18ra2sh ] TSMC35
[ -s ram_spec_file -t t18ra2sh ] TSMC25HVG2
[ -s ram_spec_file -t t18rf1sh ] TSMC18
[ -s ram_spec_file -t t18rf2sh ]
[ -s ram_spec_file -t t18rodsh -rom rom_code_file ]
[ -addTagCell ]
[ -addDummyCell ]

Example:
Qentry –M LPE –tech TSMC18 –f CHIP.gds –T CHIP -s RAM1.spec –t
t18ra1sh –s RAM2.spec –t t18ra2sh –s RAM3.spec –t t18ra2sh –c TSMC18 –i
TSMC18 –o CHIP.netlist
Use showq to check the status of your job.
The result is stored in “result_#” directory.

248
 Replace/LPE
• INPUT
– gds2
– ram spec
• OUTPUT
– output netlist
– TOP_CELL.NAME
– nodename
– spice.header
– nanosim.run
– log files for strem in, stream out, lpe

249
 VCS-Nanosim co-simulation
• Architecture

TOP (verilog)

pattern gen DUT1(spice)

(verilog)

DUT2(spice)

250
 VCS-Nanosim co-simulation
• Advantage
– Simulation directly with VCS command and option. In this way,
we no longer need to generate patterns for nanosim
simulation.
– For some case, the test pattern must depend on the response
of the DUT, such as the unpredictable locking time of a PLL. In
this way, this problem can be solved.
– Multi-chip simulation is now available.

251
 Running VCS_Nanosim

• Qentry -M VCS_NS @vcs_argument -ad=vcsAD.init

-ad is a required option for mixed signal simulation
• Example:
–Qentry –M VCS_NS a.v b.v –v tsmc18.v –f vlog.f -ad=vcsAD.init
• Use showq to check the status of your job.
• The result is stored in “result_#” directory.k

252
 Example Design
• Archtecture

test (verilog stimulus module) CHIP_sim.v

CHIP (DUT spice subckt) CHIP.spi

Origial vcs cmd: vcs CHIP_sim.v CHIP.v

• command
– Qentry -M VCS_NS CHIP_sim.v CHIP.v -ad=vcsAD.init

The DUT netlist is CHIP.spi, but a pseudo verilog CHIP.v is needed.

253
 Example Design
• vcsAD.init

indicate CHIP is an analog module config for top

use_spice -cell CHIP ;

choose nanosim -n spice.header CHIP.spi -C TOP.cfg -o wave; output wave name
set bus_format [%d];
set spice_port_order_as_vlog;

DUT

subckt port order match verilog module order

254
 Example Design
• CHIP.v
– A reference module for spice subckt port matching
module CHIP ( IOVDD, IOVSS, VDD, VSS,
CLK, HALT, RESET_, DoDCT,
X, Z, Mode, SCAN_IN,
SCAN_OUT, SCAN_EN);
inout IOVDD, IOVSS, VDD,VSS;
input [11:0] X;
output [11:0] Z;
input CLK, HALT, RESET_, DoDCT, Mode, SCAN_IN, SCAN_EN;
output SCAN_OUT;
endmodule
CHIP.spi
.subckt CHIP IOVSS VSS IOVDD VDD SCAN_OUT X[11] X[10] X[9] X[8] X[7] X[6] X[5]
+ X[4] X[3] Z[0] Z[1] Z[2] Z[3] Z[4] Z[5] X[2] X[1] X[0] HALT RESET_ CLK DoDCT
+ Mode Z[6] SCAN_IN Z[7] Z[8] Z[9] Z[10] Z[11] SCAN_EN
255
 Example Design
• TOP.cfg
set_node_v test.CHIP.IOVDD 3.3
set_node_gnd test. CHIP.IOVSS
set_node_v test.CHIP.VDD 1.8
set_node_gnd test. CHIP.VSS
set_node_cap test. CHIP.Z[11:0] 20p
set_node_cap test. CHIP.SCAN_OUT 20p
report_node_powr test. CHIP.VDD test.CHIP.VSS test.CHIP.IOVDD test.CHIP.IOVSS
print_node_logic test.CHIP.SCAN_OUT
print_node_logic test.CHIP.X[11:0]
print_node_logic test.CHIP.Z[11:0]
print_node_logic test.CHIP.HALT
print_node_logic test.CHIP.RESET_
print_node_logic test.CHIP.CLK nodename file
print_node_logic test.CHIP.DoDCT
X[0]
print_node_logic test.CHIP.Mode X[1]
print_node_logic test.CHIP.SCAN_IN ......
print_node_logic test.CHIP.SCAN_EN CLK
set_print_format for=fsdb file=merge DoDCT
......
bus_notation [ : ] 256
 Example Design
• spice.header
.lib "rf018.l" dio3
.lib "rf018.l" dio_dnw
.lib "rf018.l" dio
.lib "rf018.l" tt_rfres_sa
.lib "rf018.l" tt_rfmvar
.lib "rf018.l" tt_rfind
.lib "rf018.l" tt_rtmom
.lib "rf018.l" tt_bbmvar
.lib "rf018.l" tt
.lib "rf018.l" tt_rfesd
*epic tech="voltage 3.3“
*epic tech="temperature 100"

257
 View Simulation Result --- nWave
• Environment setup
unix% source /usr/cad/synopsys/CIC/verdi.csh

• Starting nWave
unix% nWave &

258
Load Simulation Result --- nWave

259
 Select Signals --- nWave

Signals  Get Signals ...

260
Check Simulation Result --- nWave

261
 Power Analysis Result
• The power analysis result is stored in Nanosim
simulation log (xxx.log) file
. . . . . .
Current information calculated over the intervals:

0.00000e+00 - 1.00010e+03 ns

Node: VDD
Average current : -3.53355e+05 uA
RMS current : 3.53388e+05 uA

Current peak #1 : -4.54061e+05 uA at 6.78400e+02 ns

Current peak #2 : -4.34973e+05 uA at 4.00000e-01 ns
Current peak #3 : -3.88048e+05 uA at 2.59000e+01 ns
Current peak #4 : -3.87280e+05 uA at 1.27500e+02 ns
Current peak #5 : -3.84302e+05 uA at 5.77800e+02 ns
. . . . . .
262