Material and Process Limits in Silicon VLSI

Technology
JAMES D. PLUMMER, FELLOW, IEEE, AND PETER B. GRIFFIN

Invited Paper

The integrated circuit (IC) industry has followed a steady path of

shrinking device geometries for more than 30 years. It is widely be-
lieved that this process will continue for at least another ten years.
However, there are increasingly difficult materials and technology
problems to be solved over the next decade if this is to actually occur
and, beyond ten years, there is great uncertainty about the ability to
continue scaling metal–oxide–semiconductor field-effect transistor
(MOSFET) structures. This paper describes some of the most chal-
lenging materials and process issues to be faced in the future and,
where possible solutions are known, describes these potential solu-
tions. The paper is written with the underlying assumption that the
basic metal–oxide–semiconductor (MOS) transistor will remain the
dominant switching device used in ICs and it further assumes that
silicon will remain the dominant substrate material.
Keywords—Dielectric materials, MOSFETs, semiconductor de-
vice doping, semiconductor device fabrication, silicon.

I. INTRODUCTION Fig. 1. Feature size versus time in silicon ICs.

For more than 30 years, the integrated circuit (IC) industry

has followed a steady path of constantly shrinking device all this has happened has led to an expectation that faster and
geometries and increasing chip size. This strategy has been more powerful chips will continue to be introduced on the
driven by the increased performance that smaller devices same schedule for the foreseeable future. In fact, the semi-
make possible and the increased functionality that larger conductor industry itself has developed a “roadmap” based
chips provide. Together, these performance and functionality on exactly this idea. The National Technology Roadmap for
improvements have resulted in a history of new technology Semiconductors (NTRS) [3] and most recently the Interna-
generations every two to three years, commonly referred tional Technology Roadmap for Semiconductors (ITRS) [4]
to as “Moore’s Law” [1], [2]. Each new generation has now extend this device scaling and increased functionality
approximately doubled logic circuit density and increased scenario to the year 2014, at which point minimum feature
performance by about 40% while quadrupling memory sizes are projected to be 35 nm and chips with com-
capacity. The increase in components per chip comes from ponents are expected to be available. Fig. 1 summarizes the
three key factors first identified by Gordon Moore. The trends in feature size over time.
factor of two in component density comes from a shrink Most of the history represented in Fig. 1 has been
in each lithography dimension. An additional factor of achieved with the same basic switching element (the
comes from an increase in chip area and a final factor of metal–oxide–semiconductor [MOS] transistor), the same
from device and circuit cleverness, providing the overall basic circuit topology (complimentary metal–oxide–semi-
quadrupling in chip capacity. The apparent ease with which conductor [CMOS]), and with a limited number of materials
(Si, SiO , Al, Si N , TiSi , TiN, and W, primarily). While
very substantial human and financial resources have been
Manuscript received January 28, 2000; revised September 20, 2000.
The authors are with Stanford University, Stanford, CA 94305 USA. invested in scaling dimensions and increasing chip sizes over
Publisher Item Identifier S 0018-9219(01)02065-5. the past 40 years, in many respects progress in these areas

0018–9219/01$10.00 © 2001 IEEE

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Fig. 2. Schematic cross section of a modern MOS transistor. Bottom figure is a blowup near the
source/channel boundary. Arrows indicate the current flow path and the resistors illustrate the various
regions that can affect the current drive capability of the device.

has been straightforward in the sense that no fundamentally We will describe in this paper some of the important limits
new inventions have been needed. Obviously, manufacturing and problem areas that will have to be addressed over the next
practices have improved. However, the device structures of 15 years. Many of these will be materials issues since it is
30–40 years ago and the manufacturing processes used then likely that the basic MOS transistor and the basic CMOS cir-
are quite recognizable in today’s IC industry. cuit topology will remain the industry workhorses over this
If the ITRS is a correct predictor of the next 15 years, su- entire period. We will focus primarily on “frontend” issues
perficially much will remain the same as it has for the past in this paper (structures, processes, and materials associated
30–40 years. However, there are many reasons to believe that with the switching devices in chips) since other papers in
continued device scaling will not be as straightforward in the this special issue deal with backend (interconnect) issues and
future as it has been in the past. Practical and/or fundamental with higher level device, circuit, and system issues.
limits are being approached and substantial changes to device
technologies and structures are going to be required. While
II. MOSFETs AT THE SCALING LIMIT—WHAT ARE THE
“inventions” and new materials have largely not been needed
MATERIALS ISSUES?
for the past 30 years, they surely will be needed over the next
15 years. This period will likely be the most challenging that Fig. 2 schematically illustrates the basic metal–
the IC industry has faced because it is likely that during this oxide–semiconductor field-effect transistor (MOSFET)
period we will really understand how far Moore’s Law can device used in today’s silicon chips. The basic fabrication
be extended. In fact, without new materials and inventions, process steps to manufacture such a device have been
we will certainly see the end of Moore’s Law within this pe- broadly described [5]. There are no serious competitors to
riod. It is likely, however, that solutions will be found to the replace this device in the foreseeable future. The basic struc-
difficult problems that lie ahead. The economic motivation ture will continue to evolve to allow continued performance
is substantial and the size of today’s IC industry will permit improvements, but fundamental changes are unlikely in the
enormous resources to be applied to finding solutions. next 15 years.

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Table 1
Selected Data from the NTRS [3], ITRS [4], and Logic Technology Predictions [7]

Various scenarios have been proposed for scaling the There are a number of issues associated with continued
MOSFET device, the simplest of which is due to Dennard MOSFET scaling that represent challenges for the future and,
et al. [6]. The “ideal” scaling they proposed maintains ultimately, fundamental limits. The bold entries in Table 1
constant electric fields in the device by shrinking all correspond to requirements for which there are currently no
voltages, currents, and physical dimensions by the same known solutions or at least no solutions that generally are
factor (typically in each generation) and increasing believed will work in manufacturing. These entries provide
all doping concentrations by the same factor. Actual the main topics for this paper.
scaling scenarios followed by the semiconductor industry The first issue is the gate dielectric thickness. By purely
have not shrunk voltages and currents as rapidly as geometric arguments, the gate insulator in a MOSFET needs
physical dimensions with the result that electric fields to be thin compared to the device channel length in order for
have increased over time. The motivation for doing this the gate to exert dominant control over the channel poten-
is simply the higher device performance achievable (more tial. This avoids “short channel effects,” which are largely the
current drive) when electric fields are increased. It is result of the drain electric field penetrating throughout the
likely that these general trends will continue and, in fact, channel and influencing the channel potential at the source
they are the basis for the NTRS and ITRS projections. side of the device. Practical MOSFET structures generally
Selected data from these roadmaps [3], [4] and logic require the gate dielectric thickness to be a few percent of
technology predictions [7] are shown in Table 1. the channel length. The entries in Table 1 for gate dielec-

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tric thickness are unrealizable starting in 2005 if SiO is the melting. But there are currently no known methods to main-
dielectric material. Oxides thinner than about 1.0–1.5 nm tain these metastable concentrations through the normal heat
conduct direct-tunneling currents too large for most IC ap- cycles required for device fabrication.
plications at the supply voltages listed in the table. A new The resistance of the extension region is also partially de-
higher dielectric constant material system will have to be termined by the formation of a surface accumulation region
employed starting with the 100-nm generation. A “higher ( in Fig. 2) that forms under the gate in the tail region of
” material system will allow a physically thicker dielectric the source/drain profile. This resistance is strongly affected
layer to have an “equivalent SiO thickness” corresponding by the abruptness of the extension profile because the steeper
to the entries in Table 1. Higher dielectric materials are the profile is, the shorter this accumulation region will be.
also needed for dynamic random access memory (DRAM) Thus, the entries in Table 1 for abruptness indicate progres-
storage capacitors. However, the requirements are quite dif- sively sharper profiles as the technology progresses.
ferent in this application because only a charge storage func- The entries in Table 1 related to the doping profile for the
tion is required. The two-dimensional (2-D) effects in a logic source/drain extension regions ( and profile abruptness)
device that arise because of the difference in permittivity be- are also determined by short channel effects in the device.
tween the silicon channel and the gate insulator make the di- Such effects are minimized by shallow and very abrupt
electric requirements very different in logic devices [8]. Gen- junction profiles. Thus, the depth decreases and the slope
erally, the highest dielectric constant possible is needed for becomes steeper in these profiles in the out years of the
DRAMs capacitors as shown in Table 1, whereas materials roadmap. The sheet resistance and depth entries are bold
with dielectric constants up to 30 or so are needed for active starting in 2005 and the slope entries become bold in 2008.
transistor gate insulators. The difficulty in fabricating shallow and very steep profiles
The gate electrode itself also presents some significant arises largely because ion implantation is the assumed
challenges. Polysilicon has been used for more than 25 doping technique and because of this, an anneal must be
years as the gate electrode material. However, decreasing performed to repair implant damage. During this anneal,
its resistivity, as shown in Table 1, implies increasing transient enhanced diffusion (TED) dominates dopant diffu-
the doping levels in the polysilicon, which minimizes the sion, enhancing dopant diffusivities by orders of magnitude.
resistivity of the gate electrode and helps avoid polysilicon This makes it very difficult to keep dopant profiles shallow
depletion effects. But this approach is limited by dopant and steep.
solubility limits and by dopant outdiffusion from the poly
through the thin gate dielectric and into the silicon. This
III. GATE INSULATORS
later problem is particularly acute with P gates because
boron diffuses rapidly through SiO . The likely solution is Of all of the issues outlined in the previous section, the
again new materials—metal gate electrodes. But there are one that requires the nearest term attention is the scaling
no known materials solutions that are known to work in of the gate dielectric. The interface between silicon and its
manufacturing. native oxide SiO is atomically abrupt and electrically per-
The next two rows in Table 1 relate to parasitic resistances fect to first order. This is somewhat surprising because most
in the MOSFET. Ideally, the current drive in a MOSFET is semiconductor/insulator interfaces do not have this combi-
limited by the intrinsic channel resistance ( in Fig. 2). nation of properties. Even in the Si–SiO case, there is a
In practice, all the other resistances in Fig. 2 play a signifi- large volume expansion (2.2 ) that takes place when SiO
cant role and degrade the intrinsic device capability. Normal is thermally grown on silicon, resulting in a highly stressed
design procedures require these other resistances to total less interface with the oxide under compressive stress. Yet the
than 10% of the channel resistance. Such requirements de- Si–SiO system is able to accommodate these stresses and
termine the entries in Table 1 for contact resistivity and for produce a virtually perfect electrical interface with trap and
source/drain extension sheet resistance. Both rows show bold fixed charge densities corresponding to less than one surface
entries beginning in 2005. Contacts are almost always made defect in 10 surface silicon atoms. MOS transistors require
with either TiSi or CoSi contacting heavily doped silicon this level of interface perfection and, thus, any replacement
today. There is no known manufacturable means to reduce for the Si–SiO system will need to at least approach these
the contact resistance ( in Fig. 2) in these systems to standards.
the values specified in Table 1. The entries for source/drain The entries in Table 1 for gate dielectric thickness are
extension sheet resistance ( in Fig. 2) are also in bold unrealizable starting in 2005 if pure SiO is the dielectric
starting in 2005. Here the issue is that the junction depths material. Quantum mechanical tunneling of carriers through
of these extensions ( in Fig. 2) must continue to decrease a barrier increases exponentially with decreasing insulator
to minimize short channel effects. Thus, doping levels in thickness. Oxides thinner than 1.0–1.5 nm operating at 1 V
these regions must increase in order to keep resistances low. conduct direct-tunneling currents too large to accommodate
But doping concentrations are limited by dopant solubility standby power requirements in most IC applications. Thus,
and, hence, there are lower bounds on achievable sheet resis- a new higher dielectric constant material system will have
tances for a given . It is possible to incorporate metastable to be employed starting with the 100-nm generation. In the
doping concentrations well above normal solubilities by laser limit of thin oxides, the wave functions of the gate and the

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Fig. 3. ITRS predictions and Intel logic technology data for gate
oxide thickness versus time.
Fig. 4. Quantum calculation of the inversion (solid lines) and
accumulation (dashed lines) charge distributions in silicon for a
silicon substrate begin to overlap, causing scattering and re- 1.0-nm oxide layer at bias voltages of 2 V using NEMO [11].
duced mobility. This is predicted to occur below 1.0 nm when Polysilicon depletion effect is seen in inversion and the peak
electron and hole charge in the silicon is below the oxide interface
the oxide is approximately five atomic layers thick [9], [10]. because of quantum confinement effects.
The data from the ITRS along with high-performance
logic technology data are plotted in Fig. 3 and show just how
improved activation levels. Thus, to better couple the applied
quickly the oxide thickness limits are being reached. The
gate voltage to the channel region, metal gates that are im-
data in Fig. 3 is given in terms of the equivalent physical
mune to the depletion effect become an attractive option.
oxide thickness, which represents the physical thickness of
The quantum effects in the silicon are fundamental and
the gate dielectric corrected by the ratio of the gate dielectric
occur because of carrier quantum confinement/exclusion in a
constant relative to silicon dioxide. Thus, a silicon nitride
potential field. A quantum calculation of the charge distribu-
gate dielectric ( ) can be almost twice as thick as a
tion using the computer code NEMO [11] is shown in Fig. 4.
silicon dioxide gate dielectric ( ) and still provide
The carriers drop to a low value at the barrier interfaces and
the same electrical coupling of the gate to the channel.
the peak of the carrier distribution moves deeper into the sil-
Not all of the applied gate voltage is efficiently coupled
icon. The contribution to the effective dielectric capacitance
to the channel because of polysilicon depletion effects in the
depends on , where is the silicon dielectric constant
gate electrode and quantum confinement effects in the silicon
(11.7) and is the effective distance of the carriers below the
substrate. The diagram in Fig. 4 indicates that the equivalent
interface, as indicated in Fig. 4.
electrical gate capacitance is composed of a combination of
Many high dielectric constant materials react with silicon
the depletion capacitance in the polysilicon, the physical di-
and, therefore, need a silicon dioxide buffer layer or interface
electric capacitance, and the contribution from quantum ef-
layer between the silicon and the high dielectric. The total
fects in the silicon that shift the peak of the carrier distribu-
capacitance is then given by
tion away from the interface. The combination of poly deple-
tion and the quantum correction add approximately 0.8 nm to
(1)
the equivalent physical oxide thickness to give the equivalent
electrical thickness of the dielectric in the gate capacitor.
The polysilicon depletion effect occurs when the device and is dominated by the capacitance of the low- material
is biased toward inversion and some of the applied voltage (the oxide buffer layer). In terms of the thickness and di-
begins to deplete the highly doped polysilicon near its inter- electric constant of the material, the effective physical oxide
face with the gate dielectric. Increasing the polysilicon active thickness becomes
doping, especially near this interface, helps minimize the de- (2)
pletion effect allowing more of the applied gate voltage to
influence the channel. The ITRS calls for active poly doping
The effective electrical thickness of the dielectric, which is
of 2.2 10 in the 180-nm node, rising to 1.2 10 at the
what determines the capacitive coupling between the gate
35-nm node. Typical maximum activation levels in polysil-
and the channel, is then
icon material near the dielectric interface are less than the
activation levels in the crystalline source/drain, perhaps be- (3)
cause of grain boundaries in the polycrystalline material. It is
unlikely that the high activation levels called for in the ITRS where is the quantum correction for charge in the
can be obtained in polysilicon gates, though in situ doped ma- channel ( 0.3 nm) and is the correction for poly
terial and polycrystalline silicon germanium material show depletion ( 0.5 nm).

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 Fig. 6. Schematic of standby power dissipation current paths in a
CMOS circuit configuration with the NMOS device biased in the ON
state.

off current. In the highest performance applications, active

cooling will be used, which has been shown to be able to
dissipate 1000 W cm on silicon chips [13].
Another way to examine the gate-current problem is to
consider that it is constrained to contribute no more than
Fig. 5. Tunneling currents for oxide thickness from 1.0–2.0 nm the normal off current of a device in the standby mode in a
(dashed lines) versus voltage for an NMOS device in the ON state,
calculated using NEMO [11]. Solid lines represent calculations of
CMOS configuration. As shown in Fig. 6, in a CMOS gate in
the leakage current for a 1.0 nm (comprised of a 0.25-nm oxide layer standby mode with the NMOS gate biased high, an inversion
and 1.5-nm nitride layer) and 1.5 nm (comprised of a 0.5-nm oxide layer exists even though the drain node is discharged and
layer and a 2.0-nm nitride layer) equivalent physical oxide thickness,
showing dramatic improvements in the leakage current.
the source is connected to ground. Tunneling of electrons
from the inversion channel to the positively biased gate
contributes a gate current that should not exceed the off
Fig. 5 shows calculated direct-tunneling currents for var-
current in the positive-channel metal–oxide–semiconductor
ious physical oxide thicknesses at typical bias voltages for
(PMOS) device. In a 100-nm device with an off current of
a negative-channel metal–oxide semiconductor (NMOS) de-
100 nA m , this constrains the gate-current density to be
vice in the ON state. Direct-tunneling current in a MOS device
100 A cm [14], [15]
depends on the combination of tunneling probability and the
number of tunneling carriers. Because of the higher oxide Acm cm
tunneling barrier for holes than for electrons and the heavier
Acm
effective mass of holes, the hole tunneling current is approxi-
mately an order of magnitude less than the electron tunneling nA m (5)
current at any bias condition.
When the gate is positively biased and an NMOS tran- Even if the standby power requirements are relaxed by an
sistor is in the ON state, tunneling occurs between the inver- order of magnitude, this limits the gate oxide thickness to a
sion channel electrons and the polysilicon gate. If we assume value greater than 1 nm.
that the drain current in a 100-nm device is approximately Direct-tunneling currents that flow continuously in thin
1 mA/ m, we can constrain the gate current to be perhaps oxides pose some reliability concerns. Defects such as traps
1% of that without seriously impacting the gain of the de- and interface states gradually build up in the oxide to a point
vice. This constrains the area leakage to be where the oxide suddenly and destructively breaks down
[16]. Because of the exponentially increasing tunneling cur-
m m Acm (4) rent with decreasing oxide thickness, the time to breakdown
decreases unless the gate voltage is sufficiently reduced.
Thus, even extremely high levels of gate leakage current will Avoiding reliability concerns has the same solutions as
not measurably affect the drive current performance of small decreasing the standby power consumption. A material with
devices. At these extreme gate-current levels, the reliability a higher dielectric constant, which does not introduce more
of the thin oxides is of more concern [12]. traps, can increase the time to breakdown by decreasing the
If we assume that a tolerable gate leakage is 100 Acm gate current.
[7] and assume that the gate area is 1% of a 1-cm chip with The tunneling current depends on the effective mass in the
a power-supply voltage of 1 V, the power dissipation due to dielectric, the barrier height, and the barrier thickness, with
the gate current is 1 W. This does not change significantly the tunneling probability for the case of a rectangular barrier
with temperature, while the device off current increases by being given by [17]
a factor of a 100 between room temperature and 100 C and
can approach 10% of the active power. Thus, in the highest
(6)
performance applications where the active power dissipation
will be more than 100 W, the high-gate tunneling currents
may not be a real issue until the power dissipation due to As the bandgap of the insulator increases, the dielectric con-
the gate leakage exceeds the power dissipation due to the stant of binary oxides that might be deposited on silicon tends

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Fig. 7. Bandgap versus dielectric constant for simple binary oxides
[20]. Fig. 8. Interface state density for a potential replacement gate
dielectric [20].

to decrease, as shown in Fig. 7. In general, a large bandgap

is desirable since the barrier height generally scales with the with a “V” shape toward the band edges rather than with the
bandgap. Because of the square-root dependence on the bar- “U” shape typically seen in thermal oxide capacitors [20], as
rier height and the linear dependence on thickness, there is shown in Fig. 8. This was shown to be enough to reduce the
usually an advantage in choosing a higher dielectric constant mobility by a factor of two. Thus, a low value of midgap in-
material when the aim is to reduce the tunneling current. terface state density is no guarantee that mobility will not be
The precise band lineup at the silicon dielectric interface is degraded under device operating conditions.
particularly important for insulators with a smaller bandgap Because of the large number of possible gate dielectric ma-
than SiO . To avoid thermal emission over a Schottky barrier, terials, systematic approaches to suggesting or eliminating
a barrier height of more than 1 eV is needed for both positive candidates are useful. One of the most comprehensive studies
and negative carriers. Silicon dioxide has a large enough bar- of the thermodynamic stability of potential binary oxides was
rier and amply meets this requirement with a barrier of 3.1 eV carried out by Hubbard and Schlom [21]. Its main usefulness
for electrons and 4.7 eV for holes. In general, the band lineup is in predicting when an interfacial buffer layer is likely to be
can be quite asymmetrical, which poses potential problems needed for high dielectrics. Attempts to predict the dielec-
for smaller bandgap materials [18]. For example, Ta O has a tric constant of the high- materials based on simple theory
bandgap of 4.4 eV, but only has an electron barrier of 0.36 eV have been largely unsuccessful. Another general approach to
to silicon, but a 2.9 eV barrier for holes [18]. Thus, Schottky estimating the interfacial properties between a dielectric and
emission of electrons into the conduction band is predicted to silicon is based on considerations of bonding constraints and
be a significant cause of leakage for Ta O films on silicon. coordination number [22]. This study predicted comparable
There should also be few traps in any alternative gate dielec- interface state densities for silicon nitride and for titanium,
tric or leakage currents can increase due to trap-assisted tun- tantalum, and aluminum oxides, all higher than for silicon
neling, which lowers the effective tunneling barrier. dioxide.
Another major barrier any new dielectric material will Because silicon nitride has approximately twice the di-
have to overcome is to achieve almost the same low-defect electric constant of oxide, it is an attractive material for in-
density that occurs at the interface between silicon and creasing the gate dielectric constant [23]. Gate oxides today
silicon dioxide. This is because any improvement in the are heavily nitrided in an NO or N O ambient to reduce boron
drive current caused by better capacitive coupling to the gate penetration and to increase reliability. However, the nitrogen
can easily be lost if the carrier mobility degrades. There is levels at the interface are closely controlled and are in the
an approximate relationship between mobility and interface range of one atomic percent. Higher levels of nitrogen incor-
state density that was empirically found for thermal oxide poration can lead to degraded device characteristics. These
field-effect transistors (FETs) [19] oxynitride gate dielectrics do not have a measurably different
dielectric constant than a pure SiO gate oxide. In order to
(7) raise the dielectric constant, it is necessary to use a nitride
rich or pure silicon nitride layer [24]. It is known that silicon
nitride directly in contact with silicon has a large interface
where cm eV is the concentration of charged state density, which degrades device performance. For this
states at the bias condition. This is the integral of the interface reason, a thin interfacial oxide rich layer is needed with a ni-
state density between the surface potential corresponding to tride dielectric. We can estimate the improvement that a gate
the onset of strong inversion and the band edge. For example, stack consisting of an oxide buffer layer and a nitride dielec-
the interface state density for TiO in contact with silicon tric provides as follows. Fig. 9 shows the relevant parameters
has been reported to be at midgap, rising for the calculation [25].

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 The periodic table in Fig. 10 indicates many of the popular
choices for high- gate dielectrics that have been experimen-
tally investigated, along with the binary oxides predicted to
be stable in contact with silicon at 1000 K from thermody-
namic calculations or experimental review [21].
Titanium and tantalum oxides have been proposed for
high- gate dielectrics [26]–[28]. Thermodynamically,
neither oxide is stable in contact with silicon. Titanium tends
to form the metal silicide while tantalum prefers the metal
phase

Si TiO TiSi SiO G kcal/mol (10)

Fig. 9. Nitride and oxide parameters important for determining
barrier tunneling currents. Si Ta O Ta SiO G kcal/mol (11)

A simple estimate of the improvement in the tunneling cur- A complex ternary interfacial oxide composed of
rent in a stacked dielectric can be obtained as follows [15]. Si–Ta –O , which converted to SiO after annealing,
An equivalent physical oxide thickness of 1.5 nm can be was found at the tantalum oxide/silicon interface [29], [30].
obtained from a 0.5-nm buffer oxide interface layer and a Because these oxides are thermodynamically unstable in
2.0-nm-thick nitride layer for a physical thickness of 2.5 nm contact with silicon, an SiO barrier layer must be used.
High-leakage currents are reported with polysilicon gates
[20], so if polysilicon gates are used, barrier layers must
nm (8) be formed at both interfaces to produce good results [31].
When the object is to form a layer equivalent to a 1.0-nm
physical oxide, this leaves little process margin.
Because the tunneling probability for the composite stack Oxides of hafnium and zirconium are medium- materials
based on (6) is proportional to that are thermodynamically predicted to be stable in contact
with silicon. Hafnium and zirconium can be thought of as
the transition metal counterparts of the column 4 tetrahedral
(9)
solids and their oxides have a structure like SiO . Since they
are elements from column D4 of the periodic table with four
the composite layer with a 0.5-nm SiO buffer layer and a electrons in states, there are just enough electrons to replace
2.0-nm Si N layer will have a tunneling probability sim- the silicon. In practice, sputtered material forms an interfacial
ilar to that of a 2.1-nm physical SiO layer. Thus, the gain layer upon annealing which appears to be a silicate layer [32],
from a nitride layer amounts to 0.6-nm equivalent physical [33]. Upon higher temperature annealing, the silicate layer
oxide thickness for this stack. This assumes that the effective converts to a more stoichiometric oxide layer and the films
mass in both dielectrics is the same. Full quantum calcula- tend to crystallize. The silicate interfacial layer appears to be
tions of the improvements for stacks with 1.0- and 1.5-nm important in reducing the interface state density [32], though
effective physical oxide thickness are shown in Fig. 5. The it does add a layer with a lower dielectric constant. Because
advantage of the higher layer with the SiO buffer layer of the reactions seen, it is likely that metal gates would need
diminishes further as the thickness of the stack decreases be- to be used in combination with these metal oxides, adding
cause the buffer layer must remain at a monolayer or more enormously to the process integration issues. A replacement
of oxide. However, every angstrom gained represents a sig- gate process is also a possibility [34].
nificant improvement in the leakage current, so any advances Lanthanum and yttrium oxides are column III dieclectrics
in improving the dielectric constant of the gate stack will be that have received attention as medium- materials. Alu-
important. minum oxide is another medium- material with a bandgap
This simple example shows the difficulty of incorporating near SiO that has been investigated [35], [36]. Many other
a buffer layer in a gate stack with an equivalent physical binary oxides have been proposed, but it seems unlikely that
oxide thickness of less than 1.0 nm. It also shows the simply depositing an oxide on silicon will result in a struc-
importance of the barrier height for electrons in the band ture as stable and perfect as a thermal SiO –Si interface.
lineup between the gate electrode and the dielectric material. Based on the desirable properties of the medium-
Because the bandgap tends to decrease with higher dielectric hafnium and zirconium oxides, the hafnium and zirconium
constant for simple oxides, any asymmetric band lineup silicates (Zr, Hf)Si O have been investigated as gate
can cause leakage problems due both to direct tunneling dielectrics [37]. Alloying the metal oxides with SiO or
and thermionic emission over the barrier. Asymmetric band equivalently doping SiO with elements with high polariz-
lineups have been predicted for several high- dielectric ability is expected to improve the interface quality over that
materials in contact with silicon, including tantalum oxide, of the metal oxides, making it more SiO -like in terms of
strontium titanate, and barium strontium titanate [18]. band alignment, dangling bonds, and trap densities.

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Fig. 10. Periodic table of elements with possible dielectric choices indicated [21].

in memory cells and its structure is shown in Fig. 11. The per-
ovskite structure of SrTiO is composed of a simple cubic lat-
tice of titanium ions with oxygen ions at the center of every
cube edge. The Sr ions reside at the cube centers and their
major function is providing electrons to the system. Stron-
tium has two electrons outside its krypton-like core while ti-
tanium has four electrons outside its argon-like core; these
six valence electrons compensate the six negative charges of
the three oxygen atoms that compose the SrTiO structure.
The Sr conduction band states are very high in energy and
are of no importance in determining the electronic structure
of the material [39]. The electronic structure and interface
Fig. 11. Structure of perovskite material.
gap states are determined by the Ti–O bonds [18]. Based on
the primary role of Sr in contributing electrons to the system,
it is expected that Ba or Ca substitutions would behave very
similarly.
The crystalline structure for ZrSiO is a body-centered Predictions for systems controlled by Ti–O or Ta–O bonds
tetragonal composed of SiO tetrahedra interspersed with Zr are that Schottky barrier pinning is sizable and leads to a low-
atoms. Hafnium silicate is expected to have the same struc- conduction band offset [18]. The thermodynamic stability of
ture. The use of a silicate composed of SiO and ZrO or Ti–O- or Ta–O-based materials has already been shown to
HfO structural units should act more like the SiO –Si inter- be poor in contact with silicon. Indeed, the barium–stron-
face. The dielectric constants of the silicates are lower than tium–titanate/silicon interface is too reactive to be used un-
the metal oxides, but are intermediate between the low value less a low-temperature processing route is available; in ap-
of SiO and the higher values for the metal oxides. plications for DRAM capacitor structures, it is sandwiched
A very important class of materials are the mixed metal between two metals.
oxide materials called perovskites, which have the formula In spite of these problems, a thermodynamically stable bi-
, where the is oxygen. They constitute one of the nary oxide such as SrO or BaO can act as a buffer layer be-
largest structural families known in solid-state chemistry be- tween the silicon surface and the high- perovskite or an
cause many substitutions of the metal cations are possible, in- interfacial silicide can act as a growth template [38]. The at-
cluding replacement of a cation by a combination of cations traction of the layered perovskite materials is that they might
of different valency such that the net charge remains iden- provide an epitaxial route to growing a high- layer on sil-
tical. The perovskites are of interest because they may allow icon. To do so, it is likely that many of the same tricks used
epitaxial crystalline oxides in perfect registry with the sil- to grow compound heterostructures will be used. Because of
icon substrate [38]. Strontium titanate is a simple perovskite the various transition metals that can be substituted in the
that has been widely investigated for capacitor applications perovskite structure, a lattice match with silicon is possible.

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Fig. 12. Workfunctions of possible metal gates.

Complex perovskites such as (Ba, Sr)La (Sc, Al) O Multiple thicknesses of gate oxides will be used on a chip
provide a large window of possible opportunities when com- to manage power and reliability constraints. Oxides will
bined with an underlying buffer layer. continue to be used in the highest performance circuits be-
cause of the accumulated knowledge about their reliability
IV. GATE ELECTRODES behavior. A gradual introduction of heavily nitrided oxides,
oxide/nitride stacks, or medium- dielectrics will be used to
Many of the new dielectric materials are unstable in di- lower leakage currents in most of the chip until knowledge
rect contact with silicon and by extension are unstable in of their reliability behavior accumulates. Given the enor-
the presence of the polysilicon gate material also. Thus, it mous investment in silicon technology, it is likely that these
is likely that the entire gate stack will have to be replaced, challenges will be met even if they seem very difficult at
with metal gates replacing polysilicon. Polysilicon has the present. There appear to be no fundamental materials limits
advantage that it can be doped p-type or n-type, shifting the on scaling the gate stack at least for the next decade.
workfunction so that it is suitable for NMOS and PMOS de-
vices. A compromise midgap workfunction metal gate shifts V. SHALLOW JUNCTIONS
the threshold voltage higher by half the bandgap (about 0.5
The issues associated with shallow junctions were briefly
V) compared to a highly doped polysilicon gate electrode.
introduced in connection with Fig. 2. There are two issues
If the channel doping is lowered to provide a suitable lower
which dominate the constraints placed on the source/drain
threshold voltage, then the channel doping is too low to con-
trol short-channel effects. For this reason, two different gate junction extension regions, parasitic resistance, and short
channel effects. Short channel effects are a result of the
metals are required with workfunctions near and .
The incorporation of two different metal gates in a CMOS drain electric field extending through the channel region
flow enormously complicates the fabrication process. and therefore modulating the channel potential near the
source and are discussed in more detail in other papers in
There are several candidate metals with workfunctions
this special issue [40].
near : Al, Ta, Mo, Zr, Hf, V, Ti, and several candidate
The parasitic resistance issue is quite simple. The MOS
metals with workfunctions near : Co, Pd, Ni, Re, Ir,
transistor operates through the gate potential modulating the
Pt. The diagram in Fig. 12 shows the workfunction of the
charge in the channel (inversion) region. The magnitude of
common metals in the silicon bandgap. There are also
the inversion charge and the length of the channel deter-
several conducting metal oxides as one moves toward the
mine the resistance associated with this region in the device.
right side of the periodic table in the transition metal oxides:
Simple first-order MOS device physics gives the channel re-
In O , SnO , OsO , RuO , IrO , ZnO, MoO , ReO , and
sistance as
conducting nitrides such as TiN. The problem is not a lack
of choices, but rather, which choice can be cost effectively
integrated into the process flow. If one abandons a conven- (12)
tional process flow and moves toward a gate last process
flow, then even the constraints of thermal stability in the gate where
stack are lessened. With the expertise available in chemical and gate width and channel length, respectively;
mechanical polishing (CMP), alternative process flows may applied gate voltage (usually the supply
provide a viable path toward integrating new gate stacks. voltage);
The combination of metal gates and an oxide/nitride gate threshold voltage.
dielectric allows an extension by one or two technology As device geometries are scaled down, ideal scaling [6] sug-
generations beyond what is possible with polysilicon and gests that , and all decrease at the same
SiO . It is interesting to note that any medium dielectric rate. In this scenario then, would remain constant as
replacement for oxide in high performance applications the technology is scaled. Therefore, if this were done, the
might already have to demonstrate reliability at current various parasitic resistances in Fig. 2 would simply need to
levels of 1 Acm , once thought to be the limit for silicon remain relatively constant in value from generation to gener-
dioxide. Given the trends in Moore’s Law, a likely scenario ation.
is that device and circuit cleverness will be used to control Because higher performance has been a specific objec-
the power dissipation problems caused by high-gate leakage. tive of scaling the technology, ideal scaling has not been fol-

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Fig. 13. Supply voltage and V versus time from the NTRS and ITRS.

lowed in the past and will not likely be followed in the fu- fraction of the supply voltage in order to provide sufficient
ture. Higher performance is achieved by higher current drive gate drive ( – ) for high-speed performance. Yet the
capability and, therefore, has been decreased as the threshold voltage also needs to be well above 0 V in order
technology has been scaled. This has been achieved by ag- to minimize the off state leakage current in the transistors.
gressively shrinking (see Fig. 3) and by shrinking and The rate of change of device current with gate voltage is
more slowly than ideal scaling would suggest. The latter fundamentally limited at room temperature to a 10 change
point is illustrated in Fig. 13. Note that these voltages were in current for each 60-mV change in gate voltage because
not scaled at all until the 1990s with the result that de- of the mechanism of current flow (thermionic emission over
creased approximately proportionally with feature size until a potential barrier). Thus, the threshold voltage typically
supply voltage scaling began. Thus, over time, the parasitic needs to be several times 60 mV above 0 V in order to
resistances have also been required to decrease in order to achieve reasonable off state currents. In today’s devices, this
keep as the dominant resistive component in the de- is achieved with values of about 0.5 V. With a supply
vice. voltage of 1.5–3 V, this provides reasonable gate drive in
Although these topics are covered in more detail in other the ON state. However, with a supply voltage of 0.5 V in
papers in this special issue [40], it is worthwhile making 2014, there is no room left for designing device to
some comments about Fig. 13 because of the impact this simultaneously meet OFF-state and ON-state current require-
figure has on materials issues. The fact that the supply ments. This issue is perhaps the most serious “device” issue
voltage has not been scaled as rapidly as ideal scaling might facing future generations of technology. Innovations such as
suggest has resulted in increased electric fields in device electronically controlled voltages will likely be needed
structures. Thus, materials, especially the gate dielectric, and are discussed elsewhere in this special issue [40].
have been pushed closer to materials limits. The vertical When current leaves the channel inversion layer (Fig. 2),
electric fields in gate dielectrics in today’s MOS transistors it first flows through an accumulation region before entering
are typically greater than 5 MV cm and may reach twice the source/drain extension region. The lateral profile of this
this value toward the end of the ITRS. These values are doped region is a key issue. The doping in the extension drops
approaching the physical limits of SiO and most other from a peak concentration of 10 cm today (10 cm
dielectric materials. at the end of the roadmap) to the background channel doping
Towards the end of the roadmap, the supply voltage is 10 cm today ( 10 cm at the end of the roadmap)
projected to be about 0.5 V and is limited by the maximum over a distance determined by the profile slope. The abrupt-
sustainable fields in the very thin gate dielectrics at that ness of this slope is specified in Table 1. At least over the
time and by power consumption issues in the very large latter part of the profile the extension doping is lower than
chips expected to be in manufacturing at that time. It should the carrier concentration induced in the surface accumula-
be noted in Fig. 13 that there is considerable uncertainty tion layer by the gate. Thus, the current flows through the
about the device threshold voltages expected to be used accumulation layer until it reaches a region in the extension
at that time. The threshold voltage typically needs to be a where the doping exceeds the accumulation layer carrier den-

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sity. Typically, the carrier density in the accumulation region
is on the order of 10 –10 cm [41], so the lateral extent
of the accumulation region can be significant depending on
the extension region lateral doping profile.
When the current leaves the accumulation region, it does
so gradually, resulting in a spreading resistance in se-
ries with the accumulation layer resistance . Because
of the complexity of the doping profiles in modern devices,
these resistances are best calculated today using numerical
simulation, but there are simple analytic expressions avail-
able that do provide useful estimates. Ng and Lynch [41] de-
rived such expressions and showed that both and
strongly depend on the steepness of the doping profile in the
extension region. Physically, this is because the length of the
accumulation region is determined by how steep the profile
is and, hence, decreases as the slope becomes steeper. Fig. 14. Solid solubility curves for various dopants in silicon.
Values are the equilibrium solubilities at each temperature and may
is also reduced by a steeper profile because the current not be achieved in device doped regions (after [43]).
quickly moves into more highly doped (lower resistance) re-
gions when the profile is steep. The entries in Table 1 relating
to the abruptness of the extension profile are a result of these is the thermodynamic maximum concentration that can be
considerations. accommodated in a solid without a separate phase forming,
In Fig. 2, the gate is shown overlapping the source/drain kinetic effects may limit the electrically active dopant
extension by a significant distance. In the context of the concentration that can be achieved under typical processing
above discussion, it is clear why this is required. The gate conditions. By this we mean that if the wafer temperature
forms and controls the accumulation region at the surface of is changed, some time is required for the dopant solubility
the extension and, hence, controls . If the gate overlap to reach the value characteristic of the new temperature. In
is too short then the accumulation region cannot extend as addition, the electrical solubility limit may be considerably
far as it otherwise might, with the result that may be lower than the maximum solid solubility shown in Fig. 14
significantly increased. There are a number of reports in the because of neutral cluster formation with point defects in
literature of decreases in device performance when this gate the silicon lattice. Typically, dopants above the electrical
overlap is reduced too far [42]. The required gate overlap solubility limit form an inactive complex that is electrically
can of course be reduced by increasing the steepness of the neutral and does not contribute free carriers to the doped
extension profile. In the limit of a perfectly abrupt junction, region.
the required overlap would be reduced to just the lateral Solid solubility data like Fig. 14 suggests that arsenic
extent of the junction depletion region in the extension. might be active up to concentrations of cm , but
The best one can do in terms of profiles is a perfectly flat in practice it is difficult to actually achieve electrically active
constant-concentration abrupt (box-shaped) profile whose arsenic concentrations above cm [42], [44]. The
sheet resistance is given by origin of this discrepancy is of enormous practical interest.
It is true that techniques such as laser melting of the silicon
can introduce arsenic into silicon in metastable electrically
(13)
active concentrations near the solubility limit. However,
there is an enormous driving force that tends to deactivate
where is the surface concentration and is the junction the arsenic during any subsequent thermal cycling. Upon
depth. The box-shaped profile encloses the maximum dose annealing, some of the arsenic, while not strictly forming
for a given and, hence, represents the minimum sheet re- a separate precipitate phase, forms an electrically inactive
sistance. values are specified in Table 1 and are deter- structure. One such proposed structure, which is consistent
mined primarily by short channel effects. is limited by with the experimental evidence, is that of several arsenic
electrical solubility of the dopant atoms in the silicon crystal atoms surrounding a vacancy. The arsenic atoms remain
and the mobility is then the value appropriate for silicon on substitutional sites, but adjoin a vacancy that leaves the
doped at a concentration . arsenic three-fold coordinated with the silicon lattice while
The maximum concentration of a dopant that can be retaining two electrons in a dangling bond for a full shell
dissolved in silicon under equilibrium conditions without of eight electrons. Thus, the As atoms are not electrically
forming a separate phase is termed the solid solubility [43]. active in this form and do not contribute free electrons to the
Many of the elements used as dopants exhibit a retrograde crystal.
solid solubility, where the maximum concentration that can If we use the ITRS specifications and assume the lim-
be dissolved occurs below the melting point as shown in iting active doping concentration is cm and the
Fig. 14. It is the electrically active concentration that is most limiting carrier mobility is 52 cm V s (which is a rea-
important to device designers. Though the solid solubility sonable value for both n- and p-type silicon [45]), then we

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Fig. 15. Source/drain extension junction depth and sheet resistance requirements from the ITRS [4].
Given the x values shown, sheet resistances in the dotted area are excluded if a dopant solubility of
2
2 10 cm , a mobility of 52 cm V s , and an ideal box profile are assumed.

can construct the plot shown in Fig. 15. One can immedi- VI. JUNCTION CONTACTS
ately see that the ITRS requirements beyond 2008 (the 70-nm
The final component of device resistance shown in Fig. 2
node) cannot be met even by an ideal box-shaped profile if
is the contact resistance. Contacts in today’s device struc-
the doping concentration is limited to the electrical solubility.
tures are normally made by self-aligned silicides contacting
is the resistance most affected by the extension region
heavily doped silicon. This process provides an ohmic con-
. Thus, this suggests that the ITRS requirements for
tact completely covering the area of the source/drain diffu-
cannot be met for the last few technology generations if the
sions and, therefore, minimizes the contact resistance.
device structure remains as shown in Fig. 2 and is limited
Current flows in a distributed manner from the
to equilibrium electrical solubility values.
source/drain extension to the contact. The exact flow
The situation is actually worse than this because the tech-
lines depend on the doping profile in the silicon and on the
niques used today to form doped regions in MOS devices (ion
geometry. The effective contact resistance depends on this
implantation followed by a rapid thermal anneal to activate
flow pattern or, in other words, on the effective area of the
the dopants) do not even come close to an ideal box-shaped
contact. Current crowding on the leading edge of the contact
profile. Practical profiles achievable with today’s manufac-
can be a significant effect. In this structure, the contact
turing techniques are typically a factor of two to three worse
resistance is given by [46]
than the ideal profile in terms of achievable because such
profiles are graded, which implies that the ITRS require-
ments will not be achievable perhaps as soon as the 130- contact (14)
or 100-nm generations. This is why bold entries appear in
Table 1 for at the 100-nm generation. We will return to
this point later. where
There may be opportunities in this area for new conceptual specific contact resistivity of the silicide/semicon-
approaches. One possibility is the use of metastably doped ductor contact ( cm );
silicon, that is, the incorporation of doping concentrations in sheet resistance of the source/drain diffusion
excess of the normal solubility limits. It is well established ( /square);
that such doping levels can be achieved by laser annealing for contact width;
example [44]. In these processes, the silicon is locally melted contact length.
and dopants can be “frozen in” at electrically active concen- is called the transfer length and is the av-
trations above 10 cm during the very rapid cooling that erage distance that carriers travel in the diffusion before en-
occurs after the laser pulsing. Such doping concentrations are tering the contact. For typical values of and , is
metastable, however, and any subsequent heat cycles provide greater than the physical contact length , which results
a huge driving force for precipitation and deactivation of the in the approximation in (14). In this case, the current flows
dopants. into the entire length of the contact and current crowding

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effects are minimal. Thus, the contact resistance varies in-
versely with the contact area if is constant.
The silicide formation process itself often consumes sil-
icon since the metal component (Ti, for example) is usually
deposited and then reacted to form the silicide. This has sev-
eral important consequences. First, some of the volume of the
heavily doped source/drain regions is lost or consumed by
the silicide formation. The portion of the source/drain region
which is “lost” is the top portion, which is normally the most
heavily doped and, therefore, the most conductive—exacer- 2
Fig. 16. Measured (SIMS) profiles of a 5-keV and a 1-keV 1 10
cm arsenic implant. (a) As-implanted. (b) After a 1050 C 10-s
bating the resistance problem. This increases the sheet resis- RTA anneal. 5-keV profile shows 30% dose loss [49].
tance of the remaining diffusion in which current can flow
to the contact and, therefore, increases the effective contact
resistance. Finally, the resistivity of an ohmic connection be-
tween a metal or silicide and heavily doped silicon depends found to be largely independent of the metal workfunction
strongly on the doping level adjacent to the metal. Silicon due to Fermi-level pinning. At the same time, barrier heights
consumption and dopant segregation behavior during the sili- to silicides range from approximately 0.4 to 0.9 eV, though
cide formation process can strongly affect this doping level. little is known about the workfunction of silicides. At a fun-
For a tunneling contact, the specific contact resistivity de- damental level, the formation of a Schottky contact to a semi-
pends on the semiconductor-metal barrier height and the sil- conductor is not fully understood and barrier height engi-
icon doping [46] neering might be possible by incorporation of thin interfacial
layers between the metal or silicide and the semiconductor
to modify the barrier properties. This expectation is based on
(15) the role of interface charges, electronegativity, bond strength,
and dipole moments in determining the barrier height.
The other parameter may be more amenable to
where
new conceptual approaches. One possibility is the use
contact resistivity for an infinitely high active sur-
of metastably doped silicon, as described earlier. The
face doping concentration;
near-noble-metal silicides tend to form at relatively low
actual active surface doping concentration; temperatures (200–600 C) while the refractory metal
barrier height between the silicon and metal or sili- silicides form at higher temperatures ( 600 C). Because
cide. of the importance of maintaining any metastable active
is process dependent and can change with cleaning or doping concentration in the silicon during further thermal
contact etching procedures. processing, this may put more emphasis on ultralow tem-
Required values for in Table 1 are derived from a desire perature silicide formation processes in the future. Some
to limit the total parasitic resistance in the device structure to silicides such as CoSi and NiSi are interesting because
no more than 10% of the channel resistance. If the area of they have the calcium fluorite crystal structure with a lattice
the silicide/semiconductor contact is taken to be a square de- constant that is very close to silicon. These silicides are
fined by the minimum feature size, then the implied contact candidates for low temperature epitaxial growth, a process
resistance from the numbers in Table 1 is approximately 1000 which has not yet been widely investigated. Limitations
, independent of technology generation. With reducing fea- that often occur because of the different behavior of n- and
ture sizes, this constant resistance is achieved by requiring p-type dopants during the conventional silicide formation
the contact resistivity to scale over time directly with the process might be avoided by an admittedly more complex
contact area. epitaxial growth process. An additional possibility is to
Based on (15) two key parameters in reducing are the form the silicide before the dopants are implanted and then
silicon doping and the barrier height . is limited implant directly into the silicide, followed by outdiffusion
today by the electrical solubility of dopants in the silicon, from the silicide into the silicon to form the junctions.
as discussed earlier. If we take the barrier height as one half This strategy eliminates the doped silicon consumption that
of the silicon bandgap (0.55 eV) and assume that the max- normally occurs during silicide formation and may be useful
imum electrically active dopant concentration in the silicon in reducing [47].
is cm , then is limited to about cm . These and other possibilities will have to be explored in the
Thus, the required values beyond 2005 are not achiev- near future if the requirements of the ITRS for are going
able by the contacting schemes currently employed in CMOS to be met. It is not clear at this point how “fundamental” a
technology. New approaches will be needed. The obvious limiting value of 10 cm is. If this is a practical or
areas to focus on are the barrier height and the dopant fundamental limit, new innovations will be required in device
solubility . structures to continue the performance improvements of the
Barrier height engineering in the metal–silicon system is past and these innovations will be required in the very near
often thought to be impractical because the barrier height is future.

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 2
Fig. 17. Experimental results are superimposed on Fig. 5. In both the 1- and 5-keV implants, 1 10
cm doses and RTA anneals were used [49].

VII. JUNCTION FORMATION—ION IMPLANTATION AND cess point defect concentrations which lead to anomalous
ANNEALING dopant diffusion while the damage is being repaired. This re-
pair process essentially occurs by providing thermal energy
The dominant technology used today for doping silicon to the lattice so that silicon atoms can find their way back to
is ion implantation. This process provides precise control of lattice sites. This “anneal” can be done at moderate temper-
the placement and quantity of doping atoms. In this process, atures for long times (700 C for tens of minutes to hours) or
doping ions (e.g., As ) are accelerated to energies of 1–1000 at high temperatures for short times (1000 C for 10 s). Ei-
keV and implanted into the silicon using photoresist or hard ther way, significant anomalous dopant diffusion takes place
masks like SiO to block the implant where it is not desired. during the anneal. This diffusion is known as TED and is a
The range of these ions in silicon varies inversely with energy major issue in making shallow junctions. Fig. 16 also illus-
and so the need for shallower junctions in scaled devices gen- trates the broadening of the implanted profiles during a typ-
erally implies lower implant energies. The stopping process ical high-temperature rapid thermal anneal (RTA). TED is
of these ions in the silicon involves both nuclear collisions generally minimized by using a short high-temperature an-
and electronic drag forces, both statistical processes, with the neal rather than a long low-temperature anneal essentially
result that a doping profile is produced by the implant. Ex- because the required anneal time decreases faster with tem-
amples are shown in Fig. 16 for low-energy As implants. perature than diffusivities increase with temperature.
The implantation process produces considerable damage In the example in Fig. 16, it is also interesting to note that
in the crystalline silicon substrate as a result of the nuclear the lower energy implant actually diffuses past the higher en-
collisions involved in the stopping process. At the high-dose ergy implant during the anneal step. This seems completely
levels typical of implants used to form source and drain re- counterintuitive but can be understood because the higher en-
gions or extension regions, the silicon is generally turned ergy implant loses 30% of its dose due to segregation to the
amorphous. At an atomic level, the damage consists of iso- Si/SiO interface during the anneal. Dopant diffusivities are
lated point defects (interstitials and vacancies) small com- very concentration dependent, so the lower concentrations
plexes or clusters of these point defects and more extended in the 5-keV implant diffuse more slowly than the higher
defect structures. concentrations in the 1-keV implant. The mechanisms un-
Dopants in silicon diffuse by interaction with point de- derlying all these effects are only beginning to be fully un-
fects. In the crystalline state, silicon contains small equilib- derstood and it is not clear today why the dose loss occurs
rium concentrations of isolated point defects. These concen- in the 5-keV case and not in the 1-keV case [49]. There are
trations depend exponentially on temperature and are typi- many other possible implant process conditions which need
cally close to zero at room temperature but 10 –10 cm at to be explored to provide answers to these questions.
process temperatures (700–1100 C). Dopant atoms diffuse Based on experiments of the type shown in Fig. 16, var-
by pairing with either vacancies or interstitials and hopping ious combinations of implant energies and anneal cycles have
from lattice site to lattice site in the crystal [48]. In implanted been carried out to assess whether the requirements specified
silicon, the damage created by the implant creates large ex- in the ITRS are achievable or not. One example is shown

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in Fig. 17 in which experimental results for low-energy im- dition of the surface (whether it has been damaged by a pre-
plants and RTA anneals are superimposed on the ITRS re- vious implant or not). Considerably more work is needed in
quirements in Fig. 15. Using 1-keV implants and optimum these areas to fully understand all the issues.
anneals, the 2005 (100 nm) node of the ITRS is barely achiev- Perhaps the most promising opportunity to radically alter
able and the last three nodes of the roadmap are outside the the limits, shown in Fig. 17, is to find some way to exceed
range of possibility at least for the conditions of these ex- equilibrium solid solubility limits for dopant concentrations.
periments. Even the ideal profile cannot achieve the require- As described earlier, metastable doping concentrations in ex-
ments in the last one or two technology nodes of the ITRS cess of 10 cm can easily be achieved by laser melting.
as was pointed out in the earlier discussion associated with Solidification of the silicon is so rapid following this process
Fig. 15. Note that the 1-keV implant and optimum anneal that dopant concentrations corresponding to the solubility
data come within about a factor of two of the ideal box pro- near the melt temperature are frozen into the crystal. As also
file limit, suggesting that there is not much additional room described earlier, however, such dopant concentrations easily
for improvement if these shallow junctions are limited by the deactivate under subsequent thermal cycling. Thermal cy-
doping solubility. cles currently used (and believed to be necessary for future
At very high concentrations, dopant diffusivities increase device processing) are likely sufficient to deactivate enough
dramatically, making it more difficult to keep junctions dopants that the final active concentrations will be no better
shallow under reasonable anneal conditions. This increase in than today’s limit of about cm . However, this con-
dopant diffusivity is partly due to concentration dependent clusion is not certain and needs to be more carefully investi-
diffusivities. The mechanism behind these effects is believed gated. Deactivation involves the clustering of dopant atoms,
to be the idea that point defects (vacancies and interstitials) typically with point defects. If methods can be found to sup-
can exist in both neutral and charged states in the silicon press the formation of these point defects during any neces-
lattice. The charged defect concentrations are governed by sary anneals, perhaps the metastable doping concentrations
the energy levels of these defects in the silicon bandgap can be maintained. Alternatively, or perhaps in combination
and by the Fermi level ( ) [48], [50]. In highly doped with these methods, device processing perhaps can be re-
material, the Fermi level moves away from its intrinsic level designed to limit thermal cycles so that deactivation is less
in the middle of the bandgap and can cross over the levels of a problem. Finally, an alternative device structure may be
corresponding to the charged point defects when the doping found that circumvents the issue completely by relaxing the
is high enough. This results in exponential increases in constraints on parasitic resistances shown in Fig. 2.
the concentrations of these defects and, hence, exponential
increases in dopant diffusivities as moves. The result is
VIII. MOSFETs AT THE SCALING LIMIT
dopant diffusivities that depend on n/n or p/n if negatively
charged or positively charged point defects are involved The two most obvious materials issues in scaled MOS-
respectively. The dependencies go as (n/n ) or (p/n ) if FETs at the end of the ITRS are the gate insulator and the
doubly charged defects are dominant. While these effects need for ultrashallow junctions. The first of these does not
do increase dopant diffusivities and, hence, make obtaining seem very amenable to solution by alternate device struc-
shallow junctions more difficult, they also have the positive tures because the MOSFET depends fundamentally on a gate
effect of making dopant profiles more box-like because electrode separated from the channel region by a high-quality
the high-concentration regions diffuse more rapidly and insulator. The second issue, shallow junctions, is less funda-
therefore produce a flatter profile near the surface. mental and can be attacked somewhat by device structure in-
Other anomalous diffusion effects also occur at high con- novation. We will explore both of these issues further in this
centrations, many of which are poorly understood today. In section.
boron doped regions, diffusivities have been found to be even Consider first the gate insulator issue. The ITRS specifi-
larger than concentration dependent diffusivities would pre- cations for insulator thickness are driven primarily by two
dict. This has been termed boron-enhanced diffusion or BED issues: short channel effects and device performance. Short
and is believed to be due to the formation and diffusion of ad- channel effects are primarily a geometric issue. The gate
ditional boron defect pairs that form at high concentrations needs to have tighter control of the channel potential than
[51]. the drain does in order to avoid modulation of the drain cur-
TED effects can also be greatly affected when the junc- rent by the drain voltage. Conventionally, this has implied
tions are shallow. Experimentally, it is found that anomalous that the gate insulator thickness needs to be a few percent of
diffusion due to implant damage is actually less of an issue the channel length. The ITRS assumes that this ratio will be
when the junctions are very shallow [52]. This is likely be- maintained in the future and this is what leads to insulator
cause with a surface or material interface nearby, the large thicknesses of 1 nm (equivalent SiO thickness) when the
excess concentrations of point defects created by the implant channel length is 35 nm. The most obvious solution to this
process can recombine rather than diffuse into the bulk where problem is to change to a higher dielectric constant insulator
they can affect dopant diffusion. Surfaces and interfaces are as described earlier. But this solution has very difficult ma-
thought to be very effective sites for excess point defect re- terials issues, especially if it is pushed beyond the oxynitride
combination, although this probably depends on the kind of class of materials. In fact, it is very likely that an Si/SiO in-
interface (Si-SiO or some other interface) and on the con- terface at least a monolayer thick will always be required for

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 (a)

Fig. 19. MOSFET design at 25-nm dimensions using a different

scaling scenario than the ITRS (after [55].

gate drive. The question then is whether such a device de-

sign can be modified to make it work properly at small di-
mensions. By modifying the lateral channel doping profile
as illustrated in Fig. 19, reasonable device performance was
predicted at effective channel lengths of 25 nm, toward the
(b) end of the ITRS. These complex lateral doping profiles re-
Fig. 18. (a) Schematic representations of double-gate and (b) quire careful ion implantation and suppression of TED ef-
surround-gate MOS transistor structures. fects so that the profiles stay where they are implanted. This
may not be feasible in such very small structures. Alterna-
high-quality MOSFET devices, which places a lower limit tively, vertical MOSFET structures like the surround-gate de-
on insulator thickness of about 0.3 nm even if tunneling cur- vice in Fig. 18 could use epitaxial growth to produce complex
rents were not a problem. channel doping profiles. This approach might be more fea-
Some relief from this problem can be obtained by device sible for implementing structures like that shown in Fig. 19.
structure innovations. A number of groups are exploring The series resistance issues described earlier in connection
double-gate [53] and surround-gate MOS [54] structures with the device structure in Fig. 2 present serious challenges
today. These structures, illustrated conceptually in Fig. 18, as shown for example in Fig. 17. This problem is perhaps
essentially configure the MOS gate on two sides (top amenable to solution again through device structure innova-
and bottom) of the channel in the case of the double-gate tion. The ITRS sets the junction depth at 10 nm, and it is
structure or completely around the channel like a sheath this combination of and that is unachievable in Fig. 17.
around a wire in the case of the surround-gate structure. However, the structure illustrated in Fig. 19 has a junction
Either structure affords better gate control of the channel depth of 25 nm and in the simulations described in [55],
potential and, thus, for a given channel length, they relax values as high as 50 nm were used, with reasonable short
the gate insulator thickness specification. Since current channel characteristics. The combination of a 25- or 50-nm
flows between drain and source on both sides of the channel and the sheet resistance values in the ITRS in 2014 is
(double gate) or completely around the perimeter of the achievable by standard ion implantation and RTA techniques
silicon “wire” (surround gate), these structures also improve since these values fall well above the dotted forbidden re-
the performance of the basic MOSFET device. These device gion in Fig. 17. Thus, the ITRS specifications may in fact be
structures should allow scaling by an additional one or two achievable even at the end of the roadmap through continued
generations if the ITRS scenario is followed, but they do not, device innovation. Other device structures including raised
of course, solve the fundamental problem of a limit on how source/drain configurations have also been proposed to help
thin the gate insulator can be made. In some respects, they address the series resistance problem [56].
actually complicate this problem because the gate insulator We have not specifically addressed other proposed device
now has to be grown or deposited on a more complex options such as silicon-on-insulator (SOI) devices or the in-
geometry and this may provide additional practical limits on corporation of heterostructures using materials such as SiGe.
how thin the gate insulator can be. These innovations do not change the fundamental materials
Another approach that has been proposed [55] suggests issues addressed in this paper with respect to conventional
simply accepting 1.5 nm as the limit on insulator scaling, CMOS technology. They may provide additional design op-
using SiO as the insulator since it works at these dimen- tions or more performance in some applications, but these is-
sions and setting the supply voltage at 1 V and at 0.2 V sues are outside the scope of this paper. Other papers in this
since these values provide reasonable leakage currents and special issue address some of these topics.

256 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001

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[43] F. A. Trumbore, “Solid solubilities of impurity elements in germa- B.S. degree from the University of California,
nium and silicon,” Bell Syst. Tech. J., vol. 39, p. 205, 1960. Los Angeles, and the M.S. (EE) and Ph.D. (EE)
[44] P. M. Rousseau, P. B. Griffin, W. T. Fang, and J. D. Plummer, “Ar- degrees from Stanford University, Stanford, CA.
senic deactivation enhanced diffusion, a time, temperature and con- He is currently the Frederick E. Terman Pro-
centration study,” J. Appl. Phys., vol. 84, no. 7, p. 3593, Oct. 1998. fessor of Electrical Engineering and Dean of the
[45] G. Masetti, M. Severi, and S. Solmi, “Modeling of carrier mo- School of Engineering at Stanford University. He
bility against carrier concentration in arsenic, phosphorus and has authored or coauthored over 300 technical pa-
boron-doped silicon,” IEEE. Trans. Electron Devices, vol. 30, p. pers. His current research interests focus on sil-
764, July 1983. icon devices and technology, with a significant
[46] C. M. Osburn and K. R. Bellur, “Low parasitic resistance contacts part of his work aimed at developing physically
for scaled ULSI devices,” Thin Solid Films, vol. 332, no. 1, p. 428, based models for silicon structures and fabrication processes. He is also
Nov. 1998. interested in developing new semiconductor devices, including nanoscale
[47] C. M. Osburn, J. Y. Tsai, and J. Sun, “Metal silicides: Active ele- structures, high voltage devices, and devices and circuits aimed at special
ments of ULSI contacts,” J. Electron Mater., vol. 25, no. 11, p. 1725, applications.
Nov. 1996. Dr. Plummer was elected to the National Academy of Engineering in
[48] P. M. Fahey, P. B. Griffin, and J. D. Plummer, “Point defects and 1996. He received three Best Paper Awards at the International Solid State
dopant diffusion in silicon,” Rev. Mod. Phys., vol. 61, no. 2, pp. Circuits Conference in 1970, 1976, and 1978 and the the Solid State Science
289–384, Apr. 1989. and Technology Award from the Electrochemical Society in 1991. He has
[49] R. Kasnavi, P. B. Griffin, and J. D. Plummer, “Ultra low energy im- also received several teaching awards at Stanford University.
plant limits on arsenic sheet resistance and junction depth,” in Symp.
VLSI Technol. Dig. Tech. Papers, June 2000, p. 112.
[50] W. Shockley and J. Last, “Statistics of the charge distribution for a
localized flaw in a semiconductor,” Phys. Rev., vol. 107, no. 2, p.
392, June 1957. Peter B. Griffin received the B.E. degree from
[51] A. Agarwal, D. J. Eaglesham, H. J. Gossmann, L. Pelaz, S. B. Herner, University College Cork, the M.Eng.Sc. (EE)
D. C. Jacobson, T. E. Haynes, Y. Erokhin, and R. Simonton, “Boron- degree from the National Microelectronics
enhanced-diffusion of boron: The limiting factor for ultra-shallow Research Center, Cork, Ireland, and the Ph.D.
junctions,” in Proc. Int. Electron Devices Meeting, Dec. 1997, p. (EE) degree from Stanford University, Stanford,
467. CA.
[52] A. Agarwal, H. J. Gossmann, D. J. Eaglesham, L. Pelaz, D. C. Ja- He is currently a Research Scientist at Stan-
cobson, T. E. Haynes, and Y. Erokhin, “Reduction of transient diffu- ford University. He has authored or coauthored
sion from 1–5keV Si ion implantation due to surface annihilation more than 50 technical papers, coauthored a
of interstitials,” Appl. Phys. Lett., vol. 71, no. 21, p. 3141, Nov. 1997. new textbook on Silicon VLSI Technology,
[53] J. G. Fossum, K. Kim, and Y. Chong, “Extremely scaled double-gate and consults on advanced process technology
CMOS performance projections, including GIDL-controlled with industry. His current research interests are aimed at developing
off-state current,” IEEE Trans. Electron Devices, vol. 46, p. 2195, atomistic insights into the fabrication process for silicon devices by a mix
NOv. 1999. of experimental and computational methods.

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