Module 1 - Introduction & Fabrication.
Module 1 - Introduction & Fabrication.
Module 1
INTRODUCTION
1.1 History
The first integrated circuit was flip-flop with two transistors built by Jack Kilby at Texas Instruments
in the year 1958. In the year 2008, Intel’s Itanium microprocessor contained more than 2 billion
transistors and a 16 Gb Flash memory contained more than 4 billion transistors. So in the range of
over 50 years there is the growth rate is around 53%. This incredible growth has come from steady
miniaturization of transistors and improvements in manufacturing processes. As transistors became
smaller, they also became faster, dissipate less power, and are got cheaper to manufacture. The
memory once needed for an entire company’s accounting system is now carried by a teenager in her
iPod. Improvements in integrated circuits have enabled space exploration, made automobiles safer
and more fuel efficient, revolutionized the nature of warfare, brought much of mankind’s knowledge to
our Web browsers, and made the world a flatter place.
During the first half of the twentieth century, electronic circuits used large, expensive, power-
hungry, and unreliable vacuum tubes.
In 1947, John Bardeen and Walter Brattain built the first functioning point contact transistor at Bell
Laboratories, shown in Figure 1.1(a).
Later it was introduced by the Bell Lab and named it as Transistor, T-R-A-N-S-I-S-T-O- R,
because it is a resistor or semiconductor device which can amplify electrical signals as they are
transferred through it from input to output terminals.
Ten years later, Jack Kilby at Texas Instruments realized the potential for miniaturization if multiple
transistors could be built on one piece of silicon. Figure 1.1(b) shows his first prototype of an
integrated circuit, constructed from a germanium slice and gold wires.
Transistors are electrically controlled switches with a control terminal and two other terminals that
are connected or disconnected depending on the voltage or current applied to the control.
After the invention of point contact transistor, Bell Labs developed the bipolar junction transistor,
which were more reliable, less noisy and more power-efficient.
Early integrated circuits used mainly bipolar transistors, which required a small current into the
control (base) terminal to switch much larger currents between the other two (emitter and collector)
terminals.
The problems seen with bipolar transistors were the power dissipated by the base current which
limited the maximum number of transistors that can be integrated onto a single die.
Then in 1960 came Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The
advantages seen in MOSFETs were that they draw almost zero control current while idle. It was
available in 2 forms as: nMOS and pMOS, using n-type and p-type silicon, respectively.
In 1963, the first logic gates using MOSFETs was introduced at Fairchild. It included gates used
both nMOS and pMOS transistors. This gave the name Complementary Metal Oxide Semiconductor,
or CMOS. The circuits used discrete transistors but consumed only nano watts of power, which was
about six times lesser than bipolar transistors.
MOS ICs became popular because of their low cost, each transistor occupied less area and the
fabrication process was simpler. Early commercial processes used only pMOS transistors but it
suffered from poor performance, yield, and reliability. Later on Processes using nMOS transistors
became common in the 1970s.
Even though nMOS process was less expensive compared to CMOS, nMOS logic gates consumed
power while they were idle. Power consumption became a major issue in the 1980s as hundreds of
thousands of transistors were integrated onto a single die. CMOS processes were widely adopted and
have essentially replaced nMOS and bipolar processes for nearly all digital logic applications.
In 1965, Gordon Moore observed that plotting the number of transistors that can be most
economically manufactured on a chip gives a straight line on a semi-logarithmic scale. Also he found
transistor count doubling every 18 months. This observation has been called Moore’s Law.
Level of Integration:
The process of integration can be classified as small, medium, large, very large.
1. Small-Scale Integration (SSI): The number of components is less than 10 in every package. Logic
Gates like inverters, AND gate, OR gate and etc. are products of SSI.
2. Medium Scale Integration (MSI): MSI devices has a complexity of 10 to 100 electronic components
in a single package. Ex: decoders, adders, counters, multiplexers, and demultiplexers.
3. Large Scale Integration (LSI): Products of LSI contain between 100 and 10,000 electronic
components in a single package. Ex: memory modules, I/O controllers, and 4-bit microprocessor
systems.
4. Very Large Scale Integration (VLSI): Devices that are results of VLSI contain between 10,000 and
300,000 electronic components. Ex: 8bit, 16-bit, and 32-bit microprocessor systems.
The feature size of a CMOS manufacturing process refers to the minimum dimension of a
transistor that can be reliably built. The 4004 had a feature size of 10μ m in 1971. The Core 2 Duo had
a feature size of 45nm in 2008. Feature sizes specified in microns (10−6m), while smaller feature sizes
are expressed in nanometers (10−9 m).
Silicon (Si), a semiconductor, forms the basic starting material for most integrated circuits
Silicon is a Group IV element in periodic table, it forms covalent bonds with four adjacent atoms,
as shown in Figure 1.2(a). As the valence electrons of it are involved in chemical bonds, pure silicon
is a poor conductor.
However its conductivity can be increased by introducing small amounts of impurities, called
dopants, into the silicon lattice.
A dopant from Group V of the periodic table, such as arsenic, having five valence electrons. It
replaces a silicon atom in the lattice and still bonds to four neighbors, so the fifth valence electron is
loosely bound to the arsenic atom, as shown in Figure 1.2(b). Thermal vibration at room temperature
is sufficient to free the electron. This results in As+ ion and a free electron. The free electron can
carry current and this is an n-type semiconductor.
A Group III dopant, such as boron, having three valence electrons, as shown in Fig 1.2(c). The
dopant atom can borrow an electron from a neighboring silicon atom, which in turn becomes short
by one electron. That atom in turn can borrow an electron, and so forth, so the missing electron, or
hole, can propagate about the lattice. The hole acts as a positive carrier so we call this a p-type
semiconductor.
Transistors can be built on a single crystal of silicon, which are available as thin flat circular wafer of
15–30 cm in diameter. CMOS technology provides two types of transistors an n- type transistor
(nMOS) and a p-type transistor (pMOS).
Transistor operation is controlled by electric fields so the devices are also called Metal Oxide
Semiconductor Field Effect Transistors (MOSFETs) or simply FETs. Cross-sections and symbols of
these transistors are shown in Figure 1.3.
The n+ and p+ regions indicate heavily doped n- or p-type silicon. Each transistor has conducting
gate, an insulating layer of silicon dioxide (SiO2, also known as glass), and the silicon wafer, also
called the substrate/body/bulk. Gates of early transistors were built from metal, so was called Metal-
Oxide-Semiconductor, or MOS.
nMOS Transistor:
It controls the flow of electrical current between the source and drain.
Considering an nMOS transistor, its body is generally grounded so the p–n junctions of the source
and drain to body are reverse-biased. If the gate is also grounded, no current flows through the
reverse-biased junctions and the transistor is OFF.
If the gate voltage is raised, it creates an electric field that starts to attract free electrons to the
underside of the Si–SiO2 interface.
If the voltage is raised enough, the electrons outnumber the holes and a thin region under the gate
called the channel is inverted to act as an n-type semiconductor.
Hence, a conducting path is formed from source to drain and current can flow. This is the condition
for transistor is ON state.
Thus when the gate of an nMOS transistor is high, the transistor is ON and there is a conducting
path from source to drain. When the gate is low, the nMOS transistor is OFF and almost zero current
flows from source to drain.
pMOS Transistor:
A pMOS transistor is just the opposite of that of nMOS. It is ON when the gate is low and OFF
when the gate is high
MOS transistor is a majority-carrier device - current in channel between the source and drain is
controlled by a voltage applied to the gate.
o In nMOS transistor - majority carriers are electrons
o In pMOS transistor - majority carriers are holes.
To understand the behavior of MOS transistors, an isolated MOS structure with a gate and body
but no source or drain is consider.
It has top layer of good conducting gate layer. Middle layer is insulating oxide layer and bottom
layer is the p-type substrate i.e doped silicon body. Since it is a p-type body carriers are holes
Fig 1.6 (a) nMOS demonstrating Cutoff and Fig 1.6 (b,c) Linear operation
Now considering transistor with MOS stack between two n-type regions called the source and drain
the operation is considered.
When gate-to-source voltage, Vgs is less than threshold voltage and if source is grounded, then the
junctions between the body and the source or drain are zero-biased or reverse- biased and no current
flows. We say the transistor is OFF, and this mode of operation is called cutoff. This is shown in
above fig. 1.6(a)
When the gate voltage is greater than the threshold voltage, an inversion region of electrons (majority
carriers) called the channel connects the source and drain, creating a conductive path and turning the
transistor ON Fig 1.6(b). The number of carriers and the conductivity increases with the gate voltage.
The potential difference between drain and source is Vds= Vgs - Vgd. If Vds = 0 (i.e., Vgs =Vgd),
there is no electric field tending to push current from drain to source. When a small positive potential
Vds is applied to the drain, current Ids flows through the channel from drain to source. This mode of
operation is termed linear, resistive, triode, non saturated, or unsaturated mode as shown in Fig
6 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E
VLSI DESIGN | MODULE1: INTRODUCTION & FABR ICATION 17EC 63
1.6 (c)
If Vds becomes sufficiently large that Vgd < Vt, the channel is no longer inverted near the drain
and becomes pinched off (Fig 1.6(d)). However, conduction is still brought about by the drift of
electrons under the influence of the positive drain voltage. Above this drain voltage the current Ids is
controlled only by the gate voltage and ceases to be influenced by the drain. This mode is called
saturation.
The pMOS transistor in Fig 1.8 operates in just the opposite fashion. The n-type body is tied to a
high potential so the junctions with the p-type source and drain are normally reverse-biased. When
the gate is also at a high potential, no current flows between drain and source. When the gate voltage
is lowered by a threshold Vt, holes are attracted to form a p-type channel immediately beneath the
gate, allowing current to flow between drain and source.
Where
Cg – capacitance of gate to the channel
If we model the gate as a parallel plate capacitor, then capacitance is given by Area/Thickness
Fig 1.8(a) Capacitance effect at the gate terminal Fig 1.8(b) Transistor dimensions
If gate is having length L and width W and the oxide thickness is tox, as shown in Fig 1.8(b), the
capacitance is given by
The velocity of charge carrier in the channel is proportional to lateral electric field (field between
source and drain) and it is given by,
𝑣=𝜇𝐸 (1.3)
Where μ is the proportionality constant called ‘mobility’
The electric field E is the voltage difference between drain and source to the length of channel.
Given by,
𝑉𝑑𝑠
𝐸= (1.4)
𝐿
The current in the channel is given by the total amount of charge in channel and time taken by
them to cross. The time taken is given by length to velocity.
𝐶𝑔 𝑉𝑐 𝐶𝑔 𝑉𝑐
𝐼𝑑𝑠 = 𝑣= µ𝐸
𝐿 𝐿
𝐶𝑔 𝑉𝑐 𝑉𝑑𝑠
𝐼𝑑𝑠 = µ
𝐿 𝐿
𝑉𝑑𝑠
𝐶𝑜𝑥 𝑊𝐿 [(𝑉𝑔𝑠 − 𝑉𝑡 ) − ] 𝑉𝑑𝑠
2
𝐼𝑑𝑠 = µ
𝐿 𝐿
Upon Simplification
𝑊 𝑉𝑑𝑠 (1.5)
𝐼𝑑𝑠 = µ 𝐶𝑜𝑥 ((𝑉𝑔𝑠 − 𝑉𝑡 ) − ) 𝑉𝑑𝑠
𝐿 2
𝑉𝑑𝑠
= 𝛽 ((𝑉𝑔𝑠 − 𝑉𝑡 ) − ) 𝑉𝑑𝑠
2
𝑊 (1.6)
Where 𝛽 = µ 𝐶𝑜𝑥 𝐿
The above equation for current describes linear region operation for Vgs > Vt
When Vds is increased to larger value i.e., Vds > Vsat = Vgs – Vt, the channel is no longer inverted
and at the drain channel gets pinched off.
Beyond this is the drain current is independent of Vds and depends only on the gate voltage called
as saturation current.
The expression for the saturation current is given by
𝛽 2 (1.7)
𝐼𝑑𝑠 = (𝑉𝑔𝑠 − 𝑉𝑡 )
2
The plot of current and voltage i.e., I-V Characteristics is shown in the fig.
pMOS Transistor:
pMOS transistors behave in the same way, but with the signs of all voltages and currents reversed.
The I-V characteristics are in the third quadrant, as shown in Fig 1.9
Fig 1.9 Plot of I-V characteristics of (a) nMOS and (b) pMOS
The ideal I-V model does not consider many effects that are important to modern devices. These
effects are as follows:
When transistor is not velocity saturated, current Ids is given by and with velocity saturation,
current Ids is given as
As channel length becomes shorter, lateral electrical field increases and transistor becomes more
velocity saturated and this decrease drain current Ids.
Velocity of charge carriers depend on electric field and when these carriers travel along the length of
channel, they get attracted to the surface (i.e., Gate) by the vertical electric field (field created by gate
voltage). Hence they bounce against the surface during their travel. This reduces surface mobility in
comparison with the mobility along the channel. This is known as mobility degradation and has an
impact on I-V characteristics. As mobility decreases the current also decreases.
Ideally drain current Ids is independent on Vds in the saturation region making transistor a perfect
current source.
When Vds is increased further, near the drain barrier is build due to depletion region and reduces
the length of the channel.
This results in reducing the length of the channel by L d. This is shown in Fig 1.12 below. Thus in
saturation the effective channel length is modeled as
Leff = L - Ld (1.11)
Note: Channel length modulation is important in analog designs as it reduces the gain of the
amplifier.
But for digital circuits channel length modulations has no much importance.
1.5.3 Body Effect:
MOSFETs have 4th implicit terminal called body/substrate along with gate, source and drain.
The threshold voltage Vt which is assumed to remain constant is no more a constant value and
varies as potential between source and body is varied. This effect is called body effect.
(1.13)
Where Vto is the threshold voltage when source and body are at same potential
Φs is the surface potential
γ is the body effect coefficient and these two are given by Vsb is the source to body potential
(1.14)
(1.15)
The ideal I-V model assumes current flows from source to drain only when Vgs >Vt (when gate
voltage is high). But in practical transistors, current does not abruptly cut off below threshold, but
rather drops off exponentially.
This regime of Vgs <Vt is called weak inversion/ subthreshold.
This conduction of current is known as leakage and is undesired when the transistor is off
The subthreshold conduction is modeled using equation given below
𝑉𝑔𝑠−𝑉𝑡 −𝑉𝑑𝑠
𝐼𝑑𝑠 = 𝐼𝑑𝑠0 𝑒 𝑛𝑣𝑇 (1 − 𝑒 𝑣𝑇 ) (1.16)
(1.17)
Where Idso is the current at saturation and is dependent on process and device geometry
Vt is the threshold voltage and υT voltage at room temperature.
In the expression Ids is 0 if Vds is 0 and increases to full when Vds is few multiples of Υt
Figure 1.13 shows the conduction in the subthreshold region
Subthreshold conduction is useful for designing low power analog circuits and dynamic circuits as it
reduces threshold voltage and results in low power consumptions.
As the drain voltage Vds is increased it creates an electric field that affects the threshold voltage.
This effect is called drain-induced barrier lowering (DIBL) and this effect is especially pronounced
in short-channel transistors.
As the channel length decreases, the DIBL effect shows up and the variation caused in the
threshold voltage can be modeled as
(1.18)
Where η is the DIBL coefficient
1.5.6 Junction Leakage:
The MOS structure is considered there exists p–n junctions between diffusion and the substrate.
With CMOS structures p–n junctions between diffusion and the substrate or well, forming diodes, as
shown in Fig. The well-to-substrate junction is another diode.
Fig 1.14 CMOS structure showing formation of p-n junctions between diffusion and substrate and
also between well and substrate
The substrate and well are tied to GND or VDD so that these diodes does not get into forward
biased condition until voltage is applied in normal operation but in reverse-biased conditions these
diodes still conduct a small amount of current ID. This leakage current is modeled using equation
(1.19)
Where, ID is the diode current
IS is the diode reverse bias saturation current
VD is the diode voltage (either Vsb or Vdb)
IS depends on doping levels and on the area and perimeter of the diffusion region (geometry) and
VD
Leakage current usually lies in the range of 0.1 – 0.01 fA/μm2, which is negligible when compared
to other leakage currents.
Fig 1.15 plot of gate leakage current density vs voltage for different tox
Fig 1.15 shows plot of gate leakage current density JG against voltage for different oxide thickness.
It can be observed that as oxide thickness decreases the leakage current density increases. Thus gate
oxide cannot be considered as an ideal insulator. This effects the circuit functionality and increases
power consumption due to static gate current.
Research is going on in finding an alternate to silicon dioxide and silicon nitrate is one contender
for this.
Note: As mobility of electrons is more than holes in silicon, tunneling current magnitude for nMOS
is more compared pMOS.
1.5.5 Temperature Dependence:
Carrier mobility – decreases with temperature and this is modeled using the relation
(1.20)
where
T is absolute temperature,
Tr is room temperature
kμ is fitting constant.
Threshold voltage – magnitude of threshold voltage decreases linearly with temperature and can be
modeled as
(1.21)
where
kvt is typically about 1–2 mV/K.
Junction Leakage – increases with temperature because Is (diode reverse bias current) strongly
depends on temperature
Velocity saturation – occurs sooner with temperature.
With increase in temperature drain current decreases with temperature when transistor is ON and
when transistor is OFF, the junction leakage and subthreshold conduction contribute to leakage
current and this increase. This condition is shown in the graph 1.16.
The layout designer would draws transistors with width and length W drawn and Ldrawn.
While mask preparation the actual gate dimensions may differ by X W and XL.
While diffusion process, the source and drain would tend to diffuse laterally under the gate by LD,
causing a smaller effective channel length that the carriers must traverse between source and drain.
Similarly, WD accounts for smaller width while diffusion.
Combing all these factors transistor, lengths and widths that should be used in place of L and W is
given by
(1.22)
If there is variations in the length and width of the transistor there will be variations in the
performance. For example, if the currents have to be matched then length should not be varied.
Vdsn = Vout. As the source of the pMOS transistor is tied to VDD, Vgsp =Vin – VDD and Vdsp
=Vout – VDD.
Table 1.1 : Relationship between voltages for the three regions of operation of a CMOS inverter
The objective is to find the variation in output voltage (Vout) as a function of the input voltage
(Vin). This may be done graphically, for simplicity, we assume Vtp = –Vtn and that the pMOS
transistor is 2–3 times as wide as the nMOS transistor so βn = βp.
The plot shows Idsn and Idsp in terms of Vdsn and Vdsp for various values of Vgsn and Vgsp
using drain current equation.
Fig 1.18(b) shows the same plot of Idsn and |Idsp| now in terms of Vout for various values of Vin.
The possible operating points of the inverter, marked with dots, are the values of Vout where Idsn =
|Idsp| for same Vin. These operating points are plotted on Vout vs. Vin axes in Fig. (c) to show the
inverter DC transfer characteristics.
The supply current IDD = Idsn = |Idsp| is also plotted against Vin in Fig (d) showing that both
transistors are momentarily ON as Vin passes through voltages between GND and VDD, resulting
in a pulse of current drawn from the power supply.
The operation of the CMOS inverter can be divided into five regions indicated on Fig 1.18(c). The
state of each transistor in each region and state of output is shown in Table 1.2
o In region A, the nMOS transistor is OFF so the pMOS transistor pulls the output to VDD.
o In region B, the nMOS transistor starts to turn ON, pulling the output down.
o In region C, both transistors are in saturation.
o In region D, the pMOS transistor is partially ON
o In region E, pMOS is completely OFF, leaving the nMOS transistor to pull the output down to
GND.
Similarly NMH is the difference between the minimum HIGH output voltage of the driving gate
and the minimum HIGH input voltage recognized by the receiving gate.
(1.23)
(1.24)
Where VIH = minimum HIGH input voltage, VIL = maximum LOW input voltage
VOH= minimum HIGH output voltage, VOL= maximum LOW output voltage
Inputs between VIL and VIH are said to be in the indeterminate region or forbidden zone and do
not represent any legal digital logic levels. Therefore, it is generally desirable to have VIH as close as
possible to VIL and for this value to be midway in the “logic swing,”
VOL to VOH. This implies that the transfer characteristic should switch abruptly; that is, there
should be high gain in the transition region.
nMOS transistors pass ‘0’s well but 1s poorly. Figure 1.22(a) shows an nMOS transistor with the
gate and drain tied to VDD. Imagine that the source is initially at Vs = 0. Vgs > Vtn, so the transistor
is ON and current flows. If the voltage on the source rises to Vs = VDD – Vtn, Vgs falls to Vtn and
the transistor cuts itself OFF.
Therefore, nMOS transistors attempting to pass a 1 never pull the source above VDD – Vtn. This
loss is sometimes called a threshold drop.
Similarly, pMOS transistors pass 1s well but 0s poorly. If the pMOS source drops below |Vtp|, the
transistor cuts off. Hence, pMOS transistors only pull down to within a threshold above GND, as
shown in Fig 1.22(b).
As the source can rise to within a threshold voltage of the gate, the output of several transistors in
series is no more degraded than that of a single transistor Fig 1.22(c ).
However, if a degraded output drives the gate of another transistor, the second transistor can produce
an even further degraded output Fig 1.22(d).
The problem seen with nMOS and pMOS of not passing strong 1’s and strong 0’s respectively can
be overcome by using Transmission gate.
It has an nMOS and pMOS connected in parallel as shown in fig below.
Fig 1.24 nMOS inverter with resistive load, I-V characteristics and transfer characteristics
An alternate to this is using a more practical circuit called pseudo-nMOS inverter circuit, which
uses a pMOS transistor as a load with its gate terminal always grounded.
Here pMOS will be in ON state. When Vin = 0, nMOS is OFF and as pMOS is ON the output rises
to Vdd. When Vin = 1, nMOS will be ON and pulls the output to gnd.
When the transfer characteristics is observed as the W/L ratio is varied for pMOS in the pseudo-
nMOS inverter circuit, the shape of the transfer characteristics varies.
As parameter P (i.e., as W is decreased sharper characteristics is obtained) is varied characteristics
varies with higher value of P less sharper characteristics is seen.
In the circuit P/2 represents the W/L ratio.
These types of gates are called as ratioed circuits as transfer function depends on the strength of
pull down (pMOS) to pull up (nMOS) devices.
In these types of circuits ratios must be chosen properly so that circuit operates properly.
Disadvantage seen with these ratioed circuits are
Fig 1.24 pseudo-nMOS inverter with I-V characteristics and transfer characteristics
However these circuits are used under limited circumstances such as reduced input capacitance and
smaller area.
FABRICATION
(f & g) thin SiO2 layer formation and deposition of polysilicon for gate terminal
(i & j) thick layer of SiO2 grown and masked with photoresist S and D contact cuts
(k & l) metal layer deposition and metal layer is masked and etched to form final nMOS transistor
Fig 1.25: nMOS Fabrication steps
Fig 1.27 CMOS p-well inverter showing VDD and VSS substrate connections
1. The p-well structure has an n-type substrate in which p-type devices can be formed with the help of
masking and diffusion. In order to accommodate n-type devices, deep p-well is diffused into the n-
type substrate. This is shown in Fig 1.27
2. Masking, patterning and diffusion process is same as that of nMOS fabrication. The summaries of
processing steps are:
Mask: defines the areas in which the deep p-well diffusion has to take place.
Mask 2: defines the thin oxide region (where the thick oxide is to be removed or stripped and thin
oxide grown)
Mask 3: patterning the polysilicon layer which is deposited after thin oxide.
Mask 4: A p+ mask is used (to be in effect “AND” with mask 2) to define areas where p-diffusion
is to take place.
Mask 5: –ve form of mask 4 (p+ mask) is used which defines areas where n- diffusion is to take
place.
Mask 6: Contact cuts are defined using this mask.
Mask 7: The metal layer pattern is defined by this mask.
Mask 8: An overall passivation (over glass) is now applied and it also defines openings for accessing
pads.
3. In the process, the diffusion should be carried out with special care as p-well concentration and
depth will affect the threshold voltage and also the breakdown voltage of the n- transistor.
4. To achieve low threshold voltage either deep-well diffusion or high-well resistivity is required.
5. But deep well require larger spacing between n- and p-type transistors and wires due to lateral
diffusion and therefore needs larger chip area.
6. The p-well acts as substrate for n-devices within parent n-substrate and two areas are electrically
isolated
An n-well mask is used to define n-well regions, as opposed to a p-well mask in a p-well process.
Fig. Depicts inverted circuit fabricated by n-well process.