Title Page

VLC Transceiver System Design Using LED

for IEEE 802.15.7 Standard

by

Fengyu CHE

A Thesis Submitted to
the Hong Kong University of Science and Technology
in Partial Fulfillment of the Requirements for
the Degree of Master of Philosophy
in Electronic and Computer Engineering

January 2015, Hong Kong

HKUST Library
Reproduction is prohibited without the author’s prior written consent
 Acknowledgements

First and foremost, I would like to give my greatest thanks to my thesis supervisor, Prof.
Patrick YUE, and my thesis co-supervisor, Prof. Liang WU, for their insightful guidance,
great encouragement, kind support, and endless patience during my MPhil study. They have
offered me with a valuable opportunity to work on this interesting and promising project.
They always provide timely advises to lead me to the right track of my research. Their
wisdom, kindness and enthusiasm encourage me during my study as an MPhil and will keep
influencing me in my future life.
I would like to thank Prof. Kei May LAU and Prof. Wing-Hung KI for their kindness of
serving as the thesis exam committee members of mine. I really appreciate their worthy time
and their valuable comments and suggestions. I would also like to thank Prof. Wing-Hung KI
for offering me the opportunity to collaborate with his group. The experience benefits me
greatly.
I would also like to express my thanks to Mr. S.F. LUK for his kind support in teaching
and helping me with the digital backend implementation and the chip bonding.
I want to thank Ms. Tania LEIGH WILMSHURST as well for her enthusiastic help and
support with my English in the thesis.
I am also very grateful to my colleagues in Sensor and Instrumentation Laboratory, Dr. Li
SUN, Dr. Quan PAN, Mr. Yipeng WANG, Mr. Zhengxiong HOU, Mr. Babar HUSSAIN, Mr.
Xianbo LI, Mr. Duona LUO, Miss Liwen JING, Mr. Guang ZHU, Mr. Zhixin LI, etc., and
also my colleagues in Integrated Power Electronics Laboratory, Dr. Yan LU, Mr. Lin CHENG,
Mr. Feng ZHANG, Mr. Min TAN, etc. They have given me worthy help and have made a
pleasant working environment. I would also like to thank Mr. Xinwei WAN, Mr. Qicheng
ZHANG, Mr. Guoqiang CAI, etc. for their kind help in my life.
Last but not least, I would like to express my heartfelt thanks to my parents, my girlfriend
Ruoyuan REN, and my family for their unconditional support and endless love.

iv
Table of Contents

Title Page ............................................................................................................................... i

Authorization ........................................................................................................................ ii

Signature Page ..................................................................................................................... iii

Acknowledgements ............................................................................................................. iv

Table of Contents.................................................................................................................. v

List of Figures .................................................................................................................... viii

List of Tables ........................................................................................................................ x

Acronyms and Abbreviations .............................................................................................. xi

Abstract .............................................................................................................................. xiii

CHAPTER 1 INTRODUCTION ....................................................................................... 1

1.1 VLC Background, Motivation & Potential Applications ..................................... 1

1.2 Related Works ...................................................................................................... 3

1.3 Thesis Organization.............................................................................................. 4

CHAPTER 2 SYSTEM SPECIFICATIONS ..................................................................... 5

2.1 Specifications of IEEE Standard 802.15.7-2011 .................................................. 5

2.1.1 Classes of Devices for VLC ............................................................................. 5

2.1.2 Network Topologies ......................................................................................... 6

2.1.3 Dimming & Visibility Support ......................................................................... 7

2.1.4 PHY Layer Specifications ................................................................................ 8

2.2 Link Budget Analysis ......................................................................................... 11

2.2.1 Transmit Power with Path Loss ...................................................................... 11

2.2.2 RX SNR and BER Estimation ........................................................................ 14

2.3 Transmitter Specification ................................................................................... 17

2.3.1 Digital Baseband............................................................................................. 17

2.3.2 Power Management Unit ................................................................................ 19

2.3.3 Dimmer ........................................................................................................... 20

v
 2.4 Receiver Specification........................................................................................ 20

2.4.1 Analog Front-End ........................................................................................... 20

2.4.2 Digital Baseband............................................................................................. 20

CHAPTER 3 TRANSMITTER SOC DESIGN ............................................................... 21

3.1 Digital Baseband ................................................................................................ 21

3.1.1 Reed-Solomon Encoder .................................................................................. 21

3.1.2 Interleaver ....................................................................................................... 25

3.1.3 Convolutional Encoder ................................................................................... 28

3.1.4 Run-Length Limited Encoder ......................................................................... 29

3.1.5 Digital Modulator ........................................................................................... 31

3.1.6 Top MCS Controller ....................................................................................... 31

3.1.7 Data Buffer ..................................................................................................... 32

3.1.8 Multiplexer ..................................................................................................... 33

3.1.9 Synthesis ......................................................................................................... 33

3.1.10 Place & Route ............................................................................................. 34

3.2 DC-DC Boost Converter .................................................................................... 35

3.2.1 Power Stage Working Principle ..................................................................... 35

3.2.2 Current Mode Control .................................................................................... 37

3.2.3 DC-DC Boost Converter System Design ....................................................... 38

3.2.4 Power MOSFET Design ................................................................................. 39

3.3 Dimmer............................................................................................................... 41

3.3.1 Transistor Pair Dimmer .................................................................................. 41

3.3.2 Current Balancing Dimmer ............................................................................ 42

3.4 System Integration.............................................................................................. 42

3.4.1 Interface between Digital Baseband & Dimmer ............................................. 43

3.4.2 Interface between Digital Baseband & Off-Chip ........................................... 44

3.4.3 Mixed Signal Verification .............................................................................. 46

vi
 3.4.4 SoC Floor Plan................................................................................................ 47

CHAPTER 4 RECEIVER DESIGN ................................................................................ 48

4.1 RX Analog Front-End Design ............................................................................ 48

4.2 Digital Baseband Design .................................................................................... 50

CHAPTER 5 EXPERIMENTAL RESULTS: ................................................................. 52

5.1 Chip Micrograph ................................................................................................ 52

5.2 PCB Design ........................................................................................................ 52

5.3 Measurements..................................................................................................... 56

5.3.1 DC-DC Boost Converter Steady-State Measurement .................................... 56

5.3.2 DC-DC Boost Converter Efficiency Measurement ........................................ 57

5.3.3 Current Balancing Dimmer Measurement ...................................................... 58

5.3.4 DC-DC Boost Converter Transient Response under VLC Operation ............ 60

5.3.5 VLC Dimming Function Measurement .......................................................... 62

5.3.6 PER Measurement of the Transceiver System ............................................... 63

5.3.7 Eye Diagram Measurement with Lens ........................................................... 65

5.3.8 Performance Summary ................................................................................... 65

CHAPTER 6 CONCLUSION.......................................................................................... 68

References .......................................................................................................................... 69

Appendix A EQUIPMENT FOR MEASUREMENT ..................................................... 71

vii
List of Figures

Figure 1.1 Development in Power Efficacy for Different Light Sources [2] ....................... 1
Figure 1.2 Development in Thermal Dissipation Capability [3] .......................................... 2
Figure 2.1 Network Topologies ............................................................................................ 6
Figure 2.2 Dimming Control Mechanism............................................................................. 7
Figure 2.3 Modulation-Domain Spectrum of All PHY Types ............................................. 9
Figure 2.4 PPDU Format Structure ...................................................................................... 9
Figure 2.5 Luminosity Function ......................................................................................... 12
Figure 2.6 Normalized Spectral Power Distribution of White LED .................................. 14
Figure 2.7 PD Responsivity ................................................................................................ 14
Figure 2.8 System Block Diagram of RX Front-End ......................................................... 15
Figure 2.9 Estimated BER .................................................................................................. 16
Figure 3.1 System Diagram of the Digital Baseband ......................................................... 21
Figure 3.2 Block Diagram of RS Encoder .......................................................................... 24
Figure 3.3 Block Diagram of the RS(15,11) Shift Register Encoder Circuit ..................... 25
Figure 3.4 Two Types of Errors Due to Noise ................................................................... 26
Figure 3.5 Working Principle of Interleaver ...................................................................... 27
Figure 3.6 Block Diagram of the Convolutional Encoder .................................................. 28
Figure 3.7 Puncturing Pattern for Convolutional Encoder ................................................. 29
Figure 3.8 Pre-Layout Simulation Result of the Synthesized Digital Baseband Design ... 34
Figure 3.9 Layout of the Digital Baseband Design ............................................................ 34
Figure 3.10 Basic DC-DC Boost Converter Topology....................................................... 35
Figure 3.11 Timing Diagram of Boost Converter in CCM ................................................ 36
Figure 3.12 Current Comparison of Boost Converter in CCM & DCM ............................ 37
Figure 3.13 System Diagram of a Current-Mode Control Boost Converter ...................... 38
Figure 3.14 System Diagram of the DC-DC Boost Converter ........................................... 38
Figure 3.15 NMOS20M cell ............................................................................................... 40
Figure 3.16 Christmas-Tree Layout Structure .................................................................... 40
Figure 3.17 Metal-4 Layout of Transistor Pair Dimmer .................................................... 41
Figure 3.18 Schematic of Current Balancing Dimmer ....................................................... 42
Figure 3.19 Schematic & Simulation Result of Dimming Buffer Verification .................. 43
Figure 3.20 Schematic & Simulation Result of Digital Input Signal Verification ............. 45
Figure 3.21 Schematic & Simulation Result of Digital Output Signal Verification .......... 46

viii
Figure 3.22 Simulation Result of Mixed Signal Verification ............................................. 47
Figure 3.23 Layout of TX SoC ........................................................................................... 47
Figure 4.1 System Block Diagram of RX........................................................................... 48
Figure 4.2 Responsivity & Package of the PD ................................................................... 48
Figure 4.3 Schematic & Transient Simulation Result of TIA ............................................ 49
Figure 5.1 Chip Micrograph of the TX SoC ....................................................................... 52
Figure 5.2 Schematics of COB-PCB Design ...................................................................... 53
Figure 5.3 Schematics of LED-PCB Design ...................................................................... 54
Figure 5.4 Fabricated PCBs for the TX SoC ...................................................................... 54
Figure 5.5 Current Flow of DC-DC Boost Converter ........................................................ 55
Figure 5.6 Layout of the Power Stage ................................................................................ 55
Figure 5.7 Converter Steady-State Measurement Setup ..................................................... 56
Figure 5.8 Converter Steady-State Measurement Result.................................................... 57
Figure 5.9 Converter Efficiency Measurement Setup ........................................................ 57
Figure 5.10 Converter Efficiency Measurement Result ..................................................... 58
Figure 5.11 Current Balancing Dimmer Measurement Setup ............................................ 59
Figure 5.12 Current Balancing Dimmer Measurement Result ........................................... 59
Figure 5.13 TX SoC VLC & PMU Cooperation Measurement Setup ............................... 60
Figure 5.14 VLC Transient Measurement Result ............................................................... 61
Figure 5.15 TX SoC VLC Dimming Measurement Setup ................................................. 62
Figure 5.16 TX SoC VLC Dimming Measurement Result ................................................ 62
Figure 5.17 TX SoC VLC PER Measurement Setup ......................................................... 63
Figure 5.18 Eye Diagram Measurement Result .................................................................. 64
Figure 5.19 Illuminance & PER Measurement Result ....................................................... 64
Figure 5.20 Eye Diagram with Lens Measurement Setup .................................................. 65
Figure 5.21 Eye Diagram with Lens Measurement Result ................................................. 65
Figure A.1 ADCMT 6243 & 6244 ..................................................................................... 71
Figure A.2 Kikusui PLZ164WL ......................................................................................... 71
Figure A.3 ADCMT 7461A................................................................................................ 72
Figure A.4 Agilent MSO7034B.......................................................................................... 72
Figure A.5 Extech EA33 .................................................................................................... 73

ix
List of Tables

Table 2.1 Device Classification ............................................................................................ 6

Table 2.2 Example of Visibility Patterns for 8B10B Code .................................................. 8
Table 2.3 PHY Summary...................................................................................................... 9
Table 2.4 PHY-I Operating Modes..................................................................................... 11
Table 2.5 Luminous Fluxes of Some Typical Light Sources ............................................. 12
Table 2.6 Illuminance of Some Typical Conditions ........................................................... 13
Table 2.7 Digital Baseband Pin List ................................................................................... 18
Table 2.8 Design Specification for PMU ........................................................................... 19
Table 3.1 Representations of GF(16) Elements.................................................................. 23
Table 3.2 Multiplication Table for GF(16) ......................................................................... 23
Table 3.3 Generator Polynomials for RS Codes................................................................. 24
Table 3.4 Manchester Code Mapping................................................................................. 29
Table 3.5 4B6B Code Mapping .......................................................................................... 30
Table 3.6 Synthesized Area Report .................................................................................... 33
Table 3.7 Timing Analysis Report for Setup Time ............................................................ 35
Table 3.8 Timing Analysis Report for Hold Time ............................................................. 35
Table 4.1 Design Parameters for Viterbi Decoder ............................................................. 50
Table 5.1 Performance Summary ....................................................................................... 66
Table 5.2 Design Comparison ............................................................................................ 67

x
Acronyms and Abbreviations

APD avalanche photodiode

BER bit error rate
CCM continuous conduction mode
CDR clock and data recovery
COB chip on board
CRC cyclic redundancy check
CSK color-shift keying
DC direct current
DCM discontinuous conduction mode
DMT discrete multitone
EMI electromagnetic interference
ESD electrostatic discharge
FEC forward error correction
FIFO first-in-first-out
FLP fast locking pattern
FPGA field-programmable gate array
GBW gain bandwidth product
GF Galois field
GPIB general purpose interface bus
HCS header-check sequence
Hg mercury
HPF high pass filter
IoT internet of things
IP intellectual properties
ISI intersymbol interference
LED light-emitting diode
MAC medium access control
MCS modulation and coding scheme
NRZ non return to zero
OCP over-current protection
OOK on-off keying
OVP over-voltage protection

xi
PCB printed circuit board
PD photodiode
PER packet error rate
PHR physical-layer header
PHY physical layer
PHY-I type-I physical layer
PMU power management unit
PPDU physical-layer data unit
PSDU PHY service data unit
PWM pulse width modulation
RF radio frequency
RLL run-length limited
RMS root mean square
RS Reed-Solomon
RTL register-transfer level
RX receiver
SCP short-circuit protection
SHR synchronization header
SNR signal-to-noise ratio
SoC system-on-chip
SRC shift register circuit
TDP topology dependent pattern
TIA transimpedance amplifier
TX transmitter
VLC visible light communication
VPPM variable pulse-position modulation

xii
 VLC Transceiver System Design Using LED
for IEEE 802.15.7 Standard
by

Fengyu CHE

Department of Electronic and Computer Engineering

The Hong Kong University of Science and Technology

Abstract

Owing to high energy efficiency, high reliability and low cost, solid-state lighting using
LEDs is progressively becoming popular in recent years. Due to their inherent fast response,
LEDs can also be used for visible light communication (VLC). The modulation frequency is
far beyond the flicker fusion threshold of human beings that the basic illumination of LEDs
would not be affected. VLC is projected to relief the spectrum demands for RF
communication. Recently, VLC systems for different applications under environments have
been extensively studied In particular, IEEE has released a standard, IEEE 802.15.7 on
visible-light communication Personal Area Network (VPAN) in which both a physical layer
(PHY) and a medium access control (MAC) layer are defined and various network topologies
are provided.
In this dissertation, a VLC transceiver system compliant with the type-I physical layer
(PHY-I) defined in IEEE 802.15.7 is designed and implemented. The transmitter SoC,
including a baseband (BB), a DC-DC boost LED driver and a dimmer, was fabricated in a
0.35μm CMOS process. Experimental results demonstrate that a maximum output power of
8W can be achieved with an efficiency of 83%, while the transmitter generates VLC signals
comply with the coding and modulation schemed as defined in the standard. On the other
hand, the receiver composed of an analog front-end and a digital baseband was implemented
with off-the-shelf components and in an FPGA development board, respectively. The RX
features a bandwidth of 4MHz and a transimpedance gain of 100dBΩ. With OOK modulation,
the whole VLC transceiver system measures a data rate of 266kb/s with PER <10% at a
distance of 2.2m.

xiii
CHAPTER 1 INTRODUCTION

1.1 VLC Background, Motivation & Potential Applications

Recently, energy saving for building a more sustainable environment has drawn
considerable attention. This has led to the rapid deployment of light emitting diodes (LEDs)
for general-purpose lighting to replace conventional fluorescent and incandescent lights [1].
In addition to being energy efficient, LEDs are considered environmentally friendly as they
are free of mercury (Hg). Figure 1.1 shows that the luminous efficacy of LEDs has already
reached a comparative level to the majority of commonly used standard light sources. Thanks
to their low-cost and high reliability, LEDs are predicted to be the most promising light
source in terms of energy efficiency in the next five years [2]. As shown in Figure 1.2, with
the development in the LED packaging technique, the thermal resistance of LEDs has been
substantially reduced such that their heat dissipation problem is mitigated [3]. This has led to
the production of high power LEDs for general-purpose lighting.

Figure 1.1 Development in Power Efficacy for Different Light Sources [2]

1
 Figure 1.2 Development in Thermal Dissipation Capability [3]
In addition to being utilized as a light source, LEDs can also be used as visible light
communication (VLC) source simultaneously. The basic concept behind VLC is to modulate
and demodulate visible light to encode information in the form of varying intensities of light.
People have been using VLC since as early as 800 B.C., when beacon fire served as a long
range indicator. In modern times, signal lamps are used for ship-to-ship communication and
red, yellow and green lamps are used for traffic indicators. The aforementioned are all
examples of low speed VLC [4].
During the last one and a half decades, high speed VLC has been a hot topic amongst
researchers. There are several advantages of VLC: The first advantage is the availability of
the unlicensed spectrum of visible light at hundreds of THz. This un-regulated spectrum,
packing a huge amount of bandwidth, can be used to transmit at extremely high data rates.
Secondly, there is no radio frequency (RF) radiation and no electromagnetic interference
(EMI) in the visible light, making VLC safe to the human body. Thus it can be used in some
restricted areas, such as airplanes and hospitals. Thirdly, visible light presents a unique line-
of-sight characteristic and cannot pass through walls or other opaque objects, which
guarantees the security of the communication in comparison to other less secure forms of
communication, for instance, Wi-Fi and cellular communications. Last but not the least, VLC
technology is fully compliant with existing illumination infrastructure. This can lead to a
rapid expansion of VLC services on a large scale with a considerably low cost.

2
 With dual functional LEDs, VLC could lead to the Internet of Things (IoT) due to the
ubiquitous deployment of LEDs. Under indoor situations, VLC could serve as the data link
utilizing indoor illumination infrastructure, fixed electrical appliances and mobile devices,
and in the outdoor environment, VLC could be used to transfer information between traffic
lights and vehicles [4]. Other interesting applications include underwater communication
thanks to much less attenuation of visible light compared to RF signals and a higher data rate
compared to sonar. The market for VLC technology is projected to have a compound annual
growth rate of 87.31% and reach over $9 billion by 2020 [5].

1.2 Related Works

A number of VLC transmitter systems have been developed. In [6], a typical white light
LED made of a blue LED with a phosphor coating is used as the light source. It is powered up
by the DC voltage source, while the signal is AC-coupled to the input with a Bias-T. The data
rate achieved is 10Mb/s due to the typical 2~3 MHz bandwidth limited by the slow temporal
response of phosphor emission. In [7], by applying equalization technique on white LEDs, the
bandwidth of the VLC channel is increased to 25MHz. The highest transmission data rate is
50Mb/s at 2m with the help of lenses. Furthermore, a blue optical filter is used at the receiver
(RX) side to selectively allow the blue light from white LEDs such that the frequency response of
the VLC channel is expanded to 35MHz, and more complicated modulations such as discrete
multitone (DMT) modulation are employed to achieve a gross data rate of 513Mb/s at a distance
of 0.3m [8]. Other than white LEDs, a gallium nitride blue μLED with a 3-dB bandwidth higher
than 60MHz is employed, demonstrating a 3Gb/s VLC at a distance of 0.05m [9]. Even though
the data rate of VLC systems has been demonstrated to achieve a comparable level to Wi-Fi, the
above VLC transmitters are mostly based on discrete components and thus suffer from low
reliability, large form factors, extremely high costs and high power consumption. Moreover, some
of the systems are constructed using bulky equipment. In addition, most of the VLC systems are
merely developed for functional demonstration purposes and hence, do not follow a universal
standard. Consequently, they are neither suitable to be integrated in mobile devices, nor practical
enough to support ubiquitous VLC services.

3
1.3 Thesis Organization

The objective of this research is to design and implement a lensless VLC transceiver
system for location-based information broadcasting using commercial white LEDs. Although
[7-9] all use lenses to improve the performance of VLC in terms of the communication
distance, lenses limit the field of view of a RX and also are difficult to align, which are not
feasible for broadcasting applications. Commercial white LEDs typically provides a 2~3MHz
bandwidth due to the slow response time of phosphor and the parasitic capacitance and
inductance of the device. However, compared with employing complicated equalization
circuits or utilizing advanced μLEDs to expand the frequency response, VLC systems using
commercial white LEDs are more robust and have advantages in ubiquitous deployment. The
broadcasted location-based information does not require high data rate for transmission but
the reliability of the information must be guaranteed. In the IEEE Std. 802.15.7 for VLC, The
type-I physical layer (PHY-I) provides robust forward error correction coding schemes and
well matches the application of this work [10]. Thus, PHY-I specified in the standard is
realized. The transmitter (TX) is implemented as a system-on-chip (SoC) with an on-chip
power management unit to drive the LEDs. The RX is implemented on a field programmable
gate array (FPGA). The thesis is organized as follows. The system specifications are
described in CHAPTER 2. CHAPTER 3 states the TX SoC design. In CHAPTER 4, the RX
design is provided. The measurement results, together with the measurement setups, are
presented in CHAPTER 5. Finally, CHAPTER 6 concludes the whole thesis.

4
CHAPTER 2 SYSTEM SPECIFICATIONS

2.1 Specifications of IEEE Standard 802.15.7-2011

The IEEE Standard for Local and Metropolitan Area Networks – Part 15.7: Short-Range
Wireless Optical Communication Using Visible Light (IEEE Std. 802.15.7) was released by
the IEEE 802.15.7 visible light communication (VLC) task group in 2011. The standard aims
at providing a global standard for short-range VLC utilizing the wavelength at the unlicensed
spectrum extending from 380nm to 780nm. Both a physical layer (PHY) and a medium access
control (MAC) layer are defined in the standard for achieving data rates ranging from
11.67kb/s to 96Mb/s, which is adequate to support audio and video multimedia services. The
standard takes into consideration different classes of devices and provides three network
topologies for a variety of applications. The standard also considers noise and interference
from different light sources, such as ambient light, and provides supports for dimming,
visibility, color-stabilization etc.

2.1.1 Classes of Devices for VLC

There are three classes of devices that are taken into consideration in the standard:
infrastructure, mobile, and vehicle. The performance parameters of these devices, such as
power supply capacities, mobility, communication range, etc., are summarized in Table 2.1.
Taking the infrastructure class as an example, the ample power supply indicates that high
power and high clock rate can be used to achieve long range, high data rate VLC. However,
considering the function of the infrastructure, visibility support for both the VLC active and
idle periods is necessary for lighting purposes. On the other hand, for mobile devices, the
limited power supply restricts the power consumption of the transmitter. Thus, a relatively
lower clock rate and higher error correction support may be required for compensation and
the transmitter may be switched off frequently during the VLC idle period.

5
 Table 2.1 Device Classification
Device Class Infrastructure Mobile Vehicle
Fixed Coordinator Yes No No
Power Supply Ample Limited Moderate
Form Factor Unconstrained Constrained Unconstrained
Light Source Intense Weak Intense
Physical Mobility No Yes Yes
Range Short/Long Short Long
Data Rates High/Low High Low

2.1.2 Network Topologies

Considering the varieties of applications of VLC, three network topologies, peer-to-peer,

star, and broadcast, are defined in the standard, as shown in Figure 2.1. In a peer-to-peer
topology, a device can communicate with any other device within the area that it can cover.
Once the network is formed, communication will be only carried out between the two peers
where one of the peers will function as a coordinator. In a star topology, the network is
formed by a coordinator and other devices are allowed to join the network and establish
communication with the coordinator. In a broadcast topology, no coordinator is needed. A
transmitting device only performs uni-directional communication and is not associated with
any other device
In all the aforementioned topologies, visibility support is provided to maintain the lighting
function during the VLC idle period. This guarantees the original illumination function and
mitigates flicker due to the transition between the VLC active and idle periods.

Figure 2.1 Network Topologies

6
 2.1.3 Dimming & Visibility Support

Dimming and visibility support is introduced to maintain a seamless illumination level. It

provides the capability of changing the intensity of the illumination and mitigating the flicker
problem.
Figure 2.2 illustrates the dimming control mechanism during VLC active period. In
variable pulse-position modulation (VPPM) mode, the dimming can be easily achieved by
varying the pulse width of the transmitted symbols. However, the dimming control in OOK
mode is relatively complicated. Due to the run-length limited (RLL) coding used in OOK
mode, the transmitted VLC OOK modulated symbols are always of 50% duty ratio. To
support dimming, compensation symbols (CS) are inserted into the VLC data stream. As
shown in Figure 2.2 (b), in order to achieve a 30% brightness in OOK mode, a 10% CS is
combined with a 50% VLC OOK data.

(a) VPPM Dimming

(b) OOK Modulation Dimming

Figure 2.2 Dimming Control Mechanism

7
 During the VLC idle period, rather than switching off the light, visibility patterns are
transmitted to sustain a constant dimming level. Table 2.2 enlists a set of visibility patterns
along with corresponding dimming levels. These patterns support the continuous visibility
feature and, more importantly, mitigate the interframe flicker, thereby eliminating the
perceivable brightness fluctuation between adjacent frames. As a result, the average
brightness of the VLC idle period remains equal to that of the active period.
Table 2.2 Example of Visibility Patterns for 8B10B Code

Visibility Pattern Percentage Visibility

11111 11111 100%
11110 11111 90%
11110 11110 80%
11101 11100 70%
11001 11100 60%
10001 11100 50%
00001 11100 40%
00001 11000 30%
00001 10000 20%
00001 00000 10%
00000 00000 0%

The other type of flicker is intra-frame flicker, which is defined as the perceivable
brightness fluctuation within a frame. This type of flicker is mitigated by using run-length
limited (RLL) coding, a modulation scheme, or a combination of both.

2.1.4 PHY Layer Specifications

There are 3 different types of PHY defined in the standard. Table 2.3 provides a summary
of the operating conditions, the modulation schemes used, and the transmission data rates for
each PHY. Type-I physical layer (PHY-I) has a lower data rate as there is more noise and
interference in the targeted outdoor conditions. PHY-II is designed for indoor usage, and the
data rates can achieve tens of Mb/s, owing to the more stabilized operating conditions. Both
PHY-I and PHY-II use on-off keying (OOK) and VPPM and uniformly modulate the wide
visible light spectrum. However, PHY-III is targeted at applications with multiple light
sources and detectors and thus uses color-shift keying (CSK) to distinctly modulate the wide
visible light spectrum to achieve data rates in the order of tens of Mb/s.

8
 Table 2.3 PHY Summary

PHY Type Operating Condition Modulation Scheme Data Rate

PHY-I Outdoor Low Data Rate OOK & VPPM 11.67 ~ 266.6kb/s
PHY-II Indoor Moderate Data Rate OOK & VPPM 1.25 ~ 96Mb/s
PHY-III Multi-Color Light Source & Detector CSK 12 ~ 96Mb/s

Figure 2.3 shows the modulation-domain spectrum of all the PHY types. In order to
reduce the interference from other light sources and guarantee the quality of the VLC signal,
the entire spectrum occupied by the PHY types is situated higher than the ambient light
interference region. Moreover, the spectrum occupied by PHY-I is different from the
spectrum occupied by PHY-II and PHY-III. Thus, PHY-I can coexist with PHY-II and
PHY-III.

Figure 2.3 Modulation-Domain Spectrum of All PHY Types

The final VLC data package sent out by the PHY is the physical-layer data unit (PPDU).
Figure 2.4 shows the detailed PPDU format structure for the PHY.

Figure 2.4 PPDU Format Structure

9
 The first field in the PPDU is a synchronization header (SHR). It provides an optical clock
synchronization function and indicates the start of the communication. The optical clock
synchronization is achieved by sending a fast locking pattern (FLP) of at least 64 alternate
ones and zeros. This fast transition sequence can be used by the clock and data recovery
(CDR) circuit on the receiver (RX) side to lock the clock. Following this pattern, four
topology dependent patterns (TDPs) are sent to indicate the topologies used and signal the
start of communication. The SHR is always transmitted using OOK modulation without any
encoding schemes.
A physical-layer header (PHR) is transmitted after the SHR and consists of a PHY header,
an header-check sequence (HCS), and an optional field. The PHY header contains important
information, such as the modulation and coding scheme identifier (MCS ID), the length of the
PHY service data unit (PSDU), etc. This information specifies how the PSDU is transmitted,
such as the length, the data rate, the modulation and coding scheme, etc. The HCS is a 16-bit
cyclic redundancy check (CRC )which is used to protect the aforementioned PHY header. The
optional field, transmitted in certain conditions, is used to provide tail bits for the
convolutional encoder, to specify dimmed OOK operation or to calibrate the optical channel.
The whole PHR is transmitted using OOK modulation at the lowest data rate for the chosen
optical clock rate. This is to provide an agreement between the transmitter (TX) and RX in
terms of the PHY encoding and decoding since the PHR is the first part of the PPDU that is
encoded. Furthermore, the lowest data rate implies that an encoding scheme with the highest
error correction capability is used to ensure the reliability of the PHR.
The PSDU contains the actual information that is to be transmitted. The information is
first modulated and encoded according to the MCS ID indicated in the PHR and then sent
straight after the PHR.
Table 2.4 shows the detailed operating modes of PHY-I. As mentioned before, both OOK
and VPPM are used in this PHY type. For OOK modulation, the optical clock rate is chosen
to be 200kHz. In addition, Manchester code is used as the RLL code, and both Reed-Solomon
(RS) code and convolutional code are selected for forward error correction (FEC). Moreover,
by selecting various combinations of the FEC codes, the data rates can be varied from
11.67kb/s to 100kb/s. On the other hand, for VPPM, a 400kHz optical clock is specified with
4B6B coding used as the RLL code. For the choice of FEC, only RS code is supported and
selection of a particular type can lead to a data rate ranging from 35.56kb/s to 266.6kb/s.

10
 Table 2.4 PHY-I Operating Modes
Optical Convolutional
Modulation RLL Code RS Code Data Rate
Clock Rate Code
(15,7) 1/4 11.67kb/s
(15,11) 1/3 24.44kb/s
OOK Manchester 200kHz (15,11) 2/3 48.89kb/s
(15,11) None 73.3kb/s
None None 100kb/s
(15,2) None 35.56kb/s
(15,4) None 71.11kb/s
VPPM 4B6B 400kHz
(15,7) None 124.4kb/s
None None 266.6kb/s

2.2 Link Budget Analysis

The link budget analysis studies the whole communication system, including the channel,
from the available resources point of view. It is a key step in the communication system
design for licensing the transmit power, determining the transceiver circuit topology,
predicting the system performance, etc. The link budget analysis for the VLC system is
divided into two parts, namely the transmit power with path loss and the RX signal-to-noise
ratio (SNR) and bit error rate (BER) estimation.

2.2.1 Transmit Power with Path Loss

Unlike in radio frequency (RF) design, a VLC system performs the dual functionality of
illumination and communication. Therefore, while qualifying a VLC system, the VLC signal
strength is indicated by two commonly used illumination units of light, i.e., the luminous flux
and the illuminance. Thus, in order to perform the link budget analysis, these terminologies
must be converted into electrical quantities.
The luminous flux is the measure of the power of light as perceived by the human eye.
The SI unit of the luminous flux is lumen (lm). The luminous flux is different from the radiant
flux, which measures the absolute power of the electromagnetic radiation. The luminous flux
reflects the varying sensitivity of the human eye to different wavelengths of light. The
weighted sensitivity is described as the luminosity function V(λ), as shown in (2.1) [11]. The
relative sensitivity is presented in Figure 2.5.
( ) ( ) (2.1)

11
 Figure 2.5 Luminosity Function

In illumination systems, the luminous flux is normally used to quantify the transmit power
of the light source. The luminous fluxes of some typical light sources are summarized in
Table 2.5 [12].
Table 2.5 Luminous Fluxes of Some Typical Light Sources

Light Source Luminous Flux (lm)

Candle 5-15
5W White LED 150
11W Compact Fluorescent Lamp 660
60W Incandescent Lamp 730
100W Halogen Incandescent Lamp 1,250
36W Fluorescent Lamp 2,850
80W High-Pressure Mercury Lamp 3,450
35W Low-Pressure Sodium Lamp 4,800

The illuminance is the measure of the luminous flux per unit area. The SI unit is lux,
which is equal to one lumen per square meter. The illuminance is a quantitative description of
what is commonly called ‘brightness’. Table 2.6 summarizes the illuminance of some typical
working and living conditions [13]. In VLC systems, the illuminance is commonly used to
describe the received light intensity at the RX.

12
 Table 2.6 Illuminance of Some Typical Conditions

Condition Illuminance (lux)

Emergency Stairs 20 – 100
Corridor 100 – 200
Cooking 300 – 750
Office Work 500 – 1500
Detailed Drawing, Assembly Work 1500 – 3000

By applying Lambert’s law, the received factor fRX of the transmitted power due to the
path loss is shown in (2.2), where m represents the order of the Lambertian source, ARX is the
area of the receiver, and d is the separation between the transmitter and receiver. Angle α is
the angle of emergence of the TX, and angle β is the incident angle of the RX.
( )
( ) ( ) (2.2)

With the received factor fRX, the optical power received by the RX, PRX, can be expressed
as (2.3).
(2.3)
The transmit power PTX is calculated from the spectral power distribution St(λ). However,
for commonly used light-emitting diode (LED) lights, a normalized spectral power
distribution St’(λ) is provided in the vendor’s datasheet. Figure 2.6 shows the normalized
spectral power distribution of the cool white LED used in this project. The total luminous flux,
ΦV, can be evaluated by integrating the product of the spectral power distribution St(λ) and the
luminosity function V(λ), as shown in (2.4). Inversely, by expressing the St(λ) as (2.5), the
scaling factor c can be calculated to get the actual spectral power distribution St(λ).

∫ ( ) ( ) (2.4)

( ) ( ) (2.5)

13
 Figure 2.6 Normalized Spectral Power Distribution of White LED
The responsivity of the photodiode (PD), RPD, is described in units of A/W and is also a
wavelength dependent quantity, as shown in Figure 2.7. It is of more significance to directly
calculate the received optical current rather than the received power. Therefore, the received
PD current, IPD, is calculated by integrating the product of the transmit power and PD
responsivity over the whole visible spectrum and then multiplying by the received factor, as
shown in (2.6).

∫ ( ) ( ) (2.6)

Figure 2.7 PD Responsivity

2.2.2 RX SNR and BER Estimation

Both the RX SNR and BER estimation are based on the circuitry shown in Figure 2.8.

14
 Figure 2.8 System Block Diagram of RX Front-End

To estimate the SNR, the root mean square (RMS) value of both the received signal and
the noise are calculated with reference to the input of the RX front-end. Taking OOK as an
example, the light source keeps switching on and off. For the off period, no signal current is
generated. For the on period, the received photon current is estimated in 2.2.1. With the
Manchester coding that is specified in the IEEE Std. 802.15.7, the corresponding RMS value
of the received signal is calculated as

(2.7)

The received noises generated by each stage are calculated with reference to the input as
follows.
The first stage of the RX front-end is the PD. The noise of the PD, In_PD, is usually
estimated as a combination of the shot and thermal noise as shown in (2.8). In the equation, q
is the electronic charge, ID is the dark current of the PD, and IB denotes the current induced by
the background light. RSH represents the shunt resistance of the PD. Bn is the noise bandwidth
of the system, which is equal to π/2 times the pole frequency of the transimpedance amplifier
(TIA).

( ) (2.8)

The TIA, which consists of an amplifier and a feedback resistor, is the second stage of the
front-end. The noise contributed by the TIA can be obtained from the datasheet, while the
noise of the resistor is calculated by the thermal noise equation. Both of the two noises are
suppressed by the transimpedance gain, RF, of the TIA, and the input referred noise current of
the TIA stage is expressed as

15
 (2.9)

The last stage of the front-end is the high pass filter (HPF). Regardless of the capacitor,
the noise is entirely contributed by the resistors. Similar to the TIA stage, the thermal noise of
the HPF is also suppressed by the TIA gain, and the input referred noise current is given as
( )
(2.10)

In addition, the noise that is contributed by the power supply, Vcc, is also included with
reference to the input as In_Vcc,in.
In real application, other non-ideal factors, such as clock jitters, intersymbol interference
(ISI), parasitic resistances of printed circuit board (PCB) traces, electromagnetic interferences
(EMIs), etc., will also degrade the performance of a system. These uncharacterized factors are
referred as implementation loss, IL. The IL of this system is estimated to be 10dB.
With all the previous calculations, the SNR of the RX front-end can be expressed as

( ) (2.11)

The estimation of the BER is based on an OOK modulated system without any FEC
coding. The relationship between the BER and SNR is described as

( √ ) (2.12)
√
Figure 2.9 shows the estimated BER. As shown in the figure, the RX is estimated to
achieve a BER of 1e-7 at a distance of 2m from the TX.

Figure 2.9 Estimated BER

16
2.3 Transmitter Specification

A VLC TX system-on-chip (SoC) based on the IEEE Std. 802.15.7 is designed with a
power management unit on-chip for portable lighting purposes. The SoC consists of a digital
baseband, a power management unit with an on-chip power MOSFET, and a dimmer.

2.3.1 Digital Baseband

The digital baseband of the SoC implements the IEEE Std. 802.15.7 PHY-I. The detailed
specifications are laid out in Table 2.4. All the modulation and coding schemes in both the
OOK and the VPPM modes are implemented to support data rates from the lowest, 11.67kb/s,
to the highest, 266.6kb/s, as defined in the standard specifications. The operation of the digital
baseband is controlled by an off-chip field programmable gate array (FPGA) development
board. Both the control command and the data to be transmitted are sent from the FPGA to
the baseband of the SoC. In addition, the digital baseband is also powered up by the FPGA
development board with a 3.3V supply. The information signal, after being processed through
the baseband chain, is fed to the dimmer. The dimmer predominantly uses the baseband
modulated signal to modulate the LEDs. However, an off-chip VLC signal can also be used to
control the dimmer. Furthermore, output debug signals are added for design verification. The
pins used for the aforementioned control and power supply functions are summarized in Table
2.7.

17
 Table 2.7 Digital Baseband Pin List

Pin Name # of PAD Function

DVDD 3 Power Supply for Baseband (3.3V)
DGND 4 Digital Ground
CLK_4M 1 4MHz System Clock
RST_N 1 System Asynchronous Reset
RST_CLK_N 1 System Asynchronous Reset For Clock
I_EN 1 Input Enable Signal
I_DATA 1 Input Data Signal
O_FPGA_DN 2 Execution Done To FPGA
SEL_MUX 2 Dimming Mux Selection
EX_DIM 2 External Dimming Signal
O_I_DATA 1 Echoed Input Data for Debugging
O_VLC 1 Processed VLC Signal for Debugging
O_CLK_OPT 1 Optical Clock Signal for Debugging
O_CMD 1 VLC Command Signal for Debugging
O_CMD_HDR 1 VLC Command Header for Debugging

18
 2.3.2 Power Management Unit

The VLC TX SoC is designed for portable device usage. Thus, batteries are normally used
as the power supply, with the supply voltage ranging from 2.5V to 5V. White LEDs are often
driven in series to balance the current through each LED and hence equalize the brightness of
each LED. Therefore, this power management unit (PMU) is designed to handle at most
5 LEDs in series, where the maximum output voltage is 20V. At the same time, the lowest
output voltage is selected to be 5V in order to support a wide range of applications. To fulfill
these requirements, a boosting type DC-DC converter is the optimum choice for the PMU
topology. To provide a considerable luminous power, the PMU is targeted to power up a total
of 20 LEDs, divided into 4 parallel channels consisting of 5 LEDs in series. Under the
maximum output voltage, the current going through each branch is 100mA and the maximum
output power is calculated to be 8W. Since the PMU is used to drive LEDs that target VLC
application, the switching noise is expected to affect the quality of the communication. Hence,
the switching frequency is chosen to be 2MHz, which is 5 times higher than the maximum
400kHz PHY-I optical clock rate, to mitigate the effect of the switching noise on the VLC.
The power MOSFET is integrated on-chip to achieve high system integrity. However, due to
the large area and the low quality fact of the on-chip passive components, an inductor and a
capacitor for the boosting converter are placed off-chip, with moderate values of 4.7μH and
5μF respectively. The design specifications are summarized in Table 2.8.
Table 2.8 Design Specification for PMU

Parameter Min. Typ. Max. Unit

Input Voltage 2.5 3.7 5 V
Output Voltage 5 - 20 V
Number of Channels 1 - 4 -
Output Current per Channel - - 100 mA
Output Power - - 8 W
Operating Frequency 1.4 2 2.2 MHz
Temperature -40 25 125 ℃
Inductor - 4.7 - μH
Capacitor - 5 - μF

19
 2.3.3 Dimmer

The dimmer predominantly handles the dimming function of lighting in addition to

modulating the LEDs. As one of the potential applications of the SoC is for backlighting, the
brightness of each LED channel needs to be equalized. Thus, a current balancing circuit is
designed to balance the current between two channels so as to balance the luminance. The
current difference tolerance is set to be 3%, which is commonly used in industry. While
performing current balancing, the circuit needs to be able to achieve the modulation function
for VLC. Since a pulse width modulation (PWM) dimming signal is used to modulate the
LEDs, the current balancing circuit is designed to achieve a fast response to maintain the
balancing accuracy between each channel.

2.4 Receiver Specification

A receiver, which corresponds to the TX SoC, is designed. The receiver consists of an

analog front-end and a digital baseband.

2.4.1 Analog Front-End

The analog front-end is in charge of converting the optical signal into an electronic signal
and is composed of discrete components. The range of the spectral bandwidth of the front-end
should cover the visible light spectrum, i.e., from 380nm to 780nm. The 3-dB bandwidth of
the front-end is designed to be higher than 4MHz so that the VLC signal can be restored
successfully.

2.4.2 Digital Baseband

The digital baseband demodulates and decodes the received signal from the RX front-end
according to the IEEE Std. 802.15.7. The demodulation and decoding algorithms are
implemented by Verilog-HDL and Intellectual Properties (IP) cores can be used to perform
some of the functions. The entire baseband is implemented on the FPGA.

20
CHAPTER 3 TRANSMITTER SOC DESIGN

3.1 Digital Baseband

Based on the type-I physical layer (PHY-I) specification in Table 2.4 and the instructions
in the IEEE Std. 802.15.7, the system diagram of the digital baseband is designed as shown in
Figure 3.1. Both the command and data, and the clock are sent to a top modulation and coding
scheme (MCS) controller. The physical-layer header (PHR) and PHY service data unit (PSDU)
are then sent to the Reed-Solomon (RS) encoder and go through all the functional blocks in
the data path. The modulated signal is generated at the end of the data path, and all the
functional blocks in the data path are controlled by the top MCS control block.

Figure 3.1 System Diagram of the Digital Baseband

The blocks are all implemented by Verilog-HDL, and test benches are also implemented
to perform both pre- layout and post-layout simulations for design verification.

3.1.1 Reed-Solomon Encoder

The Reed Solomon code is one type of forward error correction (FEC) code that has been
widely used in many applications, for example, data storage in CDs and hard disks, and
communication for telephones and satellites.

21
 The Reed Solomon code is usually expressed in RS (n, k), where k is the number of input
symbols being encoded and n is the number of encoded output symbols, which is also known
as the code length. Given the same code length, n, and code rate, n/k, RS (n, k) codes provide
the largest possible code minimum distance for any linear code [14]. The code length n is
always equal to 2m - 1, where m is an integer greater than one. The number of parity-checks,
which is n - k, is normally equal to 2t. The t here is called the symbol-error correcting
capability of the code, which means that with 2t parity-checks, the maximum number of
symbol-errors that can be corrected is equal to t. Take RS (15, 7) code used in PHY-I as an
example; the code length n is 15 and there are seven data symbols in each RS code. With this
RS (15, 7) code, a maximum of four symbol-errors can be corrected, which is equal to
(15 - 7) / 2.
However, an RS (15, 4) code is also used as shown in Table 2.4, in which the number of
parity-checks is an odd number, 11. This is because apart from error-correction, the RS code
is also capable of performing erasure-correction, which is usually indicated by an odd number
of parity-checks. An erasure is defined as a symbol that is marked as a ‘potential error’.
Unlike spending two parity-checks for one error-correction, one erasure-correction only
consumes one parity-check. Both the RS (15, 4) and RS (15, 2) codes in PHY-I have the
erasure-correction function.
The Reed Solomon code used in PHY-I is based on the Galois field (16). The GF(16) is a
finite field and consists of 16 elements {0, α0, α1, α2, …, α14}. All elements in the GF(16) are
of four bits and are used to represent the symbols in the RS code. To implement the RS
encoder, the GF(16) is constructed first. As specified in the standard, the GF(16) is generated
by the polynomial x4 + x + 1. The binary vector representations of all the elements in the
GF(16) are shown in Table 3.1.
Two basic arithmetic operations in the GF(16), addition and multiplication, are also
implemented to perform RS encoding. The addition in GF(16) is defined as a modulo-2
addition without using carry arithmetic. This can simply be realized by performing a bit-wise
XOR function in the digital logic design. The multiplication operation is defined by summing
the elements’ exponents modulo n = 5. For example, α6α12 = α(6+12) mod 15 = α3. This can be
easily performed using the elements’ exponents, but the logic operation in the form of vector
representation is complicated. Thus, look-up tables are created for the multiplication operation
based on the multiplication table shown in Table 3.2.

22
 Table 3.1 Representations of GF(16) Elements
Element Vector Representation
0 0000
α0 0001
α1 0010
α2 0100
α3 1000
α4 0011
α5 0110
α6 1100
α7 1011
α8 0101
α9 1010
α10 0111
α11 1110
α12 1111
α13 1101
α14 1001

Table 3.2 Multiplication Table for GF(16)

0 α0 α1 α2 α3 α4 α5 α6 α7 α8 α9 α10 α11 α12 α13 α14
α0 α0 α1 α2 α3 α4 α5 α6 α7 α8 α9 α10 α11 α12 α13 α14
α1 α2 α3 α4 α5 α6 α7 α8 α9 α10 α11 α12 α13 α14 α0
α2 α4 α5 α6 α7 α8 α9 α10 α11 α12 α13 α14 α0 α1
α3 α6 α7 α8 α9 α10 α11 α12 α13 α14 α0 α1 α2
α4 α8 α9 α10 α11 α12 α13 α14 α0 α1 α2 α3
α5 α10 α11 α12 α13 α14 α0 α1 α2 α3 α4
α6 α12 α13 α14 α0 α1 α2 α3 α4 α5
α7 α14 α0 α1 α2 α3 α4 α5 α6
α8 α1 α2 α3 α4 α5 α6 α7
α9 α3 α4 α5 α6 α7 α8
α10 α5 α6 α7 α8 α9
α11 α7 α8 α9 α10
α12 α9 α10 α11
α13 α11 α12
α14 α13

23
 In an RS (n, k) code, the first k symbols are the original message information M(x), and
the rest are the n - k parity-checks CK(x). The parity-checks are calculated by
CK(x) = xn-kM(x) mod g(x), where g(x) is a generator polynomial. A simple block diagram of
an RS encoder is shown in Figure 3.2. The generator polynomials used in PHY-I are
summarized in Table 3.3.

Figure 3.2 Block Diagram of RS Encoder

Table 3.3 Generator Polynomials for RS Codes

(n, k) g(x)
(15,11) x +α x +α6x2+α3x+α10
4 13 3

(15,7) x8+α14x7+α2x6+α4x5+α2x4+α13x3+α5x2+α11x1+α6
(15,4) x11+α9x10+α8x9+α4x8+α9x7+α13x6+α4x5+α12x4+α4x3+α5x2+α3x+α6
(15,2) x13+α3x12+α8x11+α9x10+α2x9+α4x8+α14x7+α6x6+α10x5+α7x4+α13x3+α11x2+α5x+α

Since the message information symbols are inputted sequentially, the hardware
implementations of the RS encoders are based on shift register circuits (SRCs) [15]. Take the
RS (15,11) encoder as an example, where g(x) = x4+α13x3+α6x2+α3x+α10; the block diagram of
the RS shift register encoder circuit is shown in Figure 3.3. The encoder operates according to
the steps as follows:
1. All the registers are reset.
2. SW A1 & A2 are enabled and SW B is disabled.
3. The message information symbols are clocked into the circuit sequentially for the first
11 clock cycles.
4. SW A1 & A2 are disabled and SW B is enabled.
5. The circuit is clocked for four more clock cycles to output the four parity-checks.
6. The encoding cycle is accomplished.
According to this procedure, the message information symbols are outputted in the first
11 clock cycles. At the same time, the SRC is performing the module g(x) function in parallel.
In the next four clock cycles, the parity-checks are calculated and outputted sequentially.

24
 Figure 3.3 Block Diagram of the RS(15,11) Shift Register Encoder Circuit

The other three RS encoders are also implemented in the same way by changing the size
of the SRC and the multipliers according to the different generator polynomials g(x).

3.1.2 Interleaver

In the PHY-I specification, both RS code and convolutional code are used. This is a
conventional concatenated code design, and an interleaver is usually inserted in between to
improve the noise performance. Before talking about the working principle of the interleaver,
two types of errors due to noise are discussed first.
A very common type of error is a random independent error. Figure 3.4(a) gives an
example of such an error. While a set of information is being transmitted, errors randomly
appear somewhere due to the noise effect. As mentioned earlier, by using FEC code, some of
the errors can be corrected. In this example, the RS(15, 11) is used, and therefore two errors
can be corrected in each set of code at most. Thus, the message information can be received
correctly.
The other type of error that is very important is a burst error. This is also a random error,
but unlike the independent error mentioned in the last paragraph, a burst error will randomly
appear and affect a set of consecutive data. Figure 3.4(b) shows an example of a burst error,
which affects, in total, five symbols in sequence. With the RS (15, 11), a set of code with
three symbols in the error cannot be fully corrected.
25
 (a) Independent Error

(b) Burst Error

Figure 3.4 Two Types of Errors Due to Noise

The interleaver is used to ameliorate the problem caused by a burst error. By shuffling the
sequence of data, the consecutive burst errors are averaged out and distributed uniformly in
the whole data package. In this way, with the same amount of errors in the data package, the
data has a higher probability of being corrected by an FEC code, such as RS code. The
working principle of the interleaver is described in Figure 3.5. The encoded data are loaded
vertically into the interleaver on the transmitter (TX) side. As the RS(15, 11) code is used,
there are 15 symbols in each set of data. There are, in total, four sets of data loaded into the
interleaver. While transmitting, the data are read out horizontally from the interleaver. We
assume that during transmission, there are some random burst errors and six consecutive
symbols are affected. On the receiver (RX) side, data are loaded into the de-interleaver
horizontally and read out from the de-interleaver vertically. In this way, the sequence of data
is shuffled before transmission and reorganized into the original order after being received.
The consecutive burst errors are then uniformly distributed across the four sets of data. This
makes it possible for the RS(15, 11) decoder to successfully correct all the errors.

26
 Figure 3.5 Working Principle of Interleaver

In the PHY-I TX system-on-chip (SoC), since the PSDU is transmitted immediately

following the PHR, the PSDU needs to be completely loaded into the interleaver before the
PHR is sent out. This indicates that both the PHR and the PSDU will occupy the interleaver at
the same time. Thus, to avoid conflict in terms of loading and reading the interleaver, the
interleavers for both the PHR and the PSDU are implemented. The height of the two
interleavers are both 60 bits, which is equal to the code word length of the RS encoder, 4-bit *
15. This means that 60-bit data will be loaded into the interleaver every time. The width of the
interleaver for the PHR is fixed since the length of the PHR is already defined in the standard.
However, the width of the interleaver for the PSDU is changeable. The maximum width of the
PSDU interleaver is set to be 20-column, and it supports any width that is within this range.
The interleavers are constructed based on the SRC. However, instead of a conventional one
directional shift, the SRC matrix for the interleavers can shift both horizontally and vertically.

27
 3.1.3 Convolutional Encoder

In the convolutional code, each bit in the output stream depends not only on the current
input bit, but also on the input bits processed previously. This is treated as a form of memory
and distinguishes the convolutional code from the aforementioned RS code, which is a type of
block code where there is no memory. The convolutional code is less sensitive to signal-to-
noise ratio (SNR) variations and is often used in situations where the SNR is poor. In the
IEEE Std. 802.15.7, the convolutional code is only used in the on-off keying (OOK) mode of
PHY-I, where the communication channel is very poor in outdoor conditions.
Figure 3.6 shows an example of the convolutional encoder, which is the one that is used in
the standard. The code rate is 1/3, which indicates that three encoded symbols are generated
with one input datum. The constraint length K is seven, which indicates that the encoded
symbol contains information from both the current input datum and the previous six input
data which are stored in the convolutional encoder. The six stored data are also known as the
state of the convolutional encoder, and a convolutional encoding usually starts and ends with
an all ‘0’ state. The encoded symbols are calculated by performing a modulo-2 addition
defined by the three generator polynomials g0 = 1338 = 10110112, g1 = 1718 and g2 = 1658.
For example, the generator polynomial g0 specifies that encoded symbol A0 = d6+d4+d3+d1+d0.

Figure 3.6 Block Diagram of the Convolutional Encoder

28
 The convolutional code can also be punctured to achieve varieties of code rate. Apart from
the rate-1/3 convolutional code, both the rate-1/4 and the rate-2/3 codes that are specified in
the standard are generated by puncturing. Figure 3.7(a) shows the procedure of how a rate-1/4
code is obtained. A rate-1/2 code is obtained firstly by puncturing the symbol C. Then, the
rate-1/4 code is obtained by repeating all the symbols to form an ‘AABB’ pattern. Figure 3.7(b)
describes the puncturing pattern for the rate-2/3 code. The symbol C for the first input and the
symbols A & C for the second input are punctured. In this way, the input X0X1 is encoded to
A0B0B1.

(a) Rate-1/4 (b) Rate-2/3

Figure 3.7 Puncturing Pattern for Convolutional Encoder

The hardware implementation of the rate-1/3 mother convolutional encoder is also based
on the SRC. A 6-bit shift register is used to store the state of the convolutional encoder. Every
time the new input bit is valid, the shift register will shift the new input in and shift the last bit
out. The modulo-2 addition, as mentioned before, is implemented by the XOR function to
calculate the encoded output symbols. The puncturing is easily implemented by either
duplicating the output wires or disconnecting some of the output signal.

3.1.4 Run-Length Limited Encoder

The Manchester and the 4B6B code are used as the run-length limited (RLL) codes in
PHY-I. Table 3.4 & Table 3.5 show the mapping of the input data to the output symbols for
the two RLL codes.
Table 3.4 Manchester Code Mapping

Input Datum Manchester Symbol

0 01
1 10

29
 Table 3.5 4B6B Code Mapping

4B Input Data 6B Output Symbol

0000 001110
0001 001101
0010 010011
0011 010110
0100 010101
0101 100011
0110 100110
0111 100101
1000 011001
1001 011010
1010 011100
1011 110001
1100 110010
1101 101001
1110 101010
1111 101100

Apart from mitigating the flicker problem, the two RLL codes provide a reasonable clock
recovery capability by limiting the number of consecutive ‘0’s and ‘1’s. The duty ratios of the
two RLL codes are both 50% during one output symbol. This provides a good DC balance.
Moreover, as the 4B6B code introduces some redundancies, it also provides some error
detection capability. If a 6-bit symbol received is not in the mapping table, the decoder can
generate an erasure signal to indicate a potential error and decode the symbol to a 4-bit data
symbol according to the minimum hamming distance methodology. This will help the
following RS decoder in terms of error correction.
The Manchester encoder is implemented by adding an inverted bit to the LSB of the input
data. For example, an input datum d is encoded to dd̄ according to the specification. On the
other hand, the 4B6B encoder is implemented by a look-up table.

30
 3.1.5 Digital Modulator

The OOK modulator performs a direct conversion, from ‘0’ to ‘0’, and from ‘1’ to ‘1’.
Thus, the symbols encoded by the Manchester code can be directly sent out without any
modification in the hardware implementation.
The variable pulse-position modulation (VPPM) is shown in Figure 2.2. The modulated
symbol from the logical data ‘0’ has a transition from ‘high’ to ‘low’, and vice versa for the
logical data ‘1’. As mentioned in Table 2.2, the dimming is varied in steps of 10%. To
generate the dimmed VPPM symbols, a 10 times faster clock is mandatory. Thus, a 4MHz
external clock is chosen, and both the 400kHz optical clock for the VPPM mode and the
dimmed VPPM symbols are generated by the 4MHz clock. The modulation is realized by a
multiplexer logic. The logical data select which dimmed symbol is transmitted, and the
optical clock that triggers the logical data is well aligned to the dimmed symbols so that there
is no phase mismatch during modulation.

3.1.6 Top MCS Controller

The top MCS controller controls and coordinates all the other modules in the data path to
fulfill the function of PHY-I. The control of the data path is divided into two parts, ‘LOAD’
and ‘SEND’. In the ‘LOAD’ part, both the PHR and the PSDU are encoded by the RS
encoder and loaded into the interleaver. In the ‘SEND’ part, the synchronization header
(SHR), the PHR and the PSDU are sent out sequentially according to the PHY package
specification. The SHR is sent out directly, while the PHR and the PSDU are read out from
the interleaver and encoded and modulated as specified by the MCS before being sent out.
During ‘SEND’, special attention is paid to the convolutional encoding. As mentioned
above, the convolutional encoding usually starts and ends with an all zero state. By resetting
the convolutional encoder beforehand, an all ‘0’ initial state is guaranteed. However, the
encoding cannot be ended with a reset command. To provide an all ‘0’ state ending, six extra
zeros are intentionally added to the end of the data that are read from the interleaver. This
method is called zero-tail termination. Additional logics are designed to take care of the
timing issue with the extra six zeros.

31
 The top MCS controller receives the PHR and the PSDU data and commands from off-
chip. The communication between the controller and off-chip involves five signal pins,
CLK_4M, I_EN, I_DATA, O_FPGA_LOAD_DN, and O_FPGA_SEND_DN. The CLK_4M
signal provides the controller with a 4MHz clock. The I_EN signal indicates the status of
communication. When I_EN goes high, the communication starts, and the commands and
data that come from off-chip are loaded into the command and data buffer in the controller
through the I_DATA pin. The command and data buffer performs a serial to parallel
conversion and is also used as temporary storage. The commands are executed by the
controller to set the dimming level, to select the specific MCS, or to encode and modulate the
PHR and the PSDU. The PHR and the PSDU data are sent to the encoding and modulating
data path. When the buffer is filled up with the PHR or the PSDU data, the communication is
suspended. The data are then sent to the RS encoder. A pulse signal through the
O_FPGA_LOAD_DN is generated by the controller after the data being processed. The pulse
signal indicates that the buffer is clear and the communication is continued. Meanwhile, pulse
signals are also generated through the O_FPGA_SEND_DN pin, indicating that the SHR, the
PHR, or the PSDU is sent successfully.
There are two clock dividers in the top MCS controller. The clock dividers are used to
generate the 200kHz and the 400kHz optical clocks, and the controller provides one of the
optical clocks for the other functional modules according to the MCS.

3.1.7 Data Buffer

Data buffers are inserted into all the functional modules. They are controlled by the top
MCS controller and play a very important role in providing a smooth flow in the data path for
two main reasons. One reason is that the throughputs of some of the functional modules are
different. Taking the RS(15,11) encoder as an example, each encoding period contains 15
clock cycles. There is an encoded symbol outputted for each of the 15 clock cycles, but there
are only 11 symbols inputted into the encoder for the first 11 clock cycles. Thus, the first
input symbol for the next encoding period has to be stored in the data buffer for four clock
cycles before being inputted into the encoder. The other reason why the data buffers are
essential is the port width mismatch between the adjacent modules. For example, the output
port width of the RS encoder is four bits, but the input port width of the interleaver is 60 bits.
In this situation, a 60-bit data buffer, whose function is similar to a serial to parallel converter,
is inserted before the interleaver to store the output symbols generated by the RS encoder.

32
 3.1.8 Multiplexer

Two multiplexers are implemented at the output of the data path. With the multiplexers,
the digital baseband can be by-passed and off-chip VLC modulation signals can be used to
drive the dimmer to modulate the LEDs. This provides an additional option to test the
performance of the power management unit (PMU) and the dimmer under different VLC
modulation conditions.

3.1.9 Synthesis

The whole digital baseband design is synthesized using Synopsys Design Vision. To
guarantee the performance of the system, the worst case library for AMS 0.35μm CMOS
digital devices is used in the synthesis. The register-transfer level (RTL) design, which is used
for place & route to implement the SoC, is generated from the behavioral design during
synthesis. The synthesized area report is summarized in Table 3.6.
Table 3.6 Synthesized Area Report

Number of Ports 18
Number of Nets 6061
Number of Cells 5369
Number of References 117
Combinational Area 527290.407
Noncombinational Area 1074964.835
Net Interconnect Area 419313.274
Total Cell Area 1602255.242
Total Area 2021568.516

Simulation is carried out after the synthesis to verify the function of the RTL design. One
of the two reasons is that the RTL design is compiled and optimized by the synthesizing
algorithm. The original behavioral design and the synthesizing algorithm may not be robust
enough, and the generated RTL design may not have the exact same function as the
behavioral design. The other reason for the simulation verification of the RTL design is about
the hardware delay. There is no hardware delay considered in the original behavioral design.
However, the RTL design is of the transistor level, and the library used specifies the delay of
all the digital devices. The hardware delay may cause a severe timing issue in the real
hardware implementation. The simulation result of the synthesized RTL design with hardware
delay is shown in Figure 3.8.

33
 Figure 3.8 Pre-Layout Simulation Result of the Synthesized Digital Baseband Design

3.1.10 Place & Route

The place & route process is used to generate the hardware layout of the digital baseband.
The automatic place & route is done by the Cadence Encounter. Only three layers of metal are
used for routing the design, though there are four layers of metal provided in the AMS
0.35μm HV CMOS process. This is because the automatic routing in the top metal layer does
not satisfy the design rule of the process. The size of the design layout is 1560μm x 1560μm.
The design layout is shown in Figure 3.9, and the timing analysis reports are shown in Table
3.7 & Table 3.8. There is no negative value in the table, which indicates that there is no setup
time and hold time error.

Figure 3.9 Layout of the Digital Baseband Design

34
 Table 3.7 Timing Analysis Report for Setup Time

Setup Mode all reg2reg in2reg reg2out in2out clkgate

WNS (ns) 120.374 120.374 121.204 232.639 242.135 N/A
TNS (ns) 0 0 0 0 0 N/A
Violating Paths 0 0 0 0 0 N/A
All Paths 7067 3527 3548 8 1 N/A

Table 3.8 Timing Analysis Report for Hold Time

Hold Mode all reg2reg in2reg reg2out in2out clkgate

WNS (ns) 0.003 0.166 0.003 2.115 1.17 N/A
TNS (ns) 0 0 0 0 0 N/A
Violating Paths 0 0 0 0 0 N/A
All Paths 7067 3527 3548 8 1 N/A

3.2 DC-DC Boost Converter

3.2.1 Power Stage Working Principle

A basic boost converter topology is shown in Figure 3.10. It contains a power MOSFET,
an inductor, a Schottky diode, a capacitor and a load resister.

Figure 3.10 Basic DC-DC Boost Converter Topology

Figure 3.11 shows simplified waveforms of the inductor current, the power MOSFET
current, the diode current, the output voltage and the pulse width modulation (PWM) control
signal when the converter works in the steady state in continuous conduction mode (CCM). In
this mode, the inductor current is always above zero, and it is easier to analyze the
relationship among the output voltage, the input voltage and the PWM duty ratio. There is
ripple on the output voltage, but it is relatively small compared to the absolute value of the
output voltage.

35
 Figure 3.11 Timing Diagram of Boost Converter in CCM

At stage 1, the power MOSFET is turned on. LX node is short to ground, and the Schottky
diode is reversely biased. The inductor current increases, and the current that goes through the
load resister is supplied by the capacitor. The slope of the inductor current at this stage is

(3.1)

Thus, the increase of the inductor current is

(3.2)

At stage 2, the power MOSFET is turned off and the Schottky diode is turned on. The
inductor supplies current for the capacitor and the load resistor, and the inductor current
decreases. The slope of the inductor current at this stage can be expressed by

(3.3)

Assuming that the output voltage does not change, the decrease of the inductor current is

( ) (3.4)

Since the boost converter works in the steady state, the inductor current will return to the
initial value in one clock cycle. By using volt-second balance, it can be obtained that

( ) (3.5)

Thus, the conversion ratio M can be expressed as

36
 (3.6)

The output voltage ripple that is due to the charging and discharging of the capacitor is

(3.7)

where fSW is the switching frequency of the boost converter.

When the boost converter is working in the discontinuous conduction mode (DCM), the
inductor current will return to zero, as shown in Figure 3.12. In this case, the conversion ratio
is

(3.8)

Figure 3.12 Current Comparison of Boost Converter in CCM & DCM

3.2.2 Current Mode Control

In order to control and stabilize the output voltage of a boost converter to a specific value,
a control unit is needed. Normally, a feedback circuit is used to implement the control unit.
Depending on the feedback parameters, the control unit can be classified into two control
schemes, a voltage-mode control and a current-mode control.
Figure 3.13 shows a simplified schematic of a current-mode control boost converter. The
current-mode control utilizes both the output voltage and the inductor current for the feedback
control. Compared to the voltage-mode control, which uses only the output voltage as
feedback signal, the additional feedback inductor current signal provides one more degree of
freedom for current-mode control. With this one more degree of freedom for control, an
original second order boost converter system can be treated as a first order system. Thus,
under current-mode control, the bandwidth of the feedback control loop is higher so that the
system possesses a faster transient response, and the design of the compensator is simplified.

37
 Figure 3.13 System Diagram of a Current-Mode Control Boost Converter

3.2.3 DC-DC Boost Converter System Design

According to the PMU specification, a current-mode DC-DC boost converter is designed

and the system block diagram is shown in Figure 3.14. The converter integrates the controller
and the power MOSFET on-chip with an inductor, a Schottky diode and a capacitor off-chip.

Figure 3.14 System Diagram of the DC-DC Boost Converter

38
 The on-chip controller consists of both the output voltage feedback control loop and the
inductor current feedback control loop. Moreover, a pulse skip modulation module is
designed to maintain a high efficiency at light load. To prevent the converter from damage,
protection circuits such as over-voltage protection (OVP), over-current protection (OCP), and
short-circuit protection (SCP) are designed.
The inductor current feedback control is done by sensing the current through the power
MOSFET. To avoid the sub-harmonic oscillation when the duty ratio D is larger than 0.5, a
slope compensator is designed. The compensator takes in the difference between the output
and the input voltage and generates a ramp signal for compensation.

3.2.4 Power MOSFET Design

The power MOSFET performs as a switch to charge the inductor for boosting the output
voltage up. The NMOS20M transistor, which can sustain a VDS of 25V or higher, is chosen to
avoid channel breakdown at high output voltage. The resistance of the MOSFET should be as
small as possible to minimize the conduction loss. The energy consumed on the MOSFET
degrades the efficiency of the converter and also generates heat, which may damage the chip.
The transistor size of the power MOSFET is 100,000μm / 0.5μm, and the estimated Ron is
0.1Ω.
The Christmas-tree technique is used in the power MOSFET layout for a balanced current
distribution. The unit cell of the NMOS20M transistor used is shown in Figure 3.15. There are
two 40μm / 0.5μm transistors in one unit cell. The two transistors share the same drain, and
the gates of the two transistors form an ‘O’ shape. A simplified diagram of the Christmas-tree
layout structure is shown in Figure 3.16. The Christmas-tree layout consists of 25 unit
structures. Each unit structure contains 100 unit transistor cells. The width of a unit structure
is 40μm, and the length is 1500μm. The current mainly goes from top to bottom through
Metal-4, which is the thickest layer of metal. As the current is going downward, there is less
current remaining in the upper Metal-4 that is connected to the drain of the MOSFET. Thus,
the upper Metal-4 that is labeled “Drain” is designed to be a triangular shape pointing
downward. On the lower side, the Metal-4 that is connected to the source of the MOSFET is
designed to be a triangle pointing upward to support more current coming from the source of
the MOSFET. The whole layout of the power MOSFET consumes an area of
1000μm*1500μm.

39
 Figure 3.15 NMOS20M cell

Figure 3.16 Christmas-Tree Layout Structure

40
3.3 Dimmer

The dimmer performs as a digital switch to turn the LEDs on and off. By using PWM with
different duty ratios, the turn-on time of the LEDs is varied and the brightness of the LEDs is
controlled to support different dimming levels. Meanwhile, the dimmer can function as the
modulator to modulate the LEDs for VLC. There are two types of dimmer designed. One type
of dimmer is simple and conservative. An NMOS transistor pair is designed to fully turn on
and off two branches of LEDs for dimming purposes. The other type of dimmer possesses a
current balancing capability apart from the dimming function for the remaining two branches
of LEDs.

3.3.1 Transistor Pair Dimmer

The unit transistor cell used for the NMOS transistor pair is NMOS20M, which is the
same as the one used in the power MOSFET. The size of each transistor is designed to be
4000μm / 0.5μm. The whole transistor pair forms a 5*20 matrix, as shown in Figure 3.17.
Due to the floor plan consideration, the current going through the dimmer has to turn an
undesirable 180°. Thus, a modified Christmas-tree structure combined with the interleaved
finger is used for the Metal-4 layout to avoid unbalanced current distribution, as shown in
Figure 3.17.

Figure 3.17 Metal-4 Layout of Transistor Pair Dimmer

41
 3.3.2 Current Balancing Dimmer

The schematic for the dimmer with the current balancing circuit is shown in Figure 3.18.
The design takes [16] as a reference. The amplifiers clamp the VDS of both M5 and M7 to be
the same as M3. In this way, with the same VGS, the currents going through M5 and M7 are
forced to be the same. The amplifiers are enabled to control M6 and M8 to compensate for the
unbalanced current between CH1 and CH2 when VDIM is high. M6 and M8 are high-voltage
transistors to tolerate the high voltage during switching. The parasitic capacitance of the HV-
CMOS is much larger than that of the other standard transistors. To reduce the effect of the
large parasitic capacitance and improve the response of the dimmer, the amplifier is disabled
when VDIM is low. The gates of M6 and M8 are floating and do not need to be discharged. The
bandwidth of the amplifiers is also designed to be as high as 10MHz so that the current
balancing circuit can achieve a rising and falling time of <100ns to restore the VLC
modulation signal. However, the rising time of the dimmer may differ a lot from the falling
time. When VDIM turns high, both M5 and M6 are switched on to light up the LEDs. The large
parasitic capacitance of M6 results in a relatively longer rising time. When VDIM turns low, as
long as one of M5 and M6 is switched off, the LEDs are turned off. The use of a pull-down
transistor M4 accelerates the switching off of M5 and results in a much shorter falling time.

Figure 3.18 Schematic of Current Balancing Dimmer

3.4 System Integration

The aforementioned digital baseband, the DC-DC boost converter, and the dimmer are
combined together to form the SoC. Before building the SoC, simulations have been carried
out to verify the function of each module. To guarantee the function of the whole SoC, the
system integration needs to be conducted cautiously.

42
 3.4.1 Interface between Digital Baseband & Dimmer

The digital baseband is designed to function under a 3.3V power supply. However, the
DC-DC boost converter and the dimmer are designed to be able to function with a wide power
supply range from 2.5V to 5V. When combined together, the digital baseband must be
guaranteed to possess enough driving capability to drive the dimmer even under 5V power
supply. Thus, dimmer buffers are implemented at the interface of the 3.3V digital baseband
and the 5V dimmer, as shown in Figure 3.19. The final stage of a digital output is a BUFX12
buffer. The dimmer buffer is placed between the output of the BUFX12 and the input of the
dimmer. To verify the function of the interface, simulation is carried out with a 3pF capacitor
representing the parasitic due to the routing, and the simulation result is shown in Figure 3.19.
The simulation result proves that the 3.3V digital output signal can successfully drive the
interface buffer to control the dimmer even under 5V power supply.

(a) Schematic

(b) Simulation Result

Figure 3.19 Schematic & Simulation Result of Dimming Buffer Verification

43
 Moreover, the switching noise of the digital baseband may be coupled to the control
circuitry of the boost converter through the silicon substrate. This may affect the precise
sensing and controlling of the converter. Thus, a guard ring is implemented by using
P-implantation to shield the digital portion.

3.4.2 Interface between Digital Baseband & Off-Chip

To communicate with the digital baseband, the clock and the control signals are all sent
from off-chip, and the feedback signals that indicate the operation state of the baseband are all
transmitted to off-chip. Thus, the interface between the digital baseband and off-chip needs to
be well managed. The first thing is to verify that the input signals to the baseband are not
affected by the electrostatic discharge (ESD) protection circuit, because distortion in signal
quality may induce a signal misalignment issue and thus cause timing problems. Figure 3.20
shows a schematic for digital input signal verification. The off-chip 0.5Ω resistor and 2nH
inductor represent the bonding wire parasitic, and the on-chip 8pF capacitor represents the
parasitic of the input metal pad. The values chosen for the simulation are conservative to
leave enough margins for the implementation. The ESD protection circuitry is added after the
pad capacitor and before the input buffer for the digital baseband. The simulation result is
shown in Figure 3.20. A 4MHz clock signal with a 25ns rising time is provided at node 1. At
the output of the input buffer, a sharp clock signal with a rising time <2ns is generated. This
verifies that the ESD protection circuit does not degrade the input signal quality.

44
 (a) Schematic

(b) Simulation Result

Figure 3.20 Schematic & Simulation Result of Digital Input Signal Verification

The digital output driving capability also needs to be verified so that the digital feedback
signals can be recognized off-chip. Figure 3.21 shows a schematic for the digital output signal
verification. The output signal generated from the baseband goes through the manually added
output buffers before being transmitted out. The parasitic parameters are chosen to be the
same as in the digital input verification. An extra 2pF capacitive loading is added off-chip.
From the simulation result shown in Figure 3.21, it is proved that the manually added output
buffers provide enough driving capability to achieve a rail-to-rail output signal with a rising
time <10ns.

45
 (a) Schematic

(b) Simulation Result

Figure 3.21 Schematic & Simulation Result of Digital Output Signal Verification

3.4.3 Mixed Signal Verification

One last task for the system integration is to perform a mixed signal simulation to verify
the cooperation among the digital baseband, the DC-DC boost converter, and the dimmer. In
the mixed signal simulation, the digital baseband is simulated with the Verilog-HDL test
bench, and the DC-DC boost converter and the dimmer are simulated with a power supply of
4V. As shown in Figure 3.22, the 3.3V digital output signal drives the 4V dimming buffer
output signal. With an 8V output voltage from the boost converter, the current that goes
through each branch of two LEDs is 100mA, and the current is modulated by the digital
output signal.

46
 Figure 3.22 Simulation Result of Mixed Signal Verification

3.4.4 SoC Floor Plan

The final TX SoC layout view is shown in Figure 3.23. Since the huge current that goes
through the power MOSFET should not be interrupted by other modules, the height of the
SoC is determined by the length of the power MOSFET. As the power MOSFET is only
connected to the controller of the PMU, the power MOSFET is placed on the right-hand side
of the SoC to facilitate the routing for other modules and mitigate the effects due to the huge
current switching noise. The digital baseband is placed on the left-hand side of the SoC so
that the routing for the digital baseband does not conflict with the other routing on-chip, and
this also simplifies the printed circuit board (PCB) design for testing. The boost convertor
controller is placed on the top center of the SoC and the dimmer is placed on the bottom
center.

Figure 3.23 Layout of TX SoC

47
CHAPTER 4 RECEIVER DESIGN

To quantitatively evaluate the transmitter (TX) system-on-chip (SoC), a corresponding

receiver (RX) is designed with an analog front-end and a digital baseband, as shown in Figure
4.1. The analog front-end is in charge of converting the visible light signal into an electrical
signal. The electric signal is then demodulated and decoded by the baseband in the RX.

Figure 4.1 System Block Diagram of RX

4.1 RX Analog Front-End Design

In order to perform the optical to electrical signal conversion, the analog front-end consists
of a photodiode, which converts the optical power into photocurrent, and a transimpedance
amplifier, which converts the photocurrent into a voltage signal.
The photodiode (PD) is chosen to be a commercially available BPV-10. The responsivity
of the PD is shown in Figure 4.2. At a wavelength of 450nm, the PD responsivity is
approximately 0.15A/W. The active area of the PD is 0.78mm2. However, the effective area is
as large as 7mm2, owing to the hemisphere shape of the PD package, as shown in Figure 4.2.

(a) Responsivity (b) Package

Figure 4.2 Responsivity & Package of the PD

48
 The transimpedance amplifier (TIA) is implemented using the commercial OPA-380 op-
amp with a feedback resistor. The OPA-380 op-amp possesses a gain bandwidth product
(GBW) of as high as 90MHz and a wide supply range from 2.7V to 5.5V. The feedback
resistor is selected to be 100kΩ to trade-off between the transimpedance gain and the
bandwidth, given the limited GBW. The schematic of the TIA with the PD equivalent circuit
is shown in Figure 4.3, and the transient simulation result presented in Figure 4.3 proves that
the TIA is able to successfully restore the dimmed variable pulse-position modulation (VPPM)
square wave photocurrent input signal, even at 10% duty ratio.

(a) Schematic of TIA

(b) Transient Simulation Result

Figure 4.3 Schematic & Transient Simulation Result of TIA

Moreover, a high pass filter is designed at the output of the TIA to reject the low
frequency noise and interference. The -3dB cut-off frequency of the high pass filter is 4.8kHz.
The schematic of the whole RX analog front-end is presented in Figure 2.8.

49
4.2 Digital Baseband Design

The RX digital baseband performs demodulation and decoding for IEEE Std. 802.15.7
type-I physical layer (PHY-I), which is matched to the TX SoC baseband. The baseband is
implemented on the Xilinx Virtex-5 xc5vlx110t field programmable gate array (FPGA) and
consists of a demodulator, a run-length limited (RLL) decoder, a Viterbi decoder, a de-
interleaver, a Reed-Solomon (RS) decoder and a top modulation and coding scheme (MCS)
controller, as shown in Figure 4.1.
The demodulator receives an electrical VLC signal and performs the corresponding on-off
keying (OOK) or VPPM demodulation. One main function of the demodulator is the clock
and data recovery (CDR). By executing a phase picking algorithm, the RX local clock is
aligned to the optical clock of the received VLC signal [17]. With the aligned clock, the
demodulator samples the received signal and performs the demodulation.
The RLL decoder performs an inverse mapping of the RLL code by using a look-up-table.
Since there are always redundant bits in the encoded RLL code, the inverse mapping may not
be able to find an exact result for an erroneous received code. In this situation, the decoder
finds the closest matched code in the look-up-table based on the minimum hamming distance
theory and generates an error flag. Thus, the RLL decoder also provides an error detection
capability.
The Viterbi decoder is a commonly used decoder for the convolutional code. The Viterbi
decoder is implemented using the Xilinx LogiCORE IP, Viterbi Decoder v7.0. The design
parameters are summarized in Table 4.1. Considering that the Viterbi decoder traces back a
long sequence data stream, it becomes the most time consuming process in the RX data path.
Therefore, a parallel architecture is employed to reduce the latency of the decoder. As
mentioned in Section 0, the physical-layer header (PHR) contains information needed to
decode the PHY service data unit (PSDU). Thus, before the PHR is successfully decoded, the
PSDU is temporarily stored in the first-in-first-out (FIFO).
Table 4.1 Design Parameters for Viterbi Decoder

Characteristic Parameter
Architecture Type Parallel
Constraint Length 7
Trace back Length 126
Puncturing Enabled
Output Rate 3

50
 The function of the de-interleaver has already been explained in Section 3.1.2.
The RS decoder is designed based on the decomposed inversion-less Berlekamp Massey
algorithm [18]. One master decoder is implemented, and the 4 different RS codes can all be
decoded through the master decoder by manipulating a few control signals.
The RX MCS controller controls and coordinates all the other modules in the RX data
path to process the data for PHY-I. The PHR is demodulated and decoded directly. However,
to process the PSDU, the controller first analyzes the PHR to acquire the MCS and the
package length information.

51
CHAPTER 5 EXPERIMENTAL RESULTS:

5.1 Chip Micrograph

The transmitter (TX) system-on-chip (SoC) is fabricated through the AMS 0.35μm HV
CMOS process, and the chip area is 2*4mm2. The chip micrograph is shown in Figure 5.1.

Figure 5.1 Chip Micrograph of the TX SoC

5.2 PCB Design

Two printed circuit boards (PCBs) are designed for the TX SoC measurement. One PCB is
designed for chip on board (COB) measurement, and the other PCB is designed for the LED
loading to demonstrate the SoC application. The PCB schematics are shown in Figure 5.3.
The fabricated PCBs are shown in Figure 5.4. COB-PCB consists of four layers. The top
and the bottom layers are for signal routing, and the inner two layers are for the VDD and the
GND to provide better electromagnetic noise shielding and power supply. LED-PCB is a two-
layer board because the routing for the LEDs is quite simple. Connector H1 & H2 are used for
COB-PCB & LED-PCB connection. Connector H3 on COB-PCB is used for data
communication between the SoC and the field programmable gate array (FPGA) board. The
power for the digital baseband of the SoC is also supplied from connector H3.

52
Figure 5.2 Schematics of COB-PCB Design

53
Figure 5.3 Schematics of LED-PCB Design

(a) COB-PCB

(b) LED-PCB
Figure 5.4 Fabricated PCBs for the TX SoC

54
 While designing the PCB, the layout for the power stage current flow is taken good care of
[19]. As shown in Figure 5.5, during DC-DC boost converter operation stage 1, the current
flow is marked by the red line. While the converter is operating in stage 2, the current flow is
represented by the blue line. The shadow region indicates the current changing loop area due
to the switching of the boost converter. The change in the current loop induces change in the
magnetic flux and may cause severe problems, such as ground bouncing. This will affect the
operation stability of the boost converter system. Thus, to minimize the current changing loop
area, the layout of the power stage current flow is designed as shown in Figure 5.6. The
output capacitor is placed to be as close to the SoC as possible.

Figure 5.5 Current Flow of DC-DC Boost Converter

Figure 5.6 Layout of the Power Stage

55
5.3 Measurements

5.3.1 DC-DC Boost Converter Steady-State Measurement

The converter steady-state measurement setup is shown in Figure 5.7. The SoC together
with all the peripheral components on the PCB forms the COB test unit. The ADCMT 6244 is
used as the power supply for the SoC, and the PLZ164WL is connected to the output of the
DC-DC boost converter to measure the performance of the converter under different loading
conditions. LED-PCB is connected to COB-PCB to evaluate the performance of the SoC
under actual application. The MSO7034B is used to monitor the operating status of the
converter.

Figure 5.7 Converter Steady-State Measurement Setup

Figure 5.8 shows the steady-state measurement result of the converter with the LED PCB
as load. VLX is the voltage signal at the node where the inductor and the power MOSFET are
connected. This node indicates the operating stage of the converter. The converter operates at
a switching frequency of 1.65MHz with an output voltage of 18.1V, and one branch of LEDs
is connected to the converter with a DC current of 80mA. The maximum output voltage ripple
is measured to be 269mV.

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 Figure 5.8 Converter Steady-State Measurement Result

5.3.2 DC-DC Boost Converter Efficiency Measurement

An automatic measurement platform is used to measure the efficiency of the converter.

The measurement setup is shown in Figure 5.9. The ADCMT 6244 performs as the power
supply, and the ADCMT 6243 performs as the electronic load to the SoC. The ADCMT
7461A is used to measure the output voltage of the converter. All the equipment is connected
to a computer through the general purpose interface bus (GPIB) to form the automatic
measurement platform. The operating configurations of the ADCMT 6243 & 6244 are sent
through the GPIB and the measured voltage and current values are read from the GPIB.

Figure 5.9 Converter Efficiency Measurement Setup

57
 The measured and calculated efficiency of the converter is summarized in Figure 5.10.
The efficiency is measured under a fixed input voltage of 3.7V and various output voltages
from 6V to 18V. As shown in the measurement result, the converter can achieve a highest
efficiency of 91.88% at Vout = 10V. At light load, the PSM scheme helps in maintaining an
efficiency >83% by reducing the amount of on/off switching. At heavy load, the converter
provides an output power >8W at Vout = 10V & 14V while retaining an efficiency >80%.

Figure 5.10 Converter Efficiency Measurement Result

5.3.3 Current Balancing Dimmer Measurement

The measurement setup for the dimmer with current balancing is demonstrated in Figure
5.11. The ADCMT 6244 is used to power up the SoC. Two branches of LEDs are loaded
between the converter and the current balancing dimmer. One branch consists of five LEDs,
while the other branch consists of four LEDs so as to create an unbalanced load. The
MSO7034B, combined with the current probes, is used for LED current measurement to
evaluate the current balancing capability.

58
 Figure 5.11 Current Balancing Dimmer Measurement Setup

The transient measurement waveform is presented in Figure 5.12. By controlling the VDS
of M6 and M8, the current going through the two branches are balanced. Under an 80mA DC
current, the current difference between the two branches is only 0.7mA, which is less than 1%
of the total current. The voltage difference between VCH1 and VCH2 is 3.6V, which is equal to
the voltage drop across a white LED under normal operation. The zoomed-in figures prove
that the rising time of the current balancing dimmer is no larger than 84ns and the falling time
is only 3ns. This guarantees that the 400kHz VLC signal can be successfully restored, as
shown in the zoomed-out figure.

Figure 5.12 Current Balancing Dimmer Measurement Result

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 5.3.4 DC-DC Boost Converter Transient Response under VLC Operation

Figure 5.13 shows the measurement setup for the cooperation of the converter, the dimmer,
and the digital baseband on the SoC. The ADCMT 6244 is used as the power supply to the
converter and the dimmer. The Xilinx Virtex5 FPGA development board is in charge of
controlling and supplying power to the digital baseband. The converter drives one branch of
five LEDs in series and the output voltage and current is monitored by the MSO7034B. The
VLC signal, i.e., the light, is received by the receiver (RX) analog front-end and the output
voltage of the RX front-end is also captured by the MSO7034B.

Figure 5.13 TX SoC VLC & PMU Cooperation Measurement Setup

The measurement results with the digital baseband working in on-off keying (OOK) mode,
10% dimming variable pulse-position modulation (VPPM) mode, and 50% dimming VPPM
mode are shown in Figure 5.14. In all three measurements, the current that goes through the
LED branch is set to be 80mA. The Vout is between 18V to 19V, with a maximum voltage
ripple of 381mV. The output voltage from the RX front-end is directly proportional to the
LED current, and the symbols for logic level ‘0’ and ‘1’ can be distinguished from the
captured waveform. These measurement results prove that the converter is capable of
supplying power for the LEDs under VLC operation, and the digital baseband successfully
controls the dimmer to drive the LEDs for VLC purposes.

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 (a) OOK Modulation Mode

(b) VPPM @ 10% Dimming

(c) VPPM @ 50% Dimming

Figure 5.14 VLC Transient Measurement Result

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 5.3.5 VLC Dimming Function Measurement

The measurement setup shown in Figure 5.15 is used to demonstrate the VLC dimming
function. The converter and the dimmer are supplied by the ADCMT 6244 and the digital
baseband is controlled and supplied by the FPGA board, which is the same as in Section 5.3.4.
The TX SoC drives 20 LEDs in four branches to transmit the VLC signal. The EA33 is placed
at various distances from the TX SoC to measure the illuminance.

Figure 5.15 TX SoC VLC Dimming Measurement Setup

Figure 5.16 shows the measured illuminance versus the dimming control at various
distances. The baseband operates in VPPM mode with the dimming control varying from 10%
to 90%. The linearity of the measured illuminance proves that the dimming control of the TX
SoC is working normally.

Figure 5.16 TX SoC VLC Dimming Measurement Result

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 5.3.6 PER Measurement of the Transceiver System

To evaluate the performance of the IEEE Std. 802.15.7 type-I physical layer (PHY-I) VLC
transceiver system, a packet error rate (PER) measurement setup is constructed as shown in
Figure 5.17. At the TX side, the SoC is also powered up and controlled by the ADCMT 6244
and the FPGA board. The LED PCB is connected to the COB PCB and all 20 LEDs are
driven by the SoC. The maximum current flowing through each LED is 80mA, and generates
around 20lm luminous flux. During 50% dimmed VLC, all 20 LEDs consume about 3W
power and provide a total luminous flux of approximately 200lm. At the RX side, the FPGA
board receives signal from the RX front-end and performs demodulation and decoding for the
PER measurement. The EA33 is used to measure the illuminance at the RX front-end and the
MSO7034B is used to capture the output of the RX front-end for eye-diagram plotting.

Figure 5.17 TX SoC VLC PER Measurement Setup

PER measurement quantitatively qualifies the performance of a communication system.

The PER contains two parts, a packet lost rate, plost, and a received packet error rate, which
can be calculated from the measured BER of received packages, BERreceived. Thus, the PER is
expressed as
( )( ) (5.1)

63
 The advantage of PER measurement is that it provides more comprehensive information
about the communication system, including the channel. Not only is the error in the
synchronization header (SHR), which causes the packet loss, counted, but the error that is not
corrected by the forward error correction (FEC) code is also counted in the PER. For optical
wireless communication systems, a PER <10% is commonly acceptable, which is equivalent
to a BER < 10-4 to 10-5.
The observed eye diagrams of both OOK and VPPM mode are shown in Figure 5.18.
Figure 5.18 (a) shows the eye diagram of OOK mode with a 153mV eye opening and a 13.4ns
root mean square (RMS) jitter. Figure 5.18 (b) shows the 50% dimming VPPM mode eye
diagram with an eye opening of 157mV and an RMS jitter of 13.2ns. The measured
illuminance and calculated PER for both OOK and VPPM mode are shown in Figure 5.19.
Figure 5.19 (a) indicates that for OOK mode, the transceiver system provides a PER <10%,
with a communication distance ≤2.2m and a received illuminance ≥19.3lx. Figure 5.19 (b)
proves that for the 50% dimming VPPM mode, a PER <10% can be achieved at a distance ≤
1.8m, with a received illuminance ≥31lx.

(a) OOK (b) VPPM

Figure 5.18 Eye Diagram Measurement Result

(a) OOK (b) VPPM

Figure 5.19 Illuminance & PER Measurement Result

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 5.3.7 Eye Diagram Measurement with Lens

Even though this work targets at lensless VLC, the eye diagrams measured with a lens is
also shown to demonstrate the improvement in term of the communication distance. The
measurement setup is shown in Figure 5.20. The TX is employed in the same way as 5.3.6.
On the RX side, a lens with a diameter of 5cm is placed at a certain distance in front of the
analog front-end. The output of the RX analog front-end is directly fed into the oscilloscope
without being processed by the RX digital baseband.

Figure 5.20 Eye Diagram with Lens Measurement Setup

Figure 5.21 presents the measured eye diagram with lens at 20m under VPPM mode. The
eye amplitude is approximately 50mV, which is still detectable of the RX. The measurement
result shows that the lens does contribute to the VLC transmission distance.

(a) 30% VPPM @ d=20m (b) 70% VPPM @ d=20m

Figure 5.21 Eye Diagram with Lens Measurement Result

5.3.8 Performance Summary

The detailed performance of the SoC, including the digital baseband, the boost converter
and the dimmer, is summarized as shown in Table 5.1.

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 Table 5.1 Performance Summary

Input Voltage 3.3V

IEEE Std. 802.15.7 PHY-I TX

Power Consumption 0.81mW – 1.25mW

Area 2.33mm2
FEC RS Code / Convolutional Code
BB

RLL Manchester / 4B6B

Modulation OOK / VPPM
Data Rate Up to 266.6kb/s
2.2m @73.3kb/s, 50% OOK
Distance (@PER<10%)
1.8m @71.1kb/s, 50% VPPM
Input Voltage Range 3V – 5V
Output Voltage Range 6V – 20V (2 – 6 LEDs in serial)
Boost Converter

Area 0.97mm2(Controller) + 1.6mm2(Power NMOS)

Maximum Output Power 8W
Switching Frequency 1.7MHz
Inductor 4.7μH
Capacitor 5μF
Peak Power Efficiency 91.88% @ 10V / 180mA
Area 0.45mm2
No. of Channels 4
Dimmer

Current Balance Accuracy < 1%

84ns @Rising Edge
Response Time
3ns @Falling Edge

The design comparison with two other related works is summarized in Table 5.2. Without
using lens, this work demonstrates a reliable communication range of around 2m. The
transmission energy efficiency of the TX SoC is approximately 5nJ/bit, excluding the power
consumed by the LED driver for lighting.

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 Table 5.2 Design Comparison

Parameter This Work [7] [8]

VLC 0.81–1.25mW N/A N/A
Power
LED 6W 1.5W 9.8W
Data Rate ≤ 266.6kb/s ≤ 50Mb/s ≤513Mb/s
w/o lens ~ 2m N/A N/A
Range
w/i lens > 20m 2m 0.3m
Standard Compliant IEEE 802.15.7 N/A N/A
Fully Integrated
Integration Level (VLC TX + LED Driver Discrete Discrete
+ Power MOSFET)
3-dB BW of LEDs 2.5MHz 2.5MHz 35MHz

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CHAPTER 6 CONCLUSION

Thanks to the rapid development of LED technology and the useful characteristics of
visible light, such as line-of-sight, unregulated ultra-wide spectrum, no RF radiation and no
EM interference, VLC has been regarded as a promising communication technology and has
attracted many researchers’ interest. However, most of the demonstrated VLC systems are
implemented with discrete components and the communication is carried out with no specific
standard. Therefore, these demonstrations are quite impractical and insufficient for ubiquitous
expansion of the VLC services required in the near future.
This thesis describes a design and implementation of a VLC transceiver system based on
the IEEE Std. 802.15.7. The transceiver realizes the function of the type-I physical layer
(PHY-I), and the transmitter (TX) baseband, integrated with a power management unit (PMU),
forms a system-on-chip (SoC). The front-end of the TX are commercial white LEDs. The
corresponding receiver (RX) baseband is implemented on a field programmable gate array
(FPGA), with an analog front-end that is composed of discrete components. Taking the VLC
transceiver system as an example, the link budget analysis of a VLC system is introduced to
facilitate the estimation of the performance of a VLC system.
The TX SoC is fabricated through the AMS 0.35μm HV CMOS process, and
measurements are carried out for both the on-chip PMU and the entire VLC transceiver
system. The measurement results prove that with a 3.7V input, the PMU can achieve an 8W
output power at Vout = 10V with an efficiency of approximately 83%. A peak power
conversion efficiency of 91.88% is attained at Vout = 10V with an output power of 1.8W. The
measurement of the entire VLC transceiver demonstrates a VLC of PER < 10% with on-off
keying (OOK) modulation at an effective data rate of 73.3kb/s. The TX SoC achieves a data
transmission energy efficiency of around 5nJ/bit, which is close to that of WiFi.
To our knowledge, the TX SoC is the first to implement the PHY-I of the IEEE Std.
802.15.7 on a chip and integrate the PMU together with the digital baseband. To move
forward, PHY-II and PHY-III can be implemented on the SoC, and this requires the design of
high frequency DC-DC converters and fast-response dimmers to be improved in order to
support a higher VLC operating frequency at tens of MHz. On the RX side, both the
transimpedance amplifier (TIA) in the analog front-end and the entire digital baseband of the
RX can be optimized and implemented on an SoC. Moreover, an on-chip photodiode (PD)
technique, such as the avalanche photodiode (APD), can also be examined for full system
integration.
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APPENDIX A EQUIPMENT FOR MEASUREMENT

All the equipment used for the SoC measurement is summarized as follows.
ADCMT 6243 & 6244 DC Voltage/Current Sources/Monitors

(a) 6243 (b) 6244

Figure A.1 ADCMT 6243 & 6244

The ADCMT 6243 provides a generation and measurement voltage range of 0 to ±110V,
with a current range of 0 to ±2A. The ADCMT 6244 offers a voltage range of 0 to ±20V and a
current range of 0 to ±10A. Both of the two pieces of equipment possess a source resolution
of 4½ digits and a measurement resolution of 5½ digits. These two systems are used as either
power supply or electronic loading during the measurement. Moreover, the equipped GPIB of
the two pieces of equipment provides the capability of conducting automatic measurement.
Kikusui PLZ164WL Electronic Load

Figure A.2 Kikusui PLZ164WL

The PLZ164WL operates from 0.3 to 30V. The maximum current rating is 50A. The
equipment provides six different operation modes, such as constant current, constant
resistance, constant power etc., for various applications. It is used as a resistive load for
steady-state measurement and a fast switching load for load transient measurement.

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 ADCMT 7461A Digital Multimeter

Figure A.3 ADCMT 7461A

The ADCMT 7461A offers a measurement resolution of 6½ digits and can provide
2-channel voltage measurement and 1-channel current measurement. The sampling rate is as
high as 20kSa/s. The multimeter is used for automatic measurement with the equipped GPIB.
Agilent MSO7034B Mixed Signal Oscilloscope

Figure A.4 Agilent MSO7034B

The MSO7034B oscilloscope offers 4-channel analog simultaneous monitoring with a

highest bandwidth of 350MHz and a maximum sample rate of 2GSa/s. Passive and active
probes for both 1MΩ and 50Ω input impedance are supported. The oscilloscope is used for
the transient analysis of the SoC.

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 Extech EA33 Light Meter

Figure A.5 Extech EA33

The EA33 is a lux meter for measuring illuminance. Illuminance is a measure of light
intensity per unit area as perceived by the human eye and is measured in lux. The EA33 offers
a wide measurement range up to 999900lx. The minimum resolution of the measurement is
0.01lx. This equipment is used to measure the received light intensity at various distances to
quantitatively characterize the VLC channel.

73