4-1 Chapter 4 - Processor Design

Chapter 4 Topics

• The Design Process

• A 1-bus Microarchitecture for SRC
• Data Path Implementation
• Logic Design for the 1-bus SRC
• The Control Unit
• The 2- and 3-bus Processor Designs
• The Machine Reset Process
• Machine Exceptions

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-2 Chapter 4 - Processor Design

Abstract and Concrete Register Transfer

Descriptions

• The abstract RTN for SRC in Chapter 2 defines “what,” not

“how”
• A concrete RTN uses a specific set of real registers and
buses to accomplish the effect of an abstract RTN statement
• Several concrete RTNs could implement the same ISA

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-3 Chapter 4 - Processor Design

A Note on the Design Process

• In this chapter presents several SRC designs

• We started in Chap. 2 with an informal description
• In this chapter we will propose several block diagram
architectures to support the abstract RTN, then we will:
• Write concrete RTN steps consistent with the architecture
• Keep track of demands made by concrete RTN on the hardware
• Design data path hardware and identify needed control
signals
• Design a control unit to generate control signals

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-4 Chapter 4 - Processor Design

Fig. 4.1 Block Diagram of 1-bus SRC

CPU

Figure 4.11

Control Unit

ADD

Wait
PCin
Gra
Control signals out Control unit inputs

31 0 〈31..0〉
R0
32 32-bit 32 31 0
general PC
purpose
registers Main Input/
Data Path
memory output
R31
IR

MA
A B
To memory subsystem
ALU
C MD Memory bus

C
Figures 4.2, 4.3

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-5 Chapter 4 - Processor Design

Fig. 4.2 High-Level View of the 1-Bus SRC

Design
〈31..0〉
31 0
R0
32 32-bit 32 31 0
general PC
purpose
registers

R31
IR

MA
A B
To memory subsystem
ALU

C MD

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-6 Chapter 4 - Processor Design

Constraints Imposed by the

Microarchitecture
• One bus connecting most registers
allows many different RTs, but only one
at a time
31 0 〈31..0〉
• Memory address must be copied into R0
32 32-bit 32 31 0
General
MA by CPU Purpose Registers
PC

• Memory data written from or read into

MD R31
IR

• First ALU operand always in A, result A

goes to C
MA
• Second ALU operand always comes A B
To memory subsystem
from bus ALU
C MD

• Information only goes into IR and MA C

from bus
• A decoder (not shown) interprets contents of
IR
• MA supplies address to memory, not to CPU
bus
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-7 Chapter 4 - Processor Design

Abstract and Concrete RTN for SRC add

Instruction
Abstract RTN: (IR ← M[PC]: PC ← PC + 4; instruction_execution);
instruction_execution := ( • • •
add (:= op= 12) → R[ra] ← R[rb] + R[rc]:
31 0 〈31..0〉
R0
32 32-bit 32 31 0
Tbl 4.1 Concrete RTN for add: General
Purpose Registers
PC

Step RTN
T0. MA ← PC: C ← PC + 4; R31

T1. MD ← M[MA]: PC ← C; IR

T2. IR ← MD; IF
A

T3. A ← R[rb];
IEx. A B
MA

T4. C ← A + R[rc]; ALU

To memory subsystem

T5. R[ra] ← C; C MD

• Parts of 2 RTs (IR ← M[PC]: PC ← PC + 4;) done in T0

• Single add RT takes 3 concrete RTs (T3, T4, T5)
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-8 Chapter 4 - Processor Design

Concrete RTN Gives Information about

Sub-units

• The ALU must be able to add two 32-bit values

• ALU must also be able to increment B input by 4
• Memory read must use address from MA and return data to
MD
• Two RTs separated by : in the concrete RTN, as in T0 and
T1, are operations at the same clock
• Steps T0, T1, and T2 constitute instruction fetch, and will
be the same for all instructions
• With this implementation, fetch and execute of the add
instruction takes 6 clock cycles

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-9 Chapter 4 - Processor Design

Concrete RTN for Arithmetic Instructions:

addi
Abstract RTN:
addi (:= op= 13) → R[ra] ← R[rb] + c2〈〈16..0〉〉 {2's comp. sign extend} :
31 0 〈31..0〉
R0
Tbl 4.2 Concrete RTN for addi: 32 32-bit 32 31 0
General PC
Purpose Registers

Step RTN
T0. MA ← PC: C ← PC + 4; R31

T1. MD ← M[MA]; PC ← C; IR

T2. IR ← MD; Instr Fetch

A

T3. A ← R[rb]; Instr Execn. A B

MA

T4. C ← A + c2〈〈16..0〉〉 {sign ext.}; ALU

To memory subsystem

T5. R[ra] ← C; C MD

• Differs from add only in step T4

• Establishes requirement for sign extend hardware
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-10 Chapter 4 - Processor Design

Fig. 4.3 More Complete view of Registers

and Buses in 1-bus SRC Design—Including
Some Control Signals
Figure 4.4
31 0 〈31..0〉 31 0 • Concrete RTN
R0
32 32-bit
32
PC
D Q CON
lets us add
general CONin
purpose
registers
Cond
logic
Figure 4.9 detail to the
Op
data path
5 5 c3〈2..0〉
R31
Register select
Select logic – Instruction
IR
Figure 4.5 register logic &
Select logic
A 32
new paths
c1〈31..0〉
32 c2〈31..0〉 – Condition bit
flip-flop
A B MA

ALU To memory subsystem Figure 4.6 – Shift count

C
MD register
〈4..0〉 4 0
C n n=0 Figure 4.8
Decrement Shift count, n Keep this slide in
Figure 4.7
mind as we discuss
concrete RTN of instrs.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-11 Chapter 4 - Processor Design

Abstract and Concrete RTN for Load and

Store
ld (:= op= 1) → R[ra] ← M[disp] :
st (:= op= 3) → M[disp] ← R[ra] :
where
disp〈〈31..0〉〉 := ((rb=0) → c2〈〈16..0〉〉 {sign ext.} :
≠0) → R[rb] + c2〈〈16..0〉〉 {sign extend, 2's comp.} ) :
(rb≠

Tbl 4.3

Step RTN for ld RTN for st

T0-T2 Instruction fetch
T3. A ← (rb=0 → 0: rb≠ ≠0 → R[rb]);
T4. C ← A + (16@IR〈〈16〉〉#IR〈〈15..0〉〉);
T5. MA ← C;
T6. MD ← M[MA]; MD ← R[ra];
T7. R[ra] ← MD; M[MA] ← MD;

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-12 Chapter 4 - Processor Design

Notes for Load and Store RTN

• Steps T0 through T2 are the same as for add and addi,

and for all instructions

• In addition, steps T3 through T5 are the same for ld and

st, because they calculate disp
• A way is needed to use 0 for R[rb] when rb=0
• 15 bit sign extension is needed for IR〈〈16..0〉〉

• Memory read into MD occurs at T6 of ld

• Write of MD into memory occurs at T7 of st

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-13 Chapter 4 - Processor Design

Concrete RTN for Conditional Branch

br (:= op= 8) → (cond → PC ← R[rb]):

cond := ( c3〈〈2..0〉〉=0 → 0: never
c3〈〈2..0〉〉=1 → 1: always
c3〈〈2..0〉〉=2 → R[rc]=0: if register is zero
c3〈〈2..0〉〉=3 → R[rc]≠
≠0: if register is nonzero
c3〈〈2..0〉〉=4 → R[rc]〈〈31〉〉=0: if positive or zero
c3〈〈2..0〉〉=5 → R[rc]〈〈31〉〉=1 ): if negative
Tbl 4.4
Step Concrete RTN
T0-T2 Instruction fetch
T3. CON ← cond(R[rc]);
T4. CON → PC ← R[rb];

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-14 Chapter 4 - Processor Design

Notes on Conditional Branch RTN

• c3〈〈2..0〉〉 are just the low order 3 bits of IR

• cond() is evaluated by a combinational logic circuit

having inputs from R[rc] and c3〈〈2..0〉〉
• The one bit register CON is not accessible to the
programmer and only holds the output of the
combinational logic for the condition

• If the branch succeeds, the program counter is

replaced by the contents of a general reg.

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-15 Chapter 4 - Processor Design

Abstract and Concrete RTN for SRC Shift

Right

shr (:= op = 26) → R[ra]〈〈31..0〉〉 ← (n @ 0) # R[rb]〈〈31..n〉〉 :

n := ( (c3〈〈4..0〉〉=0) → R[rc]〈〈4..0〉〉 : shift count in reg.
(c3〈〈4..0〉〉≠0) → c3〈〈4..0〉〉 ): or const. field

Tbl 4.5

Step Concrete RTN

T0-T2 Instruction fetch
T3. n ← IR〈〈4..0〉;
T4. (n=0) → (n ← R[rc]〈〈4..0〉〉);
Τ5. C ← R[rb];
T6. Shr (:= (n ≠ 0) → (C〈〈31..0〉〉 ← 0#C〈〈31..1〉〉: n ← n-1; Shr) );
T7. R[ra] ← C;

step T6 is repeated n times

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-16 Chapter 4 - Processor Design

Notes on SRC Shift RTN

• In the abstract RTN, n is defined with :=

• In the concrete RTN, it is a physical register
• n not only holds the shift count but is used as a
counter in step T6
• Step T6 is repeated n times as shown by the recursion
in the RTN
• The control for such repeated steps will be treated later

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-17 Chapter 4 - Processor Design

Data Path/Control Unit Separation

• Interface between data path and control consists of

enable signals
• Some enables select one of several values to apply to
a common point, say a bus
• Other enables change the values of the flip-flops in a
register to match new inputs (on a clock edge, only)
• The type of device used in register file has much
influence on control and some on data path
• Latch: simpler hardware, but more complex timing
× hardware
• Edge triggering: simpler timing, but about 2×
• Always use edge triggered flip-flops!

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-18 Chapter 4 - Processor Design

Reminder on Latch and Edge-Triggered

Operation

• Latch output follows input while control is high

D
D Q

C
C
Q

• Edge triggering samples input at edge time

D
D Q

C
C
Q

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-19 Chapter 4 - Processor Design

Fig. 4.4 The SRC Register File and Its Control Signals

• Rout gates selected reg.

onto bus
• Rin strobed selected reg.
from bus

• BAout differs from Rout by

gating 0 when R[0] is
selected

BA = Base Address
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-20 Chapter 4 - Processor Design

Fig. 4.5 Extracting c1, c2, and op from the

Instruction Register

• I〈〈21〉〉 is the sign bit of C1

that must be extended

• I〈〈16〉〉 is the sign bit of C2

that must be extended
• Sign bits are fanned out
from one to several bits
and gated to bus

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-21 Chapter 4 - Processor Design

Fig. 4.6 CPU to Memory Interface: MA and

MD Registers
• MD is loaded
from mem. or
from CPU
bus

• MD can drive
CPU bus or
mem. bus

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-22 Chapter 4 - Processor Design

Fig. 4.7 The ALU and Its Associated

Registers

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-23 Chapter 4 - Processor Design

From Concrete RTN to Control Signals: The

Control Sequence
Tbl 4.6—The Instruction Fetch

Step Concrete RTN Control Sequence

T0. MA ← PC: C ← PC+4; PCout, MAin, Inc4, Cin
T1. MD ← M[MA]: PC ← C; Read, Cout, PCin, Wait
T2. IR ← MD; MDout, IRin
T3. Instruction_execution

• The register transfers are the concrete RTN

• The control signals that cause the register transfers
make up the control sequence
• Wait prevents the control from advancing to step T3
until the memory asserts Done

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-24 Chapter 4 - Processor Design

Control Steps, Control Signals, and Timing

• Within a given time step, the order in which control signals

are written is irrelevant
• In step T0, Cin, Inc4, MAin, PCout == PCout, MAin, Inc4, Cin
• Some signals are combinational and take place now (i.e. ALU
select functions).
• Some signals are enables and make things happen at the
next clock edge (at the end of the control step).
• The memory read should be started as early as possible to
reduce the wait.
• MA must have the right value before being used for the read.

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-25 Chapter 4 - Processor Design

Control Sequence for the SRC add

Instruction
add (:= op= 12) → R[ra] ← R[rb] + R[rc]:
Tbl 4.7 The Add Instruction

Step Concrete RTN Control Sequence

T0. MA ← PC: C ← PC+4; PCout, MAin, Inc4, Cin, Read
T1. MD ← M[MA]: PC ← C; Cout, PCin, Wait
T2. IR ← MD; MDout, IRin
T3. A ← R[rb]; Grb, Rout, Ain
T4. C ← A + R[rc]; Grc, Rout, ADD, Cin
T5. R[ra] ← C; Cout, Gra, Rin, End
• Note the use of Gra, Grb, & Grc to gate the correct 5 bit
register select code to the regs.
• End signals the control to start over at step T0
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-26 Chapter 4 - Processor Design

Control Sequence for the SRC addi

Instruction
addi (:= op= 13) → R[ra] ← R[rb] + c2〈〈16..0〉〉 {2's comp., sign ext.} :

Tbl 4.8 The addi Instruction

Step Concrete RTN Control Sequence
T0. MA ← PC: C ← PC + 4; PCout, MAin, Inc4, Cin, Read
T1. MD ← M[MA]; PC ← C; Cout, PCin, Wait
T2. IR ← MD; MDout, IRin
T3. A ← R[rb]; Grb, Rout, Ain
T4. C ← A + c2〈〈16..0〉〉 {sign ext.}; c2out, ADD, Cin
T5. R[ra] ← C; Cout, Gra, Rin, End

• The c2out signal sign extends IR〈〈16..0〉〉 and gates it to the

bus

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-27 Chapter 4 - Processor Design

Control Sequence for the SRC st

Instruction
st (:= op= 3) → M[disp] ← R[ra] :
disp〈〈31..0〉〉 := ((rb=0) → c2〈〈16..0〉〉 {sign ext.} :
≠0) → R[rb] + c2〈〈16..0〉〉 {sign extend, 2's comp.} ) :
(rb≠
The st Instruction

Step Concrete RTN Control Sequence

T0-T2 Instruction fetch Instruction fetch
T3. A ← (rb=0) → 0: rb≠ ≠0 → R[rb]; Grb, BAout, Ain
T4. C ← A + c2〈〈16..0〉〉 {sign ext.}; c2out, ADD, Cin
T5. MA ← C; Cout, MAin
T6. MD ← R[ra]; Gra, Rout, MDbus, MDwr, Write
T7. M[MA] ← MD; Wait, End

• Note BAout in T3 compared to Rout in T3 of addi

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-28 Chapter 4 - Processor Design

Fig. 4.8 The Shift Counter

• The concrete RTN for shr relies upon a 5 bit register to hold
the shift count
• It must load, decrement, and have an = 0 test

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-29 Chapter 4 - Processor Design

Tbl 4.10 Control Sequence for the SRC shr

Instruction—Looping

Step Concrete RTN Control Sequence

T0-T2 Instruction fetch Instruction fetch
T3. n ← IR〈〈4..0〉; c1out, Ld
T4. (n=0) → (n ← R[rc]〈〈4..0〉〉); n=0 → (Grc, Rout, Ld)
T5. C ← R[rb]; Grb, Rout, C=B, Cin
T6. Shr (:= (n≠ ≠0) → n≠≠0 → (Cout, SHR, Cin,
(C〈〈31..0〉〉 ← 0#C〈〈31..1〉〉: Decr, Goto6)
n ← n-1; Shr) );
T7. R[ra] ← C; Cout, Gra, Rin, End

• Conditional control signals and repeating a control step

are new concepts

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-30 Chapter 4 - Processor Design

Branching

cond := ( c3〈〈2..0〉〉=0 → 0:
c3〈〈2..0〉〉=1 → 1:
c3〈〈2..0〉〉=2 → R[rc]=0:
c3〈〈2..0〉〉=3 → R[rc]≠≠0:
c3〈〈2..0〉〉=4 → R[rc]〈〈31〉〉=0:
c3〈〈2..0〉〉=5 → R[rc]〈〈31〉〉=1 ):
• This is equivalent to the logic expression

cond = (c3〈〈2..0〉〉=1) ∨ (c3〈〈2..0〉〉=2)∧

∧(R[rc]=0) ∨
∧¬(R[rc]=0)
(c3〈〈2..0〉〉=3)∧¬
∧¬ ∨ (c3〈〈2..0〉〉=4)∧¬
∧¬R[rc]〈
∧¬ 〈31〉〉 ∨
∧R[rc]〈〈31〉〉
(c3〈〈2..0〉〉=5)∧

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-31 Chapter 4 - Processor Design

Fig. 4.9 Computation of the Conditional

Value CON

• NOR gate does =0 test of R[rc] on bus

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-32 Chapter 4 - Processor Design

Tbl 4.11 Control Sequence for SRC Branch

Instruction, br

br (:= op= 8) → (cond → PC ← R[rb]):

Step Concrete RTN Control Sequence

T0-T2 Instruction fetch Instruction fetch
T3. CON ← cond(R[rc]); Grc, Rout, CONin
T4. CON → PC ← R[rb]; Grb, Rout, CON → PCin, End
• Condition logic is always connected to CON, so R[rc] only
needs to be put on bus in T3
• Only PCin is conditional in T4 since gating R[rb] to bus
makes no difference if it is not used

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-33 Chapter 4 - Processor Design

Summary of the Design Process

Informal description ⇒ formal RTN description ⇒ block

diagram arch. ⇒ concrete RTN steps ⇒ hardware design
of blocks ⇒ control sequences ⇒ control unit and timing
• At each level, more decisions must be made
• These decisions refine the design
• Also place requirements on hardware still to be designed
• The nice one way process above has circularity
• Decisions at later stages cause changes in earlier ones
• Happens less in a text than in reality because
• Can be fixed on re-reading
• Confusing to first time student

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-34 Chapter 4 - Processor Design

Fig. 4.10 Clocking the Data Path: Register

Transfer Timing
D Q Combinaational D Q
n Logic
E R1 Rout Rin E R2
Q’ Q’
Logic (ALU)
Clock to gate prop. bus prop. prop.
output. time Tg time Tbp time Tcomb
time Tco
Circuit
Propagation
Delay

Data Enable
Rout
Clock Enable
Rin

Clock
Tsu Th
• tR2valid (total delay) = tco + tg + tbp + tcomb + tsu
• As long as th<tdelay we don’t have to worry about it!
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-35 Chapter 4 - Processor Design

Signal Timing on the Data Path

• Several delays occur in getting data from R1 to R2:

• Clock to output delay of the flip-flop —tco
• Gate delay through the 3-state bus driver—tg
• Worst case propagation delay on bus—tbp
• Delay through any logic, such as ALU—tcomb
• Set up time for data to affect state of R2—tsu
• Data can be clocked into R2 after this time
tR2valid =tco + tg + tbp + tcomb + tsu
• There is a hold time, th, for data after clock falls but probably
not a problem if tR2valid is large!

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-36 Chapter 4 - Processor Design

Effect of Signal Timing on Minimum Clock

Cycle

• The total delay induced by the flip-flops is tff:

• tff = tco + tsu
• Note that you never add multiple tco or tsutimes!
• The minimum clock period is determined by finding
longest path from flip-flop input to flip-flop input (clock
to clock)
• Look for all flip-flop pairs with different stuff between
them.
• Find the path with the longest logic delay (usually, all flip-
flops will have the same timing parameters so only the
delay between them will affect your clock calculation).
• This is usually a path through the ALU.
• Using this path, the minimum clock period is
tmin = tg + tbp + tcomb + tff

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-37 Chapter 4 - Processor Design

Latches Versus Edge Triggered or Master

Slave Flip-Flops

• During the high part of a strobe a latch changes its

output
• If this output can affect its input, an error can occur
• This can influence even the kind of concrete RTs that
can be written for a data path
• If the C register is implemented with latches, then
C ← C + MD; is not legal
• If the C register is implemented with master-slave or
edge triggered flip-flops, it is OK
• THIS IS WHY WE ALWAYS USE FLIP-FLOPS

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-38 Chapter 4 - Processor Design

The Control Unit

• The control unit’s job is to generate the control signals in

the proper sequence
• Things the control signals depend on
• The time step Ti
• The instruction op code (for steps other than T0, T1, T2)
• Some few data path signals like CON, n=0, etc.
• Some external signals: reset, interrupt, etc. (to be covered)
• The components of the control unit are: a time state
generator, instruction decoder, and combinational logic
to generate control signals

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-39 Chapter 4 - Processor Design

SRC FSM Example (ADD,ADDI)

FETCH

• DONE & WAIT not

shown
• Mealy model FSM

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
.

4-40 Chapter 4 - Processor Design

Fig. 4.11 Control Unit Detail with Inputs

and Outputs

Master Strt Wait Done

clock OpCode IR Other signals from
the data path
Decoder
CON n=0
Clocking logic
ld add shc br
Enable
Step generator
T0
T1 Interrupts
Counter

Countln Control T2 Control

step and other
signal
4 decoder T4 external
encoder
signals
Tn – 1

Load Reset Generated control signals

PCout

Rout
ADD
PCin
Gra
Wait

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-41 Chapter 4 - Processor Design

Synthesizing Control Signal Encoder Logic

Step Control Sequence

T0. PC
out
, MA , Inc4, C , Read
in in
T1. Cout, PC in, Wait

T2. MD
out
, IR
in

add addi st shr

Step Control Sequence Step Control Sequence Step Control Sequence Step Control Sequence
T3. Grb, R ,A
out in T3. Grb, R ,A
out in T3. Grb, BA ,A
out in T3. c1
out
, Ld

T4. Grc, R
out
, ADD, C
in T4. c2
out
, ADD, C
in T4. c2
out
, ADD, C
in T4. n=0 → (Grc, R
out
, Ld)

out Gra, in out Gra, in

T5. C , R , End T5. C , R , End T5. Cout, MA in T5. Grb, Rout, C=B

T6. Gra, Rout, MDin, Write T6. ≠0 → (C out, SHR, C in,

n≠
Decr, Goto7)
T7. Wait, End
T7. C
out
, Gra, Rin, End
Design process:
• Comb through the entire set of control sequences.
• Find all occurrences of each control signal.
• Write an equation describing that signal.
Example: Gra = T5·(add + addi) + T6·st + T7·shr + ...

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-42 Chapter 4 - Processor Design

Use of Data Path Conditions in Control

Signal Logic
Step Control Sequence
T0. PCout, MAin, Inc4, Cin, Read

T1. Cout, PCin, Wait

T2. MDout, IRin

add addi st shr

Step Control Sequence Step Control Sequence Step Control Sequence Step Control Sequence
T3. Grb, Rout, Ain T3. Grb, Rout, A in T3. Grb, BA out, Ain T3. c1out, Ld

T4. Grc, Rout, ADD, Cin T4. c2

out
, ADD, C
in T4. c2
out
, ADD, C
in T4. n=0 → (Grc, Rout, Ld)
T5. Cout, Gra, Rin, End T5. Cout, Gra, Rin, End T5. Cout, MAin
T5. Grb, Rout, C=B
T6. Gra, R out, MDin, Write
T6. ≠0 → (C
n≠ , SHR, C ,
out in
T7. Wait, End Decr, Goto7)
T7. Cout, Gra, Rin, End

Example: Grc = T4·add + T4·(n=0)·shr + ...

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-43 Chapter 4 - Processor Design

Fig. 4.12 Generation of the logic for PCin

and Gra

T1 add T5

Cout addi Gra

T5 T7
add ld

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-44 Chapter 4 - Processor Design

Fig. 4.13 Branching in the Control Unit

Mck Enable

Step generator • 3-state gates allow

6 to be applied to
counter input
Counter

Control
Countln step • Reset will
decoder synchronously
4 reset counter to
step T0

0110 Load

Reset
Goto6

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-45 Chapter 4 - Processor Design

Fig. 4.14 Clocking Logic: Start, Stop, and

Memory Synchronization
1
Run (G) 2
Strt (E) J Q Done (E)
D Q
Stop (C) K Q
SDone (G)
Mck (I) Q

4
Enable (G)
Wait (C)

Read (C) J Q R (G)

3 K Q To memory system
Legend
Write (C) J Q W (G) E – External
G – Generated
C – Control signal
K Q I – Internal

• Mck is master clock oscillator

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-46 Chapter 4 - Processor Design

One-Bus SRC Controller Design

Fetch

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-47 Chapter 4 - Processor Design

Have Completed One-Bus Design of SRC

• High level architecture block diagram

• Concrete RTN steps
• Hardware design of registers and data path logic
• Revision of concrete RTN steps where needed
• Control sequences
• Register clocking decisions
• Logic equations for control signals
• Time step generator design
• Clock run, stop, and synchronization logic

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-48 Chapter 4 - Processor Design

Other Architectural designs will require a

different RTN

• More data paths allow more things to be done in one

step
• Consider a two bus design
• By separating input and output of ALU on different
buses, the C register is eliminated
• Steps can be saved by strobing ALU results directly
into their destinations

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-49 Chapter 4 - Processor Design

Fig. 4.15 The 2-bus Microarchitecture

A Bus
31 0 B Bus
(“in bus”)
R0 (“out bus”)
32
32
32 general

purpose • Bus A carries data

registers going into registers
R31 • Bus B carries data
being gated out of
IR
registers
PC • ALU function C=B is
address used for all simple
MA To memory
data register transfers
subsystem
MD

A B
ALU
C

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-50 Chapter 4 - Processor Design

Tbl 4.13 Concrete RTN and Control

Sequence for 2-bus SRC add

Step Concrete RTN Control Sequence

T0. MA ← PC; PCout, C=B, MAin
T1. PC ← PC + 4: MD ← M[MA];PCout, Inc4, PCin, Wait,
Read, MDrd
T2. IR ← MD; MDout, C=B, IRin
T3. A ← R[rb]; Grb, Rout, C=B, Ain
T4. R[ra] ← A + R[rc]; Grc, Rout, ADD, Sra,
Rin, End
• Note the appearance of Grc to gate the output of the
register rc onto the B bus and Sra to select ra to receive
data strobed from the A bus
• Two register select decoders will be needed

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-51 Chapter 4 - Processor Design

Performance and Design

T 1 − bus − T 2 − bus
%Speedup = × 100
T 2 − bus
Where
T = Exec' n.Time = IC × CPI × τ
IC ≡ Instruction Count
CPI ≡ Clocks Per Instruction
τ ≡ Clock period

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-52 Chapter 4 - Processor Design

Speedup Due To Going to 2 Buses

•Assume for now that IC and t don’t change in going from 1 bus to 2 buses
•Naively assume that CPI goes from 8 to 7 clocks.

T 1 − bus − T 2 − bus
% Speedup = × 100
T 2 − bus

IC × 8 × τ − IC × 7 × τ 8−7
= × 100 = × 100 = 14 %
IC × 7 × τ 7

Class Problem:
How will this speedup change if clock period of 2-bus machine is increased by 10%?

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-53 Chapter 4 - Processor Design

3-bus Architecture Shortens Sequences

Even More

• A 3-bus architecture allows both operand inputs and

the output of the ALU to be connected to buses
• Both the C output register and the A input register are
eliminated
• Careful connection of register inputs and outputs can
allow multiple RTs in a step

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-54 Chapter 4 - Processor Design

Fig. 4.16 The 3-Bus SRC Design

C Bus
31 0 A Bus B Bus
R0
32
32 32
32 general • A-bus is ALU
purpose operand 1, B-bus is
registers ALU operand 2, and
R31
C-bus is ALU output
IR
• Note MA input
connected to the B-
PC bus
address
MA To memory
data
subsystem
MD

A B
ALU
C

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-55 Chapter 4 - Processor Design

Tbl 4.15 SRC add Instruction for the

3-bus Microarchitecture

Step Concrete RTN Control Sequence

T0. MA ← PC: PC ← PC + 4: PCout, MAin, Inc4, PCin,
T1. MD ← M[MA]; MDrd, Read, Wait
T2. IR ← MD; MDout, C=B, Irin
T3. R[ra] ← R[rb] + R[rc]; GArc, RAout, GBrb, RBout,
ADD, Sra, Rin, End
• Note the use of 3 register selection signals in step T2: GArc,
GBrb, and Sra
• In step T0, PC moves to MA over bus B and goes through the
ALU Inc4 operation to reach PC again by way of bus C
• PC must be edge triggered or master-slave (of course!)
• If MA were a transparent latch, we could eliminate T1, but we
don’t like latch timing! Keeping it safe gives us three fetch
cycles, still.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-56 Chapter 4 - Processor Design

Performance and Design

• How does going to three buses affect performance?

• Assume average CPI goes from 8 to 4, while τ increases
by 10%:

IC × 8 × τ − IC × 4 × 1.1τ 8− 4.4
%Speedup= × 100 = × 100 = 82%
IC × 4 × 1.1τ 4.4

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-57 Chapter 4 - Processor Design

Processor Reset Function

• Reset sets program counter to a fixed value

• May be a hardwired value (like location 0) , or
• contents of a memory cell whose address is hardwired
• The control step counter is reset
• Pending exceptions are prevented, so initialization code is not
interrupted
• It may set condition codes (if any) to known state
• It may clear some processor state registers
• A “soft” reset makes minimal changes: PC, T (trace)
• A “hard” reset initializes more processor state

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-58 Chapter 4 - Processor Design

SRC Reset Capability

• We specify both a hard and soft reset for SRC

• The Strt signal will do a hard reset
• It is effective only when machine is stopped
• It resets the PC to zero
• It resets all 32 general registers to zero (not smart , actually…
Why? What should we be careful of?)
• The Soft Reset signal is effective when the machine is
running
• It sets PC to zero
• It restarts instruction fetch
• It clears the Reset signal
• Actions are described in instruction_interpretation

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-59 Chapter 4 - Processor Design

Abstract RTN for SRC Reset and Start

Processor State
Strt: Start signal
Rst: External reset signal

instruction_interpretation := (
¬Run∧ ∧Strt → (Run ← 1: PC, R[0..31] ← 0);
∧¬Rst
∧¬
Run∧¬ → (IR ← M[PC]: PC ← PC + 4;
instruction_execution):
Run∧∧Rst → ( Rst ← 0: PC ← 0); instruction_interpretation):

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-60 Chapter 4 - Processor Design

Resetting in the Middle of Instruction

Execution

• The abstract RTN implies that reset takes effect after

the current instruction is done
• To describe reset during an instruction, we must go
from abstract to concrete RTN

• Questions for discussion:

• Why might we want to reset in the middle of an instruction?
• How would we reset in the middle of an instruction?

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-61 Chapter 4 - Processor Design

Tbl 4.17 Concrete RTN Describing Reset

During add Instruction Execution

Step Concrete RTN

T0 ¬Reset → (MA ← PC: C ← PC + 4):
Reset → (Reset ← 0: PC ← 0: T ←0):
T1 ¬Reset → (MD ← M[MA]: P ← C):
Reset → (Reset ← 0: PC ← 0: T ← 0):
T2 ¬Reset → (IR ← MD):
Reset → (Reset ← 0: PC ← 0: T ← 0):
T3 ¬Reset → (A ← R[rb]):
Reset → (Reset ← 0: PC ← 0: T ← 0):
T4 ¬Reset → (C ← A + R[rc]):
Reset → (Reset ← 0: PC ← 0: T ← 0):
T5 ¬Reset → (R[ra ] ← C):
Reset → (Reset ← 0: PC ← 0: T ← 0):

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-62 Chapter 4 - Processor Design

Control Sequences Including the Reset

Function

Step Control Sequence

T0. ¬Reset → (PCout, MAin, Inc4, Cin, Read):
Reset → (ClrPC, ClrR, Goto0):
T1 ¬Reset → (Cout, PCin, Wait):
Reset → (ClrPC, ClrR, Goto0):
•••
• ClrPC clears the program counter to all zeros, and ClrR
clears the one bit Reset flip-flop
• Because the same reset actions are in every step of
every instruction, their control signals are independent
of time step or op code

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-63 Chapter 4 - Processor Design

General Comments on Exceptions

• An exception is an event that causes a change in the

program specified flow of control
• Because normal program execution is interrupted, they
are often called interrupts
• We will use exception for the general term and use
interrupt for an exception caused by an external event,
such as an I/O device condition
• The usage is not standard. Other books use these words
with other distinctions, or none

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-64 Chapter 4 - Processor Design

Combined Hardware/Software Response to

an Exception

• The system must control the type of exceptions it will

process at any given time
• The state of the running program is saved when an allowed
exception occurs
• Control is transferred to the correct software routine, or
“handler” for this exception
• This exception, and others of less or equal importance are
disallowed during the handler
• The state of the interrupted program is restored at the end
of execution of the handler

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-65 Chapter 4 - Processor Design

Hardware Required to Support Exceptions

• To determine relative importance, a priority number is

associated with every exception
• Hardware must save and change the PC, since without it
no program execution is possible
• Hardware must disable the current exception lest it
interrupt the handler before it can start
• Address of the handler is called the exception vector and
is a hardware function of the exception type
• Exceptions must access a save area for PC and other
hardware saved items
• Choices are special registers or a hardware stack

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-66 Chapter 4 - Processor Design

New Instructions Needed to Support

Exceptions

• An instruction executed at the end of the handler must

reverse the state changes done by hardware when the
exception occurred
• There must be instructions to control what exceptions
are allowed
• The simplest of these enable or disable all exceptions
• If processor state is stored in special registers on an
exception, instructions are needed to save and restore
these registers

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-67 Chapter 4 - Processor Design

Kinds of Exceptions

• System reset
• Exceptions associated with memory access
• Machine check exceptions
• Data access exceptions
• Instruction access exceptions
• Alignment exceptions
• Program exceptions
• Miscellaneous hardware exceptions
• Trace and debugging exceptions
• Non-maskable exceptions
• External exceptions—interrupts

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-68 Chapter 4 - Processor Design

An Interrupt Facility for SRC

• The exception mechanism for SRC handles external

interrupts
• There are no priorities, but only a simple enable and
disable mechanism
• The PC and information about the source of the interrupt
are stored in special registers
• Any other state saving is done by software
• The interrupt source supplies 8 bits that are used to
generate the interrupt vector
• It also supplies a 16 bit code carrying information about
the cause of the interrupt

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-69 Chapter 4 - Processor Design

SRC Processor State Associated with

Interrupts

Processor interrupt mechanism

→ ireq:
From Dev.→ interrupt request signal
To Dev. → iack: interrupt acknowledge signal
Internal → IE: one bit interrupt enable flag
to CPU → IPC〈〈31..0〉〉: storage for PC saved upon interrupt
“ → II〈〈31..0〉〉: info. on source of last interrupt
→ Isrc_info〈〈15..0〉〉:
From Dev.→ information from interrupt source
From Dev → Isrc_vect〈〈7..0〉〉: type code from interrupt source
Internal → Ivect〈〈31..0〉〉:= 20@0#Isrc_vect<7..0>#4@0:
defines an interrupt vector table
Ivect〈〈31..0〉〉
000 . . . 0 Isrc_vect〈〈7..0〉〉 0000
31 12 11 4 3 0
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-70 Chapter 4 - Processor Design

SRC Instruction Interpretation Modified for

Interrupts

instruction_interpretation :=
¬Run∧
(¬ ∧Strt → Run ← 1:
∧¬(ireq∧
∧¬
Run∧¬ ∧IE) → (I ← M[PC]: PC ← PC + 4; instruction_execution):
Run∧∧(ireq∧
∧IE) → (IPC ← PC〈〈31..0〉〉:
II〈〈15..0〉〉 ← Isrc_info〈〈15..0〉〉: iack ← 1:
IE ← 0: PC ← Ivect〈〈31..0〉〉; iack ← 0);
instruction_interpretation);

• If interrupts are enabled, PC and interrupt info. are stored in

IPC and II, respectively
• With multiple requests, external priority circuit (discussed in
later chapter) determines which vector & info. are returned
• Interrupts are disabled
• The acknowledge signal is pulsed

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-71 Chapter 4 - Processor Design

SRC Instructions to Support Interrupts

Return from interrupt instruction

rfi (:= op = 29 ) → (PC ← IPC: IE ← 1):

Save and restore interrupt state

svi (:= op = 16) → (R[ra]〈〈15..0〉〉 ← II〈〈15..0〉〉: R[rb] ←
IPC〈〈31..0〉〉):
ri (:= op = 17) → (II〈〈15..0〉〉 ← R[ra]〈〈15..0〉〉 : IPC〈〈31..0〉〉 ←
R[rb]):

Enable and disable interrupt system

een (:= op = 10 ) → (IE ← 1):
edi (:= op = 11 ) → (IE ← 0):
• The 2 rfi actions are indivisible, can’t een & branch

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-72 Chapter 4 - Processor Design

Concrete RTN for SRC Instruction

Fetch with Interrupts

Step ¬(ireq∧
∧IE) Concrete RTN ∧IE)
(ireq∧
¬(ireq∧
T0. (¬ ∧IE) → ( (ireq∧∧IE) → (IPC ← PC: II ← Isrc_info:
MA ← PC: C ← PC+4): IE ← 0: PC←← 22@0#Isrc_vect〈〈7..0〉〉#00:
Iack←←1; Iack ← 0: End);
T1. MD ← M[MA] : PC ← C;
T2. IR ← MD;

• PC could be transferred to IPC over the bus

• II and IPC probably have separate inputs for the
externally supplied values
• iack is pulsed, described as ←1; ←0, which is easier
as a control signal than in RTN

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-73 Chapter 4 - Processor Design

Exceptions During Instruction Execution

• Some exceptions occur in the middle of instructions

• Some CISCs have very long instructions, like string move
• Some exception conditions prevent instruction
completion, like uninstalled memory
• To handle this sort of exception, the CPU must make
special provision for restarting
• Partially completed actions must be reversed so the
instruction can be re-executed after exception handling
• Information about the internal CPU state must be saved
so that the instruction can resume where it left off
• We will see that this problem is acute with pipeline
designs—always in middle of insts.

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-74 Chapter 4 - Processor Design

Recap of the Design Process: the Main

Topic of Chap. 4

SRC
Informal description
Chapter 2
formal RTN description
block diagram architecture

concrete RTN steps

Chapter 4
hardware design of blocks
ctl. sequences
control unit and timing
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001
 4-75 Chapter 4 - Processor Design

Chapter 4 Summary

• Chapter 4 has done a non pipelined data path, and a

hardwired controller design for SRC
• The concepts of data path block diagrams, concrete
RTN, control sequences, control logic equations, step
counter control, and clocking have been introduced
• The effect of different data path architectures on the
concrete RTN was briefly explored
• We have begun to make simple, quantitative estimates
of the impact of hardware design on performance
• Hard and soft resets were designed
• A simple exception mechanism was supplied for SRC

Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan, Updated by David M. Zar, 2/2001