Amc 1311
Amc 1311
Amc 1311
1 Features 3 Description
• 2-V, high-impedance input voltage range optimized The AMC1311 is a precision, isolated amplifier with
for isolated voltage measurement an output separated from the input circuitry by a
• Fixed gain: 1 capacitive isolation barrier that is highly resistant
• Low DC errors: to magnetic interference. This barrier is certified to
– AMC1311: provide reinforced galvanic isolation of up to 5 kVRMS
• Offset error: ±9.9 mV (maximum) according to DIN EN IEC 60747-17 (VDE 0884-17)
• Offset drift: ±20 μV/°C (typical) and UL1577 and supports a working voltage of up to
• Gain error: ±1% (maximum) 1500 VRMS.
• Gain drift: ±30 ppm/°C (typical) The isolation barrier separates parts of the system
– AMC1311B: that operate on different common-mode voltage levels
• Offset error: ±1.5 mV (maximum) and protects the low-voltage side from voltages that
• Offset drift: ±10 μV/°C (maximum) can cause electrical damage or be harmful to an
• Gain error: ±0.2% (maximum) operator.
• Gain drift: ±40 ppm/°C (maximum)
– Nonlinearity: 0.04% (maximum) The high-impedance input of the AMC1311 is
• 3.3-V operation on high-side (AMC1311B) optimized for connection to high-impedance resistive
• High CMTI: 100 kV/μs (minimum) (AMC1311B) dividers or any other high-impedance voltage
• Missing high-side supply indication signal source. The excellent DC accuracy and
• Safety-related certifications: low temperature drift support accurate, isolated
voltage sensing and control in closed-loop systems.
– 7000-VPK reinforced isolation per DIN EN IEC
The integrated missing high-side supply voltage
60747-17 (VDE 0884-17)
detection feature simplifies system-level design and
– 5000-VRMS isolation for 1 minute per UL1577
diagnostics.
– Fully specified over the extended industrial
The AMC1311 is offered with two performance grade
temperature range: –40°C to +125°C
options: the AMC1311B is specified over the extended
2 Applications industrial temperature range of –55°C to +125°C, and
the AMC1311 is specified for operation at –40°C to
• Isolated voltage sensing in:
+125°C.
– Motor drives
– Frequency inverters Device Information(1)
– Uninterruptible power supplies PART NUMBER PACKAGE BODY SIZE (NOM)
AMC1311
SOIC (8) 5.85 mm × 7.50 mm
AMC1311B
R2
Reinforced Isolation
IN OUTP
0..2V
RSNS VCMout 2V ADC
SHTDN OUTN
GND1 GND2
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC1311
SBAS786C – DECEMBER 2017 – REVISED JUNE 2022 www.ti.com
Table of Contents
1 Features............................................................................1 8.1 Overview................................................................... 20
2 Applications..................................................................... 1 8.2 Functional Block Diagram......................................... 20
3 Description.......................................................................1 8.3 Feature Description...................................................20
4 Revision History.............................................................. 2 8.4 Device Functional Modes..........................................22
5 Device Comparison Table...............................................4 9 Application and Implementation.................................. 23
6 Pin Configuration and Functions...................................5 9.1 Application Information............................................. 23
7 Specifications.................................................................. 6 9.2 Typical Application.................................................... 23
7.1 Absolute Maximum Ratings........................................ 6 9.3 What To Do and What Not To Do..............................26
7.2 ESD Ratings............................................................... 6 10 Power Supply Recommendations..............................27
7.3 Recommended Operating Conditions.........................6 11 Layout........................................................................... 28
7.4 Thermal Information....................................................7 11.1 Layout Guidelines................................................... 28
7.5 Power Ratings.............................................................7 11.2 Layout Example...................................................... 28
7.6 Insulation Specifications ............................................ 8 12 Device and Documentation Support..........................29
7.7 Safety-Related Certifications ..................................... 9 12.1 Documentation Support.......................................... 29
7.8 Safety Limiting Values ................................................9 12.2 Receiving Notification of Documentation Updates..29
7.9 Electrical Characteristics...........................................10 12.3 Support Resources................................................. 29
7.10 Switching Characteristics........................................12 12.4 Trademarks............................................................. 29
7.11 Timing Diagram....................................................... 12 12.5 Electrostatic Discharge Caution..............................29
7.12 Insulation Characteristics Curves........................... 13 12.6 Glossary..................................................................29
7.13 Typical Characteristics............................................ 14 13 Mechanical, Packaging, and Orderable
8 Detailed Description......................................................20 Information.................................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
VDD1 1 8 VDD2
IN 2 7 OUTP
SHTDN 3 6 OUTN
GND1 4 5 GND2
Not to scale
(1) See the Power Supply Recommendations section for power-supply decoupling recommendations.
7 Specifications
7.1 Absolute Maximum Ratings
see(1)
MIN MAX UNIT
High-side VDD1 to GND1 –0.3 6.5
Power-supply voltage V
Low-side VDD2 to GND2 –0.3 6.5
IN GND1 – 6 VDD1 + 0.5
Input voltage V
SHTDN GND1 – 0.5 VDD1 + 0.5
Output voltage OUTP, OUTN GND2 – 0.5 VDD2 + 0.5 V
Input current Continuous, any pin except power-supply pins –10 10 mA
Junction, TJ 150
Temperature °C
Storage, Tstg –65 150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier are tied together, creating a two-pin device.
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum supply voltage for high-side and low-side.
(1) The typical value includes one standard deviation (sigma) at nominal operating conditions.
(2) This parameter is input referred.
(3) The typical value is at VDD1 = 3.3 V.
(4) THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.
(5) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (ValueMAX - ValueMIN) / TempRange
(6) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = (ValueMAX - ValueMIN) / (Value(T=25℃) x TempRange) x 106
IN
0V
tf tr
OUTN
VCMout
OUTP
50% - 10%
50% - 50%
50% - 90%
500 1600
AVDD = DVDD = 3.6 V, AMC1311B
AVDD = DVDD = 5.5 V 1400
400
1200
300 1000
PS (mW)
IS (mA)
800
200 600
400
100
200
0 0
0 50 100 150 200 0 50 100 150 200
TA (°C) D001
TA (qC) D002
Figure 7-2. Thermal Derating Curve for Safety- Figure 7-3. Thermal Derating Curve for Safety-
Limiting Current per VDE Limiting Power per VDE
1.E+11 Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
1.E+10 TDDB Line (<1 PPM Fail Rate)
87.5%
1.E+9
1.E+8
Time to Fail (s)
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
20%
1.E+2
1.E+1
500 1500 2500 3500 4500 5500 6500 7500 8500 9500
Stress Voltage (VRMS)
TA up to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1500 VRMS, operating lifetime = 135 years
2.5 10
vs VDD1
2 vs VDD2 8
1.5 6
1 4
0.5 2
VOS (mV)
VOS (mV)
0 0
-0.5 -2
-1 -4
-1.5 -6 Device 1
-2 -8 Device 2
Device 3
-2.5 -10
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDDx (V) D005 Temperature (°C) D019
3.0 V ≤ VDD1 < 4.5 V for the AMC1311B only AMC1311
Figure 7-5. Input Offset Voltage vs Supply Voltage Figure 7-6. Input Offset Voltage vs Temperature
1.5 2.5
Device 1
2 Device 2
1 Device 3
1.5
1
0.5
0.5
VOS (mV)
VOS (mV)
0 0
-0.5
-0.5
-1
Device 1 -1.5
-1
Device 2 -2
Device 3
-1.5 -2.5
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) D006
Temperature (°C) D007
8
IIB (nA)
0
6 -3
4 -6
-9
2
-12
0 -15
100 1000 10000 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
fIN (kHz) VDD1 (V) D010
D009
15 1
12 0.8
9 0.6
6 0.4
3 0.2
EG (%)
IIB (nA)
0 0
-3 -0.2
-6 -0.4
AMC1311 vs VDD1
-9 -0.6 AMC1311 vs VDD2
-0.8 AMC1311B vs VDD1
-12 AMC1311B vs VDD2
-1
-15
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDDx (V)
Temperature (°C) D011
D014
EG (%)
0 0
-0.2
-0.1
-0.4
-0.6 Device 1 -0.2
-0.8 Device 2
Device 3
-1 -0.3
-40 -25 -10 5 20 35 50 65 80 95 110 125 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) D015
Temperature (°C) D016
AMC1311 AMC1311B
Figure 7-13. Gain Error vs Temperature Figure 7-14. Gain Error vs Temperature
5 50
0 0
-5 -50
Normalized Gain (dB)
-10 -100
Output Phase
-15 -150
-20 -200
-25 -250
-30 -300
Figure 7-15. Normalized Gain vs Input Frequency Figure 7-16. Output Phase vs Input Frequency
5 0.04
VOUTP
4.5 VOUTN 0.03
4
0.02
3.5
Nonlinearity (%)
0.01
VOUTx (V)
3
2.5 0
2 -0.01
1.5
-0.02
1
-0.03
0.5
-0.04
0 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-0.1 0.3 0.7 1.1 1.5 1.9 2.3 2.7 VIN (V)
VIN (V) D020
D018
0.02 0.02
Nonlinearity (%)
Nonlinearity (%)
0.01 0.01
0 0
-0.01 -0.01
-0.02 -0.02
Device 1
-0.03 -0.03 Device 2
Device 3
-0.04 -0.04
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDDx (V) Temperature (°C) D022
D021
3.0 V ≤ VDD1 < 4.5 V for the AMC1311B only –55°C ≤ TA < –40°C for the AMC1311B only
-70 -70
vs VDD1
vs VDD2
-75 -75
-80 -80
THD (dB)
THD (dB)
-85 -85
-90 -90
3.0 V ≤ VDD1 < 4.5 V for the AMC1311B only –55°C ≤ TA < –40°C for the AMC1311B only
Figure 7-21. Total Harmonic Distortion vs Supply Voltage Figure 7-22. Total Harmonic Distortion vs Temperature
1000 72.5
70
67.5
100
Noise Density (PV/—Hz)
65
62.5
SNR (dB)
60
10 57.5
55
52.5
1 50
47.5
45
0.1 42.5
0.1 1 10 100 1000 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Frequency (kHz) D025 VIN (V) D026
Figure 7-23. Input-Referred Noise Density vs Frequency Figure 7-24. Signal-to-Noise Ratio vs Input Voltage
80 80
vs VDD1
77.5 vs VDD2 77.5
75 75
72.5 72.5
SNR (dB)
SNR (dB)
70 70
67.5 67.5
65 65
Device 1
62.5 Device 2
62.5
Device 3
60
60
-40 -25 -10 5 20 35 50 65 80 95 110 125
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 Temperature (°C)
VDDx (V) D028
D027
–55°C ≤ TA < –40°C for the AMC1311B only
3.0 V ≤ VDD1 < 4.5 V for the AMC1311B only
Figure 7-26. Signal-to-Noise Ratio vs Temperature
Figure 7-25. Signal-to-Noise Ratio vs Supply Voltage
0 1.49
1.48
-20
1.47
-40 1.46
PSRR (dB)
1.45
VCMout (V)
-60
1.44
1.43
-80
1.42
-100 1.41
VDD1
VDD2 1.4
-120
0.1 1 10 100 1000 1.39
Ripple Frequency (kHz) D029
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
VDD2 (V) D031
100-mV ripple
Figure 7-27. Power-Supply Rejection Ratio vs Ripple Frequency
Figure 7-28. Output Common-Mode Voltage vs Low-Side Supply
Voltage
1.49 300
AMC1311B
1.48 290 AMC1311
1.47 280
1.46 270
260
BW (kHz)
1.45
VCMout (V)
1.44 250
240
1.43
230
1.42
220
1.41
210
1.4
200
1.39 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 VDD2 (V) D033
Temperature (°C) D032
IDDx (mA)
6.5
250
6
240
5.5
230
5
220
4.5
210
4 IDD1 vs VDD1
200 IDD2 vs VDD2
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 3.5
Temperature (°C) D034 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
VDDx (V) D035
tr / tf (Ps)
6 2
5.5 1.5
5
1
4.5
4 IDD1 0.5
IDD2
3.5 0
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
Temperature (°C) D036
VDD2 (V) D037
4 3.8
3.5 3.4
3
3
2.2
2
1.8
1.5
1.4
1
1
50% - 90%
0.5 0.6 50% - 50%
50% - 10%
0 0.2
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
Temperature (°C) D038
VDD2 (V) D039
2.6 2.6
2.2 2.2
1.8 1.8
1.4 1.4
1 1
50% - 90%
0.6 0.6 50% - 50%
50% - 10%
0.2 0.2
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDD2 (V) D040
Temperature (°C) D041
AMC1311B AMC1311
Figure 7-37. IN to OUTP, OUTN Signal Delay vs Low-Side Figure 7-38. IN to OUTP, OUTN Signal Delay vs Temperature
Supply Voltage
3.8
50% - 90%
3.4 50% - 50%
50% - 10%
3
Signal Delay (Ps)
2.6
2.2
1.8
1.4
0.6
0.2
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) D042
AMC1311B
Figure 7-39. IN to OUTP, OUTN Signal Delay vs Temperature
8 Detailed Description
8.1 Overview
The AMC1311 is a precision, single-ended input, isolated amplifier with a high input impedance and wide input
voltage range. The input stage of the device drives a second-order, delta-sigma (ΔΣ) modulator. The modulator
converts the analog input signal into a digital bitstream that is transferred across the isolation barrier and
separates the high-side from the low-side. On the low-side, the received bitstream is processed by a fourth-order
analog filter that outputs a differential signal at the OUTP and OUTN pins proportional to the input signal.
The SiO2-based, capacitive isolation barrier supports a high level of magnetic field immunity, as described in the
ISO72x Digital Isolator Magnetic-Field Immunity application report. The digital modulation used in the AMC1311
to transmit data across the isolation barrier, and the isolation barrier characteristics itself, result in high reliability
and high common-mode transient immunity.
8.2 Functional Block Diagram
VDD1 VDD2
Barrier
AMC1311B
Analog Filter
IN OUTP
TX / RX
RX / TX
ΔΣ Modulator
SHTDN Isolation OUTN
GND1 GND2
Internal Clock
Modulator Bitstream
on High-side
Recovered Sigal
on Low-side
VOUTN VFail-safe
VCLIPout
VOUTP VCMout
0 2.516 V
Input Voltage (VIN)
2V
The AMC1311 output offers a fail-safe feature that simplifies diagnostics on a system level. Figure 8-2 shows the
fail-safe mode, in which the AMC1311 outputs a negative differential output voltage that does not occur under
normal operating conditions. The fail-safe output is active in three cases:
• When the high-side supply VDD1 of the AMC1311 device is missing
• When the high-side supply VDD1 falls below the undervoltage threshold VDD1UV
• When the SHTDN pin is pulled high
Use the maximum VFail-safe voltage specified in the Electrical Characteristics table as a reference value for
fail-safe detection on a system level.
8.4 Device Functional Modes
The AMC1311 is operational when the power supplies VDD1 and VDD2 are applied, as specified in the
Recommended Operating Conditions table.
RX1
High-side supply Low-side supply
(3.3 V or 5 V) (3.3 V or 5 V)
100 nF 1 uF
RX2 AMC1311B
Load
VDD1 VDD2
10 10 nF
ICROSS IN OUTP
ADC
RSNS SHTDN OUTN
10
GND1 GND2
1 uF 100 nF 100 pF
IGBT module
DC Bus
Figure 9-1. Using the AMC1311 for DC Link Voltage Sensing in Frequency Inverters
R1
AMC1311B
R2 VDD1 VDD2
100 pF
IN OUTP
GND1 GND2
R1
IN OUTP –
R3 ADC To MCU
SHTDN OUTN +
TLV9001
GND1 GND2 C2 R4
VREF
For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see
the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data
Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.
VOUTP
VOUTN
VIN
VDD1 VDD2
R1
C2 1 µF C4 1 µF
AMC1311B
C1 100 nF C3 100 nF
R2 VDD1 VDD2
GND1 GND2
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCC) typically exhibit only a fraction of their
nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting
these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is
higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves
that greatly simplify component selection.
11 Layout
11.1 Layout Guidelines
Figure 11-1 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as
possible to the AMC1311 supply pins) and placement of the other components required by the device. For best
performance, place the sense resistor close to the device input pin (IN).
11.2 Layout Example VDC
R1
VDD2
Clearance area, to be
VDD1
kept free of any
conductive materials.
C2 C4
R2
C1 C3
Top Metal
Inner or Bottom Layer Metal
Via
12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 27-Jan-2021
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
AMC1311BDWV ACTIVE SOIC DWV 8 64 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 1311B
AMC1311BDWVR ACTIVE SOIC DWV 8 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 1311B
AMC1311DWV ACTIVE SOIC DWV 8 64 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 1311
AMC1311DWVR ACTIVE SOIC DWV 8 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 1311
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 27-Jan-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive: AMC1311-Q1
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jun-2023
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jun-2023
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jun-2023
TUBE
T - Tube
height L - Tube length
W - Tube
width
Pack Materials-Page 3
PACKAGE OUTLINE
SEATING PLANE
11.5 0.25
PIN 1 ID TYP 0.1 C
AREA
6X 1.27
8
1
5.95 2X
5.75 3.81
NOTE 3
4
5
0.51
8X
0.31
7.6 0.25 C A B
A B 2.8 MAX
7.4
NOTE 4
0.33
TYP
0.13
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5 DETAIL A
(2) TYPICAL
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
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EXAMPLE BOARD LAYOUT
8X (0.6) SYMM
6X (1.27)
(10.9)
4218796/A 09/2013
NOTES: (continued)
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EXAMPLE STENCIL DESIGN
8X (1.8) SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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