VIRTUAL MEMORY

&
MEMORY MANAGEMENT
UNIT

Subject Code: EC-306 ECE Department, DTU

OBJECTIVE
 Virtual Memory

 Memory Management Unit

 Paging

 Memory Management Unit in ARM

 Multi-Tasking and MMU

 Page Replacement Policy

VIRTUAL MEMORY
• Use Physical DRAM as a Cache for the Secondary Storage
• Secondary storage can be a disk or a flash memory used as a disk
• Address space of a process can exceed physical memory size when using virtual memory
• Sum of address spaces of multiple processes can exceed physical memory
• Simplify Memory Management
• Multiple processes resident in main memory.
• Each process with its own address space
• Only “active” code and data is actually in main memory and non-active code in secondary memory
• Allocate more memory to process as needed.
• DRAM is functioning as a cache w.r.t secondary storage when we are using virtual memory

• Provide Protection
• One process can’t interfere with another.
• because they operate in different address spaces.
• User process cannot access privileged information
• different sections of address spaces have different permissions.
MEMORY MANAGEMENT UNIT
• Used in many modern microcontroller targeted for embedded applications
• Memory Management Unit provides the key service of managing tasks as independent programs
running in their own private space
• MMU simplifies programming of application tasks by providing resources for managing virtual memory
• MMU acts as a translator which converts addresses of programs and data to actual physical addresses to map that
on to actual DRAM.
• It also Enables relocation of programs with virtual address to any part of main memory
• Memory management unit (MMU) translates addresses.

logical physical
address memory address main
CPU management
memory
unit
SEGMENTATION BASED MEMORY MANAGEMENT
• Segmentation provided by simple MMU
• Program views its memory as set of segments. Code segment, Data Segment, Stack segment, etc.
• Each program has its own set of private segments.
• Each access to memory is via a segment selector and offset within the segment.
• It allows a program to have its own private view of memory and to coexist transparently with other programs
in the same memory space.

Segment based Address Generation segment selector logical address

base bound
Segment Descriptor Table (SDT)
Base: The base address of the segment
Logical address: an offset within a segment
Bound: Segment limit
SDT: Holds Access and other information about + >?
the segment
physical address access fault
PAGING
• Logical Memory area can be bigger than the physical memory
• Logical memory can be accommodated in the secondary memory
• Divide physical memory into equal sized chunks called pages
• Any chunk of Virtual Memory assigned to any chuck of Physical Memory (“page”)
Memory

0:
Page Table 1:
Virtual Physical
Addresses 0: Addresses
1:

CPU

P-1:
N-1:

Address Translation: Hardware converts virtual addresses Additional storage

To physical addresses via an OS-managed lookup table (page table)
PAGE FAULTS
• What if an address is not in in memory?
• Page table entry indicates virtual address not in memory
• This is memory exception.
• OS exception handler invoked to move data from disk/or other secondary storage into memory
• current process suspends, others active process can be resume
• OS has full control over placement and mapping of pages etc.

Before fault Memory

After fault Memory
Page Table
Virtual Page Table
Physical
Addresses Addresses Virtual Physical
Addresses Addresses
CPU CPU

Disk
Disk
SERVICING A PAGE FAULT
• Processor Signals the I/O controller
• Which provide read block of length P starting at disk address X (1) Initiate Block Read
and store starting at memory address Y
Processor
• Read Occurs
Reg
• Direct Memory Access (DMA) (3) Read
• Under control of I/O controller Done
• I / O Controller Signals Completion
Cache
• Interrupt the processor
• OS resumes suspended process
Memory-I/O bus

I/O
Memory controller

(2) DMA
disk
Disk disk
Disk
Transfer
MANAGING MULTIPLE PROCESSES
• Each process has its own virtual address space
• operating system controls how virtual pages are assigned to physical memory
• A page table for each process
• every program can start at the same address (virtual address)!
• A process should not access pages not allocated to it.
Page Tables Memory
Read? Write? Physical Addr 0:
Protection: VP 0: Yes No PP 9 1:
Page table entry contains access rights Process i: VP 1: Yes Yes PP 4
information VP 2: No No XXXXXXX
• • •
• • •
• • •
Hardware enforces this protection
(trap into OS if violation occurs) Read? Write? Physical Addr
VP 0: Yes Yes PP 6
Process j: VP 1: Yes No PP 9 N-1:
VP 2: No No XXXXXXX
• • •
• • •
• • •
PAGE ADDRESS TRANSLATION

Address Translation via Page Table

page table base virtual address

register n–1 p p–1 0
VPN acts virtual page number (VPN) page offset
page offset as
table valid access physical page number (PPN)
page i base index

concatenate

page offset
if valid=0
then page
not in memory m–1 p p–1 0
physical page number (PPN) page offset

physical address
PAGE TABLE OPERATIONS
• Translation
• Separate (set of) page table(s) per process
• Virtual page number (VPN) forms index into page table (points to a page table entry)
• Computing Physical Address
Page Table Entry (PTE) provides information about page
• if (valid bit = 1) then the page is in memory.
• Use physical page number (PPN) to construct address
• if (valid bit = 0) then the page is on disk
• Page fault (Exception is raised)
• Must load page from disk into main memory before continuing

• Checking Protection
• Access rights field indicate allowable access
• e.g., read-only, read-write, execute-only
• typically support multiple protection modes (e.g., kernel vs. user)
• Protection violation fault occurs if process doesn’t have necessary permission to access a location which is
not allowed.
INTEGRATING VM AND CACHE
• Most Caches “Physically Addressed”
• Accessed by physical addresses VA PA miss
• Allows multiple processes to have blocks in cache at same time Trans- Main
CPU Cache
• Allows multiple processes to share pages lation Memory
• Cache doesn’t need to be concerned with protection issues hit
• Access rights checked as part of address translation data

• Perform Address Translation Before Cache Lookup

• But this could involve a memory access itself (of the PTE)
• Page table entries can also become cached
hit
VA PA miss
TLB Main
Translation Lookaside Buffer CPU Cache
Lookup Memory
• Translation Lookaside Buffer” (TLB)
• Small hardware cache in MMU miss hit
• Maps virtual page numbers to physical page numbers Trans-
• Contains complete page table entries for small number of pages lation
data
ADDRESS TRANSLATION WITH TLB
n–1 p p–1 0
virtual page number page offset virtual address

valid tag physical page number

TLB
. . .

TLB hit
physical address

tag index byte offset

valid tag data

Cache

cache hit data

MULTILEVEL PAGE TABLES
 Given: Level 2
 4KB (212) page size Tables
 32-bit address space
 4-byte PTE
 Problem:
 Would need a 4 MB page table. (difficult to manage in TLB)
Level 1
 220 *4 bytes
 Common solution Table
 Multi-level page tables
 e.g., 2-level table
 Level 1 table: 1024 entries, each of which points to a Level 2 page table.
 Level 2 table: 1024 entries, each of which points to a page
...
MEMORY MANAGEMENT UNIT IN ARM
• ARM MMU performs several tasks
• Translates virtual addresses into physical address
• Controls memory access permission
• Determines behavior of the cache and write buffer for each page in memory
• When MMU is disabled all virtual addresses map one-to-one to the same physical address
• MMU will only abort on translation, permission and domain faults
Configuration and Control Components of MMU
 Configuration and control components in the MMU are
 Page tables
 TLB
 Domains and access permission
 Caches and write buffer
 CP15:c1 control register
 Fast Context switch extension
Page Tables
• ARM MMU supports multilevel page table architecture
• Two levels L1 and L2
• Master L1 page table divides the 4GB space into 1 MB sections
• L2 page table can support 1 KB, 4KB or 64 KB pages (different processes can use different size pages depending
upon the way L2 page table is configured)
• CP15:c2 register holds the translation table base address – an address pointing to the
location of the master L1 table in virtual memory
TLB OPERATION
• TLB is a special cache of recently used page translations
• TLB maps a virtual page to an active page and stores control data restricting access to the page
• Some of the ARM architecture supports locking translations in TLB.
• Ex: ARM920T, ARM922T, ARM92EJ-S, ARM1022E, ARM1026EJ-S
• The page table which are very frequently accessed for them the entries in TLB will be locked.
31 12 11 0
logical address

hit

logical page phy sical page

number number

phy sical address

31 12 11 0
DOMAINS AND MEMORY ACCESS
• Domains control basic access to virtual memory by isolating one area of memory from another
• when sharing a common virtual map
• There are 16 different domains that can be assigned to 1 MB sections of virtual memory

Cache and Write Buffer

• Configure the caches and write buffer for each page in memory
• Indicates whether a page will be cached and whether write buffer for the page be enabled or not

Use of Virtual Memory System

• Example
• Implementation of a static multi-tasking system running concurrent tasks
• Tasks can have overlapping virtual memory map
• May be located in physical memory at addresses that do not overlap
• Configure domain access and permissions in the page table to protect the system
• Demand paging not necessarily implemented
MULTI-TASKING AND MMU
• During context switch different page table activated
• Virtual to physical mapping change
• To ensure cache coherency, Caches may need cleaning and flushing
• TLB also need flushing
• MMU can relocate the task without the need to move it
• To reduce time for context switch writethrough cache policy can be followed in ARM9
• Data cache configured as writethrough will not require cleaning of data cache

Demand Paging
• Use flash memory as non-volatile store
• Disks or file system implemented in flash memory in appliances like PDA’s etc.
• copy programs to RAM during system operation for faster access
• Under these conditions Dynamic Paging with loading pages on demand
• Adopt Write-back policy for the pages because access time to flash MCU MMU
is much more compared to RAM

Demand Paging with NAND-Flash OS OS

• Has got dense storage APP1 APP1
• Have fast burst mode access but its random mode access is APP2 STACK, HEAP
not that efficient. FILE SYSTEM
SDRAM
NAND
PAGE REPLACEMENT POLICY
• LRU (Least recently Used) is the most commonly used policy
• With Nand-flash a different policy
• Because write cost for an evicting page is higher
• Keep dirty pages as long as possible
• Evict least recently used clean(non-dirty) pages first and then dirty pages
SUMMARY
• We have studied different types of memory
• Examined Cache and Virtual memory organization
• We have understood functional role of MMU and Cache controller
THANK YOU