OBJECTIVE
Memory
Basic Static SRAM Cell
Multi Ported Memory
Dynamic RAM
Memory: Basic Understanding
CPU + main memory as a big array of bytes
address bus
CPU + memory controllers/chips + I/O controllers/devices
data bus
Read
CPU Write Memory
Ready
Basic Memory Subsystem
Size
CPU -Memory Interface:
unidirectional address bus
bidirectional data bus
read control line 16x8-bit memory array
write control line
0000
ready control line 0001
1 0 1 1 0 0 1 0
size (byte, word) control line 1 0 0 0 0 0 0 1
address 1-of-16
Memory access: a memory bus transaction
Nature of the bus transaction is defined by finite state machine decoder
1111 0 1 0 1 0 0 1 1
16x1-bit memory chip
Memory
Memories come in many shapes, sizes and types
RAM - random access memory
ROM - read only memory
EPROM, FLASH - electrically programmable read only memory
NOTE: ROM, EPROM and FLASH enables random access.
Any location in the memory can be accessed randomly not necessarily
Serially or sequentially.
Memory Types
DRAM: Dynamic Random Access Memory
Very dense (1 transistor per bit) and inexpensive
Requires refresh ( because of its structure ) and often not the fastest access times
SRAM: Static Random Access Memory
Fast and no refresh required
Not so dense and not so cheap
Often used for caches
ROM/Flash: Read Only Memory
often used for bootstrapping
Basic Static RAM Cell
Read:
6-Transistor SRAM Cell
1. Select row word
2. Cell pulls one line low and one high (row select)
0 1
3. Sense output on bit and bit
Write:
1. Drive bit lines (e.g, bit=1, bit=0)
2. Select row
3. Force flip flop to change state if it is required 0 1
Simplified SRAM timing diagram: Tells how the signal to be sent or received bit bit
Write Enable is active low signal, (High means Reading) Back-to-Back inverters form flip-flop
CS ( Chip select) is selecting the corresponding IC or the
memory module for the purpose of reading
Address is provided on the bus, decoder is the part
of the memory device itself for selecting the row
Read: Valid address, then Chip Select
Access Time: address good to data valid even if not
visible on out
Cycle Time: min between subsequent mem operations
Write: Valid address and data with WE_l, then CS Reading Writing
Address must be stable a setup time before WE and CS
go low and hold time after one goes high
SRAM Read Timing Parameters
stable stable stable
tAA Max(tAA, tACS)
ADDR
tOH
CS tACS
OE tAA tOZ tOE tOZ tOE
valid valid valid
DOUT
WE = HIGH OE : enabling 3-state o/p buffers
tAA (access time for address): how long it takes to get stable output after a change in address.
tACS (access time for chip select): how long it takes to get stable output after CS is asserted.
tOE (output enable time): how long it takes for the three-state output buffers to leave the
high-impedance state when OE and CS are both asserted.
tOZ (output-disable time): how long it takes for the three-state output buffers to enter high-impedance
state after OE or CS are negated.
tOH (output-hold time): how long the output data remains valid after a change to the address inputs.
SRAM Read Timing Parameters
Embedded SRAM
Features of Embedded SRAM
Low density and high speed
Preferred choice for frequently accessed, time-critical storage
Cache and register files
Power is a serious concern
Static power due to leakage
Dynamic power due to switching of long and heavily loaded bit
and word lines and sense amplifiers in read-out circuits
There are various technologies which minimizes the power consumption but not
sacrificing the speed.
Multi-ported Memory
Motivation:
Consider CPU core register file:
one read or write per cycle limits processor performance.
It also complicates pipelining. Difficult for different instructions deca decb cell
to simultaneously read or write register file/on-chip memory. array
Very common arrangement in pipelined CPUs is 2 read ports and
1 write port.
r/w logic
Dual Ported Memory Internals r/w logic
Add decoder, another set of read/write logic, bits lines, word
lines. address
Dual ported memories are very commons in SOCs and on-chip ports data ports
memory for various DSP processors.
WL2
Example cell: SRAM WL1
Cross-coupled inverter
Repeat everything but cross-coupled inverters.
This scheme extends up to a couple more ports, then need to
add additional transistors.
b2 b1 b1 b2
Dynamic RAM
SRAM cells exhibit high speed/poor density Word
DRAM: simple transistor/capacitor pairs in high density form Line
Charge can leak out from the capacitor.
Refreshing is required at regular intervals C
Bit
. Line
.
.
Sense
DRAM Organization Amp
d x w DRAM:
dw total bits organized as d supercells of size w bits 16 x 8 DRAM chip
Row Column organization cols
0 1 2 3
Each cell has row and column address
2 bits
CPU generates address which goes to memory controller /
0
Once memory controller receives the address it generates addr
1
row and column address separately to access the data rows
memory supercell
which is stored in a particular cell. 2
controller (2,1)
(to CPU)
8 bits 3
/
data
internal row buffer
Reading DRAM Super-cell (2,1)
Step 1: Row access strobe (RAS) selects row 2.
Step 2: Row 2 copied from DRAM array to row buffer.
Row as a whole gets copied.
16 x 8 DRAM chip
cols
0 1 2 3
RAS = 2
2
/ 0
addr
1
rows
memory
controller 2
8 3
/
data
internal row buffer
Reading DRAM Supercell (2,1)
• Step 3: Column access strobe (CAS) selects column 1.
• Address bus is multiplexed between row and column bus.
• Step 4: Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU.
16 x 8 DRAM chip
Refresh operation is a dummy read operation. cols
0 1 2 3
CAS = 1
2
/ 0
addr
To CPU
1
rows
memory
controller 2
supercell 3
8
(2,1) /
data
supercell
internal row buffer
(2,1)
Memory Organization
64 MB module consisting of 8 DRAMs
Of 8MB each.
Generate the address via particular row addr (row = i, col = j)
And column address, and all the cells
Gets selected. DRAM 0
Cells provide the bits and together it 64 MB
Constitutes 64 bit doubleword at main memory module
Memory address A. consisting of
DRAM 7
Then this will be send to the CPU. eight 8Mx8 DRAMs
bits bits bits bits bits bits bits bits
56-63 48-55 40-47 32-39 24-31 16-23 8-15 0-7
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
Memory
controller
64-bit doubleword at main memory address A
64-bit doubleword
DRAM Timing Parameters
tRAC: minimum time from RAS (Row access strobe) line falling to the valid data output.
Quoted as the speed of a DRAM when buy
A typical 4Mb DRAM tRAC = 60 ns
tRC: minimum time from the start of one row access to the start of the next.
tRC = 110 ns for a 4Mbit DRAM with a tRAC of 60 ns
tCAC: minimum time from CAS (Column access strobe) line falling to valid data output.
15 ns for a 4Mbit DRAM with a tRAC of 60 ns
tPC: minimum time from the start of one column access to the start of the next.
35 ns for a 4Mbit DRAM with a tRAC of 60 ns
Time taken for a data access for DRAM is more because row access and column access time
is to be given.
Enhanced DRAMs
All enhanced DRAMs are built around the conventional DRAM core.
Synchronous DRAM (SDRAM)
Driven with rising clock edge instead of asynchronous control signals.
SDRAM is tied to the system clock and is designed to be able to read or
write from memory in burst mode (after the initial read or write latency)
at 1 clock cycle per access (zero wait states)
Double data-rate synchronous DRAM (DDR SDRAM)
Enhancement of SDRAM that uses both clock edges as control signals.
Embedded DRAM
Provides high density storage
Up to 10 times larger than SRAM
Significantly slower than SRAM
Requires dedicated process for on chip fabrication
Not well compatible with standard CMOS technology for logic implementation
Non-Volatile Memory
Mask ROM
Used for dedicated functionality
One time programmable
Contents fixed at IC fab time (truly write once!)
EPROM (erasable programmable)
Requires special IC process (floating gate technology)
Writing is slower than RAM. EPROM uses special programming system to provide special voltages and timing.
Reading can be made fairly fast.
Rewriting is slow.
erasure is first required , EPROM - UV light exposure, EEPROM – electrically erasable
Flash is a variant of EPROM
Floating Gate MOS
Floating gate is surrounded by silicon dioxide ,
which is an excellent insulator.
By controlling the terminal voltage, it is possible
to charge electrically the floating gate.
EEPROM
Erased using higher than normal voltage
Can be erased by words and not in entirety
In circuit programmable
Read in tens of nanoseconds & Writes in tens of microseconds.
Flash Memory
Uses single transistor per bit
EEPROM employs two transistors
A flash memory provides high density storage with speed
marginally less than that of SRAM’s
Write time is significantly higher compared to DRAM
Electrically erasable
In system programmability and erasability (no special system or voltages needed)
On-chip circuitry and voltage generators to control erasure and programming (writing)
Erasure happens in variable sized "sectors" in a flash (16K - 64K Bytes)
Flash
Compact flash cards uses NAND flash NAND
Small chip size
Fast burst mode access
Micro-controllers usually use NOR flash
Fast random access
Embedded Non-volatile Storage
On-chip non-volatile storage is used for storage of
Configuration information
Executable code that runs on core processors NOR
Higher read-bandwidths and less pin-out requirements
Application specific tailoring of bit-width and memory size
Security of proprietary code
Recorded data : repeated write
Current FGMOS-based memories can withstand more than 106 rewrites
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