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Lec 7

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33 views8 pages

Lec 7

Uploaded by

irtaxa60
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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07-Oct-23

 There are three ways available to microprocessor


designers to increase the processing power of the CPU:
1. Increase the clock frequency of the chip
2. Use Harvard architecture by increasing the number of
buses to bring more information (code and data) into
the CPU to be processed
3. Change the internal architecture of the CPU and use
what is called RISC architecture.

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 RISC = Reduced Instruction Set Computer.


 CISC = Complex Instruction Set Computer.

 RISC has less instructions but apparently faster


execution and less complex microcode.
 CISC has more instructions increasing the complexity
of the microcode possibly slowing the speed.

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07-Oct-23

 Multiplying two numbers.


 CISC Approach
 MULT 2:3, 5:2

 RISC Approach
 LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A

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CISC RISC
Emphasis on hardware Emphasis on software

Includes multi-clock Single-clock,


complex instructions reduced instruction only

Memory-to-memory: Register to register:


Mostly "LOAD" and "STORE" "LOAD" and "STORE"
incorporated in instructions are independent instructions
Large code sizes
Small code sizes,
Low cycles per second,
high cycles per second

Transistors used for storing Spends more transistors


complex instructions on memory registers

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07-Oct-23

 The difference between CISC and RISC becomes evident


through the basic computer performance equation:

 RISC systems shorten execution time by reducing the clock


cycles per instruction (i.e. simple instructions take less time
to interpret)
 CISC systems shorten execution time by reducing the
number of instructions per program.
 Assignment: Go over all Review Questions on page 97 and
problems 72-77 on page103.
 True or False. Instructions such as “ADD R16,
ROMmemory” do not exist in RISC microcontrollers such as
the AVR.
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 Harvard architecture has separate data and


instruction busses, allowing transfers to be performed
simultaneously on both busses.
 A Von Neumann architecture has only one bus
which is used for both data transfers and instruction
fetches

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07-Oct-23

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 In the AVR, there are several ways to repeat an


operation many times.
Using BRNE instruction for looping
 The BRNE (branch if not equal) instruction uses the
zero flag in the status register.
 Conditional relative branch
 Tests the Zero flag (Z) and branches relatively to PC if
Z is cleared
 This instruction branches relatively to PC in either
direction (PC - 63 ≤ destination ≤ PC + 64)

BRNE k -64 ≤ k ≤ +63 PC ← PC + k + 1


PC ← PC + 1, if condition is false

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07-Oct-23

 The BRNE instruction is used as follows:


BACK: . . . . . . . . . ;start of the loop
......... ; body of the loop
......... ;body of the loop
DEC Rn ;decrement Rn, Z = 1 if Rn 0
BRNE BACK ;branch to BACK if Z ~ 0

Example 3.1 : Write a program to (a) clear R20, then (b) add 3 to R20 ten
times, and ( c) send the sum to PORTB. Use the zero flag and BRNE.

What is the maximum number of times that the loop in Example 3-1 can
be repeated?
0xFF = 255

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 The maximum count is 255. What happens if we want


to repeat an action more times than 255?
 To do that, we use a loop inside a loop, which is called a
nested loop.
 In a nested loop, we use two registers to hold the count.

 Example 3-3:Write a program to (a) load the PORTB


register with the value 0x55, and (b) complement
PORTB 700 times.

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07-Oct-23

 Looping 100,000 times


 Because two registers give us a maximum value of
65,025 (255 x 255 = 65,025), we can use three registers
to get up to more than 16 million (2 ) iterations.
 The following code repeats an action 100,000 times:

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 In this instruction, the Z flag is checked.


 If it is high, the CPU jumps to the target address.

 Notice that the TST instruction can be used to examine


a register and set the flags according to the contents of
the register without performing an arithmetic
instruction such as decrement.
 When the TST instruction executes, if the register
contains the zero value, the zero flag is set; otherwise,
it is cleared.
 It also sets the N flag high if the D7 bit of the register
is high, otherwise N = 0.

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07-Oct-23

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 Conditional relative branch.


 Tests the Carry flag (C) and branches relatively to PC
if C is cleared.
 This instruction branches relatively to PC in either
direction (PC - 63 ≤ destination ≤ PC + 64).
 The parameter k is the offset from PC and is
represented in two’s complement form.
Operation:
If C = 0 then PC ← PC + k + 1, else PC ← PC + 1
Syntax: Operands: Program Counter:
BRSH k -64 ≤ k ≤ +63 PC ← PC + k + 1
PC ← PC + 1, if condition is false

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07-Oct-23

Example3-5: Find the sum of the values 0x79, 0xF5, and 0xE2.
Put the sum into R20 (low byte) and R21 (high byte).
LDI R21, 0 ;clear high byte (R21 = 0)
LDI R20, 0 ;clear low byte (R20 = 0)
LDI Rl6, 0x79
ADD R20, R16 ;R20 = 0 + 0x79 = 0x79, C = 0
BRSH N1 ;if C = 0, add next number
INC R21 ;C = 1, increment (now high byte = 0)
N1: LDI Rl6, 0xF5
ADD R20, Rl6 ;R20 = 0x79 + 0xF5 = 0x6E and C = 1
BRSH N2 ;branch if C = 0
INC R21 ;C = 1, increment (now high byte = 1)
N2: LDI Rl6, 0xE2
ADD R20, Rl6 ;R20 = 0x6E + 0xE2 = 0x50 and C = 1
BRSH OVER ;branch if C = 0
INC R21 ;C = 1, increment (now high byte = 2)
OVER: ;now low byte = 0x50, and high byte 02

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 Answer Review Questions on page 118.


 Solve all 16 problems of Sections 1, pages 136-137

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