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CMOS Mixed-Signal Circuit Design, First Edition

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 Chapter

30
Data Converter Modeling

In this chapter we continue our discussion of data converters by discussing methods to

model ideal data converters and their components using SPICE. The main goal of this
chapter is to provide tools for evaluating mixed-signal designs with large complexity,
which can be used later in the book. In particular, we will generate SPICE models, using
behavioral elements, for ideal analog-to-digital converters (ADCs) and digital-to-analog
converters (DACs) blocks. This allows us to analyze the performance of a mixed-signal
circuit block in a SPICE simulation within a reasonable amount of time. For example, if
we have designed a DAC at the transistor level and want to use SPICE to simulate its
operation, under various temperatures and matching conditions, we may apply a digital
input code generated from our ideal ADC with a sinewave input as seen in Fig. 30.1.
Similarly, given a digital signal processing (DSP) system, we can drop our ideal DAC into
the simulation at any point where there is a digital word and get an analog waveform
output.

SPICE behavioral model SPICE transistor-level model

of an ideal ADC of a DAC

In N-bits DAC Out

Ideal
ADC under
test
Digital code corresponding
to the sinewave input
Clock, f s

Figure 30.1 Generating the sinewave digital code for DAC simulation with an ideal ADC.
2 CMOS Mixed-Signal Circuit Design

Also, in this chapter we look at how the analog-to-digital and digital-to-analog

conversion process affects the signals in the system. Figure 30.2 shows the basic
conversion process. We will make extensive use of the spectral analysis capability (discrete
fourier transform or DFT) available in SPICE to look at the digital data (and analog
signals) in the frequency domain.

v Analog Digital v v
v 111
101
011
t 000
t t t
t
Anti-aliasing filter
In AAF S/H ADC DSP DAC RCF Out

Sample and hold Smoothing or

reconstruction filter

Figure 30.2 Signals resulting from A/D and D/A conversion in a mixed-signal system.

30.1 Sampling and Aliasing: A Modeling Approach

In this section we discuss how sampling a signal changes the signal's spectrum. We also
discuss how to model the sampling process in SPICE.
30.1.1 Impulse Sampling
Consider the simple sampling gate shown in Fig. 30.3a. Let's assume we apply a sinewave
input, x(t) , to this sampling gate of the form, V p sin (2πf in ⋅ t) (for the moment, a single
frequency input). The output of the sampling gate (a.k.a. sampler), y(t) , is the product of
the input and a sampling unit impulse signal or
∞
y(t) = Σ V p sin (2πf in ⋅ nT s ) ⋅ δ u (t − nTs )
n = −∞
(30.1)

v x(t) = Vp sin (2πf in ⋅ t)

v
t
In Sampler output
In t

Sampler output
1
t y(t) = x(t) ⋅ δ u (t − nT s ) Sampling impluses
Sampling impluses
(b)
δ u (t − nT s ) (a)

Figure 30.3 (a) Simple sampling gate and (b) SPICE implementation of a sampling gate.
Chapter 30 Data Converter Modeling 3

Noting that the frequency of the input is fin while the sampling frequency is f s (= 1/T s ) , the
spectrum of the input signal is seen in Fig. 30.4a. If we take the Fourier transform of the
input signal after sampling, that is, we look at the spectrum on the output of the sampler,
we get
Vp ∞
T s k =Σ− ∞
Y( f ) = ⋅ [δ( f − f in + kf s ) + δ( f + f in + kf s )] (30.2)

This is the familiar result that a sampled spectrum is repeated, at intervals of f s , as seen in
Fig. 30.4b (shown is the one-sided spectrum, which is what we will use throughout the
book). Note that if an ideal lowpass filter (LPF) is applied to the output spectrum of the
sampler (the output of the sampler is connected to an LPF) with a bandwidth greater than
f in (and lower than f n [the Nyquist frequency]), then the higher order frequency
components can be removed so that only f in remains (this is our smoothing or
reconstruction filter shown in Fig. 30.2).

Y( f ) (2 f s − f in )
fs
Volts fn = Volts
2 Vp fn fs 2 fs
Vp
Ts

f in f f in f
(a) Input spectrum (f s − f in ) (f s + f in ) (2f s + f in )
(b) Output spectrum after sampling
Figure 30.4 One-sided spectrum of a sinewave (a) before and (b) after sampling.

Example 30.1
A sampling gate is strobed with an impulse train running at a frequency of 100
MHz ( f s = 100 MHz and the time in between the impulses, Ts, is 10 ns). Sketch
the resulting output frequency spectrum if a 60 MHz sinewave is applied to the
sampler. Also, sketch the time domain input and output of the sampler.
The resulting frequency spectrum is shown in Fig. 30.5. Notice how connecting
the output of the sampler through an LPF, with an ideal abrupt cutoff frequency of
f n , results in an output sinewave with a frequency of 40 MHz. In order to avoid
this situation, that is, to avoid ending up with the wrong, or alias, signal after
sampling and reconstructing, we need to ensure that the signal frequencies applied
to the sampler are less than f s /2 (the Nyquist frequency, again, f n ). Reviewing
Fig. 30.2, we see that this is the purpose of the antialiasing filter (AAF). Notice
how, ideally, both the AAF and RCF (reconstruction filter) in Fig. 30.2 are both
ideal LPFs with a cutoff frequency equal to half the sample frequency (the Nyquist
frequency). Figure 30.6 shows the time domain sketch of the sampler's output. T
4 CMOS Mixed-Signal Circuit Design

f s − f in Original signal, f in f s + f in

Aliased signal 40 60 140 160 240 MHz f

50 100 150 200 250
fn fs 2 fs

Figure 30.5 Spectrum of a 60 MHz sinewave sampled at 100 MHz.

It should be clear from the preceding discussion that (1) sampling a signal results
in a reproduction of the sampled signal's spectrum at DC, fs , 2fs , 3fs , etc., (2) the input
signal's spectrum should have no significant spectral content above fn in order to avoid
aliasing, (3) to avoid aliasing both filtering the input signal using an AAF and increasing
the sampling frequency should be used, and (4) to reproduce the sampled signal from the
output of the sampler (which is nonzero only during the sampling impulse times) a
lowpass RCF should be used.
Note that our discussion illustrates the operation of a sampling gate driven with
impulse signals. As shown in Fig. 30.2, a practical system would have other building
blocks. We would rarely, if ever, sample a signal and then reconstruct it without
processing it first.

Input, 60 MHz Sampler outputs Alias 40 MHz sinewave

25 ns 50 ns 75 ns 100 ns

Figure 30.6 Time domain input and output for Ex. 30.1.

A Note Concerning the AAF and the RCF

Before going any further, we should discuss the ideal characteristics of the AAF and the
RCF. The ideal characteristics of these filters are shown in Fig. 30.7. Note that both of
Chapter 30 Data Converter Modeling 5

these filters must be analog by design. The ideal cutoff frequency for the filters is fn
(assuming the sampling rate on the input of the system is the same as the sampling rate on
the system's output) and the filters should ideally have linear phase. Let's discuss these two
ideal characteristics.
The ideal magnitude response, shown in Fig. 30.7a, passes all spectral content
below the Nyquist frequency while removing all signals above this frequency. The ideal
phase response, shown in Fig. 30.7b, provides a constant delay, to , to all signals below fn.
In other words, the filters remove all unwanted signals while not distorting the wanted
signals.

= 1 for AAF ∠H(jω)

H(jω) = 1/f s for RCF f n = f s /2
0
f

slope = −2πt o

f n = f s /2 f
(a) (b)

Figure 30.7 (a) Ideal magnitude and (b) phase responses for the AAF and RCF.

Example 30.2
Discuss why the ideal AAF filter will not introduce distortion into the desired
portion of an input signal.
If our input signal is called v in (t) and the desired spectral content of this signal
after filtering is called v in (t) (that is, v in (t) contains nonzero spectral content only
at frequencies below f n ), then the output of the AAF, v out (t) , will be a time-shifted
(with a constant delay of to ) and filtered version of the input, as seen in Fig. 30.8.
Note that linear phase is equivalent to saying "constant delay." If our input signal
is already bandlimited to f n , then the output of the AAF is simply a time-shifted
version of the input. T

In Out
v in (t) v out (t) = v in (t − t o )
AAF
In Out v in (t) v out (t)
0 to t

Figure 30.8 Results for Ex. 30.2.

6 CMOS Mixed-Signal Circuit Design

Example 30.3
Suppose that the circuit, shown in Fig. 30.9, is used as an AAF filter in a data
conversion system. If the inputs to the system are two sinewaves with frequencies
of 4 MHz and 40 MHz determine whether the waveforms coming out of the AAF
will be distorted. Using SPICE show the input and output signals of the AAF.

v in (t) 320 v out (t) 0 dB

5 MHz 50 MHz

v out (t) 20 dB/decade

10 pF
v in (t)

v out (t)
∠
v in (t) 0
45
500 MHz
90

Figure 30.9 AAF filter for Ex. 30.3.

The amplitude response of the simple RC filter is given by

v out 1
v in = 2
1 + (2π ⋅ RC ⋅ f )

The 4 MHz input doesn't see any attenuation. The gain, or amplitude response, of
the filter at 4 MHz is unity (0 dB). The filter attenuates the 40 MHz input by 0.779
(−2.17 dB).
The phase response of the simple RC filter is given, in degrees by
∠v out /v in = θ(f ) = −tan −1 (2π ⋅ RC ⋅ f )
The phase shift through the filter at 4 MHz is approximately zero (the 4 MHz input
doesn't see any delay while passing through the filter). This is the ideal phase
response of this filter, i.e., to = 0. Looking at Fig. 30.9 we can conclude that only
at frequencies below approximately 5 MHz will the filter not exhibit phase
distortion. The phase shift through the filter at 40 MHz is −39° (the negative sign
indicates that the output is lagging the input or, in other words, occurs later in time
than the corresponding point on the input). Since phase is related to delay by
% of period, T

to
θ(f ) = ⋅ 360 = t o ⋅ f ⋅ 360
T
Chapter 30 Data Converter Modeling 7

the delay the 40 MHz sinewave sees passing through the filter is 2.7 ns. The
SPICE simulation results are shown in Fig. 30.10 assuming each sinewave input is
centered at ground and has an amplitude of 1V.
Also note that this filter does a poor job attenuating frequencies above 50
MHz. For example, the attenuation at 500 MHz (one decade above 50 MHz) is
only −20 dB (0.1). It can be concluded that unless f s /2 (the Nyquist frequency) is
much larger than the cutoff frequency of the simple RC LPF aliasing will (possibly)
still occur in significant amounts. In fact, we could argue that because of the
inherent noise present in any electronic circuit, aliasing will always occur when
sampling a signal (the wideband noise gets aliased down into the base spectrum
[the spectrum below the Nyquist frequency]). The question then becomes, "How
much aliasing is OK?" T

Input

Figure 30.10 SPICE simulation results for Ex. 30.3.

Example 30.4
Determine the transfer function of the filter made with a 5 ns long (= to) ideal
transmission line shown in Fig. 30.11. Simulate the filter's frequency and phase
response using SPICE. This filter is called a continuous-time comb filter.
In this analysis, we assume that 500-ohm resistors do not load the input or output
of the delay line so that
v in + v in ⋅ e j⋅2π f⋅(−t o )
v out =
2
8 CMOS Mixed-Signal Circuit Design

v in e j2πf (−to )
v in Z o = 50 Ω t o = 5 ns

50 500
v out
500
v in

Figure 30.11 A continuous-time comb filter.

The transfer function can be written as

 Real Imaginary

v out 1
= ( + j⋅2πf⋅(−t o )
) = 1  + ⋅ (−t ) + ⋅ ⋅ (−t ) 
v in 2 1 e  1 cos 2πf o j sin 2πf o 
2 
 
The magnitude response of this filter is
v out 1 1
v in = 2 (1 + cos 2πf ⋅ (−t o )) + (sin 2πf ⋅ (−t o )) = 2 2(1 + cos 2πf ⋅ t o )
2 2

The phase response of this filter is given by

v  sin 2πf ⋅ (−t o ) 
∠ vout = tan −1  
in  1 + cos 2πf ⋅ (−t o ) 
Notice at f = 1/(2t o ) the phase is tan −1 (0/0) , which evaluates to ± 90 . Using

cos 2 x = 1 + cos 2x and sin 2x = 2 sin x cos x

2
the phase response is given by
v
∠ vout = π(−t o ) ⋅ f for f < 1/(2t o )
in

Notice that the phase response of this filter is linear. The SPICE simulation results,
plotted on a linear frequency scale, are shown in Fig. 30.12. The reason this filter
is called a "comb filter" should be obvious (the response looks like a comb). Notice
how the delay line length is related to the points where the magnitude response
goes to zero. Also note that this filter could be useful to isolate channels in a
communication system and easily implemented on a PC board using a microstrip
transmission line. The SPICE netlist that generated this figure is given below.
* Figure 30.12 CMOS: Circuit Design for Mixed-Signal Systems *
.AC LIN 1000 1MEG 1000MEG
Vin Vin 0 DC 0 AC 1
Rtout Vtout 0 50
Rt1 Vtout Vout 500
Rt2 Vin Vout 500
Chapter 30 Data Converter Modeling 9

T1 Vin 0 Vtout 0 ZO=50 TD=5n

.end

Finally, before leaving this example, consider the dB (magnitude) and phase
responses of this filter on a log frequency plot, Fig. 30.13. It would appear that the
magnitude of the transfer function at 100 MHz, 300 MHz, 500 MHz, etc., is
nonzero. However, as the equation for the magnitude response shows, this isn't the
case. At these frequencies v out /v in is zero indicating, in the plots shown in Fig.
30.13, that the lower limit is set by step size (number of points per decade) used in
AC SPICE simulation. Increasing the number from 1,000, which is what was used
to generate Fig. 30.13 to, say, 10,000 will give more accurate results. T

100 MHz

Figure 30.12 SPICE simulation results for the comb filter of Ex. 30.4.

Time Domain Description of Reconstruction

In this section we show why the filter shown in Fig. 30.7, an ideal brick wall lowpass filter
with linear phase response, is the ideal RCF on the output of our impulse sampler. Shown
in Fig. 30.14 is a 20 MHz sinewave sampled at 100 MHz. Suppose we want to reconstruct
the original input 20 MHz sinewave from the sampler output (the weighted impulse
functions). After reconstruction the output of the RCF should be a single-tone, 20 MHz
sinewave (it should be an exact replica of the sampler input). To determine what happens
when the output of our sampler is applied to the ideal RCF, we need to determine the time
domain response of the filter when the filter's input signal is the Dirac delta function, δ(t)
(δ(0) = ∞, else δ(t) = 0) .
10 CMOS Mixed-Signal Circuit Design

Figure 30.13 SPICE simulation results, in dB, for the comb filter of Ex. 30.4.

We know the transfer function of a system is the Fourier transform of the system's
time domain impulse response (what we are trying to find here). In other words, to
determine the transfer function of the system, we apply the unit impulse to the input of the
system (a very large amplitude, very short time duration pulse, see Fig. 30.15). We then
look at the system's output in the time domain followed by taking the Fourier transform of
this output to get the system's transfer function. Therefore (in the reverse order), to
determine the time domain response of the ideal RCF, given the transfer function, we take

Sampler input, 20 MHz

Sampler outputs Ts = 1
fs

10 ns 30 ns 50 ns 70 ns 90 ns

Figure 30.14 Impulse sampling, at 100 MHz, a sinewave at 20 MHz.

Chapter 30 Data Converter Modeling 11

Impulse Ideal RCF 1

1
input to 1/f s
RCF time t time
0 t=0
fn f

Figure 30.15 Time domain impulse response of the ideal RCF.

the inverse Fourier transform of the transfer function. The ideal RCF's transfer function
(Fig. 30.7) can be defined by
H( f ) = 1/f s for f < f n else H( f ) = 0 (30.3)
The time domain response is then given, remembering 2f n = f s , by
fn
1 ⋅ e j⋅2π⋅f⋅t ⋅ df = e j⋅2π⋅f n ⋅t − e −j⋅2π⋅f n ⋅t =
h(t) = ∫ fs j ⋅ 2π ⋅ f s ⋅ t
(30.4a)
−f n

sin 2πf n ⋅ t sin πf s ⋅ t

= = Sinc(πf s ⋅ t) (30.4b)
πf s ⋅ t πf s ⋅ t
where
sin x ≡ Sinc(x) (30.5)
x
The time-domain response of our ideal RCF is shown in Fig. 30.16. Notice that our
impulse is applied to the system's input at t = 0 and that the output actually anticipates, or
starts, before the application of the input! This indicates that the filter is noncausal and
can't be built in a practical analog circuit. Before we discuss the implications of this severe
limitation (an ideal reconstruction filter can't actually be built), consider Fig. 30.17. Figure

sin πf s ⋅ t
= Sinc(πf s ⋅ t)
πf s ⋅ t
H(jω)
1
1 0.64 = −3. 9 dB
fs

0.13
f n = f s /2 f t
0
−3T s −2T s − T s Ts 2T s 3T s

(a) Ts
(b) 0.21 = −13.5 dB
2

Figure 30.16 (a) Ideal RCF frequency response and (b) impulse response (time).
12 CMOS Mixed-Signal Circuit Design

30.17 shows the individual response outputs of an ideal RCF with the impulse train of Fig.
30.14 as the input. The output of the RCF is the weighted sum of the individual responses,
of the form Sinc(x), from each of the weighted impulse inputs into the RCF (using
superposition). While this figure is "busy," the basic concept of reconstruction should be
obvious.

Output of the RCF

time

Figure 30.17 Reconstructing the 20 MHz sinewave of Fig. 30.14.

Practically, we can't make an ideal reconstruction filter, which is a requirement for

reconstructing a waveform consisting of frequency components between DC (0) and f n .
For example, sampling a 49 MHz sinewave at 100 MHz (essentially two samples per
cycle) would require, for reconstruction, a filter with characteristics close to the ideal RCF
in order to get a signal resembling the 49 MHz input out of the system. What can we do to
ease the requirements on the RCF? Here are two possibilities:
1. Increase the sampling rate. fs. If we were to sample the 49 MHz sinewave
mentioned above at 500 MHz, we would then have roughly ten samples per cycle. The
RCF used on the output of the system can then have a slower roll-off rate. At the extreme
end, taking f s → ∞ , eliminates the need for any RCF.
2. After sampling has taken place and using a DSP, add additional points in
between the sampling times. This effectively increases the sampling rate coming out of the
system. This increase in the effective sampling frequency is known as interpolation
because the values of the additional points are determined by interpolating between the
existing data points. The increase in the effective output sampling rate eases the
requirements placed on the RCF.
SPICE Modeling the Impulse Sampler
The SPICE model of the impulse sampling gate was shown in Fig. 30.3. A voltage-
controlled switch was used to connect the input signal to the sampler's output for very
brief periods of time. In order to make the sampler more ideal, that is, with infinite input
Chapter 30 Data Converter Modeling 13

resistance, zero output resistance, etc., the SPICE model shown in Fig. 30.18 will be used.
Voltage-controlled voltage sources, with the E prefix, are used to model the ideal
operational amplifiers. The switch is modeled with a voltage-controlled switch, an S
device. The model is used in the following netlist:
* Figure 30.19 CMOS: Mixed-Signal Circuit Design *
.tran .1n 500n 0 .1n UIC
Vin Vin 0 DC 0 Sin 0.75 0.75 5MEG
Vclock Clock 0 DC 0 Pulse 0 1.5 0 0 0 100p 10n
Vtrip Vtrip 0 DC .75
Ebufin Vinb 0 Vin Vinb 100MEG
S1 Vinb Vins CLOCK VTRIP switmod
Rout Vins 0 10k
Ebufout Vout 0 Vins Vout 100MEG
.model switmod SW
.end

In this netlist, a 1.5 V, peak-to-peak, 5 MHz sinewave centered at 0.75 V is

sampled at 100 MHz. The impulses are generated using the pulse statement with zeroes
for both rise and fall times. In the simulation, the actual rise and fall times will be limited
by the transient simulation step time (which is set at a maximum of 100 ps using the .tran
statement in the netlist above). The impulses have logic amplitude levels of 1.5 V. The
switch's trip point is set at 0.75 V so that when the impulse goes above 0.75 V, the switch
is closed. Because the impulse is at 1.5 V for only 100 ps, and the input is slow in relation
to this time, the netlist approximates an ideal impulse sampling circuit. Running the netlist
above results in Fig. 30.19.

v out

v in
Sampling impluses Vout

Vins Ebufout
0

Figure 30.18 SPICE model of the ideal impulse sampler.

Using SPICE for Spectral Analysis (Looking at the Spectrum of a Signal)

Figure 30.19 shows the sampled output of our impulse sampler, in the time domain. It is
very useful, as we've already seen, to be able to look at these data in the frequency
domain. SPICE (actually Nutmeg) has the feature that it can take the discrete Fourier
transform (DFT) of a time domain signal. Performing a DFT consists of (1) windowing the
14 CMOS Mixed-Signal Circuit Design

Figure 30.19 Impulse sampling a 5 MHz sinewave at 100 MHz.

time domain signal (we will use the Hanning window [a.k.a. von Hann window] unless
otherwise indicated), (2) sampling the signal, and (3) taking the Fourier transform of the
signal. Windowing ensures that abrupt transitions do not occur at the beginning and end of
the signal to be transformed. It's important to realize that taking the DFT of a signal that
has already been sampled results in a spectrum with amplitude errors (more on this in a
moment.) To perform a DFT in SPICE we first ensure that the signal to be transformed
has a linear time step. To do this we use
linearize Vout Vin

where Vout and Vin are the signals we are interested in transforming. The linearize
command with no arguments will linearize all of the variables available in the simulation.
Next, we use the spec command (spectral analysis command) in SPICE
spec 0 200MEG 2MEG Vout Vin

This command takes the DFT of Vout and Vin over the range of DC to 200 MHz with a
resolution of 2 MHz. The minimum resolution allowed when using the spec command
(DFT) is set by the transient simulation time, or

DFT resolution ≥ 1 (30.6)

simulation time
If we simulate a circuit for 500 ns, then our minimum resolution is 2 MHz. We can look at
the spectrum of a signal using the following list of commands:
Chapter 30 Data Converter Modeling 15

linearize Vout Vin

spec 0 200MEG 2MEG Vout Vin
* Set noise floor at 120dB by adding 1uV
let voutdb=db(Vout+1e-6)
let vindb=db(Vin+1e-6)
plot voutdb
plot vindb

The spectrums, as an example, on the input and output of an impulse sampler sampling a
10 MHz sinewave at 100 MHz are shown in Fig. 30.20. Note that 1 µV was added to
both signals so as to set the noise floor in the display to −120 dB. The DC portion of the
input signal is 0.75 V while the peak voltage of the 10 MHz sinewave is also 0.75 V (0.75
V = −2.5 dB). Note that in Fig. 30.20b, because of the double sampling mentioned above,
the amplitude of the signals in the output is different than that predicted (see Fig. 30.4).
We can estimate the baseline reduction, resulting from taking the DFT of an impulse
sampled signal (the signal has nonzero values only during the sampling times) using
2 ⋅ (step size)
Baseline reduction (or duty cycle) ≈ (30.7)
Ts
For Fig. 30.20b the maximum stepsize specified in the transient simulation was 100 ps (for
each cycle of Ts one point is defined as having a total deviation, after being linearized, of
approximately 200 ps including rise and fall times, hence the factor of 2 in Eq. (30.7). The
baseline, using Eq. (30.7), is 200 ps/10 ns or 0.02 (−34 dB). The 10 MHz signal in Fig.
30.20b is −2.5 dB below the −34 dB baseline. Note how the DC signal is aliased up to the
sampling frequency (100 MHz). At DC, with reference to the baseline, the signal
amplitude is also −2.5 dB (−36.5 dB). However, when it is aliased up to the 100 MHz (the
sampling frequency) it is doubled (+6 dB). The doubling comes from adding the images
f s + 0 and f s − 0 and results in an amplitude of −36.5 dB + 6 dB or −30.5 dB.
The step size used in a transient simulation, as we saw above, is an important
parameter that needs specification when performing a spectral analysis using SPICE. In
the netlist that generates Figs. 30.19 and 30.20, we used 100 ps, but made no comment on
why this value was selected. Poor selection of the step sizes can give erroneous results if
the values are too large or cause the simulation to last a long time if the values are too
small. The transient simulation characteristics in a SPICE netlist are specified using
.tran print-step stop-time delay-time maximum-stepsize <UIC>

The step size, for a general simulation with nonideal components, can be set using
step size = 1 % ⋅ T s or with ideal components 10% ⋅ T s (30.8)
If our sample frequency, fs , is 100 MHz then we would set our step size to 100 ps using
.tran 100p 2000u 0 100p UIC

The term UIC forces the simulation to start with initial conditions (use initial conditions),
such as an initial voltage across a capacitor. The simulation always starts at zero time.
However, specifying a delay time in the simulation will make SPICE start saving data at
16 CMOS Mixed-Signal Circuit Design

2.5 dB (0.75V)
2.5 dB (0.75V) below baseline or 36.5 dB
−30.5 dB

−34 dB

Nyquist frequency 90 MHz 110 MHz

Volts

Volts

10 MHz
10 MHz Input to the sampler Output of the sampler
(a) (b)
Figure 30.20 Spectrums of the signals shown in Fig. 30.19.

the time specified by the delay-time parameter. This parameter is useful in removing, from
a spectral response, for example, the start-up transients in a simulation or keeping the size
of a raw output file from getting too large.
Representing the Impulse Sampler's Output in the z-Domain
Consider the output of an impulse sampler, y(t) , with an input of x(t) shown in Fig. 30.21.
The sampler output can be written as
∞
y(t) = x(t) ⋅ Σ δ u (t − kTs )
k = −∞
(30.9)

y(t) Ts

Ts time

Figure 30.21 Output of an impulse sampler.

Chapter 30 Data Converter Modeling 17

We can rewrite Eq. (30.9) as

y(t) = x(t)[... + δ u (t + T s ) + δ u (0) + δ u (t − T s ) + δ u (t − 2T s ) + δ u (t − 3T s ) + ...]
(30.10)
Taking the Fourier transform of this equation results in

Y( f ) = ... + x(−1)e (1)⋅j2π⋅f⋅Ts + x(0)e (0)⋅j2π⋅f⋅Ts + x(1)e (−1)⋅j2π⋅f⋅T s + x(2)e (−2)⋅j2π⋅f⋅T s + ...
(30.11)
where the term e j2π⋅f⋅T s corresponds to a phase shift of 2π ⋅ f ⋅ T s (radians) when the output
of the sampler, Y( f ) , is evaluated at the frequency f. In other words, each consecutive
sample coming out of the impulse sampler is shifted in the time domain by Ts (which is
simply saying, in words, what Fig. 30.21 shows). If we define
f
j2π⋅ f
z ≡ e j2π⋅f⋅T s = e s (30.12)
then the output of our sampler can be written as
Y(z) = ... + x(−1)z 1 + x(0)z 0 + x(1)z −1 + x(2)z −2 + ... (30.13)
or
∞
Y(z) = Σ x(k) ⋅ z −k
k = −∞
(30.14)

Example 30.5
Determine the output of an impulse sampler in the z-domain if its input, x(t), is a
unit step. What is the sampler's impulse response H(z) [= Y(z)/X(z)] ?
The unit step, u(t), is defined by
u(t) = 1 for t ≥ 0
u(t) = 0 for t < 0
The time domain output of the sampler, with u(t) as an input, is given by
∞
y(t) = Σ u(t − kT s)
k=0

or looking at the output in the z-domain

∞
Y(z) = Σ z −k
k=0

The time domain signals used in this example are shown in Fig. 30.22. The
sampler's impulse response is simply unity since the z-transform of the input
(assuming the input was passed through an ideal impulse sampler so that we can
take the z-transform of the signal) and output of the sampler are identical, that is,
H(z) = 1 . T
18 CMOS Mixed-Signal Circuit Design

Ts
Sampler output
Ideal impulse 1
In sampler Out 0
1 Sampler input
f s Sampling 0
clock time

Figure 30.22 Sampling the unit step with an impulse sampler.

Example 30.6
What is the effect of multiplying H(z), in Ex. 30.5 (or any z-domain transfer
function), by z−1?
Multiplying any z-domain transfer function by z−1 is equivalent to shifting the
system's output later in time by Ts. The result of changing the ideal sampler's
transfer function from unity to z−1 is shown in Fig. 30.23. Multiplying by z−L shifts
the output of the system later in time by L ⋅ T s T

Ts
Sampler output
Out 1
Ideal impulse z −1
In sampler 0
1 Sampler input
f s Sampling 0
clock time

Figure 30.23 Mulitplying the output of the ideal sampler by z −1 .

An Important Note
It's important to note that our impulse sampler quantizes1 the input signal in time but not
amplitude (unlike an analog-to-digital converter which quantizes the input in both time and
amplitude). The amplitude out of the ideal impulse sampler is exactly the same as the
amplitude input to sampler at the sampling impulse time. We'll find that the z-transform
can be used to describe systems using both quantization in time as well as in amplitude. In
other words, whether we are discussing digital words, in a binary format or
sampled-analog waveforms with amplitudes of volts, amps, or coulombs, we can use the
z-transform to represent the discrete-time systems that process the signals.

1
Quantize: to limit the possible values of a quantity to a discrete set of values. Quantizing in time,
for example, means that the output amplitude is only defined at certain discrete times (such as the
sampling impulse times for the ideal impulse sampler) or that the amplitude is unchanging during
certain discrete time intervals (such as seen in the output of the ideal sample-and-hold discussed in
the next section).
Chapter 30 Data Converter Modeling 19

30.1.2 The Sample and Hold

Understanding the operation of the impulse sampler of Sec. 30.1.1 is important in
understanding the concepts of aliasing and reconstruction. However, as seen in Fig. 30.2,
most mixed-signal systems employ a sample and hold (S/H) rather than an impulse sampler
so that the sampled waveform is available at times other than the sampling impulse times.
Having the samples "held" in between the sampling impulse times is important for proper
ADC operation. The disadvantage of using the S/H, as we shall shortly see, is that it will
introduce distortion into our signal.
SPICE Modeling the Sample and Hold
The block diagram of the SPICE model, for the ideal S/H, is shown in Fig. 30.24. The
inputs are Clock and Vin , while the output is labeled Vout. A SPICE netlist, using the ideal
S/H, is shown below in which an 8 MHz sinewave is sampled at 100 MHz. The simulation
results, using this netlist, are shown in Fig. 30.25.
* Figure 30.25 CMOS: Mixed-Signal Circuit Design *
.tran .1n 500n .1n UIC
Vin Vin 0 DC 0 Sin 0.75 0.75 8MEG
Vclock Clock 0 DC 0 Pulse 0 1.5 0 0 0 4.9n 10n
Vtrip Vtrip 0 DC .75
VDD VDD 0 DC 1.5
Ein Vinbuf 0 Vin Vinbuf 100MEG

S1 Vinbuf VinS VTRIP CLOCK switmod

Cs1 VinS 0 1e-10
S2 VinS Vout1 CLOCK VTRIP switmod
Cout1 Vout1 0 1e-16

Eout Vout 0 Vout1 Vout 100MEG

.model switmod SW
.end

The switches S1 and S2 in the netlist above sample the input using the input clock. Note
that both switches can be closed, momentarily in Fig. 30.24, at the same time. The time

V out
V inbuf V ins V out1
V in
1e-16
Clock
Clock 1e-10

Figure 30.24 SPICE model of the ideal sample and hold (S/H).
20 CMOS Mixed-Signal Circuit Design

Figure 30.25 Ideal S/H with an 8 MHz input.

that the switches are closed is approximately equal to the transient step time. The charge
sharing between the capacitors is affected by having both switches closed at the same
time. Values given in this figure were selected so that a million-to-one ratio existed
between the two capacitors (120 dB range.) Because both switches are closed at the same
time, the difference between the two capacitors can be made smaller without affecting the
circuit's operation. Also note that over a time set by GMIN (remember a resistor with a
value of 1/GMIN is placed across every pn-junction in a SPICE simulation and GMIN's
default value is 1e-12 or 1 GΩ) and the capacitor values the charge on the capacitors will
leak off causing droop. For the 0.1f capacitor the associated RC time because of GMIN is
100 µs (increasing this capacitor to 10f won't affect the sampling operation and pushes the
RC time up to 10 ms).
The accuracy of the S/H is ultimately limited by the tolerances, that is, RELTOL,
ABSTOL, and VNTOL of the simulation. For an accurate simulation we may add
.options RELTOL=1u VNTOL=1u ABSTOL=1p

to the netlist. The accuracy of a simulation will be discussed in greater detail later.
S/H Spectral Response
Consider the application of a sinewave, at a frequency fin , to the ideal S/H shown in Fig.
30.26. To make the discussion as general as possible assume that the output of the S/H
can return-to-zero (RZ) as shown in Fig. 30.27 (which shows coarse time quantization for
Chapter 30 Data Converter Modeling 21

v in
f in
time
time
In Sample and Out
hold (S/H) y(t)

clock

Figure 30.26 Sampling and holding an input sinewave.

a simpler figure and illustration of the concept of RZ). Note that as T approaches Ts we
get the operation of the S/H in Fig. 30.26. The output of the ideal S/H is given by
v in (t)
 ∞
h(t)

y(t) = Σ  V p sin (2πf in ⋅ nT s ) ⋅ [u(t − nT) − u(t − (n + 1)T )]  (30.15)

n=−∞  
 
Note that the sine term is only defined at discrete sampling instances so that its spectrum
is given by Eq. (30.2). The spectrum of the sampling pulse, H( f ) , because of the duality
of the Fourier transform, is given by reviewing Fig. 30.16 or calculated using
Ts
Fourier[u(t − nT) − u(t − (n + 1)T] = ∫0 [u(t − nT) − u(t − (n + 1)T]e −j⋅2π⋅f⋅t ⋅ dt (30.16)

which is evaluated as
phase magnitude
−j⋅2π⋅f⋅T
H( f ) = e − 1 = e −j⋅π⋅f⋅T ⋅ e j⋅π⋅f⋅T − e −j⋅π⋅f⋅T = e −j⋅π⋅f⋅T ⋅ T ⋅ Sinc(π ⋅ f ⋅ T) (30.17)
−j ⋅ 2π ⋅ f j ⋅ 2π ⋅ f

Sinewave in
S/H out

time

Ts

Figure 30.27 Sample-and-hold output with return to zero format.

22 CMOS Mixed-Signal Circuit Design

The magnitude of Eq. (30.17), H( f ) , is plotted in Fig. 30.28. The phase response
corresponds to a shift in time of T/2 so, to simplify the math below, we will only concern
ourselves with the magnitude response of H( f ).

h(t) H( f )
u(t − nT) − u(t − (n + 1)T)
1 T

T Ts time
f
(a) 0
1 2 3
T T T
(b)

Figure 30.28 (a) Sampling pulse and (b) its spectrum.

Multiplication in the time domain can be evaluated using convolution in the

frequency domain. The frequency spectrum of a sinewave, sampled with an ideal S/H, is
given by
∞
Y( f ) = H( f ) ∗ V in ( f ) = ∫
−∞
H(L) ⋅ V in ( f − L) dL (30.18)

or
Ideal impluse sampler response
Weighting from S/H, H(f)
∞
 Vp 
Y( f ) = T ⋅ Sinc(π ⋅ T ⋅ f ) ⋅  ⋅ Σ [δ( f − f in + kf s ) + δ( f + f in + kf s )]  (30.19)
 Ts k = − ∞ 
As T → 0 (h(t) → δ u (t) ), the frequency response of the sample-and-hold approaches the
ideal impulse sampler of Sec. 30.1.1. Also, note that using an RZ format (making T < T s )
can reduce the amount of attenuation introduced by the S/H ( H( f ) doesn't roll off as
fast.)
For most circuit designs, T = T s so that, as Eq. (30.19) shows, the
sample-and-hold operation weights the amplitude of the ideal impulse sampler's frequency
 πf   πf 
response by Sinc or Sinc . Note that at the sampling frequency (fs=1/Ts) the
 fs   2f n 
output of the ideal S/H goes to zero. Let's illustrate the frequency response of an ideal S/H
using an example.

Example 30.7
Using the ideal S/H SPICE model show and discuss the spectrum resulting from
sampling a 3 MHz sinewave at 100 Msamples/s.
Chapter 30 Data Converter Modeling 23

The results of passing a 0.75 V (peak) sinewave centered at 0.75 V (−2.5 dB)
through the ideal S/H are shown in Fig. 30.29. We have also plotted the response
of the S/H, H( f ) in this figure. The attenuation the 97 MHz image sees is

Attenuation = Sinc  π ⋅ 97  = 0.031 = −30.2 dB

100
The amplitude of the 97 MHz image is −2.5 dB below the attenuation resulting
from using a S/H or −32.7 dB. Note how at the Nyquist frequency of 50 MHz, the
signal is attenuated by −3.9 dB. Also note how the DC image at f s is attenuated
by the S/H instead of being doubled as in the impulse sampler (Fig. 30.20).
Two additional notes: First, the S/H cannot be used as an AAF since any
aliasing that occurred using the impulse sampler still occurs using the S/H. For
example, sampling a 60 MHz sinewave at 100 MHz still results in a 40 MHz alias
signal in the base spectrum (the spectrum from DC to fn ), as shown in Fig. 30.5.
Now, however, the signal is attenuated by the S/H (the attenuation is −2.4 dB at
40 MHz when sampling at 100 Msamples/s.) In other words, the S/H can be
thought of as an ideal impulse sampler followed by a Sinc response filter. Second,

3 MHz, 0.75V peak (−2.5 dB)

DC, 0.75 V
97 MHz, −32.7 dB
fn

−13.5 dB
−3.9 dB
Volts, peak

S/H response

Noise floor

fs
50 MHz
Figure 30.29 Output of a S/H after sampling a 3 MHz sinewave at 100 MHz.
24 CMOS Mixed-Signal Circuit Design

repetitively sampling and holding a signal results in only one S/H attenuation hit
(assuming the timing is such that a sampling operation is not occurring when the
previous S/H stage's output is changing). This means that topologies that use
several S/H operations on an input signal, such as a pipeline ADC, only attenuate
the signal by Sinc(πf/f s ) once. T
The output of the S/H (assuming T = T s ) should be passed through a two-stage
reconstruction filter, to recover the input signal. One of the stages will have the frequency
response of the ideal RCF of Fig. 30.16. The other stage will have a frequency response
given by
1 πf
H RCFSH ( f ) = = (30.20)
Sinc  fs  2f n sin  2f n 
πf πf

to compensate for the attenuation of the S/H Sinc response. The shape of the ideal
reconstruction filter is shown in Fig. 30.30. Again, increasing the sampling frequency
relative to the input frequency will ease the requirements placed on the reconstruction
filter. Note how using the RZ format modifies the requirements placed on the
reconstruction filter to the point, when using impulse sampling, of having the brick wall
ideal RCF of Fig. 30.7.

H RCFSH (f )

0 dB
3.9 dB (1.56)
1 1
Overall response of RCF
for a S/H

f fn f
fs 2f s

Figure 30.30 Ideal reconstruction filter response for a S/H.

Before we leave this section, let's answer the question: "What sets the value of the
noise floor in SPICE (Fig. 30.29)?" We can limit the noise floor, in Fig. 30.29 for
example, by adding 1 µV to voltages in the circuit. However, the SPICE-simulated
spectrum's noise floor, which is set by simulation variations, is limited by the RELTOL
parameter. Also, the length of the simulation can be important. ABSTOL, which defaults
to 1 pA, and VNTOL, which defaults to 1 µV, signify when a current or voltage has
converged in a SPICE simulation. If the step change in the simulation, for all currents and
voltages at a given time, is within ABSTOL (for currents) or VNTOL (for voltages), then
SPICE moves on to the next step in time (for a transient simulation). The parameter
RELTOL was added to SPICE so that simulations involving large currents and voltages
Chapter 30 Data Converter Modeling 25

were not forced to use ABSTOL and VNTOL to signify convergence. In other words, if a
current is approximately 10 A, we won't force the SPICE number for the current to be
10.000000000001. Instead we use 10.01 (the product of RELTOL [assuming = 0.001]
and 10 A) to signify convergence. To signify that a current has converged, we use the
larger of
ABSTOL or RELTOL ⋅ I simulated (30.21)
while for a voltage we use the larger of
VNTOL or RELTOL ⋅ V simulated (30.22)
For the simulation shown in Fig. 30.29, we set RELTOL to 10 −6 so that our 1 V level
signals simulate to within 1 µV of their "actual" values. This keeps the simulation noise
from setting our noise floor. The practical problem of reducing RELTOL is convergence
when nonideal components (e.g. MOSFETs) are added to the simulation. Trade-offs must
be made between simulation noise and convergence when using both ideal and nonideal
components in a simulation.
Circuit Concerns for Implementing the S/H
Figure 30.31 shows a single-ended input and output S/H implementation using either an
op-amp or an OTA (operational transconductance amplifier). At the time t0 , the φ 1 and φ 2
switches are closed while the φ 3 switches are open. During the time between t1 and t2 the
input charges the hold capacitor CH . The input is connected to the left side, or bottom
plate (the plate closest to the substrate), of CH , while because of the op-amp, the right side
(top plate) is connected to ground (or a common mode voltage, VCM). At t1 the φ 1 switch
opens and for a very short time (set by t 3 − t 1 ) the op-amp operates open loop (no
feedback). As the top plate is always at ground (or VCM) at t1 , the charge injection and
capacitive feedthrough resulting from the φ 3 switches turning off are independent of the
input signal. When the φ 2 switch turns off, the charge injection will, ideally, flow into the
low-impedance input, vin , since the impedance looking into the right of the φ 2 switch is
large. This, again ideally, leaves the voltage across the hold capacitor unaffected by the
charge injection resulting from turning off the switches. This sequence of turning off the

φ3
to t1 t2 t3
φ1 φ1
φ2 CH
v in φ2
φ3
v out
φ3
Bottom plate

Figure 30.31 Single-ended S/H operation.

26 CMOS Mixed-Signal Circuit Design

switch to the right of CH followed by turning off the switch connecting vin to CH is often,
confusingly, called bottom plate sampling. Bottom plate sampling is illustrated in its
simplest form in Fig. 30.32. In this figure the switch connected to the bottom plate of the
capacitor is turned off first. When the φ 2 switch turns off, the charge can be injected into
the low-impedance node, the input vin , or into the series combination of CH and the off
switch. The charge takes the lowest impedance path to ground and thus most of the
charge injection resulting from the φ 2 switch turning off flows through vin , leaving the
voltage across the hold capacitor unaffected. We should see why the name "bottom plate
sampling" is confusing. Reviewing Fig. 30.31, we see that the top plate of the hold
capacitor is connected to the φ 1 switch while, in Fig. 30.32, the bottom plate of the hold
capacitor is connected to the φ 1 switch.

φ2 Turns off last

CH
v in
Turns off first

φ1

Figure 30.32 Bottom plate sampling.

Returning to the discussion of the operation of the S/H of Fig. 30.31 we see that at
t3 the φ 3 switches turn on and the op-amp behaves as a voltage follower holding the
sampled input voltage. The sampling instant occurs between t1 and t3 (which should be
short to keep the op-amp output from drifting toward VDD or ground.)

30.2 SPICE Models for DACs and ADCs

In this section we develop SPICE models for ideal digital-to-analog converters (DACs)
and analog-to-digital converters (ADCs). Our goal is to have SPICE code, or subcircuits,
that we can place in a mixed-signal simulation to either (1) generate a digital word based
on an analog input (using the ideal ADC) or (2) look at the spectrum of a digital signal
(using the ideal DAC and the spectral analysis capability in SPICE [using the discrete
Fourier transform].)
30.2.1 The Ideal DAC
While there are an infinite number of ways to implement an ideal DAC in SPICE, we use a
method that results in a computationally efficient model for a DAC. Before we discuss the
implementation, let's review some fundamental characteristics of a DAC.
Chapter 30 Data Converter Modeling 27

Consider the ideal transfer characteristics of a 3-bit DAC shown in Fig. 30.33. (For
a detailed review of general DAC characteristics, see Ch. 28.) Notice in this figure that we
have drawn two reference voltages, V REF+ and V REF− , and are assuming that
V REF+ > V REF− . When a digital input of 000 is applied to the DAC, the output voltage
becomes V REF− . When the input code is increased to 001, the output of the DAC (an
analog voltage defined at discrete amplitude levels) increases by one least significant bit
(LSB). If the DAC has an input code with a number of bits, N, then we can define an LSB
as
VREF+ − V REF−
1 LSB = = V LSB (30.23)
2N
If, for example, V REF+ = 1.25 V and V REF− = 0.25 V and N = 3 , then our LSB, the vertical
distance between adjacent points in Fig. 30.33, is 0.125 V. Note that in our discussion of

V OUT − VREF−
V REF+ − V REF−
V REF+
8/8
V REF+ − 1LSB
7/8
6/8
5/8
1 LSB
4/8
3/8
2/8
1/8
V REF− Digital
0 input code, b 2 b 1 b 0
000 001 010 011 100 101 110 111

V REF+

b2
Ideal
b1 V OUT
3-bit DAC
b0

V REF−

Figure 30.33 An ideal 3-bit DAC.

28 CMOS Mixed-Signal Circuit Design

an ideal DAC we are assuming that the output of the DAC ranges from V REF− up to
V REF+ − 1 LSB . We could just as easily have assumed that the output ranged from
V REF− + 1 LSB up to V REF+ . The important thing to notice is that the DAC output range is
1 LSB smaller than the difference between the positive and negative reference voltages.
For the DAC developed in this chapter, we will assume V REF+ = VDD = 1.5 V and
V REF− = VSS = 0 V . In Ch. 33 we discuss a submicron CMOS process using these power
supply voltages, 1.5 V and 0 V. Selection of the power supply rails, which are noise free
in a SPICE simulation, allow the maximum output range for the DAC (assuming the
reference voltages are indeed the maximum and minimum voltages in the system, i.e., no
charge pumps or external, larger, power supply voltages). If we need more resolution
when using our ideal DAC, we will simply increase the number of bits, N, used and hence
decrease the value of the DAC's LSB.
SPICE Modeling Approach
We can write the output of the ideal DAC in terms of the reference voltages and digital
input codes b N (which are logic "0" or "1"), and assuming that an input code of all zeroes
results in an output voltage of V REF− , as

V OUT = (V REF+ − V REF− ) ⋅  N−1 + N0  + V REF−

b b b1 b
1
+ N−2
2
+ ... + N−1 (30.24)
2 2 2 2
or
1
V OUT = (V REF+ − V REF− ) ⋅ ⋅ (b N−1 2 N−1 + b N−2 2 N−2 + ... + b 1 ⋅ 2 1 + b 0 ) + V REF− (30.25)
2N
We can implement this equation, in SPICE, using a nonlinear dependent source (a B
source). For a 3-bit, ideal DAC, the statement that implements this equation may look like
*Nonlinear dependent source, B, for generating the DAC output
Bout Vout 0 V=((v(vrefp)-v(vrefm))/8)*(v(B2L)*4+v(B1L)*2+v(B0L))+v(vrefm)

The terms BXL correspond to logic signals that have a value of 1 V or 0 V.

Example 30.8
Write the nonlinear dependent source statement for an ideal 12-bit DAC.
The statement follows:
Bout Vout 0 V=((v(vrefp)-v(vrefm))/4096)*
+(v(B11L)*2048)+v(B10L)*1024+v(B9L)*512+v(B8L)*256
+v(B7L)*128+v(B6L)*64+v(B5L)*32+v(B4L)*16+v(B3L)*8+
+v(B2L)*4+v(B1L)*2+v(B0L))+v(vrefm)

remembering that a "+" in the first column of a line indicates that the text on the
remainder of the line behaves as if it were typed at the end of the previous line. It
doesn't indicate addition. T
The next thing we need to concern ourselves with is the digital logic levels. We
want to use our ideal DAC with nonideal (real) circuits where the logic voltage levels may
not be well defined. We need to determine and use a switching-point voltage based on the
Chapter 30 Data Converter Modeling 29

power-supply voltage VDD. We will assume the input logic code is a valid logic "1" if its
amplitude is greater than VDD/2 and a logic "0" if its amplitude is less than VDD/2. We
can implement the VDD/2 switching point, or trip voltage, using the following SPICE lines
*Generate Logic switching point, or trip, voltage
R1 VDD trip 100MEG
R2 trip 0 100MEG

The solid logic levels can be generated using the following subcircuit SPICE code. The
switch implementation is shown in Fig. 30.34.
.subckt Bitlogic trip BX BXL
Vone one 0 DC 1
SH one BXL BX trip Switmod
SL 0 BXL trip BX Switmod
.model switmod SW
.ends

1V BX is the logic input with

a, possibly, poorly defined
amplitude.
Closed when BX > trip
BXL
Closed when BX < trip

Figure 30.34 Generating logic levels using voltage-controlled switches.

Using the above code, the subcircuit definition for an ideal 8-bit DAC can be
written, as shown in Fig. 30.35. Using this subcircuit in the following netlist, we can show
the operation of an ideal 8-bit DAC:
VDD VDD 0 DC 1.5
VREFP VREFP 0 DC 1.5
VREFM VREFM 0 DC 0.0

VB7 B7 0 DC 0 pulse 1.5 0 0 200p 200p 1279.8n 2560n

VB6 B6 0 DC 0 pulse 1.5 0 0 200p 200p 639.8n 1280n
VB5 B5 0 DC 0 pulse 1.5 0 0 200p 200p 319.8n 640n
VB4 B4 0 DC 0 pulse 1.5 0 0 200p 200p 159.8n 320n
VB3 B3 0 DC 0 pulse 1.5 0 0 200p 200p 79.8n 160n
VB2 B2 0 DC 0 pulse 1.5 0 0 200p 200p 39.8n 80n
VB1 B1 0 DC 0 pulse 1.5 0 0 200p 200p 19.8n 40n
VB0 B0 0 DC 0 pulse 1.5 0 0 200p 200p 9.8n 20n

X1 VDD VREFP VREFM Vout B7 B6 B5 B4 B3 B2 B1 B0 DAC8bit

30 CMOS Mixed-Signal Circuit Design

*** Start Ideal 8-bit DAC Subcircuit *************************

.subckt DAC8bit VDD VREFP VREFM Vout B7 B6 B5 B4 B3 B2 B1 B0

*Generate Logic switching point, or trip, voltage

R1 VDD trip 100MEG
R2 trip 0 100MEG

*Change input logic signals into logic 0s or 1s

X7 trip B7 B7L Bitlogic
X6 trip B6 B6L Bitlogic
X5 trip B5 B5L Bitlogic
X4 trip B4 B4L Bitlogic
X3 trip B3 B3L Bitlogic
X2 trip B2 B2L Bitlogic
X1 trip B1 B1L Bitlogic
X0 trip B0 B0L Bitlogic

*Nonlinear dependent source, B, for generating the DAC output

Bout Vout 0 V=((v(vrefp)-v(vrefm))/256)*(v(B7L)*128+v(B6L)*64+
+v(B5L)*32+v(B4L)*16+v(B3L)*8+v(B2L)*4+v(B1L)*2+v(B0L))+v(vrefm)

.ends

.subckt Bitlogic trip BX BXL

Vone one 0 DC 1
SH one BXL BX trip Switmod
SL 0 BXL trip BX Switmod
.model switmod SW
.ends

*** END DAC Subcircuit *************************************

Figure 30.35 SPICE subcircuit netlist for an ideal 8-bit DAC.

In this netlist we are assuming V REF+ = 1.5 V and V REF− = 0 . The pulse sources step the
DAC through all possible codes, i.e. from 00000000 (= 0 V) all the way up to 11111111
(= 1.5 V − 1 LSB) in increments of 1.5/256 or 5.859 mV (= 1 LSB.) The simulation
results are shown in Fig. 30.36. It should be very easy to see how to implement any
resolution of ideal DAC at this point using SPICE.
Before leaving the ideal DAC let's discuss how to shift the ideal output
characteristics up by 1 LSB. The DAC in Fig. 30.35 has an output range of 0 V (V REF− ) to
VDD − 1 LSB (V REF+ − 1 LSB) . We can rewrite Eq. (30.25) as
1 LSB

V OUT = (V REF+ − V REF− ) ⋅ 1N ⋅(b N−1 2 N−1 + b N−2 2 N−2 + ... + b 1 ⋅ 2 1 + b 0 ) + V REF−
2
(30.26)
Chapter 30 Data Converter Modeling 31

DAC output

DAC inputs
b7
DAC inputs (level shifted for easy viewing)

b0

Figure 30.36 Simulating an ideal 8-bit DAC.

32 CMOS Mixed-Signal Circuit Design

To shift the output up by 1 LSB (so the output of the ideal DAC ranges from 1 LSB
above V REF− to V REF+ ) we simply add one to the binary-weighted term in the parentheses
1LSB

V OUT = (V REF+ − V REF− ) ⋅ 1N ⋅(b N−1 2 N−1 + b N−2 2 N−2 + ... + b 1 ⋅ 2 1 + b 0 + 1) + V REF−
2
(30.27)
This equation is trivial to implement in our ideal DAC by adding two characters to our
nonlinear dependent source, i.e., "+1."
30.2.2 The Ideal ADC
The characteristics of our ADC are shown in Fig. 30.37. (Again, a complete discussion of
ADC characteristics was given in Ch. 28.) Notice how in this figure the transfer curve is
shifted to the left. If we were to flip the curve on it's side and mark, with black dots, the
intersection of the analog input voltage with the ADC transfer curve, we would have the
DAC transfer curve of Fig. 30.33. Again 1 LSB is given by Eq. (30.23). Notice how
converting a (normalized) input voltage of 0.1 V will result in an output code of 000
which is the same output code resulting from converting 0 V. Unlike the ideal DAC, the
ideal ADC quantizes its input with the practical result of adding noise to the input signal.
This noise is often called quantization noise.
The implementation of the ideal ADC consists of an ideal S/H followed by passing
the output of the S/H (the held signal) through an algorithm to generate the output bits.
The algorithm we use is based on a pipeline ADC and follows:
1. The input signal is sampled and held.
2. This held signal is input to a comparator that compares the input value to a
reference voltage.
3. If the input signal is greater than the reference voltage, the output bit is set to a
high, and the reference signal is subtracted from the input. The difference is multiplied by
two and passed to the output of stage.
4. If the input signal is less than the reference voltage, the output bit is set low.
The input signal is multiplied by two and passed to the output of the stage.
5. This output is used as the input to the next stage and steps 2, 3, and 4 above are
repeated. This continues for N stages (where N is the number of bits in the ADC).
The reference voltage, or common mode voltage VCM , can be determined by
calculating the midpoint between V REF+ and V REF− followed by subtracting V REF− so that
the V CM is referenced to 0 V. This can be written as
V REF+ + V REF− V + V REF− V − V REF−
V CM = → V CM0 = REF+ − V REF− = REF+ (30.28)
2 2 2
We also want to level shift the input signal so that it is referenced to 0 V. In addition, we
want to shift the transfer curves to the left by 1/2 LSB as seen in Fig. 30.37. To do this we
Chapter 30 Data Converter Modeling 33

Digital
output code, b 2 b 1 b 0 1 LSB

111
110
Analog input
101
100
011
010
001
V IN − V REF−
000
0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 8/8 V REF+ − V REF−
Analog input voltage
V REF−
V REF+ − 1 LSB

V REF+

b2
Ideal
V IN b1
3-bit ADC
f clk b0
V REF−

Figure 30.37 An ideal 3-bit ADC.

use the following SPICE statement (for an 8-bit ADC where V(OUTSH) is the output
voltage of the ideal S/H [the input to the pipeline algorithm above])
* Level shift by VREFM and 1/2LSB
BPIP PIPIN 0 V=V(OUTSH)-V(VREFM)+((V(VREFP)-V(VREFM))/2^9)

The last term in this statement is 1/2 LSB, which is given by

V REF+ − V REF−
1/2 LSB= assuming V REF+ > V REF− ≥ 0 (30.29)
2 N+1
We are level-shifting the input and common-mode voltage because we want to make the
model as flexible as possible. For example, we want the ADC model to function if V REF+ =
0.5 V and V REF− = 0.25 V. Note that if V REF− = 0 and V REF+ = VDD , the model can be
simplified.
34 CMOS Mixed-Signal Circuit Design

*** START IDEAL 8-BIT ADC Subcircuit ******************************

.subckt ADC8bit VDD VREFP VREFM Vin B7 B6 B5 B4 B3 B2 B1 B0 CLOCK

* Set up common mode voltage

BCM VCM 0 V=(V(VREFP)-V(VREFM))/2

* Set up logic switching point

R3 VDD VTRIP 100MEG
R4 VTRIP 0 100MEG

* Ideal input sample and hold

XSH VDD VTRIP VIN OUTSH CLOCK SAMPHOLD

* Level shift by VREFM and 1/2LSB

BPIP PIPIN 0 V=V(OUTSH)-V(VREFM)+((V(VREFP)-V(VREFM))/2^9)

* 8-bit pipeline ADC

X7 VDD VTRIP VCM PIPIN B7 VOUT7 ADCBIT
X6 VDD VTRIP VCM VOUT7 B6 VOUT6 ADCBIT
X5 VDD VTRIP VCM VOUT6 B5 VOUT5 ADCBIT
X4 VDD VTRIP VCM VOUT5 B4 VOUT4 ADCBIT
X3 VDD VTRIP VCM VOUT4 B3 VOUT3 ADCBIT
X2 VDD VTRIP VCM VOUT3 B2 VOUT2 ADCBIT
X1 VDD VTRIP VCM VOUT2 B1 VOUT1 ADCBIT
X0 VDD VTRIP VCM VOUT1 B0 VOUT0 ADCBIT
.ends

* Ideal Sample and Hold subcircuit

.SUBCKT SAMPHOLD VDD VTRIP Vin Vout CLOCK
Ein Vinbuf 0 Vin Vinbuf 100MEG
S1 Vinbuf VinS VTRIP CLOCK switmod
Cs1 VinS 0 1e-10
S2 VinS Vout1 CLOCK VTRIP switmod
Cout1 Vout1 0 1e-16
Eout Vout 0 Vout1 0 1
.model switmod SW
.ends

* Pipeline stage
.SUBCKT ADCBIT VDD VTRIP VCM VIN BITOUT VOUT
S1 VDD BITOUT VIN VCM switmod
S2 0 BITOUT VCM VIN switmod
Eouth Vinh 0 VIN VCM 2
Eoutl Vinl 0 VIN 0 2
S3 Vinh VOUT BITOUT VTRIP switmod
S4 Vinl VOUT VTRIP BITOUT switmod
.model switmod SW
.ends
*** END ADC Subcircuit *************************************

Figure 30.38 SPICE subcircuit netlist for an ideal 8-bit ADC.

Chapter 30 Data Converter Modeling 35

Example 30.9
Modify the SPICE code of Fig. 30.38 so that the subcircuit simulates an ideal
12-bit ADC.
We can change the level-shift statement (change 9 to 13) to
* Level shift by VREFM and 1/2LSB
BPIP PIPIN 0 V=V(OUTSH)-V(VREFM)+((V(VREFP)-V(VREFM))/2^13)

and add to the pipeline algorithm

* 12-bit pipeline ADC
X11 VDD VTRIP VCM PIPIN B11 VOUT11 ADCBIT
X10 VDD VTRIP VCM VOUT11 B10 VOUT10 ADCBIT
X9 VDD VTRIP VCM VOUT10 B9 VOUT9 ADCBIT
X8 VDD VTRIP VCM VOUT9 B8 VOUT8 ADCBIT
X7 VDD VTRIP VCM VOUT8 B7 VOUT7 ADCBIT

where the last statement is a modification, in the 8-bit ideal ADC, of the existing
statement for X7. T
We can simulate the operation of our ideal 8-bit ADC in several ways. Let's begin
by simply applying a ramp from V REF− to V REF+ (0 to 1.5 V) to the ADC while clocking
the ADC at 100 MHz. The results are shown in Fig. 30.39. Additional simulations using
the ideal ADC will be left as an exercise for the reader. We are now in a position to put
our ideal ADC and DAC together so that we can look at the spectral response and
limitations resulting from quantization noise.
Summary
It's important to realize the usefulness of the simulation models we have just developed. In
any mixed-signal simulation using SPICE we can use our ideal ADC to generate a digital
signal, most often a sinewave, as an input source. We can use the DAC to convert a digital
word into an analog waveform. We can then take the discrete Fourier transform of the
resulting analog waveform, using the SPICE "spec" command, and view the digital data's
spectrum.
Note that in this chapter we are only discussing the use of the offset binary format
(see Ch. 29) for our digital words (0000... corresponds to V REF− and 1111... corresponds
to V REF+ − 1 LSB ). It should be clear that we can modify our ideal data converters to
work with any data format. We could also add digital logic to our converter subcircuit for
the format conversion and continue to use the ideal ADC/DAC developed in this chapter.

30.3 Quantization Noise

At this point we should understand the sampling process and understand the operation of
the ideal ADC and DAC. What we want to do in this section is understand quantization
noise (the effective noise added to a signal after passing through an ADC) and how it
affects the spectrum of a signal.
36 CMOS Mixed-Signal Circuit Design

ADC input and

S/H output

ADC Input

ADC Outputs and clock

b7

b0

Clock

Figure 30.39 Simulating an ideal 8-bit ADC.

Chapter 30 Data Converter Modeling 37

30.3.1 Viewing the Quantization Noise Spectrum Using Simulations

Consider the simple connection of an ideal 8-bit ADC to an ideal 8-bit DAC as shown in
Fig. 30.40. If we put a 7 MHz sinewave into the ADC with an amplitude of 0.75 V and an
offset of 0.75 V (so the sinewave swings from V REF− [= 0 V here] to V REF+ [= 1.5 V ]) and
clock the ADC at 100 MHz the waveforms of Fig. 30.41 result. Note how the output of
the DAC looks very similar to the output of an ideal S/H (see Fig. 30.25). Now, however,
the amplitude of the DAC output signal is quantized, that is, within 1 LSB (= 1.5/256 or
5.859 mV for the present simulation) of the ADC input. This quantization is not obvious
after looking at Fig. 30.41 (the time domain response). However, looking at the spectrums
of the ADC input and the DAC output reveals the difference in the noise floor between the
two (Fig. 30.42.) The inherent noise floor in the simulation that is associated with the
input signal is approximately −140 dB (0.1 µV.) The noise floor associated with the
DAC's output (the signal + quantization noise) is approximately −60 dB (1 mV). It is
desirable to determine what sets this value and its spectral content. Again note that the
ADC quantizes the signal, which results in the quantization noise.

VDD = 1.5 VDD = 1.5

Analog Digital Analog
V IN 8 V OUT
Ideal Ideal
f clk 8-bit ADC 8-bit DAC

Figure 30.40 Passing a signal through an ADC and then through a DAC.

f clk = f s = 100 MHz

Figure 30.41 Seven MHz ADC input and the corresponding DAC output.
38 CMOS Mixed-Signal Circuit Design

Signal plus noise, S+N, volts peak 7 MHz, 0.75 V peak (−2.5 dB)

DAC Output,V DFT ( f )

ADC Input

fn f clk = f s

Figure 30.42 Spectrums of the signals shown in Fig. 30.41.

To characterize the spectral characteristics of the quantization noise let's make the
following assumptions (Bennett's criteria) concerning the signal we are converting:
1. The input (to the ADC) signal's amplitude variation falls between V REF+ and
V REF− so that no saturation of the digital output code occurs. Exceeding the normal
operating range of the ADC affects the quantization noise spectrum by adding spurs or
spikes to the output spectrum.
2. The ADCs LSB is much smaller than the input signal amplitude. When this isn't
the case, the output of the ADC can appear squarewave like (when converted back into an
analog waveform) and result in a spectrum, once again, that contains spikes or spurs. We'll
see later in the book that adding or subtracting a fed-back signal (from the output based
on the expected or past quantization noise) to the input modifies this requirement.
3. The input signal is busy (not DC or a low frequency input). We define busy, for
the moment, as meaning that no two consecutive outputs of the ADC have the same
digital code. For the ideal ADC of Fig. 30.41 1 LSB = 5.86 mV and T s = 10 ns so that the
input must change at least 5.86 mV every 10 ns. We'll see that adding a high-frequency
dither or pseudorandom noise signal to the input, which can be filtered out later (either
using a digital filter or when we pass the output through the reconstruction filter), can
make the requirement on the input of being busy practical in an actual circuit.
Chapter 30 Data Converter Modeling 39

We use these assumptions (Bennett's criteria) in the following discussion unless otherwise
indicated.

V IN Ideal V OUTSH V OUT

f clk S/H

Figure 30.43 Taking the difference between the S/H input and output.

An Important Note
It's important to note that simply sampling an input waveform, using a S/H, does not result
in quantization noise, as seen in Fig. 30.29. The amplitude into the ideal S/H, at the
sampling instant, is exactly the same as the amplitude out of the ideal S/H. To understand
why this is important, consider the test setup shown in Fig. 30.43. If we input the 3 MHz
sinewave of Ex. 30.7 into this circuit, we get the outputs shown in Fig. 30.44. Clearly
there is a difference between the S/H's input and its output. However, this difference has
nothing to do with noise, an unwanted signal, since passing the output of the S/H, VOUTSH ,

V OUT

Difference output

Difference spectrum
Volts, peak

Input spectrum

Figure 30.44 (a) Time domain difference between S/H input and output and (b) spectrum.
40 CMOS Mixed-Signal Circuit Design

through the ideal reconstruction filter of Fig. 30.30 results in an exact replica of the S/H
input VIN .
RMS Quantization Noise Voltage
If we were to set up a test configuration similar to that shown in Fig. 30.43 (see Fig.
30.45), where the input to the ADC is subtracted from the DAC output, the resulting
output waveform would have little to do, in every case, with the quantization noise. This
is especially true when the input to the ADC contains a broad frequency spectrum
extending from DC to the Nyquist frequency, f n = f s /2 . However, if we simply apply a
slow linear ramp to the input of this test setup (to limit the input frequency spectrum), see
Fig. 30.45, we can (1) see the resulting quantization noise over a wide frequency spectrum
and (2) observe that the transfer curve, in the time domain, is similar to Fig. 30.37. Note
that this input violates Bennett's criteria (which, as we'll see, means the noise power
spectral density is flat from DC to the Nyquist frequency).

Slow
V IN Ramp
Ideal Ideal V OUT V OUTD
f clk ADC DAC

Figure 30.45 Taking the difference an ADC input and the DAC output.

A section of the input and output, using the test setup of Fig. 30.45, is shown in
Fig. 30.46a. It's important to understand the input/output relationship between the ideal
ADC and DAC shown in this figure. (Note that clocking the ADC too slow or putting in a
ramp that rises too quickly will distort this waveform.) As an example, when the ADC
input is slightly above 758.79 mV, in this figure, the ADC output code (input to the DAC)
changes. The ADC output code can be calculated as 755.9 mV/1 LSB ( 1 LSB = 1.5/256
= 5.86 mV for the present simulation) or 129 when the input is slightly below 758.79 mV
and 130 when the input is slightly above 758.79 mV. Looking at the transfer curves in this
figure it appears as though the output changes when the ADC code is 129.5 or 758.79
mV/1 LSB. This, as seen in Fig. 30.46b and discussed below, results in centering the
quantization error around the input (and is the reason we shifted the ADC transfer curves
by 1/2 LSB when we developed our ideal ADC model).
The difference output, between the two signals of Fig. 30.46a, is shown in Fig.
30.46b. Some points to note about this sawtooth waveform are that 1) its average value is
zero, 2) the waveform contains an abrupt transition (and so we expect a wideband output
spectrum similar to that which occurs after sampling a waveform), and 3) its peak-to-peak
amplitude is 1 LSB. Like a sinewave, which also has zero average value, we can
characterize this quantization error waveform by looking at its root-mean-square (RMS)
Chapter 30 Data Converter Modeling 41

ADC input

1 LSB = 5.86 mV
DAC output

764.65 mV

758.79 mV

Figure 30.46 (a) ADC input and DAC output.

Difference between ADC input and DAC output

when the ADC input is a slow ramp

1/2 LSB

−1/2 LSB
Note the frequency of this waveform is 10 MHz

Figure 30.46 (b) Difference between ADC input and DAC output.
42 CMOS Mixed-Signal Circuit Design

value. This value can be calculated using

T
1 (0.5 LSB − 1 LSB ⋅ t) 2 dt = 1 LSB = V LSB
T ∫0
V Qe,RMS = (30.30)
T 12 12
This value is the RMS quantization noise voltage for a specific data converter. Note that
the value of the period for this sawtooth waveform, T , doesn't appear in the evaluated
result of this equation. Also note that the sampling frequency, fs , isn't present in this
equation. For our present discussion where 1 LSB is 5.86 mV, V Qe,RMS = 1.69 mV or
−55.43 dB.
Treating Quantization Noise as a Random Variable
If Bennett's criteria hold, then the quantization noise voltage can be thought of as a
random variable falling in the range of ±0.5 LSB , as seen in Fig. 30.47. The probability
that the quantization error is −0.2 LSB is the same as the probability that the error is 0.4
LSB. In other words, there is no reason why the quantization error should have one value
more often than another value.

1/2LSB
Probability density function, ρ
∫ ρ ⋅ dQe = 1
−1/2LSB

1 1 LSB= V LSB
V LSB
Qe
−1/2 LSB 1/2 LSB

Figure 30.47 Probability density function for the quantization error in an ADC
assuming Bennett's criteria hold.

The quantization error noise power is the variance of the probability density
function. The RMS quantization error voltage is the square root of the quantization noise
power. The variance of the probability density function (the quantization noise power, PQe)
is given, knowing the average of the quantization error, Qe , is zero, by
1/2LSB
V 2LSB
P Qe = ∫ ρ ⋅ (Qe) 2 ⋅ dQe =
12
(30.31)
−1/2LSB

so that, once again, the RMS quantization noise voltage is

V LSB
V Qe,RMS = (30.32)
12
Again, if our LSB voltage is 5.86 mV, then, once again, V Qe,RMS = 1.69 mV (−55.4 dB). If
we look at Fig. 30.42, we see that the peak noise voltage, at a given frequency, varies
essentially over the entire spectrum (white noise) and has a value ranging from −60 dB
down to less than −80 dB. Note that although the entire spectrum contains quantization
Chapter 30 Data Converter Modeling 43

noise it is not because of the sampling process used in the ADC (and so quantization noise
doesn't experience aliasing). Quantization noise is added to the signal after the sampling
process during the analog-to-digital conversion process. To qualitatively understand why
the quantization error spectrum is white, in Fig. 30.42, we remember that there are abrupt
transitions in the DAC output, and if the quantization error is truly random, the times
between the changes have varying periods. We might speculate that by simulating a longer
time or using a multiple frequency input so as to "exercise" the ADC, the resulting
quantization errors are further randomized and the resulting error spectrum will be flat.
Calculating RMS Quantization Noise Voltage from a Spectrum
The voltage spectrums for the quantization noise and the input signal (Fig. 30.46a and b)
are shown in Fig. 30.48. Note that the harmonics of the noise are, as we would expect,
spaced by 10 MHz (= 1/T ). Also note, the sampling frequency doesn't affect the value of
the RMS quantization noise voltage. The peak voltage of the fundamental tone in the
quantization noise voltage spectrum is approximately −55 dB or −58 dB RMS (peak
voltages [magnitudes] are used in the spectrum plots shown in this chapter unless
otherwise indicated). To relate the RMS noise voltage calculated above, i.e., −55.4 dB, to
the values shown in Fig. 30.48 we would: (1) convert the peak voltages to RMS values by
subtracting 3 dB from each value, (2) square each result to get the mean-squared voltage,
(3) sum the mean squared values, and (4) take the square root of this sum to get the RMS
quantization noise voltage. Looking at the peak values of the first three tones in the
Voltage, peak

Quantization noise spectrum

Input ramp spectrum

Figure 30.48 Input and quantization noise spectrums for the signals of Fig. 30.46.
44 CMOS Mixed-Signal Circuit Design

quantization noise spectrum, −55 dB, −60 dB, and −65 dB we convert these values to
RMS voltages, 1.26 mV, 0.708 mV, and 0.398 mV. The quantization noise, calculated
using only the first three tones, is then (1.26) 2 + (0.708) 2 + (0.398) 2 = 1.5 mV, RMS or
−56.5 dB. Clearly, increasing the number of tones used in this calculation will cause the
result to approach Eq. (30.30) (1.69 mV).
To calculate the RMS quantization noise voltage from a DAC output spectrum we
sum the mean-squared contribution from each component (after removing the desired
tones from the spectrum) and then take the square root of the result (as mentioned above.)
See VDFT( f ) in Fig. 30.42 as an example. If the resolution of the DFT is fRES , then we can
write this as
M−1
V Qe,RMS = 1 ⋅
2
Σ V 2DFT ( k ⋅ f RES )
k=0
where M = #DFTpoints (30.33)

The factor of root two comes from changing the peak values in a spectrum to RMS
quantities. Note that the term "bin" is often used to describe the fact that the output of the
DFT is only valid at discrete frequencies (the bins.) The number of bins is also known as
the number of points in an DFT output vector (labeled #DFTpoints or M in Eq. [30.33]).
This is seen in Fig. 30.48 (also shown in Fig. 30.48 is a DFT problem known as the
"picket fence" effect, which will be discussed in a moment). If the DFT resolution in a
simulation is 1 MHz then the DFT output, assuming the starting frequency is DC (0), will
have nonzero values at DC, 1 MHz, 2 MHz, and so forth. If the stop frequency is 200
MHz, then the total number of points in a DFT output vector is 201.
Note that if Bennett's criteria hold, Eq. (30.33) will equal V LSB / 12 . If it doesn't
hold, then the V Qe,RMS calculated using Eq. (30.33) will be different from V LSB / 12 . An
input high-frequency sinewave violates Bennett's criteria. For example, consider sampling
a 25 MHz sinewave at 100 MHz. If the sample points occur at the zero crossing points on
the sinewave and at the peak/valley points, the resulting DAC output will be a rectangular
waveform with a well-defined spectrum.
After a simulation the length of the DFT output vectors can be determined using
display

command or for a specific vector, say voutd, we can use

print length(voutd)

These commands show, in the WinSPICE command window, the length of the vectors and
the type, e.g., complex, real, dB, etc. (for the display command) or the length of a
particular vector (for the "print length" command).
If we want to set a component of the DFT to a value, say zero, we may want to
use a command sequence like
let m=mag(voutd)
let m[7]=0
Chapter 30 Data Converter Modeling 45

This sequence of commands sets the eighth element of a vector to zero (since we start at
element zero). This is often done to remove a tone in an output spectrum resulting from
the input signal or some other distortion.

Example 30.10
Using WinSPICE calculate the RMS quantization noise voltage from the spectrum
of Fig. 30.48.
We begin by running the simulation that generates this figure (running the netlist
file Fig30_48.cir). After the simulation is completed we type, in the WinSPICE
command window,
display

and the following appears:

frequency : frequency, real, 401 long [default scale]
vin : voltage, complex, 401 long
vindb : decibel, real, 401 long
voutd : voltage, complex, 401 long
voutdb : decibel, real, 401 long

We see from this that the length of the DFT is 401. Note that we could have used
the length command, as we'll do below, to determine the length of the DFT instead
of the display command.
To calculate the RMS quantization noise voltage we can use the following:
let m=mag(voutd)
let qnoise=0.707*sqrt(mean(m*m)*length(m))
print qnoise

which gives a result of 2.08 mV, a value larger than the 1.69 mV calculated for
V Qe,RMS earlier. Before we discuss the discrepancy between the two RMS voltages,
notice that we took the average (mean) of the mean-squared value of voutd and
then multiplied the result by its length to sum the mean-squared voltages as
specified by Eq. (30.33). T
Now we need to discuss the difference between the SPICE simulated and the
calculated RMS quantization noise voltages above. While the implementation of a discrete
Fourier transform is outside the subject matter of this book, we can comment here on two
DFT problems and how to reduce their effects; namely, the picket-fence effect and
spectral leakage.
The picket-fence effect, and the visual reason for its name, is shown in the insert
figure in Fig. 30.48. Coherent sampling (synchronizing the quantization error, Fig. 30.46,
with the sampling clock) was used to magnify the effect. In our discussion above we
assumed, for the first tone at 10 MHz, that the contribution to V Qe,RMS was − 55 dB. On
closer inspection, we see that there are also contributions, − 61 dB, to the quantization
noise at 9.5 MHz and 10.5 MHz. At these two side frequencies, the amplitude
46 CMOS Mixed-Signal Circuit Design

1/(simulation time) = 1/T stop

1
1

DFT resolution Plotting

0.5 0.5

0
DFT points 0 1 2 0 1 2

Figure 30.49 Showing the origins of the picket-fence effect.

contribution is one-half of the main contribution (− 6 dB below the main contribution).

Figure 30.49 shows that if one over the simulation time is equal to the DFT resolution
then the boundaries between the adjacent DFT output points, spaced by the reciprocal of
the simulation time, are coincident. This results in averaging adjacent contributions when
the DFT output is generated. To reduce the effects of this averaging, we can increase the
length of the simulation (having the effect of decreasing the window width used with the
DFT). We can modify Eq. (30.6) to reduce the picket-fence effects by requiring

Simulation time, T stop ≥ 2 = 2 (30.34)

DFT resolution f res

Example 30.11
Repeat Example 30.10 if Eq. 30.34 is used to set the DFT resolution and
simulation length.
In Example 30.10 the simulation time was 2,000 ns. We could increase the
simulation time to 4,000 ns or reduce the DFT resolution from 500 kHz to 1 MHz.
In order to keep the simulation time reasonably short (and to avoid spectral
leakage discussed next) we will decrease the DFT resolution and leave the
simulation time at 2,000 ns. Figure 30.50 shows the resulting output spectrum with
the decreased DFT resolution (now 1 MHz). The RMS quantization noise voltage
calculated by SPICE, from this spectrum, is 1.71 mV RMS. T
To understand what is meant by "spectral leakage," consider the sinewave with
infinite duration shown in Fig. 30.51a. When a DFT is performed on a time domain
waveform, the first step is to "window" the waveform. The simplest window is the
rectangular window. In a simulation the duration of the sinewave is finite and set by the
simulation time or transient stop time, Tstop . We can think of taking the infinite duration
sinewave of Fig. 30.51a and multiplying it by the rectangular waveform of Fig. 30.51b to
obtain the waveform used in the simulation, Fig. 30.51c. This multiplication means the
resulting waveform is the convolution of the original sinewave spectral response (an
impulse) and the frequency domain transform of the squarewave (a Sinc waveform) in the
Chapter 30 Data Converter Modeling 47

Quantization noise voltage, peak

Figure 30.50 Eliminating the picket-fence effect from the simulation in Fig. 30.48.

1 1

t t
T stop
(a) (b)

1 1

T stop t f in f

(c) (d) Frequency spectrum of (a)

f in Log amplitude
T stop 1/T stop

f f in f
f in Linear amplitude
1/T stop
(e) Frequency spectrum of (c) (f), Von Hann (Hanning) window

Figure 30.51 Showing how spectral leakage, resulting from a DFT, affects a waveform.
48 CMOS Mixed-Signal Circuit Design

frequency domain. The result is that instead of the sinewave spectral response being an
impulse function, as seen in Fig. 30.51d, it is a weighted Sinc waveform, Fig. 30.51e. Note
how the DFT spectral response of the sinewave, Fig. 30.51e, is spread out or "leaks" into
the frequencies around the actual or continuous time response. The large ratio of the peak
value of the Sinc pulse to its first sidelobe is usually undesirable. Rather, to minimize these
sidelobes, other windowing functions are used. The one we are using in this chapter is the
von Hann (a.k.a. Hanning or Cosine) window shown, without the sidelobes, in Fig. 30.51f.
The response is shown on both linear and log amplitude scales and the width of the
window is 2/Tstop at its base (= 1 MHz if Tstop = 2,000 ns).

Example 30.12
Using SPICE, show the spectrum of a 1 V (peak) sinewave at 10 MHz over a
spectral range of DC to 200 MHz with an DFT resolution of 1 MHz and a
simulation time of 2,000 ns (windowed frequency spread of 1 MHz, Fig. 30.51e).
The results are shown in Fig. 30.52. Note how the only point in these figures that
has a nonzero value occurs at 10 MHz. The plotting lines are used to connect the
five DFT output points shown in each of these figures. T

Figure 30.52 Output spectrum of 10 MHz sinewave showing the window's effect.

We were careful, in the previous example, to select the sinewave frequency to

coincide exactly with one of the points where the DFT is calculated (10 MHz.) In the
previous example the DFT points are calculated at DC, 1 MHz, 2 MHz, ..., 200 MHz. An
error in the DFT output response occurs if spectral content doesn't fall on one of these
frequencies. Consider the following example.

Example 30.13
Repeat Ex. 30.12 if the sinewave frequency is changed to 10.4 MHz.
The DFT output is shown in Fig. 30.53. Note that although the input frequency is
at 10.4 MHz the peak in the DFT response still occurs at 10 MHz (a DFT output
point). Also notice how the spectrum of the sinewave is effectively wider than the
sinewave of Ex. 30.12. The 10.4 MHz sinewave is within the DFT resolution of
both the 10 MHz and 11 MHz points. The result is effective spectral content at
these frequencies. Sinewaves that do not fall exactly at the DFT calculation points
are smeared in the DFT output spectrum. This smearing can spread across the
Chapter 30 Data Converter Modeling 49

spectrum and affect spectral content at other frequencies. Consider the following
example. T

Figure 30.53 Magnitude and spectral response for the 10.4 MHz sinewave of Ex. 30.13.

Example 30.14
Using SPICE, plot the output spectrum resulting from adding the 10 MHz and
10.4 MHz sinewaves from the previous two examples.
The results are shown in Fig. 30.54. Note how, even though the 10 MHz sinewave
has an amplitude of 1 V, the resulting output spectrum reports an amplitude of
approximately 600 mV at 10 MHz. This is a result of contributions from the 10.4
MHz signal, after windowing, subtracting from the 10 MHz signal calculation
point. T

Figure 30.54 Magnitude and spectral response for the sum of the 10 and 10.4 MHz sinewaves.

It's important to understand that by increasing the simulation time, the window
length increases, causing the width of the Sinc spectrum, see Fig. 30.51e, to decrease.
However, increasing the simulation time without making a corresponding change in the
DFT resolution can actually be harmful to the results. For example, if 1/Tstop is 100 kHz
(simulation time of 10,000 ns) and the DFT resolution is 1 MHz then an input sinewave at
10.5 MHz will have no effect on the resulting output spectrum. In general, it's important
to make

Simulation time, T stop = 2 = 2 (30.35)

DFT resolution f res
50 CMOS Mixed-Signal Circuit Design

Also note that in a general simulation, which includes MOSFETs, we can set the step size
used in a transient simulation with Eq. (30.8). However when using ideal components, as
in this chapter, the step size can be increased to speed up the simulation time.

Example 30.15
Determine the RMS quantization noise voltage from the DAC output spectrum
shown in Fig. 30.42.
Figure 30.42 was generated with a DFT resolution of 1 MHz and a simulation time
of 1,000 ns. We will increase the simulation time to 2,000 ns. The resimulated
spectrum of the DAC output noise is shown in Fig. 30.55. Notice in this spectrum
that there is a signal at DC and 7 MHz (from the input signal.) Also, the aliased
signals are present in the output spectrum at 93 MHz, 107 MHz, and 193 MHz.
To calculate the quantization noise we would have to first zero these components
out. We can use the following WinSPICE commands to calculate the quantization
noise:
let m=mag(vout)
let m[0]=0
let m[7]=0
let m[93]=0
let m[107]=0
let m[193]=0
let qnoise=0.707*sqrt(mean(m*m)*length(m))
print qnoise

The resulting RMS quantization noise voltage is 1.72 mV. T

Signal plus Noise, S+N, Volts peak

Figure 30.55 Simulating the circuit shown in Fig. 30.40 for 2,000 ns.
Chapter 30 Data Converter Modeling 51

Note that the simulations we have shown in this chapter generate spectral
responses out to twice the clocking frequency or 200 MHz when using a 100 MHz clock.
To reduce simulation time we may limit the spectral response to the Nyquist frequency.
Also, an important component of the simulations can be the addition of
.options RELTOL=1u

to a netlist. Not including this statement or one similar (e.g., RELTOL = 10u) in a netlist
may limit the simulated noise floor to a significant voltage.
WinSPICE can also be useful if measured data is available. The data from a
spectrum analyzer can be written to a text file and loaded into a WinSPICE vector using
the load command. See the WinSPICE online manual.
The DFT's Relationship to the Continuous Time Fourier Transform
Before we leave this section, let's comment on how the discrete Fourier transform is
related to the continuous time Fourier transform. We can write the continuous time
Fourier transform of a time-varying function, v(t), using
∞
V( f ) = ∫−∞ v(t) ⋅ e −j2πf⋅t ⋅ dt (30.36)

or, if we assume a finite simulation time,

T stop

V( f ) = ∫0 v(t) ⋅ e −2πf⋅t ⋅ dt (30.37)

To approximate this continuous time Fourier transform with discrete variables, we will use
the following
dt = ∆t and t = k ⋅ ∆t where k = 0, 1, ... N (30.38)
The variable ∆t is the transient step time (the time difference between points in the DFT
algorithm) and N is the number of time steps used in the algorithm (T stop = N ⋅ ∆t) . The
frequencies where the DFT is calculated, assuming Eq. (30.35) is valid, are given by

f = n ⋅ f res = 2n where n = 0, 1, ... M − 1 (30.39)

T stop
The variable M is the number of points in the DFT output vector (the number of
frequencies the DFT is calculated at). Finally, we can relate the continuous time Fourier
transform, evaluated at discrete frequencies, to the Discrete Fourier Transform with
discrete Fourier transform, VDFT (n)

N
V( f ) f=n⋅f res ≈ Σ v(k ⋅ ∆t) ⋅ e −j(4π/N)nk
k=0
⋅ ∆t (30.40)

(noting that 4π is used in the exponent because our DFT resolution was twice the
reciprocal of the simulation time), or
52 CMOS Mixed-Signal Circuit Design

V( f ) f = n⋅fres ≈ ∆t ⋅ VDFT (n ) (30.41)

In general, a DFT output is scaled (divided by ∆t ) so that it approximates the continuous
time Fourier Transform when it is plotted. This is usually transparent to the user of the
DFT routine.
30.3.2 Quantization Noise Voltage Spectral Density
If the quantization noise voltage spectrum is truly flat (Bennett's criteria hold) we can
determine the noise power spectral density of V Qe,RMS , V 2Qe ( f ) with units of V 2 /Hz , or the
noise voltage spectral density, V Qe ( f ) with units of V/ Hz by solving
fs /2
V 2LSB
12
=2 ∫ V 2Qe ( f ) ⋅ df
0 (30.42)
where the factor of 2 accounts for the power in the negative frequencies of the spectrum.
(See Ch. 7 for a discussion of noise spectral densities.) We are assuming that the noise
power is bandlimited to the Nyquist frequency (the output of the DAC is passed through
an ideal RCF). Solving Eq. (30.42) yields
V LSB V − V REF−
V Qe ( f ) = = REF+ (30.43)
12f s 2 N 12f s

with units of V/ Hz . The quantization noise spectral density is inversely proportional to

the sampling frequency. Figure 30.56 shows that we can model the ADC as a summing
block with V Qe ( f ) added to the input signal.

Analog Analog
Digital Digital
V IN Ideal V IN
f clk 8-bit ADC

V Qe ( f )

Figure 30.56 Modeling ADC quantization noise.

After looking at Eq. (30.43) we might think that by simply increasing the sampling
frequency we can reduce the amount of quantization noise an ADC introduces into an
analog input signal. While increasing the sampling frequency spreads the quantization
noise spectral density out over a wider range of frequencies (see Fig. 30.57) with a
corresponding reduction in amplitude, the sampling frequency doesn't affect the total RMS
quantization noise voltage. However, bandlimiting the spectrum using a filter reduces the
amount of quantization noise introduced into an input signal. In the simplest case a
lowpass filter, which we will think of as an averager, can be used on the digital outputs of
Chapter 30 Data Converter Modeling 53

V Qe ( f )

VLSB
12f s

f n = f s /2 f

Figure 30.57 Quantization Noise Spectral Density.

the ADC to reduce the amount of quantization noise introduced into the signal. We can
write the amount of noise introduced into an input signal over a range of frequencies using
fH

V 2Qe,RMS = 2 ∫ V Qe ( f ) ⋅ df where f L < f H ≤ f s /2

2
(30.44)
fL

Again the factor of 2 is used to account for the contributions to V Qe,RMS in the negative
frequency spectrum (the DFT routine, discussed in the previous section, uses a one-sided
spectrum so the factor of 2 is not necessary when making calculations using the SPICE
simulation output data). Because the output of the ADC is a digital word, we would
require a digital filter to bandlimit the output spectrum of the ADC. We will discuss digital
filtering in the next chapter. For now let's show that the sampling frequency indeed doesn't
affect the quantization noise, assuming Bennett's criteria are valid, and then let's discuss
the concept of averaging to reduce quantization noise.

Example 30.16
Repeat Ex. 30.11 if the sampling frequency is increased from 100 MHz to 200
MHz.
Doubling the sampling frequency has no effect on the output quantization noise. It
remains at 1.69 mV RMS. T

Example 30.17
Repeat Ex. 30.15 if the sampling frequency is increased from 100 MHz to 200
MHz.
Again, the RMS quantization noise voltage remains essentially unchanged, i.e.,
1.68 mV RMS. Recall that the circuit shown in Fig. 30.40 is used in this example
and Ex. 30.15 with a 7 MHz input. It's instructive to show the time domain output
of Fig. 30.40 when clocked at 200 MHz, Fig. 30.58, and compare it to Fig. 30.41
(the output of the circuit of Fig. 30.40 clocked at 100 MHz). Note how the DAC
output voltage step size has decreased in Fig. 30.58 when compared to Fig. 30.41,
yet the quantization noise remains unchanged. This shows, once again, that we
must look at the spectrum of a signal to determine the quantization noise voltage
and that the "coarseness" of an output signal has nothing to do with quantization
noise. T
54 CMOS Mixed-Signal Circuit Design

Figure 30.58 Output of the circuit shown in Fig. 30.40 with 7 MHz input and 200 MHz
sampling clock. This figure should be compared to Fig. 30.41.

Reducing Quantization Noise Using Averaging

Consider the parallel combination of ADCs and DACs shown in Fig. 30.59. The top ADC
and DAC are essentially the path we had back in Fig. 30.40 clocked at 100 MHz. The
bottom path is a mirror image of the top except that its clock signal is inverted (delayed by
5 ns.) The two resistors are used to average the output of the DACs, or
V OUTA + V OUTB
V OUT = (30.45)
2

Analog
8 V OUTA Analog
V IN Ideal Ideal
f clk = 100 MHz 8-bit ADC 8-bit DAC
Digital V OUT

8
Ideal Ideal
8-bit ADC 8-bit DAC V OUTB

Figure 30.59 Using two paths to average the quantization noise.

Chapter 30 Data Converter Modeling 55

Note that this configuration effectively samples the input at 200 MHz (200 Msamples/s
[2 ⋅ f s ] ), as was accomplished in Fig. 30.58 except that now we are averaging consecutive
samples. If we input a 7 MHz sinewave into this configuration, the same signal used in
Fig. 30.41 or Fig. 30.58, we get the output shown in Fig. 30.60. Note the resemblance to
Fig. 30.58. Also note the additional phase shift. The RMS quantization noise voltage now,
however, has dropped from 1.68 mV to approximately 1.18 mV.

Figure 30.60 Output of the circuit of Fig. 30.59 with a 7 MHz input sinewave.

The Noise Spectral Density View of Averaging

In Fig. 30.59 we effectively doubled the sampling frequency. We can redraw Fig. 30.57 to
show the effects of averaging by changing the amplitude in this figure from V LSB / 12( f s )
to V LSB / 12 ⋅ (2f s ) and by increasing the frequency spectrum range as seen in Fig. 30.61.
Assuming that we are still interested in the spectrum up to f s /2 , the RMS quantization
noise can be calculated using
f s /2 2
1 ⋅ V LSB ⋅ df
V 2Qe,RMS = 2 ∫ 2 12f s
(30.46)
0

or
V
V Qe,RMS = 1 ⋅ LSB (30.47)
2 12
56 CMOS Mixed-Signal Circuit Design

V Qe ( f ), V/ Hz Original Spectrum 1 ⋅ V LSB

New Spectrum 2 12f s
VLSB
12f s

f n = f s /2 fs f

Figure 30.61 Quantization noise spectral density with two-sample averaging.

The sampling rate is effectively doubled.

In general, averaging K samples results in an RMS quantization noise voltage of

V
V Qe,RMS = 1 ⋅ LSB (30.48)
K 12
The nonaveraged noise, V LSB / 12 , is reduced by the root of the averaging factor K. We
know that the simulated V Qe,RMS in Ex. 30.17 was 1.68 mV. We simulated this circuit,
again, using an averaging of two (Figs. 30.59 and 30.60) which resulted in a simulated
V Qe,RMS of 1.18 mV. We could have estimated this RMS Quantization Noise beforehand
using Eq. (30.48) as (1.68 mV)/ 2 = 1.18 mV, which is, of course, the simulated result.
An Important Note
For averaging to effectively reduce the RMS quantization noise, the ADC and DAC must
be linear (how linear will be answered in the next chapter). Examine Fig. 30.62. In the
ideal situation, two adjacent codes are averaged to give an output that falls exactly in
between the outputs of the data converter. In the case where the data converter has a
nonlinearity, the averaged point doesn't necessarily provide an output that is much
different from the data converter outputs themselves. If the data converter contains a

Input signal Input signal

Ideal data converter switching levels

Ideal code level

Actual code level

Averaged
Points
Averaged
Points

Indicates output of the data converter

Ideal situation Nonlinearity in transfer characteristics

Figure 30.62 How ADC or DAC linearity affects averaging.

Chapter 30 Data Converter Modeling 57

missing code (an input difference between two inputs at consecutive sampling times of
1-LSB results in the same output), then the averaging does nothing. If the data converter
is nonmonotonic (an increase in the data converter's input doesn't result in an increase in
its output) then the averaged value is meaningless. Finally, note that an input DC value (a
digital code that isn't changing for the DAC, or an analog voltage that isn't changing for
the ADC) or a value that isn't "busy" (not changing by at least 1 LSB in between sampling
instances) will not benefit from averaging. These topics are discussed further in the next
chapter.
Practical Implementation of Averaging in ADCs
The averaging topology shown in Fig. 30.59 is not practical in most situations. The silicon
area required to implement the extra ADC and DAC generally costs more than is gained
by the reduction in quantization noise. Also, as we'll see later, there are other techniques
for averaging that provide a more efficient way to reduce quantization noise. Having said
this and knowing that there are better ways, we will answer the question "How do we
implement an ADC using averaging?"
Figure 30.63 shows how we can add a digital averaging filter to the output of the
ADC to reduce quantization noise. The ADC and digital averaging filter are clocked at a
rate of fclk . If K = 2, for example, then the filter will sum its previous two inputs and
output the result at a rate of fclk . This filter could be implemented with a register and an
adder. Note that the output word size increases when using the digital filter (it had better
if we are reducing the quantization noise!). For example, if the output of the ADC is an
8-bit word, then the running sum coming out of the filter, again assuming K = 2, will be
9-bits.

Analog Digital
Digital
V IN Ideal Digital
averaging
f clk ADC filter

Figure 30.63 Using a digital averaging filter to reduce quantization noise.

We might, at this point, assume that we can use a low-resolution ADC, say 6-bits,
with a significant amount of averaging to attain large resolutions (again the ADC must be
linear). Assuming the input to the ADC is busy and we place restrictions on the bandwidth
of the signals coming into the ADC then we can increase the resolution by averaging. We
have to place restrictions on the bandwidth of the signal coming into the ADC because,
unlike Fig. 30.59, we haven't increased the sampling rate of the signals. Therefore, the
amplitude of the spectral density remains unchanged. For an averaging of two, we would
have to limit our desired input signal bandwidth to fs /4. If this wasn't the case, then an
input sinewave at fs /2 would average to zero. Again, these topics will be discussed in
greater detail in Ch. 31.
58 CMOS Mixed-Signal Circuit Design

REFERENCES
[1] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS: Circuit Design, Layout, and
Simulation, Wiley-IEEE, 1998. ISBN 0-7803-3416-7
[2] L. W. Couch, Modern Communication Systems: Principles and Applications,
Prentice-Hall, 1995. ISBN 0-02325286-3
[3] S. Haykin, An Introduction to Analog and Digital Communications, John Wiley
and Sons, 1989. ISBN 0-471-85978-8
[4] P. A. Lynn and W. Fuerst, Introductory Digital Signal Processing, Second
Edition, John Wiley and Sons, 1998. ISBN 0-471-97631-8
[5] E. P. Cunningham, Digital Filtering: An Introduction, John Wiley and Sons, 1995.
ISBN 0-471-12475-3
[6] R. K. Hester, Introduction to Oversampled Data Conversion, Notes from a
tutorial at the 1995 International Solid-State Circuits Conference (ISSCC-95).
[7] W. R. Bennett, "Spectra of Quantized Signals," Bell System Technical Journal,
Vol. 27, pp. 446-472, July 1948.
[8] J. C. Candy and G. C. Temes (eds.), Oversampling Delta-Sigma Data Converters,
IEEE Press, 1992. ISBN 0-87942-285-8
[9] S. R. Norsworthy, R. Schreier, and G. C. Temes (eds.), Delta-Sigma Data
Converters: Theory, Design, and Simulation, IEEE Press, 1996. ISBN
0-7803-1045-4
LIST OF SYMBOLS/ACRONYMS
AAF - Antialiasing Filter
ADC - Analog-to-Digital Converter
C H - Hold capacitor in a S/H
DAC - Digital-to-Analog Converter
DFT - Discrete Fourier Transform
DSP - Digital Signal Processing
∆t - Time difference between points used in a DFT
φ - Clock signal
fclk - Frequency of the input clock signal
f in - Input sinewave frequency
f n - Nyquist frequency ( f n = f s /2) which is 50 MHz in this chapter. Sometimes also called
the folding frequency
Chapter 30 Data Converter Modeling 59

f res - Resolution of an DFT

f s - Sampling frequency (T s = 1/f s ) , which is 100 MHz in this chapter. Sometimes also
called the Nyquist rate
H(jω) - Transfer function
H RCFSH ( f ) = Portion of the ideal S/H reconstruction filter
k - Counting index
K - Averaging factor or oversampling ratio
LPF - Lowpass Filter
V REF+ − V REF−
LSB = V LSB = = Least Significant Bit
2N
M - Number of points in the output of an DFT (or order of modulator, see Ch. 32)
n - Counting index
N - Number of bits in a data converter or the number of time steps in an DFT
OTA - Operational Transconductance Amplifier
Qe - Quantization error
RCF - ReConstruction Filter
RZ - Return-to-Zero format
S/H - Sample and Hold
SPICE - Simulation Program with Integrated Circuit Emphasis
ρ - Probability density function
Sinc(x) = Sin(x)/x
θ - Phase of a function
T - period of a periodic waveform
to - A time delay
T s - Sampling interval (T s = 1/f s )
T stop - Final simulation time
V( f ) - Spectral density, V/ Hz
V CM - Common-mode voltage, which is 0.75 V in this book
VDD - positive power supply voltage which is 1.5 V in this chapter
V DFT (n) - Discrete Fourier Transform of V
60 CMOS Mixed-Signal Circuit Design

VOUTD - Difference between an analog input and a digitized output, see Fig. 30.45.
VOUTdB - Output signal in decibels
VINdB - Input signal in decibels
V OUTSH - Output voltage of a S/H
V Qe ( f ) - Quantization Error Spectral Density, V/ Hz
v in (t) - Time domain input voltage
V inbuf - Input signal after buffering
V ins - Input signal after sampling
V LSB - See LSB
Vout - Output voltage
V p - Peak sinewave amplitude
V Qe,RMS - RMS quantization noise voltage
V REF+ - Positive reference used in an ADC or DAC, which is 1.5 V in this chapter
V REF− - Negative reference used in an ADC or DAC which is ground in this chapter
VSS - negative power supply voltage which is 0 V in this chapter
f
j2π f
z = e j2π⋅f⋅Ts = e s

QUESTIONS
30.1 Qualitatively, using figures, show how impulse sampling a sinewave can result in
an alias of the sampled sinewave at a different frequency.
30.2 What does linear phase indicate?
30.3 What does multiplying a signal by e j⋅2πf⋅(−td ) indicate? How does the magnitude of
the resulting signal change? How does the phase change?
30.4 Show, in the time domain, the input/output of the transmission line, and output of
the comb filter in Fig. 30.11 if the input signal is a sinewave with a peak amplitude
of 1 V and a frequency of 100 MHz. Show the two 500 Ω resistors average the
input signal and the output signal of the delay line (transmission line).
30.5 Regenerate Fig. 30.19 if the switches are closed for 5 ns instead of 100 ps.
30.6 What sets the minimum resolution of a DFT in a SPICE spectral analysis?
30.7 Explain why the sinewave in Fig. 30.19 is "double sampled."
30.8 Explain why z is used in signal processing. What does multiplying a signal by z−1 do
to the signal?
Chapter 30 Data Converter Modeling 61

30.9 Sketch the implementation of a circuit that will multiply a digital signal by z−1.
30.10 Sketch the time domain representation of the five signals shown in Fig. 30.29 on
different plots. Regenerate Fig. 30.29 if the input signal is a 1 V peak sinewave at
5 MHz and zero offset. Explain the resulting plot.
30.11 Sketch the input and output spectrum for the following block diagram. Assume the
DC component of the input is 0.75 V while the AC component is a sinewave at 4
MHz with a peak amplitude of 1 V. Assume the clock frequency is 100 MHz.

In Sample and Sample and Sample and Out

hold (S/H) hold (S/H) hold (S/H)

clock

Figure 30.64 Figure used in question 30.11.

30.12 Using the models developed in the chapter design a SPICE model for the S/H of
Fig. 30.31. Use the model to regenerate Fig. 30.29.
30.13 If VREF+ = 1.5 V and VREF− = 0 regenerate Fig. 30.33 using SPICE. (Design a 3-bit
ideal DAC model in SPICE.) The y-axis will be voltages in decimal form.
30.14 If, again, VREF+ = 1.5 V and VREF− = 0, sketch Fig. 30.33 for a 1-bit DAC. Note that
the digital input code will either be a 0 or a 1 and the analog voltage out of the
DAC will be either 0 or 1.5 V. Using Eq. (30.23) what is the voltage value of 1
LSB? How does this compare to the value of 1 LSB we get from the sketch? Is
Eq. (30.23) valid for a 1-bit DAC? Why? The 1-bit DAC will be a ubiquitous
component in our noise-shaping modulators in Ch. 32 (see Fig. 32.28).
30.15 Using SPICE, implement an ideal 4-bit DAC and regenerate Fig. 30.36.
30.16 Why do the transfer curves of Fig. 30.37 show a shift of 1/2 LSB to the left? How
do we implement this shift in SPICE?
30.17 Repeat question 30.16 for an ADC.
30.18 Using the models developed in questions 30.15 and 30.17 with a clock frequency
of 100 MHz apply an input sinewave that has an amplitude of 750 mV peak
centered around 750 mV DC and a frequency of 5 MHz to the input of the 4-bit
ADC. If the ideal 4-bit DAC is connected to the digital outputs of the ADC, also
show the DAC's analog output.
30.19 Using SPICE generate the spectrums of the input and output of the signals in
question 30.18.
62 CMOS Mixed-Signal Circuit Design

30.20 Does an ideal S/H introduce amplitude quantization noise into an input waveform?
Why or why not?
30.21 Why are the amplitudes of the mirror images decreasing with an increase in
frequency in Fig. 30.44b?
30.22 Show the details of the integration in Eq. (30.30).
30.23 How are voltage spectral density, power spectral density (PSD), average power,
and RMS voltage related for a random signal? What are the units of each? Provide
answers for both continuous signals and signals that are only defined at discrete
frequencies.
30.24 How would we convert the voltage spectral density of Fig. 30.48 into a power
spectral density plot? What term in Eq. (30.33) is the PSD? How would we
rewrite Eq. (30.33) to give the average power of the quantization error?
30.25 Repeat Ex. 30.10 if we want to determine the quantization noise power. Show the
simulation results and the commands used to determine this power.
30.26 Derive Eq. (30.43).
30.27 What term is the PSD in Eqs. (30.42) and (30.44)? What are its units?
30.28 Verify, with simulations, Ex. 30.16.
30.29 Verify, using simple circuit analysis, that resistors can be used to implement
averaging as seen in Fig. 30.59 and Eq. (30.45).
30.30 How does averaging K samples of a random voltage variable reduce its RMS
value? How does the power contained in the same variable get reduced by
averaging?
 Chapter

31
Data Converter SNR

In the last chapter we developed the idea of treating an analog-to-digital converter (ADC)
as a noisy circuit block where the output of the ADC is the sum of quantization noise and
the input signal. Logically, the next step in our development of concepts is to characterize
a system using ADCs and DACs in terms of the signal-to-noise ratio (SNR). The ideal
SNR for a data converter was developed back in Ch. 28 and is repeated here for
convenience.
If we apply a sinewave with an amplitude of Vp (and thus an RMS value of
V p / 2 ) to an ADC input then, knowing the RMS quantization noise added to a busy
ADC input signal is V LSB / 12 (see Eqs. [30.30] and [30.32]), the resulting SNR for the
ADC is given by
Vp / 2
SNR ideal = 20 ⋅ log (31.1)
V LSB / 12
If we remember that
V REF+ − V REF−
V LSB = 1 LSB = (31.2)
2N
and we assume that the largest possible amplitude sinewave is the ADC input (to
maximize the SNR), that is,
2V p = V REF+ − V REF− (31.3)
then Eq. (31.1) can be rewritten as
2 N 12
SNR ideal = 20 ⋅ log = 6.02N + 1.76 (in dB) (31.4)
2 2
64 CMOS Mixed-Signal Circuit Design

Our goal in this chapter is to discuss how to determine the actual SNR of a data
conversion system and to present topologies for improving data conversion system SNR
(e.g., averaging, noise shaping, and others).

31.1 Data Converter SNR: An Overview

In this section we describe data converter performance, defining terms such as effective
number of bits, dynamic range, signal-to-noise plus distortion ratio (SNDR), and spurious
free dynamic range (SFDR). This discussion will be useful in understanding where
problems or limitations with data converter performance originate.
31.1.1 Effective Number of Bits
Equation (31.4) relates the number of bits used in a data converter to the ideal SNR when
the input signal is a sinewave that ranges from VREF+ to VREF−. In reality the measured SNR,
in most cases, will be different from the ideal value calculated using this equation. When
an SNR is measured, we relate it to the effective number of bits using
SNR meas − 1.76
N eff = (31.5)
6.02
where the measured SNR (SNR meas ) is specified in dB.

Example 31.1
Determine the effective number of bits for an ADC with V REF+ = 1.5 , V REF− = 0 ,
and a measured V Qe,RMS of 2 mV.
If we assume that the input peak amplitude, Vp , is 0.5 ⋅ (V REF+ − V REF− ) or 0.75 V,
then the measured SNR is given by
0.75/ 2
SNR meas = = 265 = 48.5 dB
2 mV
The effective number of bits, Neff , is (from Eq. (31.5]) 7.76 bits. T
Normally, the measured SNR (SNR meas ) is determined from the RMS quantization
noise, which is determined using Eq. (30.33) with measured data. The amplitude and
frequency of the input sinewave can be selected to maximize the SNR.

Example 31.2
Using the ideal 8-bit ADC and DAC shown in Fig. 31.1, which were developed in
the last chapter, and a sampling frequency of 100 MHz (= f s ) show, using SPICE,
that applying a full-scale sinewave at 24 MHz to this configuration will cause the
resulting SNR to approach the ideal value given by Eq. (31.4).
Let's begin by calculating SNR ideal . From Eq. (31.4), SNRideal is roughly 50 dB, as
the data converters have 8-bit resolution.
The time domain input and output of the circuit shown in Fig. 31.1, and the
corresponding DAC output spectrum, are shown in Fig. 31.2. The input to the
Chapter 31 Data Converter SNR 65

VDD = 1.5 VDD = 1.5

Analog Digital Analog
V IN (24 MHz) 8 V OUT
Ideal Ideal
f s = 100 MHz 8-bit ADC 8-bit DAC

Figure 31.1 Test setup used in Ex. 31.2 to show deviation from ideal SNR.

ADC in Fig. 31.1 is a 24 MHz sinewave with a peak amplitude of 0.75 V centered
on a DC voltage of 0.75 V (the peak-to-peak voltage of the input waveform is 1.5
V). The VQe,RMS measured with SPICE, remembering to zero out the wanted signals
at DC and 24 MHz and the images at 76 MHz, 124 MHz, and 176 MHz before
calculating the noise (see Ex. 30.15), is 1.497 mV. The simulated SNR is
(0.75/ 2 )/1.497 mV or 354 (51 dB), which is very close to the value calculated at
the beginning of the example. T
It's important to understand that poor selection of the input frequency (or
windowing function) can result in an SNR that is different from the ideal value calculated
using Eq. (31.4). Selecting an input sinewave frequency, fin , such that fs /fin is a whole
number creates a condition where an integral number of input sinewave cycles fit perfectly
into the sampling window (coherent sampling). This results in an output spectrum that
contains isolated tones (helping to reduce the effects of spectral leakage on the SNR).

ADC DAC
Input output
Signal plus Noise

(a) (b)
Figure 31.2 Example 31.2 (a) time domain input and output, and (b) spectrum of DAC output.
66 CMOS Mixed-Signal Circuit Design

An additional effect to consider occurs when fin is comparable to fs. The input tone
at fin undergoes amplitude attenuation (−3.9 dB at fn , Fig. 30.29).

Example 31.3
Repeat Ex. 31.2 if the input sinewave frequency is increased to 45 MHz.
The results of increasing the ADC input sinewave frequency in Fig. 31.1 to 45
MHz are shown in Fig. 31.3. Note how the DAC output contains tones at 5 MHz,
10 MHz, 15 MHz, etc., in addition to the desired tone at 45 MHz. The simulated
VQe,RMS is 2.26 mV. The input amplitude of the 45 MHz sinewave is 0.75 V (−2.5
dB). The simulated peak output amplitude at 45 MHz is 0.53 V (−5.5 dB). The
simulated SNR can be calculated
0.53/ 2
SNR= 20 log = 44.4 dB
2.26 mV
or 5.6 dB below the ideal value of 50 dB calculated using Eq. (31.4) for a data
converter with a resolution of 8 bits. T
Signal plus Noise

(a) (b)
Figure 31.3 (a) DAC output with 45 MHz input and (b) the DAC output spectrum.

Signal-to-Noise Plus Distortion Ratio

In a practical data converter the output spectrum contains not only quantization noise but
distortion resulting from nonlinearities and mismatch in the data converter circuitry. When
Chapter 31 Data Converter SNR 67

we calculate the RMS quantization noise voltage using Eq. (30.33) and nonideal
components, we are actually calculating the noise plus the distortion in the spectrum. Up
to this point we have only used ideal components, so that distortion in the output
spectrums was absent. We can rewrite Eq. (30.33) to indicate that when it is used with a
measured spectrum, both noise and distortion are included in the result as
M−1
V Qe+D,RMS = 1
2
Σ V 2DFT (k ⋅ f RES )
k=0
where M = #DFTpoints (31.6)

The signal-to-noise plus distortion ratio is then given by

Vp / 2
SNDR = 20 log (31.7)
V Qe+D,RMS
The effective number of bits, from Eq. (31.5), can then be calculated using
SNDR − 1.76
N eff = (31.8)
6.02

Example 31.4
Suppose that the test setup shown in Fig. 31.1 is used with an input sinewave
having a frequency of 7 MHz, a peak amplitude of 0.75 V, and centered around
0.75 V (so that, once again, the sinewave swings from 0 V to 1.5 V.) Using
SPICE simulation, determine the SNDR if there is a gain error in the ideal ADC in
Fig. 31.1 (it's no longer ideal) so that each stage in the pipeline algorithm used to
implement the ideal SPICE ADC has a gain of 2.1 instead of the ideal 2.0.
The resulting DAC output spectrum is shown in Fig. 31.4. The RMS noise plus
distortion voltage, V Qe+D,RMS , is calculated to be 16.9 mV, using SPICE and
remembering to zero out the desired terms at DC and 7 MHz as well as the
undesired images at 93 MHz, 107 MHz, and 193 MHz. The SNDR is then
0.75/ 2
SNDR = 20 log = 30 dB
16.9 mV
and the effective number of bits is 4.7. In other words, a 5% gain error in the ADC
amplifiers results in an effective resolution of almost half the ideal, 8-bit value. T
Measuring SNDR requires a spectrum analyzer, when looking at the output of a
DAC, or loading digital data (most often in decimal form) into a program that can perform
a DFT (such as WinSPICE [utilizing the load command] or Matlab), when looking at the
output of an ADC. Trying to measure SNDR using a time domain instrument, such as an
oscilloscope, is usually a waste of time because the dynamic range of the instrument is
comparable to the dynamic range of the data converter under test. Spectrum analyzers
utilize narrow band filtering on their input to reduce the inherent noise measured in a
circuit and can have dynamic ranges in excess of 120 dB over a very wide frequency
spectrum. Also note that the SNDR is sometimes abbreviated as SINAD (signal-to-noise
and distortion.)
68 CMOS Mixed-Signal Circuit Design

Spurious-free dynamic range

Signal plus noise and distortion

Figure 31.4 Output spectrum with ADC gain error (see Ex. 31.4).

Spurious Free Dynamic Range

Another specification of interest is the data converter's spurious free dynamic range. This
term relates the peak signal in the output spectrum (the input sinewave or carrier) to the
largest spike in the output spectrum up to the Nyquist frequency. This can be written
using
SFDR(dBc) = input carrier(dB) − unwanted tone(dB) (31.9)
For the spectrum shown in Fig. 31.4, the input sinewave (carrier) has an amplitude of 0.75
V (−2.5 dB), while the largest unwanted tone has an amplitude of −39.5 dB. The SFDR of
this data converter is then 37 dBc.
Dynamic Range
The dynamic range of a data converter can be specified in several ways. We defined
dynamic range back in Ch. 28 as the ratio of the largest output signal change (e.g.,
[V REF+ − 1 LSB]−V REF− ) over the smallest output signal change (1 LSB ). Remembering 1
LSB = (V REF+ − V REF− )/2 N the dynamic range (DR) can be written as
V REF+ − (V REF+ − V REF− )/2 N − V REF−
DR = 20 log = 20 log 2 N = 6.02N (31.10)
(V REF+ − V REF− )/2 N
If a 1,000 to 1 dynamic range (60 dB) is required, then a data converter with at least 10
bits is needed.
Chapter 31 Data Converter SNR 69

Another way to specify DR is as the ratio of the RMS full-scale input sinusoid
amplitude, Vp/ 2 , to the input sinusoid amplitude (RMS) that results in an SNDR of 0
dB. (The RMS amplitude of the input signal is equal to the RMS quantization noise plus
distortion, V Qe+N,RMS , when the SNDR is 0 dB.) This is nothing more than saying that the
SNDR can be used to specify DR.

Example 31.5
Determine the DR for the ideal ADC in Ex. 31.2 using Eq. (31.10). Compare the
result to the SNDR calculated in Ex. 31.4.
Using Eq. (31.10), the DR is 48.16 dB (the ideal value). The SNDR calculated in
Ex. 31.4 was 30 dB. Clearly, the SNDR is a better indication of DR than is the
value obtained using Eq. (31.10). T
Specifying SNR and SNDR
The SNR and the SNDR are usually specified as a function of input sinewave amplitude at
a fixed frequency, Fig. 31.5. The x-axis in Fig. 31.5 is normalized so that an input
sinewave with a peak-to-peak amplitude of V REF+ − V REF− corresponds to 0 dB. We might
be wondering how we differentiate between SNR and SNDR as both, up to this point,
have been calculated in the same way (Eqs. [31.6] and [30.33]). We continue to calculate
SNDR using a data converter output spectrum, remembering to zero out the desired tones
and images, and Eq. (31.6) as was done in Ex. 31.4. When we calculate the SNR, we
follow the same procedure except that now we also zero out any spikes or spurs (spurious
responses) in the spectrum that are "sticking up" above the noise floor in the spectrum.
These spikes come from imperfections in the data converter and result in distortion in the
output waveform. Note in Fig. 31.5 how the SNR and the SNDR coincide until the input
signal amplitude gets reasonably large (so the distortion tones increase in amplitude above
the quantization noise).
Signal-to-noise plus distortion, dB

SNR
SNDR
60

40 V REF+ − V REF−
20

0
-80 -60 -40 -20 0
Normalized input signal amplitude (dB)

Figure 31.5 Specfying SNR and SNDR for a data converter.

70 CMOS Mixed-Signal Circuit Design

31.1.2 Clock Jitter

We might assume that using the ideal data converters developed in the last chapter in a
system with "real world" input and clock signals would give us a resolution (number of
bits) set by the resolution of the ideal data converters used. However, if the clock signal
used isn't ideal, the resolution will be less than ideal. We discussed this problem, aperture
jitter, back in Ch. 28. Here we want to relate the amount of clock jitter to the data
converters SNR and thus the effective number of bits. Clock jitter is the variation in the
period of the clock signal around the ideal value
Figure 31.6 shows the basic problem. In this figure we have assumed the input
sinewave frequency is running at the Nyquist frequency fn (= fs /2 ) so that the sampling
point (when the sinewave crosses zero in this figure) is seeing the fastest transition in the
input signal. We assume the peak amount of jitter in the clock signal is ∆T s . For example,
if the sampling clock frequency is 100 MHz (T s = 10 ns ) and the peak-to-peak clock jitter
is 50 ps (= ∆T s ), then the specification of the sampling clock stability is 5,000 ppm (where
parts per million [ppm] = 10−6 and ∆T s = (stability, ppm) ⋅ (1/f s ) ).

∆T s = peak-to-peak jitter

Ts
V p sin 2πf n t = V p sin πf s t

Error in sampling, ∆V s
t
Ideal
sampling point

Aperture
uncertainty/jitter

Figure 31.6 Data converter input signal and clock jitter.

The slew rate of the signal in Fig. 31.6, at the sampling point (when the clock
signal transitions high), is given by
=1
d V sin πf t = πf V cos πf t = πf V
( p s ) s p s s p (31.11)
dt
We can relate the uncertainty in the sampling instant, ∆T s , to the uncertainty in the
sampled voltage, ∆V s , using
Chapter 31 Data Converter SNR 71

∆V s
= πf s V p , or ∆V s = ∆T s ⋅ πf s V p (31.12)
∆T s
If we require the uncertainty in the sampled voltage, ∆V s , to be at most 0.5 LSB = (VREF+
−V REF− )/2 N+1 and we remember V p = (V REF+ − V REF− )/2 , then our maximum allowable
peak-to-peak clock jitter can be determined for a particular data converter using

∆T s ≤ 1N ⋅ 1 (31.13)
2 πf s
or in terms of the sampling clock stability
∆T s
Stability, ppm = ∆T s ⋅ f s = = 1N (31.14)
Ts π⋅2
Table 31.1 relates the stability requirements placed on a sampling clock for a data
converter resolution, N, if less than 0.5 LSBs aperture error or sampling voltage
uncertainty is required of the data converter.

Resolution, N Stability, ppm ∆T s (max), ps ∆T s (max), ns

If fs = 100 MHz If fs = 44.1 kHz
6 5,000 50 113.4
8 1,250 12.5 28.3
10 312.5 3.125 7.1
12 78.1 0.78 1.77
14 19.5 0.195 0.443
16 4.9 0.05 0.111

Table 31.1 Maximum jitter, ∆T s , for 0.5 LSB sampling uncertainty.

Example 31.6
Suppose a phase-locked loop (PLL) is used to generate a clock signal for a data
converter. If the resolution of the data converter is 10 bits and the frequency of the
sampling clock coming from the PLL is 900 MHz, then specify the maximum jitter
allowed in the output of the PLL. Assume that the maximum sampling error
allowed is 0.5 LSB and that the data converter is sampling a sinewave with a
frequency of 100 MHz.
Because the sinewave being sampled has a frequency below the Nyquist value, Eq.
(31.13) cannot be used directly. Instead, after reviewing the derivation of this
equation, we can rewrite it in terms of any input signal frequency, fin , as

∆T s ≤ 1N ⋅ 1 (31.15)
2 2π ⋅ f in
72 CMOS Mixed-Signal Circuit Design

noting that when fin = fn = fs /2, Eq. (31.15) reduces to Eq. (31.13). Using Eq.
(31.13) with the numbers in this problem results in a peak-to-peak jitter of 1.56 ps!
The reader familiar with PLL design will recognize that this is a very challenging
requirement when designing a PLL (that is, to design a PLL with an output
frequency of 900 MHz and an output jitter of 1.56 ps). T
We're now in a position to answer how, given the peak-to-peak clock jitter ∆T s ,
the SNR of a data converter is degraded from the ideal value (given in Eq. [31.4]) when
the input sampling clock isn't ideal. Rewriting Eq. (31.15) and assuming

∆T s ≥ 1N ⋅ 1 (31.16)
2 2π ⋅ f in
(a resolution loss ≥ 0.5 LSB), we get

∆T s = 1 ⋅ 1 (31.17)
2 N−N Loss 2π ⋅ f in
where fin is, once again, the frequency of the input sinewave, and NLoss is the number of bits
lost due to the excess jitter. Assuming Eq. (31.16) is valid, then when NLoss is zero, the loss
in resolution is 0.5 LSB and Eq. (31.17) reduces to the equality condition in Eqs. (31.15)
or (31.16). The ideal data converter's SNR, assuming the only nonideal factor in the
system is clock jitter, can be written as
effective bits, N eff

SNR = 6.02(N − N Loss − 0.5) + 1.76 (in dB) (31.18)

Example 31.7
For an ideal 8-bit ADC clocked at 100 MHz, determine the SNR of the data
converter with 100 ps of peak-to-peak jitter in the input sampling clock, ∆T s ,
assuming the ADC's input is a full-scale sinewave at 25 MHz.
We can write the number of bits lost by solving Eq. (31.17) as a function of
peak-to-peak jitter as

N Loss = N + 3.32 ⋅ log (2π ⋅ f in ⋅ ∆T s ) assuming ∆T s ≥ 1N ⋅ 1 (31.19)

2 2π ⋅ f in
or
N Loss = 8 + 3.32 ⋅ log(2π ⋅ 25MEG⋅100ps) = 2 bits
The effective number of bits, Neff , is then 5.5 and the SNR is 34.87 dB. T
Using Oversampling to Reduce Sampling Clock Jitter Stability Requirements
Suppose we limit the maximum input frequency coming into an ADC to fin , such that the
sampling frequency is related to the maximum ADC input frequency by
fs fs
= K ⋅ f in = f n or f in = (31.20)
2 2K
Chapter 31 Data Converter SNR 73

In other words, we are getting at least 2K samples for every cycle of the input sinewave. If
we were sampling at twice the Nyquist frequency ( fs ), where K = 1, then we would get
two samples for every cycle of the input signal. Notice that Eq. (31.15) gives the
maximum jitter specification for a given input frequency and data converter resolution, but
it doesn't specify the sampling frequency, fs , or the sampling frequency period, Ts .
For a given maximum jitter, ∆T s , we can reduce the requirements placed on the
stability of the oscillator by increasing the sampling frequency. This can be written as
Stability(new), ppm = [stability(old), ppm] ⋅ K (31.21)
If we were sampling at 1 MHz and the stability required was 10 ppm, then the jitter in the
sampling clock would be at most 10 ps, peak-to-peak. Increasing the sampling rate to 100
MHz, with 10 ps jitter would require an oscillator stability of 1,000 ppm. If we were to
increase the sampling clock frequency to 1 GHz, then the stability of the clock would be at
least 10,000 ppm (the period of the sampling signal is 1 ns and the jitter is 10 ps or 1%
[10,000 ppm] of the sampling period).
Note that the oversampling factor symbol, K, is the same symbol that indicates the
number of samples averaged on the output of a data converter to reduce RMS
quantization noise voltage (see Sec. 30.3.2). The choice of variable was made for a reason
(which will be discussed further in the next section).

Example 31.8
In Table 31.1 we saw that the 16-bit data converter clocked at 44.1 kHz could
have at most 111 ps peak-to-peak jitter to limit the sampling uncertainty to 0.5
LSB. We saw that the stability required of the oscillator under these circumstances
was 5 ppm at 44.1 kHz. What would happen to the stability requirements of the
oscillator generating the sampling clock if we increased the sampling clock
frequency to 128 ⋅ 44.1 kHz= 5.645 MHz ?
We know that the input bandwidth, prior to increasing the sampling frequency, is
limited to 44.1 kHz/2 or 22.05 kHz (= B, the bandwidth of the input signal). We
then assume the maximum input frequency, fin , remains at or below 22.05 kHz
even after we increase the sampling frequency. We can define the oversampling
factor, in this example, as
f s /2 2.822 × 10 6
K= = = 128
f in 22.05 × 10 3
The jitter requirement remains 111 ps whether we use a sampling frequency of
44.1 kHz or 5.645 MHz. However, now that the clock frequency has increased to
5.645 MHz, the stability required of the oscillator has gone from approximately 5
ppm to 640 ppm. T
It's important to note that the oversampling ratio, K, is given by
f s /2 f n
K= = for f in ≤ B (31.22)
B B
74 CMOS Mixed-Signal Circuit Design

If we desire less than 0.5 LSBs aperture error, and we are using oversampling, then we
can use Eqs. (31.13) and (31.22) to write

∆T s ≤ 1N ⋅ K = 1N ⋅ 1 (31.23)
2 πf s 2 2πB
where, once again, B is the bandwidth of the input signal and K is the oversampling ratio.
As shown by this equation and in Eq. (31.21), using oversampling reduces the
requirements placed on the stability of the sampling clock.
A Practical Note
We need to point out that the effects of clock jitter are possible even if the clock is
perfectly stable because of the clock's finite transition times (rise and fall times). If the rise
time of the clock signal in Fig. 31.6 is finite, say 50 ps, then the same derivations and
discussions concerning jitter in the previous section can be applied to determine how the
SNR of the data converter is affected. We would assume the aperture window is a
function of the transition times of the sampling clock signal. The slower the transition
times, the larger the sampling uncertainty. In any practical data converter the SNR, and
thus the effective number of bits, will be reduced because of the clock jitter and finite
transition times as the input signal frequency increases.
Modeling Clock Jitter with SPICE
It's useful in many situations to determine how clock jitter affects a data converter's
performance. Consider the block diagram shown in Fig. 31.7. This is our basic
configuration, used previously, to show data converter operation. Now, however, we have
changed the sampling clock from an ideal pulse source to a source that contains jitter. The
questions we want to answer in this section are "How do we use SPICE to model a jittery
clock source?" and "How does the jitter affect the SNDR of the data converter?"

VDD = 1.5 VDD = 1.5

Digital
8 V OUT
V IN (8 MHz) Analog Ideal Ideal
f s = 100 MHz 8-bit ADC 8-bit DAC Analog

Jittering clock

Figure 31.7 Simulating ideal data converters using a sampling clock with jitter.
To begin, let's consider the single frequency frequency modulation (SFFM) source
available in SPICE. This source generates a frequency modulated (FM) sinewave using the
following syntax
SFFM(VO VA FC MDI FS)

where the parameters describe the following function

V SFFM (t) = VO + VA⋅sin ([2π ⋅ FC ⋅ t] + [MDI ⋅ sin (2π ⋅ FS ⋅ t)]) (31.24)
Chapter 31 Data Converter SNR 75

The modulation index (MDI) will set the peak-to-peak jitter time in the waveform while
the signal frequency (FS) describes the rate at which this jitter varies. The carrier
frequency (FC) will set the clock frequency (FC = 100 MHz in Fig. 31.7). The term VO is
available to add a DC offset to the signal (which we will assume is zero in our discussion),
and the value VA sets the amplitude of the frequency modulated sinewave. The question
we need to answer now is, "How do we convert the FM sinewave generated using Eq.
(31.24) into a squarewave suitable for driving our ADC?"
Figure 31.8 shows that a switch and the SFFM source can be used to generate the
sampling clock with jitter. When the FM source transitions above zero, the top switch
closes and the clock output goes high. When the source transitions below zero, the bottom
switch closes and the clock output goes low.

VDD = 1.5 V

Closed when V > 0

V Clock out
Closed when V < 0 with jitter
SFFM
source

Figure 31.8 Generating a clock with jitter using a switch and an SFFM source.

The average period of the sampling clock generated by the SFFM source is given
by

T s = 1 or f s = FC (31.25)
FC
The peak phase excursion of the clock signal is set by MDI. The peak phase excursion can
be related to the sampling frequency using
∆T s
2⋅MDI = 2π ⋅ (31.26)
Ts
or the peak-to-peak jitter, ∆Ts, is given by

∆T s = 1 ⋅ 2MDI = MDI (31.27)

2π FC πf s

Example 31.9
Using SPICE, generate the output spectrum of an oscillator assuming the oscillator
frequency is 100 MHz and the peak-to-peak jitter is 100 ps. Assume FS = 1 MEG.
We can begin this example by noting FC = 100 MHz and the modulation index is
π ⋅ 100ps⋅100MEG = 0.0314 . The SPICE netlist and the resulting spectrum are
shown as follows and in Fig. 31.9, respectively.
76 CMOS Mixed-Signal Circuit Design

* Figure 31.9 CMOS2: Mixed-Signal Circuit Design *

.tran .2n 10000n 0 .2n UIC
*WinSPICE command scripts
*#destroy all
*#run
*#plot clock xlimit 0 100n
*#plot vclock xlimit 0 100n
*#linearize clock
*#spec 90MEG 110MEG 200k clock
*#plot db(clock)
VDD VDD 0 DC 1.5

Vclock Vclock 0 DC 0 SFFM 0 1 100MEG 0.0628 1MEG

Rclock Vclock 0 100MEG

SH VDD clock Vclock 0 Switmod

SL 0 clock 0 Vclock Switmod
Rload clock 0 100MEG

.model switmod SW
.end
Note that the resolution of the DFT was 200 kHz (set by Eq. [30.35] and that the
signal frequency, FS, was 1 MEG (which sets the spacing between the tones in Fig.
31.9). The period of the 100 MHz clock, in this example, varies sinusoidally from
9.95 ns to 10.05 ns over a time frame of 1 µs (1/FS.) While this spectrum is
interesting, it isn't representative of an actual oscillator where the noise is random.
Peak Signal plus Noise Voltage, dB

Figure 31.9 Spectrum of a sampling clock signal with noise.

Chapter 31 Data Converter SNR 77

While our simple model will never be capable of generating truly random noise, we
can, for a given simulation time, make the simulated spectrum of the oscillator
approach something that looks more realistic (and thus more random over a given
simulation time). Toward this goal, let's attempt to make the oscillator spectrum
more continuous. We can do this by requiring

FS = 1 (31.28)
simulation time
We apply this result in the following example. T

Example 31.10
Repeat Ex. 31.9 if the FS is set using Eq. (31.28).
Using Eq. (31.28) and a simulation time of 10,000 ns, we get an FS = 100 kHz.
Resimulating, using this value of FS, gives the results shown in Fig. 31.10. The
amplitude of the square wave varied from 0 to 1.5 V (varied from 0 to A).
Remembering that the harmonics of the clock (a square wave) have a value of A/2
at DC and a value of 2A/nπ , where n = 1, 3, 5, ... at the other harmonics, we can
calculate the peak amplitude of the fundamental tone in Fig. 31.10 (or Fig. 31.9) as
(2 ⋅ 1.5)/π = 0.955 V or −0.4 dB. T
Peak signal plus noise voltage, dB

Figure 31.10 Oscillator spectrum using Eq. (31.28) to set phase variation time.

Note that a measured spectrum with anomalous spikes would generally indicate
that the noise (the spikes) is not random and could be the result of coupling from an
adjacent circuit. The coupling could be through the substrate or power connections, or it
78 CMOS Mixed-Signal Circuit Design

could be capacitive. If the oscillator jitter is only due to MOSFET noise, in general, no
unwanted spikes will exist in the oscillator's output spectrum.
In the frequency domain the jitter (which is called phase noise) is usually specified
at some offset to the fundamental carrier and taken with reference to the carrier. For
example, at a 1 MHz offset in Fig. 31.10 (at 99 MHz or 101 MHz), the spectrum has a
peak amplitude of approximately −50 dB. The phase noise at a 1 MHz offset would then
be given with reference to the carrier as −50 dB − (−0.4 dB) (the carrier amplitude) =
−49.6 dBc. However, when talking about phase noise, we are generally referring to a
single-tone sinusoid (not a square wave with odd harmonics).
Using Our SPICE Jitter Model
The model we've just developed is difficult to use in a practical simulation because of the
finite step time used by SPICE. For example, if we are trying to model the effects of 100
ps of clock jitter on a data converter's performance, then our step size in the simulation
should be much smaller than 100 ps. This requirement can lead to very long simulation
times or, if the step size is comparable to the simulated jitter, questionable results (see the
example below). Nevertheless, the model is useful in many situations.

Example 31.11
Suppose a 100 MHz sampling clock has 500 ps of jitter. Determine how the SNR
of an ideal data converter will be affected when clocked with this signal. Assume
the topology and input signal of Fig. 31.1 are used.
We begin by using Eq. (31.19) to calculate the number of bits lost
N Loss = 8 + 3.33 log(2π ⋅ 25MEG⋅500p) = 4.3 bits
The SNR of the 8-bit system is determined using Eq. (31.18)
SNR = 6.02(8 − 4.3 − 0.5) + 1.76 = 21 dB
The next factor that we need to determine is the modulation index, MDI,
which simulates 500 ps of jitter. Using Eq. (31.27) we get
MDI = 2π ⋅ 100MEG⋅500p = 0.314
To keep the simulation time relatively short, we'll simulate for 2,000 ns with a step
size of 100 ps. The resolution of the DFT is 1 MHz (set by Eq. [30.35]). The rate
at which the jitter varies is set by Eq. (31.27) and is 500 kHz. The DAC output
spectrum is shown in Fig. 31.11. The simulated V Qe+N,RMS is 93 mV. The SNR is
then given by 20 ⋅ log   0.75/ 2  /93mV  = 15 dB (practically worthless). We see
the simulated SNR is fully 6 dB below the calculated SNR. We may speculate that
this is due to both the jitter we purposely introduced into the clock and the jitter
introduced by the varying step size in the SPICE simulation. When we used a pulse
source to clock our ADC in previous simulations, the jitter was absent because of
the exact timing of the pulse statement and the fact that the rise and fall times were
set by the simulation step size. T
Chapter 31 Data Converter SNR 79

Peak signal plus noise and distortion voltage, dB

Figure 31.11 DAC output spectrum for Ex. 31.11.

31.1.3 A Tool: The Spectral Density

The observant reader may have noticed, in the last section, that we only discussed the
peak-to-peak jitter, ∆T s , and how it affects the data converter's performance. It is very
useful, in many situations, to also have an idea of how the spectrum or spectral
characteristics of the data converter's output change as a function of the random sampling
jitter or a random variable such as noise. In this section we discuss tools useful in
describing the spectrum of a random signal.
The Spectral Density of Deterministic Signals: An Overview
Consider the simple sinewave signal of the form
V in (t) = V p sin 2πf in t (units, V) (31.29)
This signal is termed "deterministic" because the signal has a well-defined shape whether it
is continuous or sampled. We can find the average power of this signal, as a function of
time Rin(t), using the autocorrelation function (ACF) for continuous signals given by
T 0 /2

R in (t) = lim 1 ∫ V in (τ) ⋅ V in (τ + t) ⋅ dτ (units, V2) (31.30)

T 0 →∞ T 0
−T 0 /2

The average value of Eq. (31.29) as a function of time is then

T 0 /2

R in (t) = lim 1 ∫ [V p sin 2πf in τ] ⋅ [V p sin 2πf in (τ + t)]dτ (31.31)

T 0 →∞ T 0
−T 0 /2
80 CMOS Mixed-Signal Circuit Design

or knowing

sin A ⋅ sin B = 1 [cos(A − B) − cos(A + B)] (31.32)

2
we can write
V2p
V 2p ⋅ sin 2πf in τ ⋅ sin 2πf in (t + τ) = [cos 2πf in t − cos 2πf in (t + 2τ)] (31.33)
2
When we integrate this result, the term cos [2πf in (t + 2τ)] represents a sinusoid with a
frequency of 4πf in (remembering our integration variable is τ) and a phase shift of 2πf in t .
Over a long period of time this term averages to zero. Therefore, we can write the average
value of Eq. (31.29) as a function of time (the autocorrelation function)
T 0 /2
V 2p V 2p
R in (t) = lim 1 ∫ ⋅ cos 2πf in t ⋅ dτ = ⋅ cos 2πf in t (units, V2) (31.34)
T 0 →∞ T 0 2 2
−T 0 /2

The spectrum of the average value of a function can be found by taking the Fourier
transform of the autocorrelation function. The result is called the power spectral density
function (PSD) and is given by
∞
 units, V 2 /Hz or V 2 ⋅ s  (31.35)
P in ( f ) = ∫ R in (t) ⋅ e −j⋅2πf⋅t ⋅ dt
−∞
 

The power spectral density function of Eq. (31.29) is then, with the help of Eq. (31.34),
V 2p
P in ( f ) = ⋅ [δ( f + f in ) + δ( f − f in )] (units, V2/Hz) (31.36)
4
This is simply two impulses in the frequency spectrum located at ± fin with an amplitude of
V 2p /4 (V 2 /Hz) . The total average power of this signal is given by
∞ ∞
P AVG =
−∞
∫ P in ( f ) ⋅ df = 2 ⋅ ∫ P in ( f ) ⋅ df (units, V 2/Ω or watts) (31.37)
0

assuming a 1-Ω (normalized) load, which, for Eq. (31.29), is V 2p /2 (V 2 ) .

The voltage spectral density, with units of V/ Hz , is simply the square root of
Eq. (31.35) (that is, the square root of the PSD [= P in ( f ) ]). The root mean square
(RMS) voltage of a signal is given by
∞ ∞
V RMS = P AVG = 2 ∫ P in ( f ) ⋅ df = 2 ∫ (voltage spectral density) 2 ⋅ df (31.38)
0 0

The RMS value of Eq. (31.29) is simply, as one would expect for a sinewave, V p / 2 .
Note the similarity between Eq. (31.38) and Eq. (31.6). The factor of root 2 in Eq. (31.6)
is used because VDFT ( f ), the output of WinSPICE, is the peak voltage at a given
(one-sided spectrum) frequency (and so dividing VDFT [ f ] by 2 results in RMS voltages
as a function of frequency).
Chapter 31 Data Converter SNR 81

Example 31.12
Determine the ACF, PSD, average power, and RMS value of a signal V(t) made up
of three sine waves with peak amplitudes of V1 , V2 , and V3 with frequencies of f1 ,
f2 , and f3 .
Using Eqs. (31.30) and (31.34), the ACF is
V 21 V2 V2
R(t) = cos 2πf 1 t + 2 cos 2πf 2 t + 3 cos 2πf 3 t (units, V 2 )
2 2 2
The PSD (positive frequencies) is determined using Eqs. (31.35) and (31.36)
V 21 V2 V2
P( f ) = ⋅ δ( f − f 1 ) + 2 ⋅ δ( f − f 2 ) + 3 ⋅ δ( f − f 3 ) (units, V 2 /Hz)
4 4 4
The average power, using Eq. (31.37), is
V 21 + V 22 + V23
P AVG = (units, watts)
2
Finally, the RMS value of the signal is given by

V 21 + V 22 + V 23
V RMS = (units, V)
2
Note that if we added phase shifts to our signals the results would be the same; the
phase shift doesn't change the signal's average value, so we get the same results
whether sines or cosines are used in our original spectrum. T
Next, suppose that the sinewave specified by Eq. (31.29) is sampled at a rate of fs
V in (nT s ) = V p sin (2πf in ⋅ nT s ) (31.39)
The ACF for a sampled signal can be written as
N
R in (nT s ) = lim
N→∞
1
(2N + 1) Σ V in (kT s) ⋅ Vin (kTs + nTs )
k=−N
(31.40)

which results in
V 2p
R in (nT s ) = cos 2πf in ⋅ nT s (units, V 2 ) (31.41)
2
The PSD is the Fourier transform of this equation (see Eq. [30.2] in the last chapter),
V 2p ∞
P in ( f ) =
4T s Σ [δ( f − f in + kf s ) + δ( f + f in + kf s )]
k=−∞
(31.42)

The RMS value of the sampled sinewave, Eq. (31.39), assuming we have passed the signal
through an ideal reconstruction filter (RCF) with a bandwidth of fs/2, is simply, once
again, V p / 2 . The PSD of the signal, after passing through the RCF, has an amplitude of
V 2p /4 at frequencies of ± fin.
82 CMOS Mixed-Signal Circuit Design

The Spectral Density of Random Signals: An Overview

Let's use our jitter discussion of the last section to illustrate how to look at the spectrum
of a random signal. We'll do this in two parts: (1) we'll begin by assuming the jitter is a
random variable that falls between two limits and has equal probability of lying anywhere
in the region (just as was assumed for the quantization error probability density function
when calculating the RMS quantization noise voltage in the last chapter), and (2) then
assume the jitter has a Gaussian distribution around some average value (the more
practical and realistic situation) and determine how the output of the ADC is affected.
Consider the representations of clock jitter shown in Fig. 31.12. Trace 1 in this
figure shows the ideal position of the rising edge of a clock signal. This point is
represented on the probability density function (PDF), ρ(t) , at time zero. On the next
rising edge of the clock, trace 2, the edge is a little too early and is represented on the
PDF as shown. We are assuming, probably incorrectly for most practical situations, that
the rising edge of the clock is falling within the peak-to-peak boundaries with the equal
probability of being in the correct position (as shown in trace 1) or at the edge of a
boundary (as shown in trace 4). We also know that the area under the PDF curve in Fig.
31.12 must equal unity, and the average value (also known as the mean or the expected
value and denoted by < y > or y ) of a PDF is given by
∞
Average value, y, = ∫ t ⋅ ρ(t) ⋅ dt
−∞
(31.43)

Example 31.13
Determine the average value of the jitter with the PDF shown in Fig. 31.12.

Trace
1 Ideal clock edge position ρ(t)
Probability density function, PDF
2 Edge too early
5 1 3 4
2
Edge too late 1
3
∆T s

4 Edge at the boundary

−∆T s 0 ∆T s time
5 Edge close to boundary
2 2

Peak-to-peak jitter, ∆T s

Figure 31.12 Clock jitter assuming the edge falls with the same probability
anywhere within the peak-to-peak limits.
Chapter 31 Data Converter SNR 83

We can use Eq. (31.43) to determine the average value of any PDF. Applying this
equation to the PDF shown in Fig. 31.12 results in
∆T s /2
Average value, y, = ∫ t ⋅ 1 ⋅ dt = 0
−∆T 2
∆T s
s

This somewhat obvious result means that the average position of the clock rising
edge is the ideal position indicated by trace 1 in Fig. 31.12. Any PDF that is
symmetrical about some center point will have an average equal to the center
point. T
The variance of the PDF is defined as the average of the square of the signal's
departure from its average value. For a random signal this can be written as
∞

∫ (y − y)
2 2
σ 2 = (y − y) = ⋅ ρ(y) ⋅ dy (31.44)
−∞

where σ is the standard deviation of the PDF (the square root of Eq. [31.44]). For our
purposes, in this book, we can think of variance as the average power of a random
(voltage) signal and the standard deviation as the RMS value of the signal (see Eqs.
[31.37] and [31.38]). Example random signals include the time difference between the
actual edge of a clock and the ideal edge location (jitter), the voltage difference between
the input of an ADC and the ADC's reconstructed output (quantization noise), and the
random fluctuations of electrons due to thermal motion in a resistor (thermal noise).

Example 31.14
Determine the RMS value of the jitter when the jitter has a probability density
function, PDF, as shown in Fig. 31.12.
Using Eq. (31.44) the variance of the jitter PDF is
∆T s /2
(∆T s ) 2
σ2 = ∫ t 2 ⋅ 1 ⋅ dt = 1 ⋅ t 3 ∆T s /2
−∆T s /2 = (seconds2)
−∆T /2
∆T s 3 ⋅ ∆T s 12
s

and thus the RMS jitter is

∆T s
RMS jitter, σ = (seconds)
12
where ∆Ts is the peak-to-peak jitter in the sampling clock rising edge. Note the
similarity to the derivation of VQe,RMS in the last chapter. T
A more useful discussion of jitter can be constructed if we assume the jitter has a
Gaussian PDF, as shown in Fig. 31.13, and attempt to describe how the jitter in the
sampling clock affects an ADC output spectrum with a single-tone input. Using Eqs.
(31.11), (31.12), and (31.15), we can write the sampling error voltage (review Fig. 31.6),
at a given time, as
∆V s (t) = δT s (t) ⋅ V p ⋅ 2πf in ⋅ cos 2πf in t (31.45)
84 CMOS Mixed-Signal Circuit Design

ρ(t)
Probability density function, PDF
∆T s
RMS jitter = σ ≈
6
ρ(t) = 1 ⋅ exp  − t 2 
 
Peak-to-peak jitter ≈ ∆T s σ 2π  2σ 2 

3σ

σ 2σ Time
0

6σ ≈ ∆T s

Figure 31.13 Sampling jitter with a Gaussian probability distribution.

where δT s (t) is a random variable indicating the jitter in the sampling clock at a given
time. (The variable δT s (t) is the time difference between the actual clock transition time
and the expected transition times that are spaced by Ts [see Fig. 31.12].) The peak-to-peak
value of δT s (t) is ∆T s , while its average value is zero. Again, we assume that the jitter
probability distribution function is Gaussian, as seen in Fig. 31.13.
Rewriting Eq. (31.45) using a discrete time step nTs, the sampling error can be
written as
Sampling error amplitude Carrier term

∆V s (nT s ) = δT s (nT s ) ⋅ Vp ⋅ 2πf in ⋅ cos 2πf in nT s (31.46)

We're interested in the spectrum of this error signal as it will add to our RMS quantization
noise plus distortion voltage, effectively lowering the data converter's SNDR. Notice that
the spectrum of Eq. (31.46) will have aliased components (and so will the sampled signal)
so we need to filter out these components above fs /2 (with the reconstruction filter.) Also
note that multiplying the sampling error by the cosine term in Eq. (31.46) simply shifts the
error spectrum to a frequency fin. The cosine terms acts like a carrier in an amplitude-
modulated signal. This is illustrated in Fig. 31.14.

Sampling error amplitude spectrum Data converter output spectral content resulting from jitter

f 0 f in f
0

Figure 31.14 Modulating sampling error with an input sinewave frequency.

Chapter 31 Data Converter SNR 85

Example 31.15
Repeat Ex. 31.7 assuming the clock jitter has a Gaussian PDF.
In this example the peak amplitude of the input signal, Vp , is 0.75 V, the input
frequency, fin , is 25 MHz, and the peak-to-peak jitter is 100 ps. The average
power in the sampling error amplitude spectrum is
2 2
(V p ⋅ 2πf in ) ∆T 2 (V p ⋅ 2πf in )
P AVG,jitter = σ 2 ⋅ =  s  ⋅ (31.47)
2 6 2
or
100 ps  2 (0.75 ⋅ 2π ⋅ 25 MHz) 2
P AVG,jitter =   ⋅ = 1.93 × 10 −6 V 2
 6  2
while the RMS voltage associated with this error is 1.39 mV. The quantization
noise associated with this 8-bit data converter is
V LSB V REF+ − V REF−
V Qe,RMS = = = 1.69 mV
12 2 N 12
The RMS noise voltage due to clock jitter and quantization effects is then given by
1.39 2 + 1.69 2 mV = 2.1 mV
We can calculate the SNR using
0.75/ 2
SNR= 20 ⋅ log = 48.1 dB
2.1 mV
giving an effective number of bits, from Eq. (31.5), equal to 7.7. Note that this is a
significant improvement over what was calculated in Ex. 31.7, where the jitter
variation was always the peak-to-peak value. T
The PSD of the sampling error amplitude, described by Eq. (31.46), can be
determined with the help of Eq. (31.37)
2 ∞
(V p ⋅ 2πf in )
σ2 ⋅ = 2 ∫ P jitter ( f ) ⋅ df (31.48)
2 0

If the spectrum of the phase noise due to jitter is narrow, as seen in Fig. 31.14, then the
spectral density of the sampling error, Pjitter( f ), is concentrated around the frequency of
the input sinusoid. However, if we assume the phase noise spectrum is white and evenly
distributed throughout the base spectrum (so that we integrate Eq. [31.48] from DC to
fs/2), we can write
2
2 (V p ⋅ 2πf in )
P jitter ( f ) = σ ⋅ (31.49)
fs 2
The power spectral density of the sampling error voltage, assuming even distribution of
the noise throughout the base spectrum, is shown in Fig. 31.15.
86 CMOS Mixed-Signal Circuit Design

P jitter ( f ), V 2 /Hz
2
σ 2 ⋅ (Vp ⋅ 2π ⋅ f in )
fs 2

0 f s /2 f

Figure 31.15 Sampling amplitude error PSD assuming sampling error spectrum is white.

Specifying Phase Noise from Measured Data

It's important to note that we have been discussing clock signals that are square waves
(that is, have odd order harmonics) and so discussing jitter (a time-domain term) is,
generally, more appropriate than discussing phase noise (a frequency domain term).
However, because the terms are both widely used to indicate the same, basic, effect (a
variation in the period of a periodic waveform), we will briefly discuss phase noise
specification from measured oscillator data.
Consider the representation of a measured oscillator spectrum (power spectral
density) shown in Fig. 31.16. In general, oscillator noise is specified in terms of the carrier
voltage (or power) with units of dBc (decibels with respect to the carrier). The ratio of the
power of the fundamental (called the carrier or sampling clock) at fs is taken to the noise
power in a bandwidth at some offset from the fundamental
10⋅log  V 2 
10⋅log  V 2 /Hz 
 f H1

Phase noise, dBc/Hz = 10 ⋅ log  ∫ P osc ( f ) ⋅ df  − 10 ⋅ log P( f s ) (31.50)
f 
 L1 
where the first term is the noise power at an offset from fs.

P osc ( f ), V 2 /Hz

0 fs f
f L1
f H1
Figure 31.16 Measured oscillator spectrum.
Chapter 31 Data Converter SNR 87

31.2 Improving SNR using Averaging

We first introduced the concept of averaging back in Sec. 30.3.2 to reduce the RMS
quantization noise voltage. In this section we'll continue this discussion showing that the
SNR of a data converter can be improved by using averaging provided the data converter
is linear to within the resolution of the improvement, the input signal is bandlimited, and
the input signal is busy (not a DC signal).
31.2.1 Using Averaging to Improve SNR
Recalling that averaging K outputs from a data converter with a busy input results in an
RMS quantization noise voltage (see Eq. [30.48]) of
V
V Qe,RMS = 1 ⋅ LSB (31.51)
K 12
we can now, with the help of Eq. (31.1), write the ideal signal-to-noise ratio using
averaging as
SNR ideal = 6.02N + 1.76 + 10 log K (31.52)
where N is the number of bits (the resolution) of the data converter whose output is being
averaged. Using no averaging, that is K = 1, results in Eq. (31.52) simplifying to Eq.
(31.4). Averaging two samples causes the SNRideal to increase by 3 dB or the effective
resolution of the data converter to increase by 0.5 bits. The increase in resolution due to
averaging can be written as
10 log K
Increased resolution, N Inc = (31.53)
6.02
Figure 31.17 shows how averaging the output of a data converter changes the effective
resolution of the data converter. Note that the increase in resolution is based on the
following assumptions: a busy input signal, the input signal is bandlimited, and the data
converter is linear to the final resolution (data converter resolution, N, + improvement in
resolution, NInc) coming out of the averaging circuit.

Improvement in resolution, N Inc

(bits added)
SNR ideal = 6.02(N + N Inc ) + 1.76

5.00

3.33

1.67

0
1 10 100 1k K Number of points averaged

Figure 31.17 Using averaging to improve data converter resolution.

88 CMOS Mixed-Signal Circuit Design

Spectral Density View of Averaging Revisited

We know, from our previous discussions, that if the quantization noise is random, we can
determine its spectral density using
∞
V LSB
σ= = 2 ∫ P Qe ( f ) ⋅ df (31.54)
12 0

where P Qe ( f ) is the quantization noise power spectral density. Also, from the last chapter
we can write
2
P Qe ( f ) = [V Qe ( f )] (31.55)
We might think that if the quantization noise is white (Bennett's criteria hold, so
there is no correlation from one data converter output sample to the next) then the
spectral content of the noise is spread evenly in frequency from zero to infinity (P Qe [ f ] is
a constant with frequency). This would also mean that P Qe ( f ) approaches zero, from Eq.
(31.54), in order to make the average power, that is, the variance (σ 2 ), of the quantization
noise equal to (V LSB ) 2 /12 .
Before we address this concern (our spectral density approaching zero), let's
review how we calculated the RMS quantization noise voltage, V Qe,RMS , from the
spectrum given in Fig. 30.48 back in Ch. 30. In this figure we looked at the entire
spectrum (or most of the spectrum, up to 200 MHz or 2fs , where significant spectral
content is found) to determine V Qe,RMS (see Ex. 30.11 and the discussion concerning the
figure). We know that the quantization noise doesn't experience aliasing since quantization
occurs after sampling. So while it is correct to look at a wide spectrum to calculate noise,
it would be more useful to limit our view of the spectrum to frequencies up to the Nyquist
frequency (= f n = f s /2) , where our desired signal spectrum should reside. We can do this
by assuming the entire quantization noise power lies in the base spectrum or
fs /2
V 2LSB
12
=2 ∫ P Qe ( f ) ⋅ df (31.56)
0

or
2
V
P Qe ( f ) = 1 ⋅ LSB (31.57)
f s 12
The PSD of the quantization noise is plotted in Fig. 31.18. Note the similarity to Fig.
30.57 (the voltage spectral density of the quantization error).
Consider the result of adding two consecutive ADC outputs as shown in Fig.
31.19. A simple sum will be considered the average of the two consecutive ADC output
signals. The finite digital output word length, in this case 8 bits, can limit the resolution of
the resulting sum. In the cases where we do need to do a division by two we could simply
use the top eight bits of the sum (a shift-right operation). In most of the discussions
related to digital words in this book, averaging will be equivalent to addition. The current
Chapter 31 Data Converter SNR 89

P Qe ( f ), V 2 /Hz

V 2LSB
12 ⋅ f s

f n = f s /2 f

Figure 31.18 Quantization noise power spectral density.

time sample coming out of the ADC is labeled x(nT s ) , while the previous ADC output is
x[(n − 1)T s ] . The output of the simple digital averager is
y(nT s ) = x(nT s ) + x[(n − 1)T s ] (31.58)
remembering that Bennett's criteria must be valid for averaging to effectively reduce the
quantization noise. For example, applying a DC input signal to the circuit of Fig. 31.19
will not result in higher accuracy (the output of the averager will remain the same as the
output of the ADC [actually the averaged output is twice the ADC output]). We'll discuss
this restriction in more detail in a moment when we discuss adding a dither or pseudo
random noise signal to the input to randomize the quantization noise (make its spectrum
white). Also note that there are restrictions on the allowable range of input frequencies
when using this configuration to avoid amplitude distortion. For example, if f in is 50 MHz
(with f s = 100 MHz ), then it's easy to show that the resulting digital averager output is
zero (see Fig. 31.20).

Analog
Simple digital averager.
V IN = V p sin (2πf in ⋅ t) 8
Ideal x[nT s ]
f s = 100 MHz 8-bit ADC
y[nT s ]
9
Digital Digital Output
(averaged)
8 Eight 8
latches x[(n − 1)T s ] Adder

Figure 31.19 Using two paths to average the quantization noise.

Let's show that the digital averager of Fig. 31.19 can be thought of as a filter and
look at how passing the ADC output through the averager affects the ADC's signal plus
quantization noise and distortion output spectrum. This will also tell us how we have to
restrict the input frequencies applied to the ADC to avoid amplitude distortion or
something similar to what's shown in Fig. 31.20.
90 CMOS Mixed-Signal Circuit Design

V in (t) These two points average to zero

time
20 ns 40ns

Figure 31.20 The limitations placed on ADC input frequency when using averaging.

Consider the redrawn (Fig. 31.21) z-domain version of the digital averaging filter
of Fig. 31.19. The filter's transfer function can be found directly from Fig. 31.21 or by
taking the z-transform of Eq. (31.58) as
Y(z)
H(z) = = 1 + z −1 (31.59)
X(z)
f
j2π f
Remembering from Eq. (30.12) that z = e s we can write
real imaginary

f in
−j2π f  f in   f in 
H(z) = 1 + e s = 1 + cos −2π + j⋅sin −2π (31.60)
 fs   fs 
Taking the magnitude of this equation results in
2 2
  f in     f in  
H(z) = 1 + cos  2π  + sin  2π  (31.61)
  fs     fs  

or simplifying and changing the notation to H( f ) with f = f in

  f 
H( f ) = 2 1 + cos  2π  (31.62)
  fs  
and the phase is given by
 −sin  2π f  
  fs  
−1
∠H( f ) = tan   (31.63)
 1 + cos  2π f  
  f s  

X(z)

Y(z)
ADC output Simple digital filter Output

z −1 X(z)
z −1

Figure 31.21 Z-Domain representation of the averager shown in Fig. 31.19.

Chapter 31 Data Converter SNR 91

Referring to Ex. 30.4 of the last chapter the phase can be written as
f
∠H( f ) = −π ⋅ (units, radians) for f < f s /2 (31.64)
fs
The magnitude and phase responses of this simple digital filter are shown in Fig. 31.22.
Note that this is the discrete version of the comb filter discussed in Ex. 30.4. Also note
that (1) the phase response is linear, (2) the response is periodic (as is the response of any
digital filter), and (3) at an input frequency of half the Nyquist frequency, f s /4 , the
magnitude response is 2 (3 dB down from the DC gain of two).

∠H( f )
H( f ) 2 degrees
90
2 f in (Hz)

-90
f s /4 f s /2 fs 3f s /2 f in (Hz) f s /2 3f s /2

Figure 31.22 Magnitude and phase response for the simple digital filter of Fig. 31.21.

We can also see that (1) averaging results in an attenuation of many of the input
signal frequencies (as shown in Fig. 31.22) and (2) indeed the average of the input signal
goes to zero, as was shown in Fig. 31.20, when the input signal frequency is f s /2.
If we assume the output quantization noise power spectral density, P Qe ( f ) , for the
ADC shown in Fig. 31.19 is white then the output of the simple digital filter has the PSD
shown in Fig. 31.23 (the product of the filter response squared with the noise PSD). The
average power contained in this PSD is
f s /2
V2LSB   f 
P AVG = 2 ∫0 12 ⋅ f s
⋅ 2 1 + cos  2π  df
  fs  
(31.65)

P Qe ( f ), V 2 /Hz

V 2LSB
3 ⋅ fs

f n = f s /2 f

Figure 31.23 Quantization noise power spectral density after averaging two samples.
92 CMOS Mixed-Signal Circuit Design

or
f = f /2
V 2LSB V 2LSB  f s V2
P AVG = +  sin 2π  = LSB (31.66)
6 6π  fs  f = 0 6

The power in an input sinewave before averaging is V 2p /2 (the RMS voltage of the
sinewave is V p / 2 ). Averaging (adding) two samples results in an increase in the desired
signal amplitude by two and so the power increases to 2V 2p (the RMS voltage increases to
(2V p )/ 2 ). This is important because now the SNR, on the output of the digital averaging
filter, is
2V p / 2 Vp / 2
SNR= 20 log = 20 log (31.67)
V LSB / 6 V LSB / 24
or in terms of a generic averaging constant K (see Eqs. [31.51] or [30.48]), the effective
RMS quantization noise voltage is
1 V LSB
V Qe,RMS = ⋅ (31.68).
K 12
Without rederiving the equations presented at the beginning of this section, we should see
how averaging affects a data converter's SNR.
An Important Observation
Equation (31.68) assumes the averaging filter does not attenuate the input signal. If, for
example, the input frequency were f s /4 , then the RMS amplitude of the desired signal
would change from (2V p )/ 2 to  V p ⋅ 2  / 2 or simply V p (because of the root two
gain at f s /4 , as shown in Fig. 31.22) and the SNR would be the same as the output of the
ADC in the nonaveraged circuit. If the input frequency were greater than f s /4 , then the
SNR would actually be worse than the nonaveraged SNR! Therefore, we have to restrict
the input frequency bandwidth, B, to frequencies less than f s /4 when averaging two terms
in order to avoid degrading the data converter's SNR. In general, for an arbitrary number
of averages K, we can write the restrictions on the input bandwidth using
f s /2 f n
B= = and f in ≤ B (31.69)
K K
We have already presented this equation (Eq. [31.22]) when discussing how oversampling
affects sampling clock jitter stability requirements. The averaging factor K is commonly
called the oversampling ratio to denote the ratio of the Nyquist frequency to the input
signal bandwidth. This can sometimes be confusing since, as we showed in the last
chapter, oversampling an input waveform alone, without averaging, does not lower the
amount of quantization noise in a data converter's output spectrum. Nevertheless, stating
that a data converter is using oversampling is synonymous with stating the data converter
employs an averaging filter. The averaging filter used on the output of an ADC is called a
Chapter 31 Data Converter SNR 93

decimating filter while the reverse averaging filter used on the input of a DAC is called an
interpolating filter. We will discuss these filters in detail in the next sections.

Example 31.16
Suppose the input sinewave in Fig. 31.19 has a peak amplitude of 0.5 V and a
frequency of 20 MHz. Determine the peak amplitude of the averager output and
the delay through the circuit. Comment on any assumptions made.
Using Eq. (31.62) we get

H( f ) = 2  1 + cos  2π 20   = 1.62
 100 
and so the peak amplitude of the output sinewave is 0.5 ⋅ 1.62 = 809 mV . Ideally,
the amplitude out of the averager is twice the input or, in this case, 1 V.
The delay through the filter is determined using Eq. (31.64) and knowing
Phase shift
f
2π ⋅ f ⋅ ∆t = −π
fs
The constant delay (knowing the minus sign indicates the output of the filter
occurs after, or later in time than, the input signal) can then be written as
T
∆t = 1 = s (31.70)
2f s 2
and so, for this example, ∆t = 5 ns .
Note that we are not discussing the effects of quantization noise, that is, the
fundamental minimum voltage that can be resolved. We are assuming continuous
amplitude signals throughout the system in order to simplify the filter calculations.
This assumption falls apart if, for example, the peak-to-peak amplitude of the input
sinewave is reduced to a value below one least significant bit. This will cause the
circuit to function as if the input were a DC signal. T
Jitter and Averaging
We can apply the averaging discussion just developed directly to the jitter discussion
presented earlier in the chapter and answer the question, "How does averaging affect the
sampling amplitude error power (resulting from jitter) in a data conversion system?" If we
assume that the jitter has a Gaussian PDF, then the average power in the sampling error
amplitude, from Ex. 31.15, is
2
 Vp 
P AVG,jitter = σ ⋅ ⋅ 2πf in  (31.71)
 2 

where σ is the standard deviation of the jitter (see Fig. 31.13). It may be helpful to rewrite
Eq. (31.68) in terms of the quantization error power as
94 CMOS Mixed-Signal Circuit Design

2
V
P Qe,AVG = (V Qe,RMS ) = 1 ⋅ LSB
2
(31.72)
K 12
and apply the same derivation to Eq. (31.71) to give
2
 Vp 
P AVG,jitter = 1 ⋅  σ ⋅ ⋅ 2πf in  (31.73)
K  2 
This equation shows that the sampling error amplitude power, PAVG,jitter, introduced into the
data converter's output spectrum decreases with averaging. Averaging two samples causes
the sampling error amplitude power to decrease by 3 dB. This effectively reduces the jitter
requirements placed on the sampling clock. While this may not appear to be very
significant at first glance, consider what happens if, for example, 256 samples are averaged
(K = 256 ). The sampling error power decreases by 24 dB, making clock jitter, when using
a reasonably stable oscillator, almost not an issue. Also note that a doubling in the jitter's
standard deviation, σ , results in a 6 dB increase in sampling error amplitude power.
Relaxed Requirements Placed on the Antialiasing Filter
The use of averaging will also lead to relaxed requirements of the antialiasing filter (AAF).
Figure 31.24a shows the requirements placed on the AAF without averaging. As we saw
in the last chapter, ideally, the transition from the 3 dB frequency to the "stop frequency"
or Nyquist frequency should be infinitely sharp (the filter should abruptly change from a
gain of unity to a gain of zero [something small]). When using averaging, Fig. 31.24b, we
have to limit our desired input signal bandwidth to B; see Eq. (31.69). The rolloff of the
filter in part (b) of the figure can be much more gradual and in many cases a simple, single
pole, RC filter is all that's needed for an AAF. Also, our averaging filter will attenuate the
ADC output spectrum, as seen in Fig. 31.22, and help to remove input signal power above
f s /2K . The significance of this will be easier to see as the number of points averaged
increases and our averaging filter's response gets sharper with more attenuation (as
discussed in the next section). Of course, the penalty for the relaxed requirements of the
AAF is reduced signal bandwidth for a fixed sampling frequency.

H( f ) H( f )
f 3dB B = f s /(2K)

1 1

f n = f s /2 f f n = f s /2 f
(a) (b)
Figure 31.24 (a) AAF requirements without averaging, and (b) AAF requirements with averaging.
Chapter 31 Data Converter SNR 95

Data Converter Linearity Requirements

Consider the cases for averaging ADC outputs shown in Fig. 31.25. In part (a) we show
the ideal situation where the black dots indicate two consecutive outputs spaced by one
LSB (time is not shown in this figure). The ADC outputs in part (a) are located on the
ideal levels, while the averaged output falls exactly in the middle of these levels (and hence
our increased resolution).
Part (b) of this figure shows the situation where the ADC outputs are shifted
downwards by 0.5 LSBs from their ideal levels. Following this offset, the averaged point
shifts downwards as well. In part (c) the top output of the ADC (the top black dot) is
shifted downwards by 0.5 LSBs and so the averaged point shows a 0.25 LSB offset from
its ideal position. While we used a single LSB difference to show averaging, we could use
any number of LSBs to show that the ADC accuracy must be equal to or better than the
desired final digital filter output accuracy.
The number of bits in the ADC (its resolution) N, and the number of bits
improvement in resolution after filtering, NInc , are used with the final, total number of bits
(the number of bits coming out of the digital filter) to give
N Final = N + N Inc (31.74)
The ADC output should ideally change in increments of the exact LSB voltage. In reality,
the changes will be different from the ideal output levels (as just discussed). In order to
achieve an increase in the number of final bits, the output of the ADC must be accurate (its
actual levels must be spaced from the ideal levels) to within
V REF+ − V REF−
± = ± (0.5 LSB) ⋅ N1 (31.75)
2 N Final+1 2 Inc
where no averaging (NInc = 0 and K = 1) means the ADC is at least 0.5 LSBs accurate.
This is a significant limitation when using averaging to increase the resolution of an ADC.

ADC output 1

Ideal level 0.5 LSB

Averaged point DNL
1 LSB 1 LSB 1 LSB
Averaged point

ADC output 2 Averaging two points (nonideal)

DNL of 0.5
Averaging two points (ideal)
(c)
(a) Averaging two points (nonideal)
offset of 0.5
(b)
Figure 31.25 Linearity requirements when averaging.
96 CMOS Mixed-Signal Circuit Design

This is especially true when a resolution greater than 10 bits is desired with INL and DNL
less than ± 0.5 LSBs. Later in the chapter, and in the next chapter, we will look at
feedback topologies that may relax the accuracy requirements placed on the ADC and
allow averaging to more effectively remove quantization noise.

Example 31.17
To illustrate the requirements placed on the accuracy of the original ADC in more
detail, consider averaging 16 consecutive ADC output samples: 15 at a digital
code of zero and one at a digital code of 1 LSB. Determine the accuracy required
of the ADC, the size of the word coming out of the averaging filter assuming the
ADC is 8 bits, and the final word size after considering the increase in resolution.
The ideal output of the digital filter will be 1/16 of the original ADC's LSB. We
can write this as
16 consecutive ADC outputs

Average = 1 + 0 + 0 + ... + 0 ⋅ (Original LSBs)

16
where 1 is a data converter output of 00000001 and 0 is 00000000. Averaging 16
sample points from Eq. (31.53) will give an increase in resolution of 2 bits.
(Getting only a 2-bit increase may be tough to see using only a single LSB
difference in the ADC outputs but may be easier to see if the codes are different by
several LSBs.) Because the ADC is 8 bits, the final resolution will be 10 bits.
(Note that an increase in resolution of 1.5 bits would also require a 10-bit word.)
However, if we add 16 8-bit words (where the value of the words, in the general
case, can range from 00000000 to 11111111), we end up with a 12-bit word size.
To get to our desired 10-bit word size we throw out the lower 2 bits. Another way
of stating this is that we divide the 12-bit word by four (shift right two times to
remove the lower two bits in the word). Here, where only one ADC output of the
16 is 00000001, the output of the averaging filter would end up being
0000000000. We would need to see at least four ADC outputs of 00000001 in
order to see the 10-bit filter output go to 0000000001. If the input is busy, we will
unlikely have the case where only one of the 16 filter inputs is 00000001 and the
other inputs are 00000000. (More on this below in the dither discussion.)
The INL and DNL of the ADC must be less than ± 0.125 LSBs (8-bit LSB),
from Eq. (31.75), in order for the output of the filter to be ± 0.5 LSBs accurate (a
10-bit LSB).
Note that an ADC output of all ones, that is, 11111111 (255) corresponds to
an analog voltage of VDD − 1 LSB where 1 LSB = (V REF+ − V REF− )/256
(VDD − 1 LSB =255 ⋅ 1 LSB) . The maximum output of the filter, after averaging
16 ADC output samples, is (16 ⋅ 255)/4 = 1111111100 (1020) or, in terms of a
voltage, 1020 ⋅ 1 LSB where 1 LSB = (V REF+ − V REF− )/1024 . In both cases an
output of all zeroes corresponds to V REF− and, also in both cases, the maximum
analog output voltage is V out = 0.9961 ⋅ (V REF+ − V REF− ) . T
Chapter 31 Data Converter SNR 97

Example 31.18
Specify the accuracy required of an 8-bit ADC if it is to be used with oversampling
to attain 12 bits with INL and DNL of ± 0.5 LSBs.
The increase in the number of bits, NInc , is 4. The accuracy required of the 8-bit
ADC, from Eq. (31.75), is ± (1/32) of an LSB. If VREF+=1.5 V and VREF−= 0 then
the LSB of the ADC is 5.86 mV. The output of the ADC must be within ± 183 µV
of the ideal ADC output levels in order to arrive at a final, after averaging,
resolution of 12 bits (with a 12-bit accuracy of ± 0.5 LSBs). Also, according to
Eq. (31.53), we will have to average 256 consecutive ADC outputs to get a 12-bit
output. T
Adding a Noise Dither to the ADC Input
Our assumption, when discussing the benefits of averaging or calculating the spectral
density of the quantization noise, falls apart for DC or slow-moving signals (the ADC
input is not "busy"). To solve this problem consider adding a noise signal to the ADC
input that has a frequency content that falls within the range
fs fs
≤ f < (31.76)
2K 2
so that it can be filtered out with the averaging filter. This noise is often called dither (a
state of indecision or agitation) because it helps to randomize the spectral content of the
quantization noise making it white (a flat spectrum, see Fig. 31.18).
Figure 31.26 shows the basic idea. In part (a) a DC signal is applied to the ADC
that falls halfway between two ADC transition codes spaced apart by 1 LSB. The output
code of the ADC remains unchanged with time. In part (b) a noise signal is added to the
DC input which has two benefits: (1) the quantization noise (the difference between the
input signal and the reconstructed ADC output code) changes with time, and (2) the
output of the ADC has some variation which makes it possible to determine the DC
voltage after averaging.

ADC Output code N

1 LSB

DC Input signal

ADC Output code N-1

(a) (b)

Figure 31.26 (a) DC input signal and (b) DC input signal with dither added.
98 CMOS Mixed-Signal Circuit Design

We can add the noise signal to our desired input signal with a circuit similar to
what's shown in Fig. 31.27. Simple resistors add and reduce the noise signal to the ADC
input. The noise signal source is, most easily, derived from some sort of asynchronous
logic circuit and has a peak amplitude (before reduction) of VDD (= 1.5 V in this chapter).
In this figure note that we have indicated that the dither signal amplitude should be
approximately 0.5 LSB RMS (remembering the signal is, ideally, random and bandlimited
as specified by Eq. [31.76]). This number, 0.5 LSB RMS, is subjective, and no exact rules
as to its selection can be given other than the desire that the peak-to-peak amplitude be
greater than 1 LSB. One disadvantage of adding the dither is that the allowable range of
input signals shrinks (a DC signal at VDD − 1 LSB will not benefit from dithering since
the ADC will be at its full-scale output).

Input with dither Input with dither

Input Input 50
ADC ADC

5,000
Dither Approximately 0.5 LSB RMS dither Dither
noise 0 to 1.5V generating
source digital
circuit
Block diagram
Circuit implementation
Figure 31.27 Adding dither to an ADC input signal.

Before we discuss the implementation of a dither source, consider one possibility

(a Gaussian PDF) for the desired probability density function (PDF) of the dither signal
and DC input shown in Fig. 31.28 (the input to the ADC). If we average this signal over a
long time, we get the average or DC input signal since the dither averages to zero. This

ρ(t)
Probability density function, PDF

1 ⋅ exp  − (V in − V in ) 
2
ρ(t) =  
RMS dither = σ = 0.5 LSB σ 2π  2σ 2 

Amplitude variation
with time
σ = 0.5 LSB Volts

DC in, V in
Figure 31.28 Input to the ADC, dither and DC, with a Gaussian probability distribution.
Chapter 31 Data Converter SNR 99

would also mean that we can have some dither spectral content below f s /2K as long as
we average enough ADC output samples to make its contribution to the SNDR small. It
is generally a good idea to use Eq. (31.76) as a guide for allowable dither spectral content.
Finally, it's important that any dither signal we generate has a symmetrical PDF (the dither
signal must average to VDD/2 before amplitude reduction). If not, an unknown DC offset
(the known DC offset is the VDD/2 attenuated by the resistive divider in Fig. 31.27) in the
data converter's (actually the filter's) output will result.
An example of an implementation of a dither noise source is shown in Fig. 31.29.
The outputs of the rows of inverters, which are tied together, will occur asyncronously
and fight against each other causing the amplitude of the dither signal to occupy levels
other than the normal logic levels of VDD and ground for significant amounts of time. The
dither signal can be made more random by adding more rows of inverters. The challenge
to this design is setting the number of inverters used in each row so that the spectral
content falls within the desired range (which may require a large number of inverters) and
keeping the output of the dither circuit uncorrelated with the sampling clock. Other
techniques for generating random noise, such as using linear serial feedback registers, can
be found in most books covering communication systems.

Dither
out

Figure 31.29 One possible implementation of a dither circuit.

The Z-plane
It will be very helpful in our discussion of mixed-signal circuits and systems to gain an
intuitive feel for the frequency response of a discrete-time system by looking at the
z-domain representation of the system. Toward this goal, consider the transfer function of
the simple digital averager depicted in Figs. 31.19 and 31.21 with a z-transform of

= 1 + z −1 = z +z 1
Y(z)
H(z) = (31.77)
X(z)
Y(z) is the system's output, while X(z) is the system's input. Note that the system is
discrete in time but not necessarily in amplitude. We can apply the z-transform to
switched-capacitor circuits with continuous-valued amplitudes as well as to data
converters with quantized values of amplitude. It is very useful, for an intuitive
100 CMOS Mixed-Signal Circuit Design

understanding of the frequency response of a discrete system, to plot the transfer function
in the z-plane (Fig. 31.30). Figure 31.30 also shows how Eq. (31.77) can be displayed on
the z-plane. A pole is located at z = 0 (at the location the denominator goes to zero and
the transfer function goes to infinity) and a zero is located at z = −1 (at the location where
the numerator goes to zero).

f Imaginary
j2π⋅ f
z=e s
z-plane
Indicates a pole 1
Indicates a zero
6
Indicates six poles at a location
2
Indicates two zeroes at a location Real

Unit circle indicates the

magnitude of a z-domain signal 1
is unity.

Figure 31.30 The z-plane.

The z-plane is usually used to describe the frequency response of a discrete time
system, H( f ), by assuming the input to the system is a unit magnitude sinusoid with
f
j2π f
varying frequency, f. This input, 1 ⋅ e s ( = z) , evaluates the output of the system or
phase
magnitude
f
j2π f
H( f ) = H(z) evaluated when z = 1 ⋅ e s (31.78)
We should now see that the unit circle, shown in Fig. 31.30, indicates the relationship
between z and f when specified by Eq. (31.78). Therefore, to determine H( f ) from a plot
of H(z) on the z-plane, we simply evaluate H(z) along the unit circle. To show how this
transfer function evaluation is performed, consider Eq. (31.77) and the corresponding plot
of its pole and zero shown in Fig. 31.30 along with the magnitude of Eq. (31.77) or Eq.
(31.59) plotted against the frequency in Fig. 31.22. At DC ( f = 0 and z = 1 ⋅ e 0 = 1∠0)
point A in Fig. 31.31, the gain of the circuit is two and is calculated using

H( f ) = distance to zero (31.79)

distance to pole
The distance from the zero to point A is 2 while the distance between the pole to point A
is 1. Therefore, as shown in Fig. 31.22, the magnitude of H( f ) is 2. The phase of the
transfer function is calculated along the positive x-axis using
∠H( f ) = ∠ of zero − ∠ of pole (31.80)
Chapter 31 Data Converter SNR 101

z-plane
f
j2π⋅ f
z=e s
Point B, f = f s /4, 5f s /4 ...

H(z) = z +z 1 Also at point B, z = e jπ/2

Point A, DC or f = 0, f s , 2f s ...

Figure 31.31 The z-plane pole and zero for Eq. (31.77).

which, as seen in Fig. 31.22, results in a phase angle of zero. Next consider evaluating the
H(z) at f s /4  f = f s /4 and z = 1 ⋅ e j 2 = 1∠90  , point B in Fig. 31.31. The distance from
π

the pole to point B is 1 while the distance from the zero is 2 resulting in a magnitude
2 . The angle from the pole along the x-axis to point B is 90°, while the angle from the
zero is 45° resulting in an overall phase response of −45° (verify with Fig. 31.22).
Also note that (1) any digital filter's or system's frequency response is periodic with
period f s (one complete revolution around the unit circle), (2) we normally are only
concerned with evaluating H(z) over the top half of the unit circle (from DC to f s /2 [the
Nyquist frequency, f n ]), and (3) a pole at the origin has no effect on the magnitude
response of H(z) but does affect the phase response (as shown in Ex. 30.6 in which
multiplying H(z) by z−1, adding a pole at the origin to H(z), simply shifts the output later in
time). Finally note that the number of poles in H(z) must be greater than or equal to the
number of zeroes if the digital filter/system is to be realizable in hardware (the output of
the system cannot occur before the system's input).

Example 31.19
Determine, using the graphical approach just discussed, the magnitude and phase
of the transfer function shown in Fig. 31.32 at a frequency of f s /4 .
If we label the length from a pole (zero) to the evaluation point p (z), then the
magnitude of the transfer function is given by
z
H(z) = p ⋅1p
1 2

Labeling the angles for the poles and zeroes as indicated in the figure, we can write
the phase response as
∠H(z) = θ 3 − θ 2 − θ 1 T
102 CMOS Mixed-Signal Circuit Design

z-plane z-plane
Evaluated here

z1 p1 θ1
p2 θ3
θ2

Magnitude reponse Phase response

Figure 31.32 The z-plane pole and zero plot for Ex. 31.19.

Example 31.20
Determine the frequency response of a digital system with the time domain
response
y[nT s ] = x[nT s ] + y[(n − 1)T s ]
Sketch the hardware implementation of the system and its frequency response.
The z-domain transfer function for this system is
Y(z) = X(z) + Y(z) ⋅ z −1
or

H(z) = 1 = z (31.81)
1 − z −1 z − 1
The hardware implementation of the system is shown in Fig. 31.33 along with the
z-domain representation. Note that the size of the words used (the number of bits
coming out of the adder and the number of latches) depends on the application.

x[nT s ]
y[nT s ] X(z)
Y(z)
y[(n − 1)T s ] Y(z)z −1
z −1
Latches 1 = z
Clock H(z) =
1 − z −1 z − 1

Figure 31.33 Block diagram of a digital integrator used in Ex. 31.20.

Chapter 31 Data Converter SNR 103

Figure 31.34 shows the z-plane representation of this system along with the
magnitude and phase response of the system. This circuit is called a digital
integrator. To show why, let's determine the magnitude and phase responses, using
Eq. (31.81), and noting the z in the numerator is simply a phase shift
Phase shift

H(z) = z → e j2π fsf ⋅ 1 =e

f
j2π fs
⋅ 1 (31.82)
z−1 f
j2π fs f f
(−1 + cos 2π fs ) + j sin 2π f s
e −1
Knowing
1 1
= (31.83)
a + jb a + b2
2

we can write (see Eq. [31.61])

H( f ) = 1 = 1 (31.84)
2 2 f
 −1 + cos 2π f  +  sin 2π f  2(1 − cos 2π f s )
 fs   fs 

and, evaluating the phase directly from the z-plane plot,

From zero From pole

 f 
− π + π = 180 − 90 (degrees) for 0 < f < f s (31.85)
f f
∠H( f ) = 2π
fs  fs 2  fs
At DC the phase contribution from the zero is 0°, while the phase contribution
from the pole, at a frequency just above DC, is 90°. The result is an overall phase
response of −90°. At fs /4 the phase contribution from the zero is 90°, while the
phase contribution from the pole is 135°, resulting in an overall phase response of
−45 °. T
1 = z H( f )
H(z) =
1 − z −1 z − 1 z-plane

0.5

f s /2 fs 3f s /2 f
∠H( f )
degrees
90

f
90

Figure 31.34 The z-plane representation along with magnitude and phase response
for a digital integrator.
104 CMOS Mixed-Signal Circuit Design

Consider the possible input to our digital integrator (Fig. 31.33) and the resulting
output shown in Fig. 31.35a and 31.25b respectively. In this figure we are using +1 to
indicate the peak positive input sinewave amplitude and −1 to indicate the peak negative
input amplitude. The frequency of the sinewave is f s /2 and so, according to our
magnitude plot in Fig. 31.34, the gain is 0.5 (the peak-to-peak amplitude of the sinewave
is reduced by one-half). Looking at Fig. 31.35, we should see that the initial state of the
register (the latches) used in the integrator will, together with the input, determine the DC
offset in the output waveform. For example, if the latches initially contained zero and the
first sample was +1, as seen in Fig. 31.35a, then we would get the waveform shown in Fig.
31.35b. If, instead, the first sample were −1, then the entire waveform in Fig. 31.35b
would shift downwards by +1. In any integrator, digital or analog, the "initial conditions"
will affect the output waveform.
The next important factor we should notice in Fig. 31.35 is that we picked the
peaks of the input sinusoid as our inputs to the digital integrator. Shifting our ADC output
sampling points by Ts/2 results in a signal of all zeroes being applied to the digital
integrator. The result is no change in the integrator's output. Shifting the sampling points
by Ts/3 results in an integrator input of ± 0.5 with a corresponding integrator peak-to-
peak output of ± 0.25 . In any case, at f s /2 , the output of the digital integrator is one-half
the input signal's amplitude.

x(t)
x(nT s )
+1

time
-1 (a)
y(t) 2T s 4T s

+1

time
y(nT s ) (b)

Figure 31.35 (a) Input and (b) output of the digital integrator of Fig. 31.33.

In the above discussion we used decimal numbers to represent the input and output
signals of the integrator. In a practical implementation we use binary numbers. Let's use
our ideal 8-bit data converters to illustrate the number system concerns. In these
converters V REF− = 0 and V REF+ = 1.5 V with V LSB = 5.859 mV . A code of all zeroes
corresponds to 0 V while a code of all ones corresponds to 1.494 V. The common mode
voltage, V CM , = (V REF+ + V REF− )/2 = 0.75 V . Again this number system is called offset
binary. Figure 31.36 illustrates the representation of a full-scale sinusoid using the offset
binary number format.
Chapter 31 Data Converter SNR 105

11111111 (1.494 V)
(255)
10000000 (0.75 V)
(128) time
00000000 (0 V)
(0)
Figure 31.36 Representing a sinusoid in binary offset format.

We should compare the binary offset numbers of Fig. 31.36 to the decimal
numbers of Fig. 31.35 and notice that if we apply the DC components of each signal to the
integrator, we get totally different results. In Fig. 31.35 the DC component of the input
has a decimal value of 0. Applying 0 to our integrator causes the output of the integrator
to remain unchanged. In Fig. 31.36 the DC component of the input is the common mode
voltage (halfway between the reference voltages) of 10000000. Applying this value to the
integrator results in the integrator's output increasing until the output changes from all
ones to all zeroes (the output rolls over). Clearly, the binary offset representation has
some practical limitations when used in a digital integrator. To avoid these problems, the
binary offset format is usually converted into the two's complement format prior to
application to the digital integrator.
In two's complement the left-most bit is the sign bit. A zero represents a positive
number (except for all zeroes, 00000000, or the common mode voltage) and a one
represents a negative number (see Fig. 31.37). A binary offset number can be translated
back and forth between a two's complement number by simply complementing the MSB of
the code (running the MSB through an inverter). For this reason, and others that will be
discussed later (ease of implementing subtraction and no overflow problems), two's
complement is the preferred format for data words in digital filtering.

01111111 (1.494 V)
V CM + 127 ⋅ V LSB
(+127)
00000000 (0.75 V) V CM = 0.75 time
11111111 (0.7441) V CM − V LSB
(−1)
V CM − 128 ⋅ V LSB
10000000 (0 V)
(−128)
Figure 31.37 Representing a sinusoid in two's complement format.
106 CMOS Mixed-Signal Circuit Design

31.2.2 Decimating Filters for ADCs

We saw, from Eq. (31.69), that when we employ averaging in a data converter we have to
limit the input signal bandwidth, B, to the Nyquist frequency, fn , divided by the number of
points averaged, K. Knowing this, we may want to lower the rate at which these samples
are coming out of the averaging filter to simplify the circuitry after averaging and to lower
the power dissipation. Our new, effective sampling frequency is given by
fs
f s,new = 2B = (31.86)
K
This reduction in the effective sampling frequency is termed decimation and is illustrated
with the block diagram shown in Fig. 31.38. The term decimation (or decimate) can be
confusing since, among other things, the dictionary definition is, "to select by lot and kill
one in every ten." The origin of the word comes from a method of punishing military
troops by selecting one in every ten for execution. Our much more kind-hearted definition
will mean that we are passing the input word through a lowpass digital filter and then
down-sampling the result. This procedure is effectively passing the digital data through an
antialiasing filter and then resampling the result at a lower rate.

Decimate and average

x[nT s ] y[Ki ⋅ T s ]
In Out
K

Input word rate, f s Output word rate, f s /K

Figure 31.38 Block diagram of a decimation filter.

The Accumulate and Dump

In the simplest form we can write the input and output of the decimation filter, in the time
domain, as
K⋅i−1
x[n ⋅ T s ]
y[Ki ⋅ T s ] = Σ
n=K(i−1) K
(31.87)

which is nothing more than averaging K input samples. Before going any further, we
should make sure we understand this equation. Our decimation filter will take K input
samples, add them together, and then divide the result by K to obtain the average of the
input. If K = 16 and i = 1, then samples x[0] through x[15] are summed and divided by 16.
As we saw in Ex. 31.17, the actual division by K is dependent on the increase in
the number of bits in the output word. For example, if our input word is 8-bits and K = 16
then the output word, before dividing by K, is 12-bits (adding sixteen, 8-bit words, results
in a 12-bit word). If the ultimate increase in resolution is 2-bits, then the final output word
size is 10-bits and we throw the lower 2-bits away. This could effectively mean that
instead of dividing by 16, we divide by 4.
Chapter 31 Data Converter SNR 107

We can rewrite Eq. (31.87) in the z-domain (so that we have the z-domain
representation for the decimation filter) as
K−1
Y(z) 1
H(z) = =
X(z) K Σ z−n = K1 (1 + z −1 + z −2 + ... + z 1−K)
n=0
(31.88)

or
−1
H(z) = 1 ⋅ 1 − z −1 ⋅ (1 + z −1 + z −2 + ... + z 1−K ) (31.89)
K 1−z
or finally, the z-domain transfer function for the decimator (averager), is
−K
H(z) = 1 1 − z −1 (31.90)
K1−z
If K = 2, Eq. (31.90) becomes
(z + 1)(z − 1) 1
H(z) = 1 = (1 + z −1 ) (31.91)
K z(z − 1) K
noting that we have already discussed this case, Eq. (31.59), earlier. Note also that the
division by K may be ignored in this case since, as discussed earlier, the word size
increases by one bit when adding the two words. (However, our realized increase in
resolution is only 0.5 bits meaning the SNR increases by 3 dB.)
One circuit used to implement Eq. (31.90) is shown in Fig. 31.39 and is called an
accumulate-and-dump circuit. To understand the operation of this circuit let's assume the
bottom set of latches are reset. The sampling clock is used to clock this set of latches K
times until the sum of K inputs is accumulated. At this time the accumulated sum is
dumped into the output latches. Also, at this time, the bottom set of latches is reset to zero
to start the accumulation process for the next set of K input samples. Note the clock rate
on the input of the circuit is fs and the clock rate coming out of the circuit is fs /K.

Input, x[nT s ] Output, y[Ki ⋅ T s ]

Latches

Clock
Dump the sum into
this set of latches.
Clock, f s
Latches
Reset
Accumulate the sum in this f s,new = f s /K
set of latches
divide by K
Assuming K = 8

Figure 31.39 An accumulate-and-dump circuit used for decimation and averaging.

108 CMOS Mixed-Signal Circuit Design

We can determine the frequency response of the accumulate-and-dump circuit by

f
j2π f
setting z = e s in Eq. (31.90) or
f f
−j⋅K⋅2π −j⋅2π
H( f ) = 1 ⋅ 1 − e = 1 ⋅ 1−e
fs f s,new

f f
(31.92)
K −j⋅2π⋅ fs K −j⋅2π⋅ fs
1−e 1−e
or, knowing 1 − e −jx = (1 − cos x) + j sin x = (1 − cos x) 2 + (sin x) 2 = 2(1 − cos x) ,

sin  Kπ f s  sinc  Kπ fs 
f f f
2(1 − cos K2π f s )
H( f ) = 1 ⋅ =1⋅ = (31.93)
sin  π f s  sinc  π f s 
K K
2  1 − cos 2π f s 
f f f

We can sketch the frequency response of the accumulate-and-dump averager/decimator

for different values of K as seen in Fig. 31.40. Note that the accumulate-and-dump circuit
averages K samples while also reducing the output word rate to f s /K (decimation). For

Decimate and average

x[nT s ]
Analog in Out In Out, y[Ki ⋅ T s ]
ADC K
Clock out, f s /K

fs Clock in H( f )
H( f )
z-plane
−2
K=2 H(z) = 1 − z −1
2 1−z

f s /2 3f s /2 f in (Hz)
B
4
−4
Note different scale! K=4 H(z) = 1 − z −1
1.08 1−z
3
f s /4 f s /2 3 f s /4
B

8
K=8 −8
Note different scale! H(z) = 1 − z −1
1−z
1.7 7
f s /8 f s /4 3f s /8
B

Figure 31.40 Frequency response of the accumulate-and-dump for various values of K.

Chapter 31 Data Converter SNR 109

obvious reasons, Eq. (31.93), the frequency response of the accumulate-and-dump circuit,
or an averaging filter with the z-domain response given by Eq. (31.90), is sometimes
called a sinc filter.

Example 31.21
Determine the pole and zero locations (verify the z-plane plot in Fig. 31.40) for an
averaging filter that averages eight samples.
We can write the z-domain representation of the averager using Eq. (31.90)
without the scaling factor K as
−8
H(z) = 1 − z −1 = 7z − 1
8

1−z z (z − 1)
or

(z − 1)(z + 1)(z − j )(z + j )  z + 12 − j ⋅ 12   z + 12 + j ⋅ 12   z − 12 − j ⋅ 12   z − 12 + j ⋅ 12 

H(z) =
z 7 (z − 1)
T
The general shape of the frequency response of an averaging filter is shown in Fig.
31.41. It's desirable to determine the amount of attenuation provided by this filter by
specifying the ratio of the peak value of the main lobe to the peak value of the first side
lobe. If this ratio is large enough, we can limit our concerns to the filter response below
f s /K . Also note that the "gain" of the filter K is somewhat irrelevant in a frequency
response discussion because increasing K simply means our digital word size is increasing.
The output of the filter is scaled (divided), as discussed earlier, by some number less than
K to get the final increase in resolution (the final number of bits increase over the input
word size).

H( f )
K Main lobe
First sidelobe

Maximum input signal

bandwidth f s /K 2( f s /K) 3( f s /K) f
B = 0.5( f s /K)
Figure 31.41 General frequency response of an averaging filter, Eq. (31.90).

The attenuation can be determined using Eq. (31.93) evaluated at 1.5(f s /K) as
Main lobe = K ⋅ sin  1.5π  for K ≥ 3 (31.94)
First sidelobe  K 
This equation is plotted in Fig. 31.42 against averaging factor K. Note how the maximum
amount of attenuation, as the number of averages increases, approaches 13.5 dB. This is a
significant limitation and results in the need to cascade averaging filter stages to attain a
large amount of attenuation at frequencies above f s /K (more on this topic in a moment).
110 CMOS Mixed-Signal Circuit Design

dB
13.5 dB
13

Main lobe
11
First sidelobe

3 4 6 8 10 K

Figure 31.42 Averaging filter attenuation versus number of points averaged K.

It's also of interest to determine how much droop the filter will introduce into the
signal frequencies of interest. Figure 31.43 shows the droop (attenuation) at the maximum
input bandwidth, B. We can calculate the amount of droop, again using Eq. (31.93) when
f = f s /(2K) = B , as

Droop = 1 (31.95)
K ⋅ sin  2K
π 


H( f ) droop, dB

K -3.5
droop
-3.6
-3.8
B = 0.5( f s /K) f -4.0
3 4 6 8 10 K
Figure 31.43 Droop at edge of signal bandwidth when using an averaging filter.

It should be obvious that if we desire large amounts of attenuation through our

digital averaging (sinc) filter, we have severe limitations (only 13.5 dB attenuation
maximum) when using the basic accumulate-and-dump circuit of Fig. 31.39. To increase
the attenuation we might try to cascade accumulate-and-dump circuits as seen in Fig.
31.44. This cascade has several practical problems. While the attenuation can be increased
to L ⋅ 13.5 dB , where L is the number of stages, the final output sampling frequency drops
to f s /K L and the maximum input frequency, B, drops to 0.5f s /K L . To illustrate the
limitations imposed by a cascade of accumulate-and-dumps, let's assume we need 60 dB of
attenuation through the filter and our sampling frequency, f s = 100 MHz . If K = 8, then
we need to cascade five accumulate-and-dump stages. The sampling frequency coming out
of the final stage is 3 kHz! The droop at 1.5 kHz (B) remains 3.9 dB. Clearly, cascading
accumulate-and-dump circuits is not practical for most situations.
Chapter 31 Data Converter SNR 111

In Out
Accumulate Accumulate Accumulate
f s clk and dump clk and dump clk and dump clk f s /K 3
f s /K f s /K 2

Figure 31.44 Cascading accumulate-and-dump circuits to increase filter attenuation.

Averaging without Decimation

The accumulate-and-dump performed averaging and decimation in one stage. In other
words, for example with K = 4, it summed four input samples, as shown in the sequence
below, and passed the result to the output:
First output of the accumulate and dump Second output

x(1) + x(2) + x(3) + x(4) + x(5) + x(6) + x(7) + x(8) + x(9) + ... (31.96)
We can get a much more efficient and practical filter if we average the input samples
without decimation (sample frequency reduction). The final output clocking frequency
(after decimation) can be set to 2B (Eq. [31.69]) and can occur in a later stage in the
filter's construction. The reduction in sampling frequency reduces power and circuit
complexity (for example, serial multipliers can be used in a digital filter).
Consider the running sum shown below
First output of averager

x(1) + x(2) + x(3) + x(4) + x(5) + x(6) + x(7) + x(8) + x(9) + ...
Second output of averager

x(1) + x(2) + x(3) + x(4) + x(5) + x(6) + x(7) + x(8) + x(9) + ...
Third output of averager

x(1) + x(2) + x(3) + x(4) + x(5) + x(6) + x(7) + x(8) + x(9) + ...
Fourth output of averager

x(1) + x(2) + x(3) + x(4) + x(5) + x(6) + x(7) + x(8) + x(9) + ... (31.97)
It should be obvious that the outputs of the averager occur at the same rate as the
averaging filter's input (no change in the sampling frequency). The z-domain
representation of the averager is the same as the accumulate-and-dump's transfer function
x[nT s ] + x[(n − 1)T s ] + x[(n − 2)T s ] + ... X(z)(1 + z −1 + z −2 + ... + z 1−K )
y(nT s ) = → Y(z) =
K K
(31.98)
or, reviewing Eqs. (31.88) and (31.89), results once again in
−K
H(z) = 1 1 − z −1 (31.99)
K1−z
where the division by the number of points averaged, K (K is four in Eq. [31.97]) is
performed by simply adjusting the final word size to the desired length (as discussed
112 CMOS Mixed-Signal Circuit Design

earlier and in Ex. 31.17). The transfer function of a cascade of L of these averaging filters
can be written as
−K L
H(z) =  1 1 − z −1  (31.100)
K 1 − z 

or
L
 sinc Kπ f 
H( f ) = 
fs 
f 
(31.101)
 sinc π 
 fs 

Before we discuss the implementation of the averaging filter (a.k.a. sinc filter), let's
borrow the results from Figs. 31.42 and 31.43 and notice the attenuation for a cascade of
L averaging filters is
L
Main lobe = K ⋅ sin  1.5π  ≈ L ⋅ 13 dB for K ≥ 8 (31.102)
First sidelobe  K 
while the droop, at the maximum input frequency, B, is
−L
Droop =  K ⋅ sin  π   ≈ L ⋅ (−3.9) dB for K ≥ 8 (31.103)
 2K 
Also note that Eq. (31.69) is still valid, which means that we don't have a significant
restriction on the maximum allowable input frequency.
To compare the cascade of averaging filters to the limitations imposed by a
cascade of accumulate-and-dumps as discussed earlier, let's once again assume we need 60
dB of attenuation through the averaging filter and our sampling frequency is
f s = 100 MHz . If K = 8, then we need to cascade five averaging filter stages as seen in
Fig. 31.45. The clock frequency coming out of the final stage is 100 MHz and needs to be
reduced to 12.5 MHz in the last stage by simply dividing the clock down before clocking a
final set of latches or by using an accumulate-and-dump for the final stage. The 12.5 MHz
output rate and 6.25 MHz input frequency bandwidth, B, should be compared to the 3
kHz output clock frequency and 1.5 kHz input frequency calculated earlier for the cascade
of accumulate-and-dumps. The droop B remains 19.5 dB and can be a serious concern in
many situations. Obviously, limiting the input bandwidth further reduces the droop at B.
Figure 31.46 shows the frequency response of a cascade of averaging filters (the frequency
response is given by Eq. [31.101]).

In
1 − z −8 1 − z −8 1 − z −8 1 − z −8 1 − z −8 Out
clk 1 − z −1 1 − z −1 1 − z −1 1 − z −1 1 − z −1 clk

All sections are clocked at 100 MHz L=5

Figure 31.45 Cascading averaging circuits to increase filter attenuation.

Chapter 31 Data Converter SNR 113

H( f )
L ⋅ 3.9 dB
KL

B = 0.5( f s /K) L ⋅ 13 dB

f s /K 2( f s /K) 3( f s /K) f
f s /(2K)
Figure 31.46 General frequency response of an averaging filter, Eq. (31.101).

Relaxed Requirements Placed on the Antialiasing Filter Revisited

Consider the input (to the ADC) spectrum shown in Fig. 31.47a resulting from passing an
input signal through an anti-aliasing filter (AAF). The AAF has to remove all spectral
content above f s − f s /K, as we'll show in a moment, to avoid aliasing when using a digital
averaging filter (with spectral response shown in Fig. 31.46). On the output of the ADC,
after sampling and aliasing, the characteristics of the signal are shown in Figs. 31.47b and
31.47c. In Fig. 31.47b we show the individual reproductions of the original base spectrum.
In part (c) we combine the spectrums to show the continuous ADC output spectrum and
include a sketch of the digital filter frequency response. From Fig. 31.47c we should see

In B = f s /(2K) ADC, out fs

f s /K

f s − f s /K f f s /(2K) f s − f s /K f

(a) Input spectrum to the ADC. (b) Output spectrum of the ADC with aliasing.

ADC, out f s /K Filter out f s /K fs

digital filter
response

f s /(2K) f s − f s /K f f s /(2K) f s − f s /K f
(c) Same as (b) except showing a continuous (d) Output of the digital filter after removing
spectrum. Thin line is digital filter response. aliased components.

Figure 31.47 How a digital (averaging) filter helps remove aliased spectral components.
114 CMOS Mixed-Signal Circuit Design

why the AAF has to limit the ADC input spectral content to f − f s /K . At f s /K the output
of the digital filter goes to zero. This assumes the first sidelobe in the digital filter is
sufficiently small so that the amount of aliasing past fs /K is negligible. In many systems
that employ a digital signal processor, an additional abrupt-cutoff lowpass digital filter is
used after the averaging and decimation process to provide additional alias signal removal.
Note, in Fig. 31.47d the output of the digital filter, as mentioned earlier, has a
periodic frequency response (and so the spectrum out of the digital filter will still have
aliased components but hopefully not in the base spectrum). As a further example of the
periodic nature of all digital filters, consider the K = 8 averaging filter frequency response
shown in Fig. 31.48 (see Fig. 31.40 for a comparison). Note that the number of points in
the frequency response between DC and f s that go to zero (the number of zeroes in the
transfer function) is seven (since the zero at DC is canceled by the pole at DC [z = 1 ]).

H( f )
1 − z −8
K=8 H(z) =
1 − z −1
8
f s /4 f s /2

f s /8 3f s /8 fs 2f s
B

Figure 31.48 The periodic nature of a K = 8 averaging filter.

Implementing Averaging Filters

If we are not careful, the averaging filter can take up a large amount of chip area. In this
section we discuss how to implement an averaging filter with a response given by Eqs.
(31.100) and (31.101). To begin, let's break the averaging filter up into two parts, without
including the scaling factor K,
L integrators
L differentiators
−K L L
H(z) =  1 − z −1  = (1 − z −K ) ⋅ 
L 1  (31.104)
1−z  1 − z −1 
We have already looked at the transfer function of an integrator in Ex. 31.20. An alternate
digital integrator design is shown in Fig. 31.49. The only difference between the circuit of
Fig. 31.49 and Fig. 31.33 is the change in the phase response of the circuit.

X(z) Y(z)
z −1
Y(z) = [Y(z) + X(z)]z −1
y(nT s ) = y[(n − 1)T s ] + x[(n − 1)T s ] Y(z) −1
H(z) = = z
X(z) 1 − z −1
Figure 31.49 Alternate digital integrator.
Chapter 31 Data Converter SNR 115

x[nT s ] y[nT s ] X(z) Y(z)

x[(n − 1)T s ] X(z)z −1

−1
z
Clock Latches H(z) = (1 − z −1 )

Figure 31.50 Block diagram of a digital differentiator.

The z-domain representation and schematic of a differentiator are shown in Fig.

31.50. Note the use of subtraction in the differentiator. The time domain description of a
digital differentiator is given by
y[nT s ] = x[nT s ] − x[(n − 1)T s ] (31.105)
and the z-domain transfer function is given by
Y(z)
H(z) = = (1 − z −1 ) (31.106)
X(z)
The frequency response of the differentiator is (see Fig. 31.51)

 f
H( f ) = 2 1 − cos 2π (31.107)
 fs 
and the phase response is

∠H( f ) = π − π for 0 < f < f s

f
(31.108)
2 fs
Again, like all of the digital filters we have discussed in this chapter, the phase response is
linear (constant delay, meaning no phase distortion). Also note, assuming the two's
complement number representation is used for the input/output (I/O) in the differentiator,
that subtraction of two numbers, A − B , can be accomplished by using an adder with the B
input complemented (run through inverters) prior to application to the adder and the adder
carry-in tied to a logic one.

∠H( f )
H( f ) H(z) = (1 − z −1 ) = z −z 1 degrees
2
90
2 f (Hz)

-90
f s /4 f s /2 fs 3f s /2 f (Hz) f s /2 3f s /2

Figure 31.51 Magnitude and phase response of digital differentiator.

116 CMOS Mixed-Signal Circuit Design

Next consider the digital comb filter (or differentiator over a range of frequencies)
circuit shown in Fig. 31.52. We should recognize this circuit's transfer function from Eq.
(31.104) as

H(z) = 1 − z −K = z −k 1
K

z
with a magnitude response given by

 f
H( f ) = 2 1 − cos 2πK
 fs 

x[nT s ] y[nT s ] X(z) Y(z)

K Latches x[(n − K)T s ] X(z)z −K

D Q D Q D Q
z −K

H(z) = 1 − z −K = z −k 1
clk clk clk K
Clock
z
fs Figure 31.52 Block diagram of a digital comb filter.

Figure 31.53 shows the z-plane and frequency responses for comb filters with
various values of comb filter delays K. Before we proceed with the implementation of the
averaging filter defined by Eq. (31.104), let's discuss, intuitively, how we take the basic
digital comb filter and make a lowpass, averaging filter. Remember that we evaluate
1 − z −K around the unit circle, in the z-plane, to determine H( f ) . If we look at Fig. 31.40,
we see that the only difference between a comb filter and a lowpass averaging filter is the
fact that we have added a pole to the transfer function at DC (i.e. z = 1) to cancel the zero
at DC. This is important as we will be able to make highpass and bandpass averaging
circuits by taking a comb filter and canceling the zeroes placed at other points on the unit
circle. We'll discuss this in more detail in the next two sections. Note that by using Eqs.
(31.79) and (31.80), we should be able to see why canceling a zero with a pole at DC
results in an a lowpass filter.
The comb filter of Fig. 31.52, or the differentiator of Fig. 31.50, is an example of a
finite impulse response (FIR) digital filter. Applying a unit amplitude impulse to the input
of the comb filter, and zeroes at all other times, causes the output of the comb filter to go
to a one at the moment the impulse is applied and KT s seconds later, and a zero at other
times. In other words, the output response of the filter has a finite duration.
The integrator (sometimes called an accumulator) shown in Fig. 31.34 is an
example of an infinite impulse response (IIR) digital filter. Applying a unit amplitude
impulse to the input of the digital integrator, with zeroes the remaining times, causes the
output of the integrator to increase to one and remain at one indefinitely. In other words,
the output response of the integrator is of infinite duration.
Chapter 31 Data Converter SNR 117

H( f ) H(z) = 1 − z −K = z −k 1
K

z z-plane K=3
2 H(z) = 1 − z −3
3

f s /3 2f s /3 fs f (Hz)
H( f )
z-plane K=4
2 H(z) = 1 − z −4
4

f s /4 f s /2 3f s /4 fs f (Hz)

H( f )
z-plane K = 16
2 H(z) = 1 − z −16
16

f s /4 f s /2 3f s /4 f s f (Hz)
f s /16 15 f s /16
Figure 31.53 Frequency response and z-plane plots for various values of K in a comb filter.

Equation (31.104) can be implemented by cascading L integrators and L comb

(differentiators) filters as shown in Fig. 31.54. As we discussed earlier, the integrators
have "infinite" gain at DC, which can result in register overflow. However, if we use two's
complement number representation, we'll see that we get the correct answer out of the
filter as long as the word length used to implement the filter is long enough (using two's
complement will avoid overflow problems).

L integrators L comb filters

In 1 1 1 Out
1 − z −K 1 − z −K 1 − z −K
1 − z −1 1 − z −1 1 − z −1
All sections clocked at the same rate
Figure 31.54 Implementation of an averaging filter using integrators and comb filters.

Example 31.22
Consider an averaging filter (Eq. 31.104) using L = 3 and K = 8 with an input
word length of 8 bits. Determine the final number of bits coming out of the filter
and show that a constant input of 01110000 (+112 two's complement) results in
the correct output code. Also, discuss overflow concerns.
118 CMOS Mixed-Signal Circuit Design

From Eq. (31.53) we can calculate an increase in resolution of 1.5 bits per filter
stage so the final output word size should be 13 bits (the original 8-bits input plus
an additional 4.5 bits from averaging 83 [= KL ] samples).
The "gain" of the filter at DC is, from Fig. 31.46, K L = 512 . This means that
our 8-bit input of 112 (0111 0000) will be multiplied by 512 and result in an
output, prior to scaling, of 57344, or a binary code of 0 1110 0000 0000 0000 (17
bits in the general case). From Eq. (31.100) we would then divide this code by 512
(drop the lower nine bits.) However, this would result in an output word size equal
to the input word size (both 8-bits and no increase in resolution). So, for the
general input signal that is time-varying and to get the final 13 bits, we divide the
17-bit filter output by 16 (drop the lower four bits so our final output is 13 bits or
0 1110 0000 0000 [3,584 = 32 ⋅ 112 since 13-bits]). A block diagram of the filter
implementation is shown in Fig. 31.55. A MUX is needed in between each
integrator stage to adjust the two's complement word size up by log 2 K bits.

1 Add MUX here

MSB select 1 − z −1
0000 1 11 1 1
ADC 1111 0 MUX z −1
In, 8 11 1 − z −1 14 1 − z −1
11 Word size increases
7 log 2 K bits in each
8-bits binary
integrator stage
offset 1111 0000 Two's complement, 11-bit,
000 0111 0000 (filter input) 17

1 − z −8
17 17 17 17 17
1 − z −8 1 − z −8
Use inverter for 17 1 Out, 13-bits
subtraction in two's Drop lower 4 bits
complement Carry
in (to change to binary
8 registers offset complement
17
D Q D Q D Q the MSB)
clk clk clk

Figure 31.55 Block diagram of the filter discussed in Ex. 31.22.

Let's discuss overflow concerns. To keep the discussion simple, let's just
consider a single integrator and comb filter stage, that is, L = 1. A constant two's
complement, 8-bit, input of 0111 0000 (+112) into the integrator will result in an
output, assuming we start with all zeroes, of
Output (Sum0) 000 0000 0000 0 (or V CM [two's complement])
Input1 000 0111 0000 112
Sum1 000 0111 0000 112
Chapter 31 Data Converter SNR 119

Input2 000 0111 0000 112

Sum2 000 1110 0000 224
or since the input is a constant 000 0111 0000 (112)
Sum3 001 0101 0000 336
Sum4 001 1100 0000 448
Sum5 010 0011 0000 560
Sum6 010 1010 0000 672
Sum7 011 0001 0000 784
Sum8 011 1000 0000 896
Sum9 011 1111 0000 1008
Sum10 100 0110 0000 1120
Sum11 100 1101 0000 1232
Sum12 101 0100 0000 1344
Sum13 101 1011 0000 1456
Sum14 110 0010 0000 1568
Sum15 110 1001 0000 1680
Sum16 111 0000 0000 1792
Sum17 111 0111 0000 1904
Sum18 111 1110 0000 2016
Sum19 000 0101 0000 80 Overflow!
Sum20 000 1010 0000 192

These sums are applied to our comb filter. Since K = 8, we won't have a
meaningful comb filter output until our ninth integrator output. At this time the
output of the comb filter will be the difference between Sum1 and Sum9, that is,
Sum9 − Sum1. The ninth integrator output is 1008 while the first is 112. The
difference being 896 (011 1000 0000 or 8 ⋅ 112 with 11 bits). In fact, we can take
any difference between sums spaced eight clock cycles apart, even after overflow,
and get this result (looking only at the lower 11 bits.) For example, Sum18 −
Sum10 is
Sum18 111 1110 0000 (2016)
minus Sum10 100 0110 0000 (1120)
(896)

In two's complement, for subtraction, we complement, and add one (set the adder
carry-in bit high) to the number we are subtracting, which gives, for this example,
Sum18 111 1110 0000
Sum10(comp) 011 1001 1111
plus 1 (adder carry)
011 1000 0000 (896)

noting that we threw out the 12th bit in the sum. As a final example,
Sum19 000 0101 0000 (80) or Sum19 000 0101 0000
minus Sum11 100 1101 0000 (1232) or Sum11(comp) 011 0010 1111
difference (-1152 or 896) plus 1
011 1000 0000 (896)

While this last discussion focused on L = 1, we could use any number of stages as
long as the register size in our integrators can accommodate a binary number of at
least K ⋅ 2 N , where N is the number of bits in the input word. T
120 CMOS Mixed-Signal Circuit Design

We might notice from this example that the amount of hardware needed to
implement the averaging filter is significant. The main contributors to the final filter layout
size are the registers used in the comb filters (a total of twenty-four 17-bit registers are
used). It turns out, as discussed earlier, that we can use the reduction in clock frequency
(decimation) to reduce the number of registers used in the comb filter, Fig. 31.56. By
dividing the clock frequency down by K, we can reduce the number of registers used in
each comb filter to one. In either Fig. 31.54 or Fig. 31.56 the delay used in the comb filter
is KTs. Figure 31.56 is the preferable way to implement decimation/averaging filters
(however, see aliasing description below for practical implementation concerns).

L integrators (Important: See aliasing discussion below)

In 1 1 1
1 − z −1 1 − z −1 1 − z −1
fs clock Note the use of one register

L comb filters

÷K 1 − z −1 1 − z −1 1 − z −1 Out
f s /K clock

L
 1 − z −K  In Out
  K
 1 − z −1 
Transfer function of Decimate and average
decimating and averaging filter (schematic symbol)

Figure 31.56 Using a reduction in clock frequency to lower complexity in averaging filters.

Aliasing Concerns When Using Decimation

While we are used to discussing aliasing concerns when sampling an analog waveform, we
can also discuss aliasing when (re-) sampling a digital waveform. Reducing the sampling
or clocking frequency (decimation) can be thought of as resampling a digital waveform at
a lower rate, Fig. 31.57. In Fig. 31.57 the averaging filter can be thought of as the
antialiasing filter with nonzero spectral content up to f s /K (assuming the side lobes are
sufficiently below the main lobe), while the set of latches on the output can be thought of
as the sampler.
Figure 31.58a shows the output spectrum of the averaging filter (see, also, Fig.
31.47), assuming the side lobes are sufficiently small so that they are not a concern. If we
resample this signal at f s /K , we get the spectrum shown in Fig. 31.58b. The resulting
spectrum shows a problem (aliasing in the base spectrum) that would be encountered
using the filter of Fig. 31.56 unless our input signal bandwidth, B, is limited, using an
analog antialiasing filter or a separate digital filter, to f s /2K . As discussed earlier (Fig.
Chapter 31 Data Converter SNR 121

Used for sample rate reduction.

Digital Averaging Filter
Throw out K − 1 samples
In Out
D Q
clk
f s /K
fs clock Clock Out
÷K

Figure 31.57 Resampling a digital waveform.

31.47), we can use the averaging filter for additional aliased signal removal. While we may
only be interested in signal content up to B (Eq. [31.69]), we can still have unwanted
signal content between B and f s /K that will alias into the base spectrum. It is desirable to
eliminate this problem altogether. We can do this by resampling at 2(f s /K) . The
averaging/decimation filter shown in Fig. 31.56 is changed so that the divider divides by

Averaging filter output spectrum Assuming K = 8

f s /K = 2B

(a)

f s /K f s /2 fs f

Output spectrum after resampling at f s /K (= 2B = f s /8 here)

(b)

f s /8 3f s /8 5f s /8 7f s /8 f
f s /4 f s /2 3f s /4 fs
Output spectrum after resampling at 2( f s /K) = f s /(K/2) (= 4B = f s /4 here)

(c)

f s /4 f s /2 3f s /4 fs f

Figure 31.58 Showing signal spectrum (a) prior to decimation and (b) and (c) after.
122 CMOS Mixed-Signal Circuit Design

K/2 . By adding a register to the comb filter the comb filters are 1 − z −2 . The resulting
spectrum is shown in Fig. 31.58c. Note that aliasing is a very important concern when
designing the averaging filter.
If the first sidelobe amplitude isn't sufficiently small, as was assumed in Fig. 31.58,
a larger resampling frequency or decimation frequency can be used to minimize aliasing. A
common intermediate clocking frequency is 4 ⋅ (f s /K) . A sample averaging filter output
waveform is shown in Fig. 31.59a, where the sidelobe amplitude is no longer insignificant.
Figure 31.59b shows the spectrum, assuming K = 8 and the resampling frequency is
f s /2 (= 4 ⋅ [ f s /8]) (meaning the divider in Fig. 31.56 is f s /[K/4]) and each comb filter
stage uses four registers [1 − z −4 ] ). Note how the third side lobe is aliased into the base
spectrum in this example, while the first sidelobe was aliased into the base spectrum in Fig.
31.58c (although it was not shown in the figure). Figure 31.60 shows that the ratio of the
main lobe to the third sidelobe is approximately 20 dB (assuming K ≥ 8 ). The possible
large amount of baseband aliasing together with the droop at B may result in the desired
input bandwidth, B, being limited to frequencies below f s /(2K) with an the external
analog AAF or an additional digital filter (more on this in a moment). Finally, notice that
at DC (or very low frequencies) in Figs. 31.58b, 31.58c, or 31.59b there is essentially no
aliased signal. This is the result of the zeroes in the averaging filter transfer function, Eq.
(31.99), falling at multiples of the decimation frequency.

Averaging spectrum with significant sidelobes. Assuming K = 8

(a)

f s /8 f s /2 fs f

Spectrum after decimation 4(f s /K) = f s /2 = 8B

Third side
(b)
lobe aliased
in the base
spectrum
f s /8 f s /2 fs f

Figure 31.59 Showing signal spectrum with significant side lobes (a) prior to
decimation and (b) after decimation.

A Note Concerning Stability

Consider the weighted integrating filter block diagram shown in Fig. 31.61. The output of
the circuit is fed back to the input after it is multiplied by a. Multiplication by a may be
performed with a dedicated multiplier or it may simply be a shift operation (multiplying by
Chapter 31 Data Converter SNR 123

H( f )
KL

Droop
≈ L ⋅ 20 dB
L ⋅ 3.9 dB

f s /K 2( f s /K) 3( f s /K) f
B = 0.5( f s /K) (7/2)( f s /K)
Figure 31.60 Decimating at four times the Nyquist rate. Showing (aliased) third sidelobe.

0.5 is simply a shift-right operation). The output of the circuit in the time domain may be
written as
y[nT s ] = x[(n − 1)T s ] + a ⋅ y[(n − 1)T s ] (31.109)
or
y[nT s ] = x[(n − 1)T s ] + a ⋅ x[(n − 2)T s ] + a 2 ⋅ x[(n − 3)T s ] + a 3 ⋅ x[(n − 4)T s ] + ... , (31.110)
which will obviously blow up if a > 1 .

X(z) Y(z)
z −1
Y(z) = [aY(z) + X(z)]z −1
y(nT s ) = a ⋅ y[(n − 1)T s ] + x[(n − 1)T s ] a
Y(z) z −1
H(z) = =
X(z) 1 − a ⋅ z −1

Figure 31.61 A weighted integrating filter.

The z-domain representation of Eq. (31.109) is

H(z) = z −1 a (31.111)

Figure 31.62 shows the z-plane and magnitude plots specified by this equation. If a > 1
H(z) becomes unstable, so for a stable system we must require our poles to reside within
the unit circle. (There are no restrictions on the location of zeroes.) This sounds simple
enough; however, notice that we have, in most of the previously discussed digital filters,
placed poles right on the unit circle. If there is rounding in our digital numbers, we could
be faced with an unstable digital filter. This would be a very common occurrence in a
digital filter implemented using software, if care was not taken to avoid rounding errors.
Since we use integer numbers in our hardware implementations, instability shouldn't be a
problem unless we start to try to round numbers to decrease hardware complexity
(performing divisions or multiplications) without being careful.
124 CMOS Mixed-Signal Circuit Design

H(z) = z −1 = 1
1 − az −1 z − a
z-plane

H( f )
1
a 1−a

1
1+a
f s /2 fs 3f s /2 f

Figure 31.62 The z-plane representation and magnitude response

for a weighted integrating filter.

Decimating Down to 2B
In many situations (for example, we want to transmit the modulator output) it is desirable
to reduce the clocking frequency down to twice the Nyquist frequency. Since the Nyquist
frequency for our input bandwidth B is f s /(2K) , our final output clocking frequency
would be f s /K = 2B . As we have just discussed this second stage decimation can result in
significant aliasing. To eliminate this aliasing, a digital filter is often used to limit the
bandwidth, after the first stage decimation, to f s /(2K) (= B). Before we proceed any
further, let's summarize the discussion so far for the different situations.
1. The input to the ADC is bandlimited to B [= f s /(2K)] . In this situation we can
use the topology of Fig. 31.56 directly, decimating the sampling clock from fs to fs /K in
one stage. The comb filters use one register. The smallest size averaging/decimation filter
results in this situation and the output clock rate is 2B.
2. The input, to the ADC is bandlimited to 2B (= f s /K). In this situation the
averaging filter provides some aliased signal removal, see Fig. 31.47. Assuming the aliased
signal content in the first side lobe is insignificant, we can use the topology of Fig. 31.56
with a divider of (K/2) and two registers in each comb filter; that is, each comb filter has a
transfer function of 1 − z −2 . The sampling clock gets reduced from fs to fs/(K/2). The
output clocking rate is now 4B.
3. The input to the ADC is bandlimited to the Nyquist frequency fs /2 (the general
situation where the analog AAF has the most relaxed requirements). In this situation the
averaging filter will again provide some aliased signal removal. We can use the topology
of Fig. 31.56 with a divider of (K/4) and four registers in each comb filter, that is, each
comb filter has a transfer function of 1 − z −4 . The sampling clock gets reduced from fs to
fs/(K/4) and the output clock rate is 8B.
Chapter 31 Data Converter SNR 125

Limits input frequency content to f s /2

First stage decimation Second stage decimation

Analog in, f in L digital Out

 1  [1 − z −4 ]
L
filter
AAF ADC   D Q
Fig. 31.64a (b) (c)  1 − z −1  (d) (e) clk (f)

Clock in, f s Clk

÷ K/4 ÷4

Higher frequency clock can be used f s /K = 2B

in the digital filter to simplify circuitry
Figure 31.63 General averaging and decimation topology for an oversampled ADC.

4. Figure 31.63 shows the entire system for case 3 above, with the addition of a
digital filter on the output of the first-stage decimation for reducing the sampling, or
output clocking frequency, to 2B. The digital filter used in the second decimation stage is
generally a half-band digital filter (covered in most books on digital filtering). Half-band
filters are used because of the simplicity of their implementation (half of the filter's
coefficient are zero) and the fact that the filter's transition frequency is symmetric around
its clocking frequency divided by four (which we can use, with a divider or using two,
cascaded, half-band filters to set the filter's cutoff frequency to B when the clocking
frequency is 4[ f s /K] = 8B ).
Figure 31.64 shows the spectrum of the signals in Fig. 31.63 for the general
situation. Figure 31.64a is the AAF input, which we have drawn with an arbitrary shape.
In 31.64b we see that the AAF limits the input signal spectrum to f s /2 (and we should
see, once again, the relaxed requirements placed on the AAF when using oversampling).
Figure 31.64c shows the ADC's output spectrum resulting from sampling the input
waveform (actually the output of the AAF). After first stage decimation, Fig. 31.64d, the
signal is passed through a sinc (averaging) filter and then resampled at 4(f s /K) (= f s /2
when K = 8). Figure 31.64e shows the output of the half-band filter prior to
down-sampling (second stage decimation). The figure assumes the half-band filter is
clocked with an effective clock frequency of 4B (the actual clock frequency is 8B as
discussed above) or 4[ f s /(K/4)] . So the filter's cutoff frequency is B. The half-band filter's
implementation may also use the high frequency clock signal to simplify the filter's
implementation. Finally, Fig. 31.64f shows the spectrum resulting after final decimation.
The clock frequency out of the final stage is 2B, while the desired signal bandwidth is B.
It's important to remember that unless there is some reason to lower the clock
frequency (for example, we want to store the ADC/averaging filter's digital output in
memory), we can avoid the aliasing problems associated with decimation (see Fig. 31.58)
and the added complexity. Also note that the desired spectrum of Fig. 31.64e must
ultimately be reconstructed using a DAC and a reconstruction filter (RCF). Because of the
unwanted spectral content, directly adjacent to the desired content, the reconstruction
becomes more challenging when decimating down to 2B.
126 CMOS Mixed-Signal Circuit Design

f s /2 fs Assuming K = 8
B 8B = f s /2
Input signal spectrum
(a)
f

(b) Spectrum after AAF

f
ADC output
(c)
f
After first stage decimation
(d)
f
4B
After passing through half-band filter
(e)
f
After second stage decimation down to 2B
(f)
B f
Desired signal spectrum
Figure 31.64 Spectrums of the resulting signals for the decimation scheme shown in Fig. 31.63.

31.2.3 Interpolating Filters for DACs

In the last section we discussed how we were able to average the outputs of a lower
resolution ADC with an averaging filter to increase the effective ADC resolution, Fig.
31.40. In this section we discuss how to interpolate between adjacent digital DAC input
words to attain a large effective output resolution while reducing the required resolution
of the DAC, Fig. 31.65. (To interpolate is to estimate a value between two known
values.) We use the same symbols and terminology of the last section in this section.

Interpolate and introduce Reconstruction

additional digital words N bits filter
x[Ki ⋅ T s ]
Digital in Out In Analog out
K DAC RCF
N + N Inc y[nT s ]

fs Clock in

Interpolation Filter
Figure 31.65 Block diagram of a DAC that uses interpolation to increase effective DAC
resolution.
Chapter 31 Data Converter SNR 127

Also, as in the last section, Bennett's criteria must be valid. In particular, the digital
word must be busy and the DAC must be linear to the final desired resolution (that is, the
N-bit DAC must be linear to N + NInc).
The Dump and Interpolate
Figure 31.66 shows the basic idea of introducing digital words in between the words
coming into the interpolation circuit of Fig. 31.65. The inputs to the interpolating filter are
indicated by the thicker lines in the figure. The interpolator introduces additional samples
in between these inputs. If the frequency of the input samples is 2B then the frequency of
the samples coming out of the interpolator is
f s = K ⋅ 2B (31.112)
noting that, since we are using the same notation as used in the last section, the rate of
words being clocked into the DAC is the same ( f s ) as the rate at which the ADC was
clocked in the last section.

Digital words Interpolator adds these digital words

input to DAC (adds K − 1 samples)

time
Interpolator inputs

Figure 31.66 How the interpolation circuit increases the sample rate while
introducing samples in between the existing samples.

If the inputs to the interpolator are x[Ki ⋅ T s ] and the outputs of the interpolator
are y[nT s ] , we can write
K⋅i−1
x[Ki ⋅ T s ] − x[K(i − 1) ⋅ T s ]
y[n ⋅ T s ] = x[K(i − 1) ⋅ T s ] + Σ
n=K(i−1)
[n − K(i − 1)] ⋅
K
(31.113)

to describe the operation of the interpolator. Rewriting this equation to show only the
change between adjacent outputs results in
x[Ki ⋅ T s ] − x[K(i − 1) ⋅ T s ]
y[n ⋅ T s ] − y[(n − 1) ⋅ T s ] = (31.114)
K
Taking the z-transform of this equation results in
−K
Y(z)(1 − z −1 ) = X(z) ⋅ 1 − z (31.115)
K
or
Y(z) 1 1 − z −K
H(z) = = (31.116)
X(z) K 1 − z −1
128 CMOS Mixed-Signal Circuit Design

which is the familiar transfer function for our averager presented in the last section. The
implementation of our interpolator, termed a Dump and Interpolate, is shown in Fig.
31.67. The input words are dumped into latches which serve two purposes: (1) to store
two consecutive, slow input words for generation of the incremental change in the fast
output samples, and (2) to pass the interpolator input words directly to the output,
through the multiplexer (MUX), every K clock cycles. The ÷ K is implemented simply by
removing the lower bits of the adders output word. As we saw with the
accumulate-and-dump circuit, this implementation has practical problems that result in the
need to use other implementations (which we'll discuss next).

Interpolate the additional values using latches and adder

Dump input into these latches

÷K Latches
Input, x[Ki ⋅ T s ]
Latches Latches

MUX Latches
Clock, f s /K
divide by K Output, y[nT s ]

Clock, f s

Figure 31.67 A dump-and-interpolate circuit used for interpolation and reverse averaging.

Practical Implementations of Interpolators

We can demonstrate the implementation of interpolating filters for reducing the
requirements placed on the resolution of the DAC by considering the four basic cases
discussed in the last section concerning the spectral content of the input signals (which are
now digital signals, that is, in the last section our input signal to the ADC was analog,
while in this section the input to the interpolating filter is digital).
1. The input signal bandwidth is limited to B [= f s /(2K)] and is clocked at 2B. In
this case we can perform the interpolation in one stage as seen in Fig. 31.68. Note how we
have, when compared to Fig. 31.56, switched the order of the integrators and the comb
filters. We are still using the slower clock, f s /K , to generate the K ⋅ T s delay in the comb
filters. The rate at which the words are coming out of the interpolator is f s (= 16B if
K = 8) . The word size coming out of the comb filters is the same as the input word size,
that is, N + N Inc . The word size increases as we move through the integrators, as we saw
in Ex. 31.22. The word size coming out of the final integrating stage, prior to dropping the
lower bits, is N + N Inc + L ⋅ log 2 K . The digital bits we connect to the DAC are the MSBs
of this word, where the lower N Inc + L ⋅ log 2 K bits are dropped.
Chapter 31 Data Converter SNR 129

N + N inc Drop all but N MSB bits

L comb filters L integrators
L
In
(1 − z −1 )
L  1  Output to DAC
 1 − z −1 
f s /K clk
N + N inc bits ÷K N + N inc + L ⋅ log 2 K bits
fs Clock Clock to DAC

Figure 31.68 Implementation of a single stage interpolation filter. See Fig. 31.55
for handling the word size increase in the integrators.

2. The input to the interpolator/DAC has the spectrum shown in Fig. 31.58c and is
clocked at 4B. The interpolating filter has the same topology shown in Fig. 31.68 except
that two registers are used in the comb filter and the divider is changed to K/2. Again, the
DAC is clocked at fs. The RCF together with the sinc filter used in the interpolator limits
the output spectral content.
3. The input to the interpolator/DAC has the spectrum shown in Fig. 31.59b and is
clocked at 8B. The interpolating filter has the same topology as the one shown in Fig.
31.68 except that four registers are used in the comb filter (see Fig. 31.63) and the divider
is changed to K/4. Again, the DAC is clocked at fs. The RCF together with the sinc filter
used in the interpolator limit the output spectral content.
4. Our input spectrum is shown in Fig. 31.64f and clocked into the interpolation
filter at 2B (the general situation that results in the most relaxed requirements on the
RCF). The basic, general interpolation structure is shown in Fig. 31.69. Figure 31.70
shows the spectrums at various points in this circuit. The input spectrum to the
interpolation circuit is shown in Fig. 31.70a. This input is connected to a set of latches
clocked at 2B. The output of these latches is connected to the digital filter, which clocks
the values in at 8B and has a response, as seen in Fig. 31.70b. We need to understand
what's happening at this point. If we look at the output register used in Fig. 31.63, we see

First stage interpolation Second stage interpolation

digital L
In L  1  Out
D Q filter
[1 − z −4 ]   DAC RCF
(a) clk (b) (c)  1 − z −1  (d) (e)

Analog
f s /K = 2B 4( f s /K) = 8B
÷4 ÷ K/4
Clock, f s

Figure 31.69 General interpolation and reverse averaging topology for an oversampled DAC.
130 CMOS Mixed-Signal Circuit Design

f s /2 = 8B here fs Assuming K = 8
Input Nyquist rate

(a)
B f
Input holding register sinc response
(b)
B 4B f
Nyquist rate after resampling
After passing through half-band filter
(c)
B 4B f
Sinc response After passing through second-stage interpolator filter
(d)

f
Desired signal spectrum. Nyquist rate after resampling

(e)
3B f
RCF response may leave some unwanted spectral content
RCF reponse eliminates all unwanted spectral content

Figure 31.70 Spectrums of the resulting signals for the interpolation scheme shown in Fig. 31.69.

that we were only saving one out of every four samples coming out of the digital filter. In
Fig. 31.69 we are "estimating" these samples by simply clocking each input value four
times into the digital filter. Figure 31.71 shows the situation in more detail. It is desirable
to determine how this input holding register affects the spectrum of the input signal. We
can relate the input of the register (a set of latches) to the register's output using
4⋅i−1
x[4(i − 1) ⋅ T s ]
y[nT s ] = Σ
n=4(i−1) 4
(31.117)

If we look at the change between adjacent outputs we get

y[n ⋅ T s ] − y[(n − 1) ⋅ T s ] = x[4i ⋅ T s ] − x[4(i − 1) ⋅ T s ] where n = 4(i − 1) (31.118)
which results in a transfer function of
−4
H(z) = 1 − z −1 (a sinc filter) (31.119)
1−z
Since we are only looking at one out of every four pairs of possible samples, set by the
requirement that n = 4(i − 1) (where n and i are both integers), the value of the transfer
function will actually be 1/4 of Eq. (31.119).
Chapter 31 Data Converter SNR 131

same signal In, x[4i ⋅ T s ]

Digital filter
In In Out
D Q D Q
x[4i ⋅ T s ] clk clk y[nT s ]
t 4iT s
Filter input
holding register Out, y[nT s ]
f s /K = 2B ÷4
4( f s /K) = 8B

t nT s

Figure 31.71 Showing effects of digital filter input holding register on the input data.

In the general interpolation scheme discussed in most digital signal processing

books, zeroes, that is digital words with a value of zero, are used for the extra values
when interpolating (increasing the sampling frequency). This is commonly known as
zeroes padding the input waveform. Adding K − 1 zero values into a waveform, between
adjacent words, results in an effective reduction in the input waveform's amplitude by K.
This is easy to understand if we think of a DC input of 1 and then add three adjacent
zeroes. The resulting waveform will now have an average value of 0.25. The reduction in
amplitude can be compensated for by multiplying the input (or output) by four, in this
example, which is simply a shift left two times. Here, in Fig. 31.69, we are avoiding the
amplitude reduction by simply clocking the same input value four times (here K = 4 ). The
drawback, as discussed above, is the added sinc response in the signal path.
Figure 31.70c shows the output of the digital filter which, again, is generally (but
not necessarily, see Ch. 35) implemented using a half-band digital filter. At this point the
digital word size is essentially the same size as the input word size. After passing through
the sinc filter, the word size and word rate (frequency) increases, as indicated in Fig. 31.68
and Ex. 31.22, with a resulting attenuation of the images in the spectrum, Fig. 31.70d.
Note how the first side lobe amplitude affects the amount of residual spectral content from
the images at 4B. Finally, the reconstruction filter attenuates the remaining unwanted
spectral content.
The RCF deserves additional comment. Figure 31.70e shows two RCF responses.
In one case the RCF limits the spectral content to 3B. This results in elimination of any
unwanted spectral content at the cost of a complex analog filter implementation. In the
second case the RCF limits the spectral content to f s /2 (the same response as the AAF).
While resulting in a simpler filter, the spectrum still contains unwanted spectral content, in
addition to the desired content between DC and B, as shown in Fig. 31.70e. The actual
RCF used depends on the application. The point here is that the design of the RCF can be
more challenging than the design of the AAF in a mixed-signal system.
132 CMOS Mixed-Signal Circuit Design

31.2.4 Bandpass and Highpass Sinc Filters

There are many situations, especially in communication systems, where we may want to
perform data conversion on a range of frequencies that doesn't extend from DC to B, as
has been assumed in this book up until this point. Bandpass ADCs and DACs, for
example, are becoming popular in radio communication systems. In this section, we
introduce bandpass and highpass averaging sinc-shaped filters.
Canceling Zeroes to Create Highpass and Bandpass Filters
As we saw in Fig. 31.40, we can generate a lowpass filter by canceling the zero at DC in a
comb filter, see also Eq. (31.79) for an intuitive explanation of the lowpass frequency
response. We can generate a highpass filter by canceling a comb filter zero at f s /2 , as seen
in the example shown in Fig. 31.72 with K = 8. The same equations, Eqs. (31.94) and
(31.95), can be used to describe the behavior of this filter where, in the highpass response,
the main lobe has shifted to f s /2 . Also, when looking at Fig. 31.72, remember that the
frequency response of a digital filter is periodic with period fs.

1 − z −8
= 7z −
8 1
8 1+z −1 z (z + 1)
7

f s /2 DC
f s /4 f s /2 fs f
3f s /8

Figure 31.72 A highpass filter implementation using a comb filter.

We can generate a bandpass filter by canceling the zeroes at f s /4 and 3f s /4, or

some other frequencies, using a digital resonator. The general topology of the bandpass
digital filter is shown in Fig. 31.73. Keeping in mind that the digital resonator is used to
cancel the zeroes of the comb filter, we can write
H D (z) = 1 = z2 = z2
1 − 2 cos  2π f s  ⋅ z −1 + z −2 z 2 − 2 cos  2π f s  ⋅ z 1 + 1  z − e +j⋅2π fs   z − e −j⋅2π f s 
f f f f

  
(31.120)

Comb filter Digital resonator

In 1 Out
1 − z −K
1 − 2 cos  2π f s  ⋅ z −1 + z −2
f

Figure 31.73 Implementing a sinc bandpass filter.

Chapter 31 Data Converter SNR 133

The time domain representation of this equation is

 f
y[nT s ] = 2 cos  2π  ⋅ y[(n − 1)T s ] − y[(n − 2)T s ] + x[nT s ] (31.121)
 fs 
It's desirable to determine at which frequencies the cosine term is an integer, a zero, or a
value that results in a trivial multiplication, that is, a shift so that we can implement the
bandpass filter with trivial multiplications. In other words, we want a filter that uses only
delays and additions so that its implementation is simple. The first frequency we will
investigate is f s /4. At this frequency the cosine term is zero and the digital-resonator/
comb filter transfer function (the bandpass transfer function in Fig. 31.73) reduces to
−K
H(z) = 1 − z −2 (31.122)
1+z
The magnitude and z-plane response of this filter, for K = 8, is shown in Fig. 31.74.

1 − z −8 = z 8 − 1 f s /4
4 1 + z −2 z 6 (z 2 + 1)
6

DC
f s /8 3f s /8 fs f
f s /4 f s /2

Figure 31.74 A bandpass filter implementation using a comb filter and digital resonator.

We can determine the magnitude response of Eq. (31.122) following the same
procedure used to determine Eq. (31.93). The result, for the f s /4 resonator, is

2  1 − cos K2π f s  sin  Kπ f s 

f f

H( f ) = = K = 4, 8, 12, 16, ... (31.123)

2  1 + cos 4π f s  cos  2π f s 
f f

At the center of the passband, that is f s /4 , H( f ) = K/2. The ratio of the main lobe to the
first side lobe, on either side, is plotted in Fig. 31.75 along with the lowpass sinc filter
response and is calculated using
Main lobe = K ⋅ sin 3π (31.124)
First side lobe 2 K
The cosine term in Eq. (31.121) can be set to ±1 when f = f s /6 or f s /3 resulting in
a bandpass filter that is easy to implement. It should be clear that with the appropriate
choice of sampling frequency, number of zeroes K used in the comb filter, and value of the
cosine term, many different combinations of simple bandpass filters can be implemented
using these techniques.
134 CMOS Mixed-Signal Circuit Design

dB Low pass response

13.5 dB
13

11

Main lobe
First sidelobe
9 Bandpass response when f = f s /6 or f s /3

7
Bandpass attenuation when f = f s /4
5

3
3 4 6 8 10 12 16 K

Figure 31.75 Lowpass and bandpass filter attenuation versus number of comb filer zeroes K.

The ratio of the main lobe to the first sidelobe for f = f s /6 or f s /3 is given,
assuming K = 12, 24, ... , by

K sin  2K
3π   π 3π 
 sin  3 − 2K 
Main lobe = = 1.15K sin  3π  sin  π − 3π  (31.125)
First side lobe sin π3 2K 3 2K
which is approximately 13.5 dB for K = 24, 36, 48 ... and 10.15 dB for K = 12, see Fig.
31.75.
To increase the amount of attenuation between the main lobe and the first side lobe
in a bandpass filter implementation, we can cascade filter sections (as we did in the
lowpass filter implementations discussed earlier). For example, cascading five f s /4
bandpass filters with K = 8 will result in an attenuation of 57 dB. Also, note that by
changing the sampling, or filter clock frequency fs , we can easily change the bandpass
filter's center frequency. A change in the clock frequency, and its selection, can easily be
implemented using a counter and some control logic.

Example 31.23
Sketch the block level circuit diagram for an f s /4 digital resonator.
From Eq. (31.121) the time domain representation of the f s /4 resonator can be
written as
y[nT s ] = x[nT s ] − y[(n − 2)T s ]
The implementation is shown in Fig. 31.76. T
Chapter 31 Data Converter SNR 135

x[nT s ] y[nT s ]

Q D Q D H(z) = 1
clk clk 1 + z −2
fs
f s /4 resonator

Figure 31.76 Implementation of a digital resonator.

Frequency Sampling Filters

Consider the topology of a comb filter and resonators shown in Fig. 31.77. We are feeding
the output of the comb filter through the resonators (with different center frequencies) and
then using the combined sum of the resulting bandpass filter responses (the sinc shapes) to
build a bandpass filter. This is exactly the same as reconstructing a waveform in the time
domain using an ideal RCF, as discussed in the last chapter (see Fig. 30.17), except now
we are using the summation of the frequency domain sinc responses to generate a
bandpass filter with a variable width. Note how every other digital resonator is subtracted
rather than added to the final result. This is to account for the phase reversal between
adjacent resonator outputs.

Digital resonators
f1

−1
f2
f1
Comb filter f3
In
1 − z −K Out

−1
f X−1

fX

Sinc responses
Desired filter response

f1 f3 f5 Sidelobes not shown

f2 f4 f6
Figure 31.77 A frequency sampling filter.
136 CMOS Mixed-Signal Circuit Design

31.3 Using Feedback to Improve SNR

We have seen that by averaging the outputs of an ADC, or interpolating between inputs of
a DAC, the effective data converter resolution can be increased. As specified by Eq.
(31.52), every doubling in (octave increase in) K (where K is the number of points
averaged or the oversampling ratio) results in a 0.5-bit increase in effective resolution. An
effective ADC resolution increase of 6-bits requires averaging 4,096 samples. If a 1 MHz
signal bandwidth is of interest, our sampling clock frequency, f s , will have to be 8.192
GHz!
In this section we briefly introduce the idea that feedback can be used with data
converters (ADCs and DACs) to improve overall data conversion system performance
(lower the amount of averaging or oversampling needed to attain a given resolution over a
certain bandwidth). A topology of this nature is called a modulator or coder (for
analog-to-digital conversion) or a demodulator or decoder (for digital-to-analog
conversion). The complete analog-to-digital interface (a circuit block that functions as an
ADC) would be made up of a modulator and a decimating filter, while the
digital-to-analog interface (a circuit block that functions as a DAC) would consist of an
interpolating filter and a demodulator. This can be confusing since, for example, a
modulator will contain a low-resolution ADC in a feedback configuration which, together
with the decimating filter, behaves like a high-resolution ADC.
31.3.1 The Discrete Analog Integrator
An analog building block that we will find useful in implementing our data converters,
using feedback, is the discrete analog integrator, DAI, shown in Fig. 31.78. Here we're
assuming the reader is familiar with the material presented back in Ch. 27 covering
switched-capacitor circuits (for example, the reader is familiar with the operation of
parasitic insensitive integrators). The two clocks signals, φ 1 and φ 2 , form nonoverlapping
clock signals (see Fig. 14.5 in Ch. 14). Also, we are assuming the common mode voltage,
VCM , falls halfway between the mixed-signal system's high- and low-reference voltages.
Table 31.2 shows the various relationships between the possible inputs and outputs
for the DAI of Fig. 31.78. Let's derive the input/output relationships for the most general
situations where both v1 and v2 are the inputs.

Input Output connected to φ 1 Output connected to φ 2

−1 z −1/2 ⋅ C I
v 1 = input and v 2 = V CM z C
⋅ I
1−z −1 CF 1 − z −1 C F
−z −1/2 −1 ⋅ C I
v 2 = input and v 1 = V CM C
⋅ I
1 − z −1 C F 1 − z −1 C F
v 1 and v 2 are both inputs V 1 (z) ⋅ z −1 − V 2 (z) ⋅ z −1/2 C I V 1 (z) ⋅ z −1/2 − V2 (z) C I
⋅ ⋅
1 − z −1 CF 1 − z −1 CF

Table 31.2 Discrete analog integrator input/output relationships

(see also Eqs. [31.136] and [31.137]).
Chapter 31 Data Converter SNR 137

CF
φ1 φ2
φ1
V CM
CI φ2 v out
v1
v2
V REF+ + V REF−
Ts V CM =
2 Bottom
φ1 plate
(the plate closest
φ2 to the substrate)

t
n−1 n
n − 1/2

Figure 31.78 Schematic diagram of a discrete analog integrator (DAI).

To begin, let's assume the output of the DAI is connected to the op-amp through
the φ 1 switch. When the φ 1 switches are closed ( φ 1 is high) at n − 1 (the instance when
the switches shut off), the charge stored on CI is
Q 1 = C I (V CM − v 1 [(n − 1)T s ]) (31.126)
and the output of the integrator is v out [(n − 1)T s ] . When the φ 2 switches turn on the
charge stored on CI becomes
Q 2 = C I (V CM − v 2 [(n − 1/2)T s ]) (31.127)
remembering that the op-amps holds its noninverting input terminal at VCM. The difference
in these charges, Q 2 − Q 1 , is transferred to the op-amp's feedback capacitor resulting in an
output voltage change. This change can be written as
(v out [nT s ] − v out [(n − 1)T s ])C F = C I (v 1 [(n − 1)T s ] − v 2 [(n − 1/2)]T s ) (31.128)
or writing this equation in the z-domain results in
CI
V out (z)(1 − z −1 ) = (V 1 (z) ⋅ z −1 − V 2 (z) ⋅ z −1/2 ) (31.129)
CF
The transfer function of the DAI with the output connected to the φ 1 switches is then
C I V 1 (z) ⋅ z −1 − V 2 (z) ⋅ z −1/2
V out (z) = ⋅ (31.130)
CF 1 − z −1
Similarly, if we connect the output through the φ 2 switches (the edges we label n in Fig.
31.78 shift in time by T s /2 ) we can write
138 CMOS Mixed-Signal Circuit Design

Q 1 = C I (V CM − v 1 [(n − 1/2)T s ]) (31.131)

Q 2 = C I (V CM − v 2 [nT s ]) (31.132)
and
(v out [nT s ] − v out [(n − 1)T s ])C F = C I (v 1 [(n − 1/2)T s ] − v 2 [nT s ]) (31.133)
The transfer function of the DAI with the output connected to the φ 2 switches is then
C I V 1 (z) ⋅ z −1/2 − V 2 (z)
V out (z) = ⋅ (31.134)
CF 1 − z −1
Note that if V 2 (z) = V CM , this equation can be written as
V out (z) C I z −1/2
H(z) = = ⋅ (31.135)
V1 (z) C F 1 − z −1
which has a frequency response, H( f ) , shown in Fig. 31.34. Note that the factor C I /C F
simply scales the amplitude response. If this factor is unity then the magnitude response, as
shown in Fig. 31.34, is 0.5 at f s /2 . The z −1/2 term in the numerator simply modifies the
phase response of the DAI (delaying the output by T s /2 or −180 degrees) and has no
effect on the magnitude response. (We'll discuss this more in a moment.) Note that at this
point we could discuss the frequency responses of the transfer functions given in Table
31.2. However, we would see that the discussions and results earlier in the chapter for the
digital integrator would apply to the DAI with no, or little, modifications.

Example 31.24
Determine the transfer function of the DAI of Fig. 31.78 without the switches on
the output of the op-amp.
Reviewing Fig. 31.78 we see that charge is transferred to the feedback capacitor
only when the φ 2 switches are closed. Therefore, the output only changes states
during the time interval when the φ 2 switches are closed. The transfer function of
the DAI, when no switches are used on the output of the op-amp, is given by Eq.
(31.134). Using the φ 1 switches simply adds a half clock cycle delay, z −1/2 , to the
integrator's transfer function (instead of the output changing with the rising edge
of φ 2 , the output changes one-half cycle later on the rising edge of φ 1 ). T
A Note Concerning Block Diagrams
As we draw block diagrams describing our modulator topologies in this chapter and the
next we often show a circuit like the one shown in Fig. 31.79. The summation, gain, and
integrating blocks are implemented with a single switched-capacitor DAI having the
transfer function given by Eq. (31.134). The gain, G, of the DAI is set by the ratio of
capacitors as indicated in the figure. It's important to realize that this circuit is entirely
analog and is interfaced to, in general, both ADCs (Vout[z] is connected to the input of an
ADC ) and DACs (V2[z] is connected to the output of a DAC).
It should be clear from both Fig. 31.79 and Table 31.2 that many different
combinations of discrete analog building blocks are possible. Figure 31.80 shows two
Chapter 31 Data Converter SNR 139

V 1 (z) 1 C I V 1 (z) ⋅ z −1/2 − V 2 (z)

G ⋅ z −1/2 V out (z) = ⋅
1 − z −1 CF 1 − z −1

CI
G V 2 (z) G=
CF
Discrete analog integrator

Figure 31.79 Block diagram of a DAI.

other possibilities. In part (a) the capacitors used have the same parasitic capacitance on
each plate (see the lateral capacitor in Fig. 33.11 for example), so there is no benefit to
using a bottom-plate insensitive topology (Fig. 31.78). The transfer function of this DAI is
CI −1
V out (z) = ⋅ z ⋅ (V 2 (z) − V 1 (z)) (31.136)
C F 1 − z −1
noting each input signal sees the same delay, i.e., z−1 when the outputs are connected
through φ1 controlled switches and z−1/2 delay when no switches or φ2 controlled switches
are used. If the integrator inputs must see the same delay and the capacitors available have
asymmetric parasitic capacitance, the topology of Fig. 31.80b can be used. Its transfer
function is

V out (z) = z −1 ⋅  C I1 ⋅ V (z) + C I2 ⋅ V (z)  (31.137)

1 − z −1  C F 
1 2
CF
noting the input signals can be scaled independently (a useful feature in filter design).

φ1 φ2 CF
(a)
V 1 (z) φ1
V CM V out (z) =
CI
V 2 (z) CI z −1
⋅ ⋅ (V 2 (z) − V 1 (z))
C F 1 − z −1
CF

(b)
V CM C I1 φ1
V CM V out (z) =
V 1 (z)
z −1 ⋅  I1 ⋅ V 1 (z) + I2 ⋅ V 2 (z) 
C C
1 − z −1  C F CF
C I2
V 2 (z)

Figure 31.80 Other forms of DAIs.

140 CMOS Mixed-Signal Circuit Design

31.3.2 Modulators
The basic topology of a feedback modulator or coder is shown in Fig. 31.81. Depending
on the circuit blocks used for A(z) and B(z) feedback modulators can be separated into
two categories: predictive modulators and noise-shaping modulators [10].

In X(z) Y(z) Out

A(z) ADC
(to digital
Analog Digital filtering.)
Analog

DAC B(z)

Figure 31.81 Block diagram of a feedback modulator.

Predictive modulators (a.k.a. predictive coders), an example being delta-

modulation, attempt to feed back an analog signal with the same value as the input signal.
This drives the output of the summer to zero, reducing the required input range of the
ADC and, possibly, the quantization error introduced by the ADC. Predictive modulators
effectively output the change in the input signal over time. Noise-shaping modulators, an
example being sigma-delta-modulation (also known as delta-sigma-modulation), on the
other hand, feed back (and output) the average value of the input signal. This signal can be
filtered (averaged) to reduce the accuracy required of the analog circuit components.
Noise-shaping modulators effectively output the average of the input signal over time. In
a noise-shaping data converter the averaging and decimating filter, as discussed earlier, is
connected to the output of the modulator. Because of the averaging used in noise-shaping
modulators, the analog components, in the forward path of Fig. 31.81, require less
accuracy. However, the DAC's output, in the feedback path (which is subtracted from the
input), doesn't experience the averaging so, once again, the DAC must be linear to the
final desired resolution of the data converter. DAC linearity concerns have led to the use
of a single-bit DAC (an inverter, see Ch. 29), in many noise-shaping data converter
applications. The one-bit DAC is inherently linear. (Two output points determine a line!)
Because of the relaxed requirements placed on the analog circuit components, we will
concentrate the next chapter, in detail, on noise-shaping topologies for both ADCs and
DACs. Notice that both predictive and noise-shaping modulators utilize oversampling.
To understand these statements in more detail, let's use the additive quantization
noise model for the ADC developed in Ch. 30 and shown in Fig. 30.56. Figure 31.82
shows Fig. 31.81 redrawn using this model where the quantization noise is represented in
the z-domain by E(z). We can relate the inputs (the wanted input signal and the unwanted
quantization noise) to the output of the feedback modulator by
Chapter 31 Data Converter SNR 141

Signal transfer function, STF(z) Noise transfer function, NTF(z)

A(z) 1
Y(z) = ⋅X(z) + ⋅E(z) (31.138)
1 + A(z) ⋅ B(z) 1 + A(z)B(z)
In a predictive modulator the feedback filter, B(z), has a large gain so that, ideally, the fed
back signal equals the input signal. If A(z) = 1 (a wire), then both the STF (signal transfer
function) and the NTF (noise transfer function) have a value of, approximately, 1/B(z).
Recovering the input signal requires passing the output of the predictive modulator
through an analog filter with a transfer function of precisely B(z) (noting that B[z] is a
digital filter in the modulator of Fig. 31.82). The required precision of the analog filter (the
matching between the filter in the modulator and the filter in the demodulator) limits the
attainable resolution when using predictive modulators. Notice that both the input signal
and the quantization noise experience the same spectral shaping (spectral discrimination is
absent in a predictive modulator). Also note that the name "predictive" comes from the
modulator attempting to predict the input signal in order to drive the output of the
summer to zero. If the prediction is perfect, the signal that is fed back exactly matches the
input signal.

z-domain representation
E(z) of the quantization error

ADC
In X(z) Y(z) Out
A(z)

Analog Analog Digital

DAC B(z)

Figure 31.82 Block diagram of a feedback modulator.

In a noise-shaping modulator the gain of the forward path, A(z), is large in the
signal bandwidth so that the STF is approximately unity (assuming B[z] = 1). The NTF, on
the other hand, will approach zero, ideally, in the bandwidth of interest. Note that the
signal spectrum passes through the modulator essentially unchanged, while the
quantization noise spectrum is shaped (and thus the name noise-shaping). No precision
filter or analog components are required, as discussed earlier, except, perhaps, for the
DAC in the feedback path of the modulator. We'll see in the next chapter that if A(z) is an
integrator, the quantization noise is pushed to higher frequencies so that it can be removed
with the averaging filter. This is a very important concept, as a noise-shaping modulator
does not reduce the quantization noise to attain higher resolutions, but rather pushes the
noise to frequencies outside of the signal bandwidth of interest.
142 CMOS Mixed-Signal Circuit Design

REFERENCES
[1] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS: Circuit Design, Layout, and
Simulation, Wiley-IEEE, 1998. ISBN 0-7803-3416-7
[2] L. W. Couch, Modern Communication Systems: Principles and Applications,
Prentice-Hall, 1995. ISBN 0-02325286-3
[3] S. Haykin, An Introduction to Analog and Digital Communications, John Wiley
and Sons, 1989. ISBN 0-471-85978-8
[4] P. A. Lynn and W. Fuerst, Introductory Digital Signal Processing, Second
Edition, John Wiley and Sons, 1998. ISBN 0-471-97631-8
[5] E. P. Cunningham, Digital Filtering: An Introduction, John Wiley and Sons, 1995.
ISBN 0-471-12475-3
[6] R. K. Hester, Introduction to Oversampled Data Conversion, Notes from a
tutorial at the 1995 International Solid-State Circuits Conference (ISSCC-95).
[7] W. R. Bennett, "Spectra of Quantized Signals," Bell System Technical Journal,
Vol. 27, pp. 446-472, July 1948.
[8] J. C. Candy and G. C. Temes (eds.), Oversampling Delta-Sigma Data Converters,
IEEE Press, 1992. ISBN 0-87942-285-8
[9] S. R. Norsworthy, R. Schreier, and G. C. Temes (eds.), Delta-Sigma Data
Converters: Theory, Design, and Simulation, IEEE Press, 1996. ISBN
0-7803-1045-4
[10] S. K. Tewksbury and R. W. Hallock, Oversampled, Linear Predictive and
Noise-Shaping Coders of Order N>1, IEEE Trans. Circuits and Sys., Vol.
CAS-25, pp. 436-447, July 1978.
LIST OF SYMBOLS/ACRONYMS
ACF - Autocorrelation Function, see Eq. (31.30)
ADC - Analog-to-Digital Converter
B - Bandwidth of the input signal, see Eq. (31.69)
DAC - Digital-to-Analog Converter
dBc - Decibels with respect to the carrier, see Eq. 31.9
DR - Dynamic Range, see Eq. (31.10)
∆T s - Peak-to-peak amount of clock jitter
∆V s - Uncertainty in the sampled voltage
fclk - Clock frequency. Also, sometimes called sampling frequency, fs
fin - Input sinewave frequency
Chapter 31 Data Converter SNR 143

fn - Nyquist frequency, which is fs /2. Sometimes also called the folding frequency.
fres - Resolution of a DFT
fs - Sampling frequency. Also, sometimes called clock frequency, fclk , or Nyquist rate.
H( f ) - Transfer function of a system
H(z) - Z-Domain representation of H( f )
K - Oversampling factor or number of points averaged. See Eq. (31.22) or Eq. (31.51)
L - Order of sinc averaging filter
LSB - Least Significant Bit, see Eq. (31.2)
M - Order of a noise-shaping modulator (see Ch. 32.)
N - Ideal data converter resolution (number of bits)
Neff - Effective number of bits, see Eq. (31.5)
NFinal - Final data converter resolution after averaging, see Eq. (31.74)
NInc - Increase in data converter resolution, see Eq. (31.53)
NLoss - Number of bits lost because of sampling jitter. see Eq. (31.17)
PDF - Probability Density Function, see also ρ(t)
PAVG - Total average power in a waveform
Pin( f ) - Power Spectral Density (PSD), see Eq. (31.35)
Pjitter( f ) - PSD of the sampling error voltage due to jitter, see Eq. (31.49)
Posc( f ) - PSD of the output of an oscillator, see Eq. (31.50)
PSD - Power Spectral Density
PQe( f ) - Quantization noise power spectral density
ppm - Parts per million, a multiplier of 10 −6
L - Number of sections used in an averaging filter
Rin(t) - Autocorrelation function, see Eq. (31.30)
ρ(t) - Probability Density Function, PDF
σ - Standard deviation or square root of the variance
σ 2 - Variance of a PDF, see Eq. (31.44)
Rin(t) - Autocorrelation function, see Eq. (31.30)
RMS - Root Mean Square
SFDR - Spurious Free Dynamic Range, see Eq. (31.9)
144 CMOS Mixed-Signal Circuit Design

SINAD - SIgnal-to-Noise And Distortion. Same as SNDR.

SNR - Signal-to-noise ratio
SNRideal - Ideal signal-to-noise ratio for a data converter, see Eq. (31.1)
SNRmeas - Measured signal-to-noise ratio for a data converter, see Ex. 31.1
SNDR - Signal-to-Noise plus Distortion Ratio, see Eq. (31.7)
Ts - Sampling period
VDFT( f ) - Discrete Fourier transform of V
VLSB - The voltage weighting of a least-significant bit, see Eq. (31.2)
Vp - Peak value of a sinewave
Vin(t) - Input signal, see Eq. (31.29)
VQe( f ) - Power spectral density of the quantization noise, see Eq. (31.54)
VQe,RMS - Root mean squared quantization noise, see Ch. 30.
VQe+D,RMS - Root mean squared quantization noise and distortion, see Eq. (31.7)
VREF+ - Positive reference voltage used in a data converter
VREF− - Negative reference voltage used in a data converter
VRMS - An RMS voltage
y - Average value of y, see Eq. (31.44)
f
j2π f
z - Defined as e s = e j2πfT s
QUESTIONS
31.1 Develop an expression for the effective number of bits in terms of the measured
signal-to-noise ratio if the input sinewave has a peak amplitude of 40% of (VREF+ −
VREF−).
31.2 Determine a data conversion system's SNR if the measured VQe,RMS is 1 mV and the
maximum peak-to-peak amplitude of an input sinewave is 1 V.
31.3 Repeat Ex. 31.2 if the sampling frequency is increased to 200 MHz. Does the SNR
change?
31.4 Why is the amplitude of the tone at 45 MHz in the DAC output spectrum shown in
Fig. 31.3b smaller than the amplitude of the ADC input signal? What is the origin
of the noise added to the DAC output signal in Fig. 31.3b?
31.5 When using Eq. (31.8) what is the assumed ADC input signal? Put your answer in
terms of the ADC reference voltages.
31.6 Describe in your own words the difference between specifying SNR and SNDR.
Chapter 31 Data Converter SNR 145

31.7 Suppose a perfectly stable clock is available (∆Ts is zero in Eq. [31.12]). Would we
still have a finite aperture window if the clock has a finite rise time? Describe why
or why not?
31.8 How do the number of bits lost because of aperture jitter change with the
frequency of an ADC input sinewave? If the ADC input is a DC signal is aperture
jitter a concern? Why?
31.9 Show the time domain signal that generates the spectrum shown in Fig. 31.10.
Verify in the time domain that the signal's rising and falling edges do indeed vary
from their ideal positions.
31.10 Describe in your own words the problems with simulating clock jitter using
SPICE.
31.11 What does the autocorrelation function (ACF) tell us about a signal? What is the
ACF of a 1 V DC signal. Show the simple calculations leading up to your answer.
31.12 Plot the power spectral density of a sinewave. From this plot show how to
determine the average and RMS values of the sinewave. Show the procedure for
both one-sided and two-sided spectrums.
31.13 Sometimes the average power specified by Eq. (31.37) is termed total average
normalized power of a signal. Why?
31.14 When WinSPICE generates a plot from a DFT the units on the y-axis are volts
peak (the peak value of a sinewave at a given frequency). How do we change this
plot into RMS voltages, voltage spectral density, and power spectral density vs.
frequency?
31.15 Repeat Ex. 31.12 if the sinewaves are first sampled.
31.16 Suppose the jitter in a clock signal can be characterized using the PDF shown in
Fig. 31.12. Further if ∆Ts = 100 ps estimate the RMS value of clock jitter, standard
deviation, and variance of the jitter.
31.17 Suppose that a noise voltage has the PDF shown in Fig. 31.12. If the maximum
voltage deviation from the ideal value is 10 µV estimate the RMS value of the
noise (the standard deviation) and the noise power (the variance).
31.18 Repeat question 31.17 if the noise voltage has a Gaussian PDF as seen in Fig.
31.13.
31.19 Repeat Ex. 31.1 if we want to include an error from sampling jitter, PAVG,jitter of 1
µW.
31.20 If a DC signal is input to a data conversion system, is Eq. (31.51) valid? Name
three conditions on the input signal in order for this equation to be valid.
146 CMOS Mixed-Signal Circuit Design

31.21 Suppose the standard deviation of the quantization noise in a data conversion
system is 1 mV. Using Eq. (31.56) plot the PSD of the quantization noise.
Comment on the assumption that the noise power is limited to the Nyquist
frequency. Does this result in an over- or underestimate for the actual noise power
in the spectrum of interest?
31.22 Show why averaging two 8-bit words, as seen in Fig. 31.19, must result in a 9-bit
word. (Why isn't the sum of the two words divided by two [the average] another
8-bit word?)
31.23 Why must Bennett's criteria be valid for the averaging to reduce the quantization
noise in Fig. 31.19? Give an example where averaging will not reduce quantization
noise.
31.24 Show a figure similar to Fig. 31.20 where an input sinewave with a frequency of
fs/4 is sampled at fs. Show that the magnitude of the resulting fundamental
(indicating that the sinewave lies in the frequency range of DC to fn) sinewave is
2 , as indicated in Fig. 31.22.
31.25 Assuming Eq. (31.68) is valid rederive Eq. (31.4) including the effects of
averaging K ADC output samples. Is Eq. (31.4) or the equation derived here valid
for a slow or DC input signal? Comment on why or why not.
31.26 Assuming Bennett's criteria are valid, does averaging ADC outputs (or DAC
inputs) put any restrictions on the bandwidth of the input signal? Why? Give an
example.
31.27 Comment on the statement "The factor of 2 in the magnitude response of Fig.
31.22 at low-frequencies simply indicates that the digital word length increases by
one bit."
31.28 What is the magnitude response of z −2 + z −3 .
31.29 Repeat Ex. 31.15 if 16 ADC outputs are averaged, that is, K = 16.
31.30 How accurate does an 8-bit ADC have to be in order to use a digital filter to
average 16 output samples for a final output resolution of 10-bits (see Eq.
[31.53]). Assume the ideal LSB of the 8-bit converter is 10 mV. Your answer
should be given in both mV and % of the full-scale.
31.31 If a DC signal is applied to a data converter can a digital averaging filter be used to
increase the system's resolution? What about if a dither signal is added to the DC
input? Use simple time domain drawings to illustrate your answers.
31.32 Name three characteristics of all digital filters.
31.33 Plot Eq. (31.59) on a z-plane. Using this plot show how to graphically determine
the magnitude and phase responses shown in Fig. 31.22.
31.34 The magnitude response shown in Fig. 31.34 becomes infinite as the input signal
approaches DC. Since the filter is digital, what is the maximum output of the filter?
Chapter 31 Data Converter SNR 147

31.35 Show that the peak (+127) and valley (−128) amplitudes of the two's complement
signals in Fig. 31.37 sum to −1.
31.36 Summarize the method of changing a number from binary offset to two's
complement. Demonstrate addition and subtraction using two's complement
numbers. Show how, in two's complement, 8, 33, and 111 sum to 152. Assume a
10-bit word size.
31.37 Suppose a digital filter sums 16 inputs and then outputs the total. If the filter is
clocked at 100 MHz, plot the magnitude response of the filter.
31.38 Comment on the benefits and drawbacks of using an averaging filter with and
without decimation.
31.39 Verify the z-domain function specified by Eq. (31.100) has a frequency response
given by Eq. (31.101). How are the typical input and output signals in the time
domain related for this filter?
3
31.40 What is the magnitude response of (1 − z −1 ) . Sketch a block diagram
implementation for this filter.
31.41 Resketch Fig. 31.53 if, in each transfer function H(z), a pole is added at DC.
31.42 Show the problem with not using a MUX at the input of the adders in Fig. 31.55.
31.43 Is it possible for the accumulate-and-dump circuit to output a spectrum with
aliasing if the input signal is bandlimited to fs? Why or why not?
31.44 In the discussions in this chapter we assumed the digital signals are much larger
than an LSB of a data converter. What happens if this is not the situation for the
sinc averaging filter?
31.45 Is it possible to decimate a digital waveform down to 2B and then later, with some
other hardware or software digital filter, remove all of the aliased signals from the
desired signal?
31.46 Suppose the waveform shown in Fig. 31.66 is the input to a decimator. If K = 8,
what would the output of the decimator look like? Use integers to illustrate your
understanding.
31.47 Suppose a digital word is clocked into a hold register and held there for eight
clock cycles before another word is clocked into the hold register. Is this similar to
the analog sample-and-hold? If the sampling rate (clock frequency) is increased by
a factor of 8 after the hold register what kind of digital filter can we think of the
hold register as being?
31.48 Show that the digital resonator of Fig. 31.76 can be modified if we add a multiplier
to the circuit, so that Eq. (31.120) can be implemented.
148 CMOS Mixed-Signal Circuit Design

31.49 It is more correct to write our DAI continuous time input signals in Fig. 31.78 as
v 1 (t) + V CM and v 2 (t) + V CM
Knowing this rederive Eq. (31.130).
31.50 Repeat question 31.49 for Eq. (31.134).
31.51 Using the results from question 31.49, derive the transfer function, Eq. (32.139),
for the circuit shown in Fig. 32.92 (in the next chapter).
31.52 Show the detailed derivation of Eq. (31.138).
31.53 Summarize the advantages and disadvantages of predictive and noise-shaping data
converters.
 Chapter

32
Noise-Shaping Data Converters

In this chapter we discuss the design of noise-shaping (NS) data converters. Our approach
will be to develop NS theory along with SPICE behavioral models to illustrate, using
simulations, the operation of NS ADCs and DACs. Our goals are to discuss the
fundamentals of NS data converter design and to put a framework together for SPICE
simulations. Having a simulation framework available will allow us to (1) perform a
behavioral simulation using nearly ideal components to determine fundamental
performance limitations of a particular NS converter topology, and (2) replace behavioral
models with actual, MOSFET-based circuits in steps to design and simulate the operation
of a NS data converter in stages. While we can replace the behavioral models with
MOSFET-based circuits, we will delay this discussion (MOSFET-based circuit design in a
submicron process) until the next chapter. This chapter will focus on NS theory and
examples, using simulations, to illustrate the use of the theory.

32.1 Noise-Shaping Fundamentals

In this section we develop SPICE behavioral models to illustrate NS data converter design
and then we present the theory behind the design of first- and second-order NS data
converters using single-bit DACs and ADCs.
32.1.1 SPICE Models
Because data converters employing averaging, such as an NS data converter, can require a
significant number of samples for meaningful operation (the simulation time may be
relatively long), we need to be careful not to develop simulation models that are inefficient
or too complex. At the same time it is desirable to have models complex enough to include
the nonideal effects that occur in the actual circuits used. For example, an op-amp will
have finite gain and an offset voltage while the switches will have nonzero "on" resistance.
150 CMOS Mixed-Signal Circuit Design

In the material that follows we attempt to develop models that are robust, including
fundamental limitations of the circuits used, while at the same time attempting to generate
simple models for fast simulations.
Nonoverlapping Clock Generation and Switches
In this chapter, as we did in Chs. 30 and 31, we assume VDD = 1.5 V (the positive power
supply voltage), VSS = 0 V (the negative power supply voltage), VREF+ = 1.5 V (the
positive data converter reference voltage), V REF− = 0 V (the negative data converter
reference voltage), and f s = f clk = 100 MHz (the sampling, or clock frequency, of the data
converter). The SPICE pulse statements used to generate two 100 MHz nonoverlapping
clocks can be written as
Vphi1 phi1 0 DC 0 Pulse 0 1.5 0 200p 200p 4n 10n
Vphi2 phi2 0 DC 0 Pulse 0 1.5 5n 200p 200p 4n 10n
R2 phi1 0 1MEG
R3 phi2 0 1MEG

where the resistors ensure that the clocks are not floating (not the only elements
connected to the nodes phi1 and phi2 as the clocks may be used exclusively to control
switches in a simulation). The statements used to set up the power supply voltages,
reference voltages (if used), common-mode voltage, and switch trip points can be written
as
VDD VDD 0 DC 1.5
Vtrip Vtrip 0 DC 0.75
VCM VCM 0 DC 0.75
VREFP VREFP 0 DC 1.5
VREFMVREFM0 DC 0

The trip voltage is used in simulating the operation of the switches to indicate when the
switch should be opened or closed. Figure 32.1a shows the use of the basic switch in
SPICE. When phi1 (φ 1 ) is above the trip voltage (0.75 V here), the S1 switch is closed.
When the node phi2 is above the trip voltage, S2 is closed. The SPICE statements
specifying the operation of these switches, in the manner described, are
S1 1 2 phi1 Vtrip switmod
S2 2 3 phi2 Vtrip switmod
.model switmod SW RON=1k

The parameter RON can be used to model the switches' on resistance as shown in Fig.
32.1b. This may be useful when simulating finite settling time effects in a data converter.

φ1 φ2 Node numbers

RON
1 2 3
S1 S2

(a) (b)

Figure 32.1 Using a switch in SPICE.

Chapter 32 Noise-Shaping Data Converters 151

Op-Amp Modeling
Behavioral modeling of op-amps could take up an entire chapter by itself. Here we
introduce a trivial model that is easily modified to account for real op-amp imperfections.
Figure 32.2 shows the basic op-amp symbol and a voltage-controlled-voltage-source used
to simulate the operation of an op-amp. The SPICE statement that specifies the op-amp is
Ein 3 0 2 1 100MEG

where the open-loop gain of the op-amp is 100 million.

1 3
3 1
2 E1
2

Figure 32.2 Simple SPICE op-amp model.

Example 32.1
Determine and simulate the gain of the circuit shown in Fig. 32.3.
This circuit is our discrete analog integrator (DAI) shown in Fig. 31.78 with the v2
input connected to VCM. The transfer function of this circuit in the z-domain is

H(z) = z −1 (32.1)
1 − z −1
From Fig. 31.34 and Eq. (31.84) the magnitude of Eq. (32.1), in the frequency
domain, is (noting the z −1 in the numerator of Eq. [32.1] is a delay of Ts that adds
to the phase of the integrator but doesn't affect the magnitude response)

C F = 1p
φ1 φ2

φ1
V CM
V out
1p
V in C I = 1p
V CM = 0.75 V f clk = f s = 100 MHz

0.75 + 0.05 ⋅ sin (2π ⋅ 5MHz ⋅ t)

Figure 32.3 Circuit used in Ex. 32.1.

152 CMOS Mixed-Signal Circuit Design

H( f ) = 1 = 3.2 (32.2)
2  1 − cos 2π 100
5 


resulting in a peak output voltage of 160 mV (peak-to-peak voltage of 320 mV).

The simulation results are shown in Fig. 32.4. Notice how the output, at DC, is
defined by the initial state of the feedback capacitor, CF . In this case the input and
output of the integrator start at the same voltage. The phase shift can be
calculated, using Eq. (31.85) and knowing the zero is not present, as −99°. Finally,
the SPICE netlist used to generate this plot is listed below.
* Figure 32.4 CMOS: Mixed-Signal Circuit Design *

.tran 1n 500n 0 1n UIC

*WinSPICE command scripts

*#destroy all
*#run
*#plot Vout Vin ylimit 0.6 1.2

*Input power and references

Vtrip Vtrip 0 DC 0.75
VCM VCM 0 DC 0.75

*Input Signal
Vin Vin 0 DC 0 Sin 0.75 50m 5MEG

*Clock Signals
Vphi1 phi1 0 DC 0 Pulse 0 1.5 0 200p 200p 4n 10n
Vphi2 phi2 0 DC 0 Pulse 0 1.5 5n 200p 200p 4n 10n
R2 phi1 0 1MEG
R3 phi2 0 1MEG

*Use a VCVS for the op-amp

Eopamp Voutop 0 VCM Vinm 100MEG

*Setup switched capacitors and load

CI Vtop Vbot 1p
CF Voutop Vinm 1p
Cload Vout 0 1p

*Setup switches for the integrator

S1 VCM Vtop phi1 VTRIP switmod
S2 Vin Vbot phi1 VTRIP switmod
S3 Vtop Vinm phi2 VTRIP switmod
S4 Vbot VCM phi2 VTRIP switmod
S5 Voutop Vout phi1 VTRIP switmod
.model switmod SW RON=100

.end

T
Chapter 32 Noise-Shaping Data Converters 153

Output

Input

Figure 32.4 Integrator input and output for Ex. 32.1.

SPICE Modeling a 1-Bit ADC (A Comparator)

Modeling a nonclocked comparator is straightforward using switches as seen in Fig. 32.5.
When the positive comparator input is greater than the negative input, the output of the
comparator is high. When the negative input is greater than the positive input, the output
of the comparator is low. In the implementation we might need to connect large, dummy
resistors (or small capacitors) to the comparator inputs to keep the nodes from floating.
For a clocked comparator we will add, before the continuous comparator S/H. The basic
topology of our S/H was shown back in Fig. 30.24.

VDD

S1 Vout 0 Vinm Vinp switmod

S2
S2 VDD Vout Vinp Vinm switmod
Vinp Vout .model switmod RON=100

S1
Vinm
Inputs

Figure 32.5 Modeling a comparator in SPICE.

154 CMOS Mixed-Signal Circuit Design

32.1.2 First-Order Noise Shaping

The block diagram of a NS feedback modulator is shown in Fig. 32.6. In the end of Ch. 31
we showed that the output of the modulator, Y(z), can be related to the input, X(z), and
the ADC's quantization noise, E(z), by
STF(z) NTF(z)

A(z) 1
Y(z) = ⋅X(z) + ⋅E(z) (32.3)
1 + A(z) 1 + A(z)
where STF( f ) is the signal's transfer function and NTF( f ) is the noise's transfer function.

E(z)
Delta Sigma ADC
In X(z)
A(z) = z −1 Y(z) Out
1 − z −1
Digital
Integrator
Analog

DAC

Figure 32.6 Block diagram of a noise-shaping (NS) modulator.

Consider what happens if A(z) is an integrator (implemented using a DAI) as

shown in the figure. Equation 32.3 becomes
Y(z) = z −1 X(z) + (1 − z −1 )E(z) (32.4)
This equation is important! It shows the input signal simply passes through the modulator
with a delay while the quantization noise is differentiated (see Fig. 31.51 for the magnitude
response of a digital differentiator with a transfer function 1 − z −1 ). We can think of the
noise differentiation as pushing the quantization noise to higher frequencies. We'll come
back to how NS affects the quantization noise spectral density, VQe( f ), in a moment. But
first let's attempt to understand what's happening here.
In Fig. 32.6 the summer takes the difference (Delta) between the input signal and
the fed back signal. The integrator accumulates or sums (Sigma) this difference and feeds
the result back, via the ADC and DAC, to the summer. This forces the output of the
modulator to track the average of the input. Sometimes the fed back signal will have a
value greater than the input signal, while at other times the fed back signal will be less than
the input signal. The average signal fed back, however, should ideally be the same as the
input signal. Note that this type of NS modulator is often called a Delta-Sigma or
Sigma-Delta modulator. Also, at this point, we should see the need for the averaging
filters discussed in the last chapter.
Chapter 32 Noise-Shaping Data Converters 155

A circuit implementation of a first-order NS modulator is shown in Fig. 32.7. For

the moment we use a single-bit ADC and DAC (both implemented using the clocked
comparator) for gain linearity reasons (discussed in more detail later). The analog voltage
coming out of the integrator is compared to the common-mode voltage (this is our 1-bit
ADC) using the comparator. For the 1-bit DAC a logic-0 has an analog voltage of 0 V,
while a logic-1 has an analog voltage of VDD (= 1.5 V here) so that the comparator's
output can be used directly (fed back to the DAI).

φ1 φ2 φ1
1p
V CM
V CM V out
1p V CM
Clocked comparator
V in
f s = 100 MHz

Figure 32.7 Circuit implementation of a first-order NS modulator.

The comparator is clocked on the rising edge of φ 1 resulting in a Ts delay (z −1 ) in

series with the fedback signal and a delay of Ts/2 (z −1/2 ) in series with the input signal. To
understand this statement, remember that the nonoverlapping clock dead time (the time
both φ 1 and φ 2 are low) is short and, practically, the falling edge of φ 2 occurs at the same
instance as the rising edge of φ 1 (and so we could also use φ 2 to clock the comparator).
This results in a transfer function (see Eq. [31.130] and Table 31.2) to the input of the
comparator (which can also be thought of as the ADC output since the fed back signal and
modulator output are the same signal) of

Desired ADC input/output = z −1 (V − V ) (32.5)

in out
1 − z −1
After careful review we should see that the circuit implementation of Fig. 32.7
corresponds to the NS modulator represented by the block diagram shown in Fig. 32.6.
We can use the SPICE models developed in the last section to demonstrate the
operation of the NS modulator of Fig. 32.7. Assuming our sampling frequency is 100
MHz, the input is a 500 kHz sinewave centered around VCM (= 0.75 V) with a peak
amplitude of 0.7 V. The input and output of the modulator are shown in Fig. 32.8. It's
important to understand the signals in this figure. When the sinewave is at its peak
amplitude, the output of the modulator stays high, a logic one, most of the time. When the
sinewave is moving through the common mode voltage, the output bounces back and
forth between VDD and ground so that its average value, VDD/2, matches the input value.
To construct a (higher resolution) ADC the output of the modulator is connected
to a digital averaging filter, as shown in Fig. 32.9. The output of the digital filter is a
156 CMOS Mixed-Signal Circuit Design

Modulator input Modulator output

Figure 32.8 Modulator, Fig. 32.7, input and output.

digital word representing the analog input voltage. For a detailed discussion of the
requirements placed on the anti-aliasing filter (AAF) and the digital filter (or
digital-decimation filter if decimation is used), see Ch. 31.

1-bit
Analog input Digital
AAF NS modulator Digital Output
Filter
fs
Clock input Decimation filter

Figure 32.9 ADC using a NS modulator and digital filter.

We might wonder if we can use an analog filter, instead of a digital filter in the
topology of Fig. 32.9, to remove the high-frequency quantization noise. The output of the
resulting circuit will be analog, so it can't be used as an ADC. While this may not be of
practical use at the moment, it does help in understanding how the NS modulator
functions. Passing the modulator output of Fig. 32.8 through a simple RC lowpass filter,
with a time constant of 100 ns, results in the waveform shown in Fig. 32.10. Increasing the
time constant results in a smoother output signal. However, increasing the time constant
too much can affect the amplitude of the desired signal. Also, note the phase shift through
the modulator and filter.
Chapter 32 Noise-Shaping Data Converters 157

Output after RC
filtering

Input

Figure 32.10 Using a simple RC lowpass filter on the output of the NS modulator of Fig. 32.7.

A Digital First-Order NS Demodulator

So far our noise-shaping discussion has centered around analog-to-digital conversion.
Figure 32.11 shows a first-order NS demodulator-based topology for digital-to-analog
conversion. While, once again, the discussion concerning selection of the digital
interpolating and reconstruction filters is given in Ch. 31, we are interested here in the
topology of the first-order NS demodulator for use in a DAC.

1-bit
Digital input Digital Analog output
NS demodulator RCF
Filter
fs
Clock input
Interpolation filter

Figure 32.11 DAC using a NS modulator and digital filter.

Figure 32.12a shows a block diagram of a first-order NS demodulator for use in a

DAC. Figure 32.12b shows the practical implementation. The only differences between
this circuit and the circuit of Fig. 32.6 is that the DAI is replaced with an all-digital
integrator (see Fig. 31.49), and the quantizer (comparator) is replaced with a circuit that
performs quantization by selecting (using the MSB of the accumulator output word)
digital VREF+ (= 011111... in two's complement, see Fig. 31.37) or VREF− (= 10000...)
which, for our current discussion, are VDD and ground.
158 CMOS Mixed-Signal Circuit Design

E(z)
Quantizer
In X(z) z −1 Out
1 − z −1
Digital
Accumulator
Digital

(a)
V CM = 00000.... = 0.75 V (here)
Accumulator Quantizer
In MSB Out
D Q
clk
011111...
1
fs 100000... 0 MUX

(b)

Figure 32.12 Block diagram of (a) a NS demodulator and, (b) a more detailed
implementation for use in a DAC.

Modulation Noise in First-Order NS Modulators

Here we present a more detailed discussion of the quantization noise spectrum for a
first-order NS modulator. To begin let's write Eq. (32.4) in the time domain,
Y[nT s ] = X[(n − 1)T s ] + E[nT s ] − E[(n − 1)T s ] (32.6)
which shows the output is a function of the first difference (order) of the quantization
noise E[nTs] − E[(n − 1)Ts]. Intuitively note that the smaller we make Ts (the faster we
sample since T s = 1/f s ), the closer our digital output Y[nTs] approaches the analog input
X[nTs].
Next, using Eq. (32.4), let's write the product of the noise transfer function and
E[z] (the modulation noise) of the first-order NS modulator in the frequency domain as

NTF(z)E(z) = (1 − z −1 )E(z) → NTF( f )V Qe ( f ) =  1 − e fs  ⋅ LSB

f
−j2π V
(32.7)
12f s
where we have used, see Fig. 30.57,
V LSB 
E( f ) = V Qe ( f ) = units, V/ Hz  for 0 ≤ f ≤ f s /2 (32.8)
12f s 
and
V REF+ − V REF−
V LSB = (32.9)
2N
Chapter 32 Noise-Shaping Data Converters 159

where N is the number of bits used in the low-resolution ADC/DAC in the modulator.
Using a single-bit ADC/DAC in a NS modulator, N = 1, results in V LSB = 1.5 V (see Prob.
30.14 for a discussion of when Eq. [32.9] isn't valid). This again shows that we are not
reducing the quantization noise, but are rather pushing it to higher frequencies so that it
can be filtered out. Using Eq. (31.107), we can write the PSD of the NTF (the PSD of the
first-order modulator's modulation noise) as
V 2LSB  f  units, V 2 /Hz 
NTF( f ) 2 ⋅ V Qe ( f ) 2
= ⋅ 2 1 − cos 2π   (32.10)
12f s  fs 
Figure 32.13 shows the PSD of the first-order NS modulation noise for V LSB = 1.5 V and
f s = 100 MHz . Note how now we are discussing modulation noise instead of quantization
noise. The modulation noise is the quantization noise after being differentiated by the NS
modulator. The modulation noise is the unwanted signal added to the input signal. After
reviewing Fig. 32.13 we see that the magnitude of the modulation noise is significant.
However, after passing this signal through a lowpass filter, we can remove the higher
frequency noise resulting in a lower value of data converter RMS quantization noise,
VQe,RMS. Figure 32.14 shows the PSD of the noise if we limit our view to 1 MHz. The point
here is that by restricting the bandwidth of the modulation noise we can, theoretically,
drive the RMS quantization noise in our signal to zero. Of course, by lowering the
bandwidth of the digital filter on the output of the modulator we also limit the possible
bandwidth, B, of the input signal. Notice that we have violated Bennett's criteria by
utilizing a quantizer with an LSB that is comparable to the input signal. Now, however,
we are using feedback that adds or subtracts a signal from the input and ultimately affects
the quantizer input.

V 2 /Hz, × 10 −9

f, Hz, × 10 6
f n = f s /2 = 50 MHz
Figure 32.13 Modulation noise for a first-order NS modulator.
160 CMOS Mixed-Signal Circuit Design

V 2 /Hz, × 10 −12

f, Hz, × 10 6

Figure 32.14 A limited view of the modulation noise of Fig. 32.13.

Example 32.2
Using SPICE, show the modulation noise spectrum associated with the NS
modulator of Fig. 32.7. Compare the simulation results to the theoretical results
shown in Fig. 32.13.
Following the procedure given back in Sec. 30.3.1, Fig. 30.46, to determine a data
converter's quantization noise spectrum, we apply a slowly moving voltage ramp
to the input of the modulator. Then we look at the difference between the input
and output of the modulator (the modulation noise). The simulation results are
shown in Fig. 32.15a and 32.15b. We used the following WinSPICE commands to
generate these plots (added directly into the netlist)
*#plot Vout Vin
*#let Vqev=Vout-Vin
*#linearize Vqev
*#spec 0 100MEG 200k Vqev
*#let Vqedb=db(Vqev)
*#plot Vqedb

The first command is used to generate Fig. 32.15a. The second command is used
to generate the difference between the modulator's input and output (the
modulation noise). Notice how, in Fig. 31.15a, the output of the modulator stays
low most of the time, when the input to the modulator is close to ground, while the
output stays high most of the time when the input is close to VDD. The third and
Chapter 32 Noise-Shaping Data Converters 161

Modulator output

Input ramp

(a)

Volts
Voltage, peak

(b)

Figure 32.15 (a) Input and output of the NS modulator of Fig. 32.7, and (b)
modulation noise output spectrum.
162 CMOS Mixed-Signal Circuit Design

fourth commands in the above list generate the spectrum of the modulation noise
(the spectrally shaped quantization noise). The last commands are used to plot,
Fig. 32.15b, the spectrum of the modulation noise (units of Volts). It may be
helpful, at this point, to review Fig. 30.48 and the associated discussion. To
change this plot (Fig. 31.15b) into a power spectral density (units of V 2 /Hz ) we
can square the magnitude of the modulation noise and then divide the result by the
resolution of the Fourier transform ( f res = 200 kHz in Fig. 32.15). The list of
commands used to generate a power spectral density from Fig. 32.15b would be
*#let mrms=mag(Vqev)/1.414
*#let Vqepsd=10*log10(mrms*mrms/200k)
*#plot Vqepsd

Using this sequence of commands results in a spectrum with amplitude values that
are similar to the values given in Fig. 32.13 (and have the same units). However,
the shape would remain essentially unchanged from Fig. 32.15b.
Notice that the shape of the modulation noise shown in Fig. 32.15b (in
decibels) matches fairly well with the spectrum shown in Fig. 32.13. This is the
case even though the quantization noise spectral density, E( f ), is not flat (is not
white), as was assumed in Eq. (32.7). The important thing to notice in Fig. 31.15b
is that the modulation noise spectrum decreases with decreasing frequency (at 20
MHz and below), as was predicted using Eq. (32.10) and shown in Fig. 32.13. T
RMS Quantization Noise in a First-Order Modulator
If we limit the range of frequencies we look at to calculate the quantization noise to values
below fs , then we can rewrite Eq. (32.10) as
f 
units, V/ Hz 
V LSB
NTF( f ) ⋅ V Qe ( f ) = ⋅ 2 sin π  (32.11)
12f s f s

The RMS quantization noise present in a bandwidth, B, can be calculated, see Eq. (30.44),
using
B B
V 2LSB f
V 2Qe,RMS = 2 ∫ NTF( f ) 2 VQe ( f ) 2 ⋅ df = 2 ⋅ ⋅ 4 ⋅ ∫ sin 2 π ⋅ df (32.12)
0
12f s 0
fs

Remembering that the maximum bandwidth of our input signal is related to the sampling
frequency, fs , and the oversampling ratio, K, by
fs
B= (32.13)
2K
and, for small values of x,
sin x ≈ x (32.14)
then
Chapter 32 Noise-Shaping Data Converters 163

V LSB π
V Qe,RMS ≈ ⋅ ⋅ 13/2 (32.15)
12 3 K
This equation should be compared to Eq. (31.51). Further we can describe the ideal data
converter SNR using first-order NS, see Eqs. (31.1) - (31.4) as

= 6.02N + 1.76 − 20 log π + 20 log K 3/2 (in dB)

Vp / 2
SNR ideal = 20 ⋅ log (32.16)
V Qe,RMS 3
or
SNR ideal = 6.02N + 1.76 − 5.17 + 30 log K (in dB) (32.17)
This equation should be compared to Eq. (31.52) where we saw every doubling in the
oversampling ratio, K, results in a 0.5-bit increase in resolution (called simple
oversampling). Here we see that every doubling in the oversampling ratio results in 1.5
bits increase in the resolution (or a 9 dB increase in SNRideal). A first-order NS
modulator's performance is compared to simple oversampling in Fig. 32.16.

Improvement in resolution, N inc

(Bits added) 30 log K − 5.17
N inc =
6.02
16.6
SNR ideal = 6.02(N + N inc ) + 1.76
13.3
First-order NS
10.0

6.66

3.33 Simple oversampling

0
1 10 100 1k 10k K , Oversampling ratio

Figure 32.16 Comparing simple oversampling to first-order noise-shaping.

Examples 32.3
Determine the ideal signal-to-noise ratio and the maximum signal bandwidth
allowed, B, for the first-order NS modulator of Fig. 32.7 if 16 of its output
samples are averaged (K = 16).
Because the sampling frequency, fs, is 100 MHz, we can use Eq. (32.13) to
determine the maximum input signal bandwidth, B, is 3.125 MHz. Using Eq.
(32.17) we can solve for the SNRideal as (knowing that the NS modulator of Fig.
32.7 uses a 1-bit quantizer) 38.73 dB. This corresponds to an equivalent data
converter (ADC) resolution, using Eq. (31.4), of 6.14 bits (number of bits added is
164 CMOS Mixed-Signal Circuit Design

5.14). Note that the ADC is made with the components, modulator, and digital
filter, shown in Fig. 32.9. T
Decimating and Filtering the Output of a NS Modulator
It's important to note that Eq. (32.17) was derived assuming the output of the modulator
was passed through a perfect lowpass filter with a bandwidth of B. Passing the output
through a sinc averaging filter, see Fig. 31.41, will result in a poorer SNR because the
higher frequency noise components will not be entirely filtered out. In this section we want
to answer two questions: (1) what order, L (see Eq. [31.104]), of sinc averaging filter
should be used in the digital filter on the output of the NS modulator, and (2) assuming we
use only this filter (no half-band filter or additional filtering), how will the ideal SNR of the
first-order NS modulator be affected.
We begin to answer to the first question by writing the increase in the number of
bits, Ninc, as
30 log K − 5.17
N inc = (32.18)
6.02
If our NS modulator uses a 1-bit ADC, then the final, after the digital filter, resolution of
the resulting data converter is Ninc + 1 bits. (An NS modulator using a 5-bit ADC [often
called a multibit NS modulator] would ideally have an output resolution of Ninc + 5 bits.)
Further, we saw in Ex. 31.22 and Fig. 31.55 that the word size increased by log 2 K bits in
each stage so that we can require
30 log K − 5.17
L ⋅ log 2 K ≥ (32.19)
6.02
Solving this equation results in L being greater than or equal to 2. In general, we can write
L = 1+M (32.20)
where M is the order of the modulator. For a first-order modulator we use two stages in
the averaging filter, or,
−K 2
H(z) =  1 1 − z −1  (32.21)
K 1 − z 
In the next section we discuss second-order NS modulators (M = 2). For these modulators
we use a sinc averaging filter with L = 3.

Example 32.4
Sketch the implementation of the digital decimation filter for the modulator
described in Ex. 32.3. Assume the final output clocking frequency is 100 MHz/16
or 6.25 MHz. Do not be concerned with aliasing (use only the averaging filter).
The transfer function of the digital filter is (see Eq. [31.93])
Chapter 32 Noise-Shaping Data Converters 165

2
 sin  16 ⋅ π f s 
f 
− −16 2
 
H(z) =   = H( f ) =
1 z 1
  16 ⋅ 
 1 − z −1   sin  π f s 
f

 
The block diagram of the filter is shown in Fig. 32.17. The increase in resolution
through each accumulator (integrator) stage is log 2 16 = 4 bits. The resolution
calculated in Ex. 32.3 was 6.14 bits, which we round up to 7-bits. Because the
output of the digital filter is 9-bits, we drop the lower two bits (divide by 4) to get
our final 7-bit resolution. T

In 5 59 9 9 9 Out
1 1 1 − z −1
00001 select −1
1 − z −1
1 1−z −1 1−z Digital
11111 0 MUX
fs Add MUX f s /K
÷K Drop the lower
Clock 2 bits so that
Decimation filter output is 7 bits.

Figure 32.17 Sinc filter used for decimating the output of the NS modulator of Fig. 32.7.

Next let's answer how filtering with a sinc filter affects the SNR of the data
converter. Remember the SNRideal was calculated in Eq. (32.17) assuming the modulation
noise was strictly bandlimited to B. Figure 32.18 shows the PSD of the NTF 2 ( f )
⋅ V Qe ( f ) 2 (the modulation noise) of the first order NS modulator. Also shown in this
figure is the shape of the averaging filter's magnitude response squared (see Eqs. [32.22],
[31.90] and [31.93]). Here we are showing the shape of a filter with L = 2 (set by Eq.
[32.20] for a first-order modulator) and K = 16. We limit our range to fs /2.

4
  f 
 1 sin  Kπ f s  
H( f ) 2
= ⋅ 
 K sin  π f  
  fs  

V 2LSB f
NTF( f ) 2 ⋅ V Qe ( f ) 2 = ⋅ 4 sin 2 π
12f s fs

f s /K f s /2
B, Ideal maximum input frequency
Figure 32.18 Showing modulation noise and filter response.
166 CMOS Mixed-Signal Circuit Design

We can calculate the RMS quantization noise resulting from a cascade of a first-
order modulator and an averaging filter using
f s /2

V 2Qe,RMS = 2 ∫ NTF( f ) 2 ⋅ V Qe ( f ) 2 ⋅ H( f ) 2 ⋅ df (32.22)

0

sin 4  Kπ fs 
f
f s /2
V2
V 2Qe,RMS = LSB ⋅ 84 ⋅ ∫0 ⋅ df (32.23)
sin 2  π f s 
12f s K f

f
If we let θ = π , then this equation can be written as
fs
= K⋅ π4

V2 sin 4 (Kθ)
2
8 fs
V 2Qe,RMS = LSB ⋅ 4 ⋅ π ⋅
12f s K ∫0 sin 2 θ
dθ (32.24)

and finally,
V LSB 2
V Qe,RMS = ⋅ 3/2 (32.25)
12 K
This equation should be compared to Eq. (32.15), which was derived assuming the digital
filter was ideal with a bandwidth of B. The SNR resulting from using a first-order (M = 1)
NS modulator and a second-order (L = 2) sinc averaging filter is
SNR sinc = 6.02N + 1.76 − 3.01 + 30 log K (in dB) (32.26)
Comparing this to SNRideal given in Eq. (32.17), we see that using a sinc filter for
averaging results in only a 2.16 dB difference (increase) in SNR over the ideal filter. If we
remember that using a sinc filter results in a droop in the desired signal, see Fig. 31.46, the
SNR will be lower than what is predicted by Eq. (32.26). (Note that an analysis of higher
order modulators using sinc averaging filters would show that as long as Eq. [32.20] is
valid the deviation from SNRideal is negligible.)
We have not talked about the effects of sample rate reduction (decimation) on the
SNR. The modulation noise aliased into the base spectrum is a concern when decimating
the output of the modulator. The major difference between filtering the outputs of the data
converters in the last chapter and filtering the output of an NS modulator is the spectral
characteristics of the noise. In the last two chapters we assumed the quantization noise
spectral density was white (see Fig. 30.57). As we've seen in this chapter the modulation
noise increases with increasing frequency (see Fig. 32.18). This can mean that the amount
of modulation noise aliased into the base, or desired, spectrum can be more of a concern.
The major concern when decimating, in most situations, is the input signals that reside at
frequencies > B and the resulting aliasing degradation of the SNR (see, for example, Fig.
31.59).
Chapter 32 Noise-Shaping Data Converters 167

Implementing the Sinc Averaging Filter Revisited

We chose to implement the sinc averaging filter for the first-order NS modulator of Fig.
32.7 with the topology shown in Fig. 32.17. We might wonder what the implementation of
the averaging filter would look like if we had used a cascade of accumulate-and-dumps
similar to what is shown in Fig. 31.44 (assuming the larger reduction in output clocking
frequency [ fs /K2 instead of fs /K] and the possible aliasing isn't a concern [as discussed in
Sec. 31.2.2]). For a first-order NS modulator (M = 1) the desired transfer function of the
averaging filter (L = 2) was given by Eq. (32.21).
f
j2π f
A cascade of two accumulate-and-dumps is shown in Fig. 32.19. Since z ≡ e s

the overall transfer function of the averaging filter is

−K
H(z) = 1 − z −1
2

(32.27)
1−z
This equation shows that adding a second accumulate-and-dump results in averaging K2
samples while not providing a reduction in the first sidelobe's amplitude. Because the
bandwidth of the filter is reduced using this topology, we get a corresponding reduction in
quantization noise on the output of the filter (and corresponding increase in the
attenuation when looking at a fixed frequency in the stop band). While we could modify
the cascade of accumulate-and-dumps to operate properly, with a final output clocking
frequency of fs /K, the simplicity and ease of designing the averaging filter using the
topology of Figs. 32.17, 31.54, or 31.56 makes them the topology of choice, in most
situations, for a NS modulator averaging filter.

Accumulate-and-dumps

In Out
1 − z −K 1 − z −K
2

f s clk 1 − z −1 clk 1 − z −K clk

f s /K f s /K 2

Figure 32.19 Problems with cascading accumulate-and-dump circuits.

The time interval we average the output of the modulator over is related to the
order of sinc averaging filter as shown in the following two examples. A time interval
longer than KTs is used when L ≥ 2 .

Example 32.5
Determine the time domain impulse response of a first-order averaging filter (L =
1) with K = 8. Assume decimation is not employed in the filter.
The transfer function of the filter is given, after reviewing Eqs. (31.89) and
(31.90), by
168 CMOS Mixed-Signal Circuit Design

−8
H(z) = 1 − z −1 = 1 + z −1 + z −2 + z −3 + z −4 + z −5 + z −6 + z −7
1−z
The time domain relationship between the input and the output is then
y[nT s ] = x[nT s ] + x[(n − 1)T s ] + x[(n − 2)T s ] + ... + x[(n − 7)T s ]
The time-domain impulse response of the first-order averaging filter is shown in
Fig. 32.20. Note the rectangular shape. T

x[nT s ]
1 Impulse input
time, n/T s
0
y[nT s ]
1 Output
time, n/T s
0 1 2 3 4 5 6 7 8 9 10 11

Figure 32.20 Impulse response of an L = 1 averaging filter.

Example 32.6
Repeat Ex. 32.5 if a second-order averaging filter is used.
The transfer function of the filter is
−8 2
H(z) =  1 − z −1  = 1 + 2z −1 + 3z −2 + 4z −3 + 5z −4 + ... + 3z −12 + 2z −13 + z −14
1 − z 
The time domain relationship is
y[nT s ] = x[nT s ] + 2x[(n − 1)T s ] + 3x[(n − 2)T s ] + ... + 2x[(n − 13)T s ] + x[(n − 14)T s ]
The impulse response of the second-order averaging filter is shown in Fig. 32.21.
Note the triangular shape of the curve and how the impulse response of the
second-order filter lasts twice as long as the first-order's response. T

y[nT s ]
8

1
time, n/T s
0 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16

Figure 32.21 Impulse response of an L = 2 averaging filter.

Chapter 32 Noise-Shaping Data Converters 169

Analog Sinc Averaging Filters Using SPICE

It can be very useful to simulate the operation of a sinc averaging filter of the form
−K L
H(z) =  1 1 − z −1  (32.28)
K 1 − z 
Implementing this filter using digital circuits can result in long simulation times. Also, the
output of the filter will be digital requiring the use of a DAC to reconstruct the analog
input voltage. While in an actual chip design we may (will) want to simulate the actual
circuit fabricated (the digital implementation of the filter), it is still nice to have a
computationally efficient ideal filter for fast simulations during the development of the
modulator.
After reviewing Fig. 32.10, and the associated discussion, we see that we can pass
the output of the modulator directly through an analog filter to reconstruct the analog
input voltage (with the unwanted quantization noise). Using an analog filter eliminates the
need for an additional DAC and makes observing the resulting modulator/filter output
simulation spectrum straightforward. The question now becomes, "How do we make a
simple sinc-shaped analog filter that models the digital implementation?"
We saw in Fig. 31.53 that a digital comb filter has a transfer function of 1 − z −K .
We also saw in Ch. 30 that we can implement an analog comb filter using a transmission
line, Fig. 30.11. Here we attempt to use the simple circuit shown in Fig. 32.22a to
implement a comb filter in SPICE. The integrator, Fig. 31.33, can be implemented using a
similar topology and is shown in Fig. 32.22b. To get a filter with a continuous-time

Out H(z) = 1 − z −K
In
1
KT s
Voltage controlled voltage source
used for summing.
Transmission line delay of KT s
(a)

Out
In
1 Ts
Transmission line
1

H(z) = 1
Used as an 1 − z −1
inverting buffer (b)

Figure 32.22 (a) Implementation of a comb filter in SPICE, and

(b) implementation of an integrator.
170 CMOS Mixed-Signal Circuit Design

transfer function equivalent to Eq. (32.28) (see Eqs. [31.100] and [31.101]), we can
cascade L of these sections. The resistors used on the output of the transmission lines, in
Fig. 32.22 are used to terminate the transmission lines. The following example
demonstrates the implementation of a sinc averaging filter in SPICE.

Example 32.7
Generate a SPICE model for the digital filter used with the first-order modulator
of Fig. 32.7. Assume, as in Ex. 32.4, that K = 16. Specify the droop in the output
when an input sinewave has a frequency of B.
In this modulator the clocking frequency is 100 MHz (Ts = 10 ns). The delay in the
comb filters is 160 ns, while the delay in the integrators is 10 ns. The SPICE netlist
is shown below. Note how the input to the filter is isolated using a buffer, and the
integrators are isolated by the comb filters. The output is scaled at the end of the
netlist to 1/K2 to normalize the filter's gain (see Fig. 31.46).
The simulation results are shown in Fig. 32.23. The input to the filter is a 1-V
sinewave that is swept from DC to 50 MHz (= fs /2). The droop at B (= 100
MHz/(2⋅ 16) = 3.125 MHz) is 7.8 dB (which matches what was predicted in Fig.
31.46).
* Figure 32.23 CMOS: Mixed-Signal Circuit Design *

.AC LIN 1000 1k 50MEG

*WinSPICE command scripts

*#destroy all
*#run
*#set units=degrees
**#plot db(vo2) ylimit 30 0
*#plot db(vout) ylimit 0 -60

Vin Vin 0 DC 0 AC 1

*Input buffer
Ebuf1 Vobuf 0 Vin 0 1

*Comb filter 1
EC1 Vo1 0 Vobuf Vf1 1
TC1 Vobuf 0 Vf1 0 ZO=50 TD=160n
RC1 Vf1 0 50

*Integrator filter 1
EI1 Vo2 0 Vo1 Vb1 1
TI1 Vo2 0 Vf2 0 ZO=50 TD=10n
RI1 Vf2 0 50
EB1 Vb1 0 0 Vf2 1

*Comb filter 2
EC2 Vo3 0 Vo2 Vf3 1
TC2 Vo2 0 Vf3 0 ZO=50 TD=160n
RC2 Vf3 0 50
Chapter 32 Noise-Shaping Data Converters 171

*Integrator filter 2
EI2 Vo4 0 Vo3 Vb2 1
TI2 Vo4 0 Vf4 0 ZO=50 TD=10n
RI2 Vf4 0 50
EB2 Vb2 0 0 Vf4 1

*Scale the output by 1/K^2 (1/256=0.00390625)

Ebuf2 Vout 0 Vo4 0 .00390625

.end
T

Figure 32.23 Frequency response of the L = 2 sinc averaging filter.

Using our SPICE Sinc Filter Model

The analog sinc averaging filter model we've just developed is difficult to use in a practical
simulation for several reasons. To begin with, the actual shape of the pulses (their rise and
falltimes together with the over- and undershoot in the pulse shape) coming out of the
modulator is now important where, in a digital implementation, it is not. The frequency
content of the analog pulse stream differs from the spectral content of the digital data.
This leads to analog sinc filter output waveforms with distortion that wouldn't be found in
the output of the digital sinc filter. For a digital implementation a modulator output rise
time of 1 ns is no different from a risetime of 100 ps. In the analog implementation,
however, the risetime does matter (consider what happens, in Fig. 32.10, if the risetime of
the digital data coming out of the modulator is slowed down). Also, the SPICE
implementation of the transmission lines isn't tolerant to fast pulse edge transitions. This
leads to difficulty with convergence and, possibly, long simulation times.
172 CMOS Mixed-Signal Circuit Design

Analog Implementation of the First-Order NS Modulator

A continuous-time implementation of a first-order NS modulator is shown in Fig. 32.24. If
we write the sum of the currents through the resistors (and thus through the feedback
capacitor) as
V CM − V in V CM + V out
iF = + (32.29)
R R
then the output of the integrator can be written, assuming the input and output are
referenced to VCM , as

= −1 (V in − V out )
iF
V OI = (32.30)
jωC jωRC
where ω = 2πf and noting how we switched the inverting and noninverting inputs of the
comparator to compensate for the inverting gain of the integrator. Knowing, from Eq.
(31.82), that
z −1 = 1 (32.31)
1 − z −1  −1 + cos 2π f  + j sin 2π f
 fs  fs

f
or, for f << f s (which must be valid for any oversampling converter) where cos 2π fs ≈ 1
f f
and sin 2π fs ≈ 2π f s , then
z −1 ≈ 1 (32.32)
1 − z −1 j2π f
fs

Finally, we see that the topology of Fig. 32.24 behaves like a modulator with a block
diagram of Fig. 32.6 when

fs = 1 (32.33)
RC
If this equation doesn't hold, the topology of Fig. 32.24 may still function correctly as a
NS modulator, except that the above analysis would include an integrator gain. (Which,

R φ Clocked at f s

C V CM
V in R
V out
V CM

−V out

Figure 32.24 Analog circuit implementation of a first-order NS modulator.

Chapter 32 Noise-Shaping Data Converters 173

combined with the high gain of the comparator, may still result in an overall forward path
gain of one. We will discuss component gains in the modulator later.)
Analog integrator-based implementations of modulators can be simpler and easier
to breadboard and test on the bench, lower power, and less susceptible to clocking noise
(capacitive feedthrough and charge injection). The two main drawbacks are the difficulty
in setting the integrator gain to a precise value (in integrated versions) and the integrator's
susceptibility to the fed back pulse shape (a problem also encountered using the analog
sinc filters of the last section).
Using a DAI, the gain of the integrator is set by a ratio of capacitors, see Fig.
31.79 (and Ch. 27). Variations in the absolute oxide capacitance for a given process run
don't affect the integrator's gain. Using the analog integrator in a purely monolithic form,
however, can result in RC time constant variations of 50% or more.
Figure 32.25 shows how the shape of the pulse affects the output of the analog
integrator. In part (a) we see the ideal pulse shape and the ideal area under the pulse (the
shaded area). In part (b) we see how the finite rise time and fall time can affect the actual
area under the curve and thus the output of the integrator. To minimize these unwanted
effects we can use wider pulses as shown in parts (c) and (d), which means we run the
modulator at a slower clocking frequency. Increasing the width of the pulses minimizes the
percentage of the area affected by the transition times. Note that the feedback signal
directly subtracts from the input signal so that any noise or unwanted variation in the fed
back signal, such as an amplitude variation, can be considered as adding noise to the input
(and thus degrading the modulator's SNR). This is important! We will discuss the fed back
signal, and how to isolate/implement the actual voltage fed back to the integrator, again in
the next section.

Ideal area

(c) Wider, ideal, pulse shape

Ideal shape Shape with under-
(ideal area is and overshoot
shaded)
(a) (b)
(d) Increasing pulse width (going
slower) to minimize nonideal pulse
characteristics.
Figure 32.25 Comparator output pulse shapes, input to the integrator.
The DAI is less susceptible to the pulse shape fed back from the comparator.
Reviewing Fig. 32.7 we see that as long as the output of the comparator can charge or
discharge the switched capacitor to within the final resolution of the converter, before the
φ 2 switches turn off, the circuit functions as expected. Note that the comparator, having a
174 CMOS Mixed-Signal Circuit Design

digital output, doesn't limit the rate the switched capacitor is charged but rather the
limiting factor is the op-amp (since the top plate is tied to the op-amp's inverting input and
charged from the op-amp's output through the feedback capacitor).
The Feedback DAC
Up until this point we have been feeding the output of the comparator directly back to the
integrator. This works fine as long as the logic "1" (VDD) or logic "0" (ground) voltages
are clean (have no noise on them). Noise on these fed back voltages directly adds or
subtracts from the input signal and thus decreases the modulator's SNR. In any practical
mixed-signal integrated circuit the digital supply and return are commonly noisy with
variations in the hundreds of mV. As discussed in Ch. 28, it is common to separate the
analog and digital power supplies on-chip (and so the modulator should be powered with
the analog supply). Because of this, and the desire to set the fed back voltage V REF+ and
V REF− independent of VDD and ground, the output of the comparator is often connected to
the simple 1-bit DAC circuit shown in Fig. 32.26. It's important to remember that the
output of the DAC must be able to charge the integrator's input switching capacitance (see
Fig. 32.7) to within the final desired resolution of the converter in half a clock cycle
(before the φ 2 switches open).

V REF+ Decoupling capacitor (may be an NMOS device)

To integrator To comparator

1 LSB = VREF+ − VREF−

V REF−
Figure 32.26 One-bit DAC for use in a NS modulator.

Understanding Averaging and the Use of Digital Filtering with the Modulator
In the following discussion we assume, as before, that V REF+ = VDD = 1.5 V and V REF− =
ground (1 LSB = 1.5 V) . We also assume the input voltage to the modulator falls within
VDD and ground so that the output of the modulator doesn't saturate in a string of ones or
zeroes (more on this below). In this section we want to discuss, intuitively, the operation
of the digital filter used on the output of the modulator (see Fig. 32.9).
Before discussing the digital filter let's remember that we can recover the analog
input voltage using an analog filter as shown in Fig. 32.10. This means that if the output of
the modulator is a continuous string of zeroes, then the output of the analog filter will be
zero volts. Other possible modulator outputs and their averages are shown in Fig. 32.27.
Chapter 32 Noise-Shaping Data Converters 175

1.5
Average =
1.5
4
= 0.375
0
1.5
Average =
1.5
2
= 0.75
0
Modulator output

1.5 (31)⋅(1.5)
(Repeats every 32) Average = 32
0
1.5 (7)⋅(1.5)
Average = 8
0
1.5 1.5
Average = 8
0
0 Average = 0 V

8 16 24 32 40

Figure 32.27 Modulator outputs and their corresponding averages.

Example 32.8
Plot the ideal I/O transfer curve for the 1-bit DAC. Also plot the non-ideal transfer
curve if V REF+ = 1.45 V (instead of 1.5 V). Comment on how the output of the
NS-modulator/decimator (the data converter) will be affected.
The transfer curves are shown in Fig. 32.28. The offset in the positive reference
voltage results in a gain error in the data converter (but no nonlinearity). T

Ideal

1.5
Output, V

Nonideal

0
0 0.75 1.5 Comparator input, V
Figure 32.28 Ideal and nonideal transfer curves for the 1-bit DAC and comparator cascade.

Next let's consider the case where the modulator's input is a DC signal and our
data converter's resolution is only limited by the number of samples we can take in a given
time, KTs . Equation (32.13) shows that as K approaches infinity, B approaches zero (DC).
Figure 32.14 shows that at DC the spectral density of the modulation noise is zero.
Feeding the output of our first-order modulator to a single accumulate-and-dump, see
Figs. 31.39 and 31.41, can provide the needed digital filtering. As seen in Fig. 31.41,
176 CMOS Mixed-Signal Circuit Design

increasing K causes the filter's amplitude response at DC to increase (the number of bits
coming out of the counter increases) and the sidelobes move toward DC. Also, as seen in
Fig. 31.58b, we don't have aliasing at DC, so the reduction in output clocking frequency
(decimation) to f s /K can be accomplished with the single accumulate-and-dump stage.
However, there may still be aliasing from higher frequencies. Note that we have just
described a first-order NS modulator driving a counter where the counter is reset and
read-out every KTs clock cycles and clocked at a rate of fs . Practically, for large K, the
limiting factor in the resolution of the NS modulator is the noise inherent in the circuit
(mainly thermal and flicker noise sources from the MOSFETs) and, more importantly, the
finite gain and linearity of the op-amp (more on this later). Note that in our perfect
modulator a single output going high out of one-million outputs would correspond to an
average input voltage of only 15 µV . This would also mean that we would need to
average at least one million and one (1,000,001) modulator outputs with our simple
counter for a constant output.
In our cascade of two accumulate-and-dumps, Eq. (32.27) and Fig. 32.19, we
average K2 samples. The cascade behaves, from a frequency response point of view, like a
single accumulate-and-dump. For the cascade of L sinc filters, however, the number of
modulator outputs averaged is
Number of modulator outputs averaged = L ⋅ K − 1 (32.34)
As we saw in Ex. 32.6, the cascade of sinc filters results in a weighted average of the
filter's inputs. For our first-order modulator of Fig. 32.7 and the digital filter of Fig. 32.17
with a transfer function, once again, of
−16 2
H(z) =  1 − z −1  (32.35)
 1−z 
we perform a weighted average on 31 of the modulator's outputs. The time domain
impulse response of this filter (without decimation), again see Ex. 32.6, is given by
y[nT s ] = x[nT s ] + 2x[(n − 1)T s ] + 3x[(n − 2)T s ] + ... + 15x[(n − 14)T s ] + 16[(n − 15)T s ] +
15x[(n − 16)T s ] + 14x[(n − 17)T s ] + ... + 2x[(n − 29)T s ] + x[(n − 30)T s ] (32.36)
For a continuous filter input of "1" the output of the filter is 256. Note that this is the same
result we get with the cascade of two accumulate-and-dumps and is the "gain" ( KL ) of the
filter at DC. For our current discussion the minimum resolution we can represent with the
maximum output value of 256 (realizing the minimum output value, which corresponds to
a continuous modulator output of all zeroes, is 0) is (1.5)/256 = 5.86 mV . We want this
value to be less than the resolution calculated in Ex. 32.3, which was 6.14 bits (1.5/26.14 =
21.27 mV) so that our modulation noise, for a given bandwidth, limits the data converter's
resolution and not the digital filter. This is why adding an additional sinc filter stage (say,
L = 3) will not increase the data converter's resolution. The fundamental way to increase
the first-order modulator's resolution is to increase the number of samples averaged (the
oversampling ratio), K. Note also, that increasing L will have the undesirable effect of
increasing droop in the bandwidth of interest.
Chapter 32 Noise-Shaping Data Converters 177

Example 32.9
If the desired input to an ideal first-order NS modulator is a DC signal, would it be
better to use a single sinc filter (a counter or accumulate-and-dump) or a cascade
of two sinc filters of the form given by Eq. (32.35)?
Equation (32.20) was derived assuming we wanted to maximize the input signal
bandwidth, B. If we are measuring a DC signal with, ideally, zero-bandwidth, then
we want to minimize the digital filter's bandwidth to remove unwanted noise that
may corrupt the DC signal. This means, for higher resolution with correspondingly
longer conversion time, the single-stage filter is the best choice. T
In Fig. 32.17 we indicated that the word size coming out of the filter, after
dropping the lower two-bits, is seven-bits. This means, in two's complement, that outputs
of 011 1111 (+63), 100 0000 (−64), and 000 0000 (0) correspond to the maximum input
(V REF+ − 1 LSB ), minimum input (V REF− ), and common-mode voltage (VCM = 0.75 V)
respectively, see Fig. 31.37. A continuous modulator output of "1" would correspond to
an input of VREF+ , which would be outside the possible digital filter output words and
result in the incorrect filter output code of 100 0000. Note that here
1 LSB= (V REF+ − V REF− )/2 7 = 11.719 mV , which is, again, below the 21.27 mV
fundamental RMS noise limit of the modulator in a bandwidth, B.
Next, let's consider the situation where one out of every 64 modulator outputs is a
logic 1 (and the sequence repeats indefinitely). As we saw in Fig. 32.27, averaging this
output results in an analog voltage of 1.5/64 or 23.44 mV. Using Eq. (32.36), we can
write the sequence of digital filter outputs (in decimal form and assuming our single-pulse
input to the filter marks the beginning of the output) without decimation as
1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0, (followed
by 32 more zeroes and then the sequence repeats itself).
If decimation is employed, as in Fig. 32.17, then the outputs of the filter look like
1,15,0,0 (summed = 16)
noting that shifting in time doesn't change the sum of the sequence if the samples output
by the decimation process are spaced apart by 16 (K). For example, the sequence
4,12,0,0 (summed = 16)
also has the same sum of 16. Figure 32.29 shows plots of our modulator input and the
reconstructed filter output. Our modulator input is a constant DC signal of 23.44 mV
while at the same time the digital filter output is a repeating sequence. What we are seeing
is the ripple associated with passing the output of the modulator through the filter.
Additional filtering, including the RCF, will reduce the ripple (because of the reduction in
bandwidth). We should point out that this ripple represents a major difference between
Nyquist-rate data converters and oversampling converters. Note how averaging 4 output
samples after decimation or 64 samples before decimation results in the digital
reconstructed output value matching the input value.
178 CMOS Mixed-Signal Circuit Design

Digital filter out Decimated output

15 87.9 mV

Input voltage 23.44 mV

1 5.86 mV
16 32 48 64 80 96 128 144
Sample number

Figure 32.29 Ripple in the output of a digital filter. Note how the
average of the filter output is equal to the input voltage.

Figure 32.30 shows the output of an RC filter, with a time constant of 1 µs, when
connected to the output of the modulator of Fig. 32.7. The modulator input voltage is
23.44 mV. The analog RC filter, like the digital filter, will not totally filter out the higher
frequency components of the modulation noise and thus there will be some ripple on the
output signal. Again, as in the digital filter, reducing the bandwidth of the filter (increasing
the time constant) will reduce the peak-to-peak amount of ripple.

Figure 32.30 Showing how we have ripple on the output of an analog filter connected to
a modulator with a DC input.

Example 32.10
What are the 7-bit, two's complement, representations of the numbers in Fig. 32.29
assuming they are originally represented using 9-bit, two's complement, words as
in Fig. 32.17? What is the four-sample average of these words?
Chapter 32 Noise-Shaping Data Converters 179

The 9-bit two's complement representations of 0, 1, and 15 are 1 0000 0000, 1

0000 0001, and 1 0000 1111, respectively. Dropping the lower two bits and
knowing, for our 7-bit representation that 1 LSB= 11.719 mV , results in 100 0000
(0), 100 0000 (0), and 100 0011 (VCM − 61⋅11.719 mV = 35.157 mV). Averaging
the filter outputs, as we did in Fig. 32.29, results in a value of 8.79 mV, which is
different from the input voltage of 23.44 mV. By dropping the lower 2 bits we
actually lost resolution. This can be confusing until we remember that at DC the
possible resolution of the ideal modulator and digital filter is infinite. Over a
bandwidth, B, however the resolution of the converter is limited to less than 7 bits
as discussed in Ex. 32.3. Not throwing out the two lower bits is useful if additional
digital filtering is used in the mixed-signal system. Otherwise the two lower bits are
just random values (noting that when we averaged the four samples in Fig. 32.29 it
was equivalent to passing the digital data through an additional lowpass, sinc
averaging filter with K = 4). T
Pattern Noise from DC Inputs (Limit Cycle Oscillations)
The ripple on the output of the filter can cause noise in the base spectrum of interest. The
frequency of the ripple and the amplitude of the ripple depend on the DC input value. As
compared with Fig. 32.30, Fig. 32.31 shows the RC filter output if the modulator input is
changed to 0.75 V (the common-mode voltage). The frequency of the ripple is higher and
the peak-to-peak amplitude of the ripple is smaller. The modulator output, with an input
of 0.75, is a square wave of alternating ones and zeroes. The first harmonic of this signal is
at half the clocking frequency or, in this example, 50 MHz. Since the ripple frequency lies

Figure 32.31 Filter ripple when input is the common-mode voltage of 0.75 V.
180 CMOS Mixed-Signal Circuit Design

outside our base spectrum (which, from Ex. 32.3, is from DC to 3.125 MHz) it will not, in
a significant way, affect the SNR. (In the digital filter a zero in the digital filter's transfer
function will most likely fall at half the clocking frequency eliminating the ripple altogether
and resulting in a constant filter output value.) The frequency of the ripple in Fig. 32.30,
however, is 1/640 ns or 1.564 MHz, which is well within our base spectrum. The resulting
tone will lower the SFDR and the SNR of the data converter. The question now becomes,
"How do we minimize the possibility of unwanted tones appearing in the data converter's
output spectrum?"
If we look at the digital filter output data shown in Fig. 32.29 we see that the
"ripple" amplitude of the digital data is fully 87.9 mV peak-to-peak or significantly above
the data converter's LSB value (noting that after the RCF/half-band filter this ripple value
will be reduced). Looking at this figure, we see that it would be better to spread or flatten
the data out over all four cycles of the repeating waveform. Although we may still have a
tone, or repeating sequence, at a frequency in the base spectrum, the amplitude of the tone
will be well below the LSB of the data converter (and so it won't affect the SFDR of the
data converter). To accomplish this spread or randomization we can add a noise dither
source (see the last chapter) to our basic NS modulator, as seen in Fig. 32.32. By applying
the dither to the input of the comparator (quantizer) the dither will be noise-shaped like
the quantization noise (the spectral content of the dither, Eq. [31.76], is less important).

Dither V CM
Source
φ2 φ1
φ1
1p
V CM
V out
V in 1p V CM

Figure 32.32 Adding a dither source to a first-order NS modulator.

The output of the modulator in our discussion and generation of Fig. 32.29 was a
single bit going high followed by 63 zeroes as shown in Fig. 32.33a. Note how the period
of the output is repetitive. If our dither source is used, the output may look something like
what is seen in Fig. 32.33b. The average of the waveform, over several cycles, is the same
as in part (a), while the period of the waveform varies and randomizes the power
contained in a particular frequency (tone). What this means is that the output spectrum of
a data converter, with a DC input, will not contain tones at specific frequencies sticking up
above the noise floor and resulting in a decrease in the SFDR. However, the peak-to-peak
amplitude of the ripple in the time domain may actually get worse. As seen in Fig. 32.33b,
the occasional shorter spacing between the output ones can result in a larger digital filter
output code. Again, we should point out that this variation, or ripple, in the output code is
a basic difference between a NS modulator-based data converter and a Nyquist-rate data
converter.
Chapter 32 Noise-Shaping Data Converters 181

Output of the modulator without dither added Output going high

Modulator output

63 zeroes 63 zeroes 63 zeroes 63 zeroes

(a)

Output of the modulator with dither added

time
(b)
time
Figure 32.33 Output of our modulator (a) without and (b) with a dither source.

As a final example, let's consider how a tone can occur in a modulator output that
has heavy transition densities (numerous one-zero transitions). If the input to the
modulator is the common mode voltage, VCM , of 0.75 V, then the output of the modulator
is an alternating sequence of ones and zeroes. Changing the input voltage upwards by a
small amount will result in the output of the modulator staying high once in a while instead
of going low (resulting in two consecutive logic one outputs). An example is seen in Fig.
32.34 where the input to the modulator was increased to 0.77 V. As the double ones are
spaced apart by approximately 350 ns, we can estimate a tone in the resulting output
spectrum at a frequency of 1/350 ns or 2.86 MHz.
Finally, note that unwanted tones are usually not a problem if the input signal is
busy and random (not DC as discussed in this section). Later in the chapter, we discuss
second-order modulators that utilize two integrators. The second integration helps to
spread the repeating sequences out over a longer period of time so that, hopefully,
negligible unwanted tone energy is present in the base spectrum.

Two consecutive output ones

Figure 32.34 Modulator output showing how tones can occur with higher transition density.
182 CMOS Mixed-Signal Circuit Design

Integrator and Forward Modulator Gain

So far we haven't discussed the shape or amplitude of the integrator's output. Because we
are using near-ideal components in our simulations, we haven't seen any limitations due to
the finite op-amp output swing. Figure 32.35 shows the integrator's output for the input
and output signals shown in Fig. 32.8 (using the modulator of Fig. 32.7). Clearly the
output swing of the op-amp is beyond the power supply rails. If the transistor-level model
of the op-amp were to replace the ideal op-amp, the integrator's output would saturate at
voltages less than VDD (= 1.5 V here) or greater than ground. While in some situations
op-amp saturation is not necessarily bad (the gain of the integrator goes to zero), it is
desirable to understand how decreasing forward loop gain affects the performance of the
modulator. Note also, in Fig. 32.35, how the output of the integrator makes the largest
change when it passes through the comparator reference voltage, VCM = 0.75 V, since the
fed back signal, the comparator output (a full-scale signal), is input to the integrator.

Maximum op-amp swing

0.75

Figure 32.35 Output swing limitations in the op-amp (integrator).

Consider the linearized model of our first-order NS modulator shown in Fig.

32.36. The gain of the integrator, see Eq. (31.135) or Fig. 31.79, is given by
CI
GI = (32.37)
CF
We have also drawn the comparator with a gain. Up until this point we have assumed the
gain of the comparator is unity. We'll comment on this more in a moment. Let's define the
modulator's forward gain as
Chapter 32 Noise-Shaping Data Converters 183

E(z)
ADC
In X(z) z−1 Y(z) Out
GI Gc
1 − z −1

GF = GI ⋅ Gc

Figure 32.36 Block diagram of a NS modulator showing forward gains.

GF = GI ⋅ Gc (32.38)
We can rewrite Eq. (32.4) using this gain as
z −1 ⋅ G F 1 − z −1
Y(z) = −1 (G
⋅ X(z) + ⋅ E(z) (32.39)
1+z F − 1) 1 + z −1 (G F − 1)
If GF approaches zero (the integrator saturates while the comparator gain stays finite),
then the output of the modulator is the sum of the integrated input and the quantization
noise. (This is bad.) Since the quantization noise is not spectrally shaped it will be difficult
to filter the modulator's output to recover the input signal. If the forward gain is greater
than two, then, as seen in Fig. 31.62 and the associated discussion, the poles of the
transfer function reside outside the unit circle and the modulator will be unstable. We can
restrict the values of the forward gain to
0 ≤ GF ≤ 2 (32.40)
Ideally, however, the gain is one.

Example 32.11
Show, using SPICE simulations and the modulator of Fig. 32.7, that an integrator
gain of 0.4 will result in an op-amp output range well within the power supply
range.
Figure 32.37a shows a schematic of the modulator with GI = 0.4. Figure 32.37b
shows the output of the integrator (the output of the op-amp) in the modulator of
part (a) with the input sinewave shown in Fig. 32.8. The output swing is limited to
roughly 80% of the supply range. For general design it is desirable to set our
integrator gain to 0.4. This ensures our integrator doesn't saturate unless the input
to the modulator goes outside the supply voltage range.
It's interesting to note that in both modulators, Fig. 32.7 and Fig. 32.37, the
forward gain is unity. This is a result of the effective gain of the comparator
changing forcing the forward gain, controlled by the fed back signal, to unity.
What this means is that our modulator functions as expected with a signal gain of
one (Eq. [32.4] is valid) whether GI is 1 or 0.4. We discuss how this change in
comparator gain occurs next. T
184 CMOS Mixed-Signal Circuit Design

φ1 φ2 φ1
1p
V CM
V CM V out
V CM

0.4p Clocked comparator

V in
f s = 100 MHz
(a)

(b)
Figure 32.37 (a) First-order NS modulator with an integrator gain of 0.4, and (b)
the output of the op-amp.

Figure 32.38 shows the transfer curves for the comparator. The x-axis, the
comparator input, is the output of the integrator in our modulator. Shrinking the
integrator's output swing while holding the output swing of the comparator at the supply
rails (1.5 V) results in an increase in effective comparator gain. This gain variation, with
the integrator output swing, helps to set the forward gain of the modulator to precisely 1.
We can write this using equations as
Integrator gain, G I Comparator gain, G c GF

Integrator output Comparator(modulator) output Modulator output

⋅ = (32.41)
Modulator input Integrator output Modulator input
Chapter 32 Noise-Shaping Data Converters 185

1.5

Output, V Gain is the slope of these lines.

0
0 0.75 1.5 Comparator input, V
Input signal

Figure 32.38 Comparator gain as a function of input voltage.

If the modulator is functioning properly, then the average value of the modulator output
will be equal to the modulator input and thus GF = 1. It's interesting to note that this result
(precise integrator gain isn't important) will apply to any integrator that is directly
followed by an ADC.
Before leaving this section, let's point out a couple of problems with a noise-
shaping modulator that uses a multibit ADC, Fig. 32.39. Since the output of the integrator
is the input signal to the ADC, the limited integrator output swing will directly affect the
range of ADC output codes. Limiting the range of ADC output codes will then limit the
allowable range of modulator inputs unless scaling is used (shifting the output codes or
sizing of capacitors in the DAI). Next, notice in Fig. 32.39 how the variation in the gain of
the ADC, with input signal, is more limited than the gains attainable with the simple
comparator of Fig. 32.38. Limiting the range of ADC gains can result in modulator

Digital
output code

111
110
101
100 Dashed lines indicate ADC gain

011
010
001
000
0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 8/8
Analog input voltage (integrator output)
Figure 32.39 A 3-bit ADC.
186 CMOS Mixed-Signal Circuit Design

forward gains that are not exactly unity. This is especially true at high input frequencies
where the gain of the integrator is low. However, if the integrator gain is high, the
effective gain of the ADC is not important. The point here is that using a multibit ADC
will increase the open-loop gain requirements of the op-amp used in the integrator.
Comparator Gain, Offset, Noise, and Hysteresis
It's of interest to determine how the performance of the comparator affects the operation
of the modulator. Both the comparator's offset and input-referred noise, Fig. 32.40a, can
be referred back to the modulator's input, Fig. 32.40b. By doing so we can determine how
they effectively change the input signal seen by the modulator. As seen in Fig. 32.40, the
high gain of the integrator, A( f ), reduces the effect of the comparator's noise and offset
on the input signal. For example, if the gain of the integrator at DC is 1,000 and the offset
voltage of the comparator is 50 mV, then the input-referred offset is only 50 µV.

Comparator's input-referred
noise and offset, V n,comp ( f ) Input-referred noise and offset, V n,comp ( f )/A( f )

In Out In Out
A( f ) A( f )
Comparator Comparator
Integrator Integrator
(a) (b)
Figure 32.40 (a) Referring the comparator offset and noise to (b) the input of the modulator.

To determine the minimum gain and maximum allowable hysteresis requirements

of the comparator, let's review Fig. 32.37. We see that when the output of the comparator
changes states, the output of the integrator changes by at least
C I V REF+ − V REF−
Change in integrator output = G I ⋅ (VDD − V CM ) = ⋅ (32.42)
CF 2
For the modulator of Fig. 32.27 this equation can be evaluated as 0.3 V. As long as the
hysteresis is much less than this value and the gain of the comparator (1.5/0.3 or 5) is
large enough so that the comparator can make a full output transition with this input
difference, then the modulator will function properly. Very simple, low-performance
comparator designs can be used while not affecting the modulator's performance.
Op-Amp Gain (Integrator Leakage)
Now that we've discussed the gain of the comparator, let's determine how high the
open-loop gain of the op-amp must be for proper integrator action. With low op-amp
gain, some of the charge stored on the integrator's input capacitor, CI , is not transferred
to the feedback capacitor, CF . This loss of charge is sometimes referred to as integrator
leakage. The charge on the input capacitance effectively leaks off when it is transferred to
the feedback capacitance.
Chapter 32 Noise-Shaping Data Converters 187

We can write the open-loop, frequency-dependent gain of the op-amp as AOL( f ).

The output voltage of the op-amp is then v out = A OL ( f )(v + − v − ) , where v + is our
common-mode voltage VCM (the noninverting terminal of the op-amp), see Fig. 31.78, and
v − is the op-amp's inverting input terminal. Following the procedure to derive Eq.
(31.134), we can rewrite Eq. (31.132) with finite op-amp gain as
 v [nT s ] 
Q 2 = C I V CM − out − v 2 [nT s ] (32.43)
 A OL ( f ) 
or, rewrite Eq. (31.134) to include the effects of finite op-amp gain to get
C I V 1 (z) ⋅ z −1/2 − V 2 (z)
V out (z) = ⋅ (32.44)
CF  CI  −1
 1 + C F A OL ( f )  − z
1

Using this result in Eq. (32.3) and, as discussed in the last section, assuming the forward
gain of the modulator, GF , is one gives
C
z −1 1 + C FI A 1
OL ( f)
− z −1
Y(z) = C
⋅ X(z) + C
⋅ E(z) (32.45)
1 + CI A 1
1 + CI A 1
F OL ( f ) F OL ( f )

The gain error term

CI 1
ε gain = ⋅ (32.46)
C F A OL ( f )
is ideally zero so that Eq. (32.45) reduces to Eq. (32.4). Note how reducing the
integrator's gain, CI /CF , reduces the gain error while increasing the gain required of the
comparator. Note also how the denominator term is common in both the signal and the
noise. This term results in a data converter gain error (it behaves as if it were an op-amp
offset voltage that is a function of the integrator's output amplitude [which results in the
gain error] and frequency), but it will not affect the modulator's SNR. To determine the
increase in the modulator's output noise (the change in the shape of the modulation noise)
we need to look at the noise transfer function including the effects of the gain error
NTF ε (z) = (1 + ε gain ) − z −1 (32.47)
or, in the frequency domain,
 f
NTF( f ) 2
= 2(1 + ε gain ) 1 − cos 2π + ε 2gain (32.48)
 fs 
Following the same procedure used to arrive at Eq. (32.15) and assuming constant
op-amp gain, AOL( f ), from DC to B, results in
V 2LSB  fs 3 fs 
⋅  4(1 + ε gain ) π2 ⋅ 1 ⋅   + ε 2gain ⋅
2
V 2Qe,RMS = 2 ⋅
2K 
(32.49)
12f s  f s 3 2K  

noting that if ε gain = 0 , this equation reduces to Eq. (32.15).

188 CMOS Mixed-Signal Circuit Design

If we assume the contribution to the noise from the error term squared, ε 2gain , is
small, which is valid for op-amp gain
A OL ( f ) > K (the oversampling ratio) (32.50)
over the frequency range of DC to B, then we can rewrite Eq. (32.16), to include the
effects of finite op-amp gain, as
SNR gerr = 6.02N + 1.76 − 20 log π + 20 log K 3/2 − 10 log (1 + ε gain ) (32.51)
3
The largest degradation in the SNR, resulting from integrator leakage, can be estimated as
0.5 dB if K ≥ 8 (ε gain ≈ 1/8 neglecting GI ). The minimum gain⋅ bandwidth product of the
op-amp is estimated as
Op-amp unity gain frequency, f u = K ⋅ B = f s /2 (32.52)
assuming the op-amp is rolling off at 20 dB/decade at B (a dominant pole compensated
op-amp). Otherwise, the minimum gain of the op-amp can be estimated simply as the
oversampling ratio, K.
To illustrate typical op-amp requirements, let's consider the modulator of Fig.
32.37 with K = 16 and B = 3.125 MHz (see Ex. 32.3). The fu of the op-amp is estimated,
using Eq. (32.51), as 50 MHz. If the open-loop response of the op-amp starts to roll off at
10 kHz, then the DC gain of the op-amp must be at least 5,000. However, we could also
use an op-amp with a DC gain of 100 (remembering low integrator gain increases the
undesirable effects [noise and offset] of the comparator on the performance of the
modulator) that rolls off at 500 kHz.
Op-Amp Settling Time
Equation (32.52) can be used, for the moment, to provide an estimate for the settling time
requirements of the op-amp in a first-order modulator. Assuming the settling time is linear,
and not slew-rate limited, we can write the change in the op-amp's output (assuming a
dominant pole compensated op-amp, see Eqs. [27.37] and [27.38]) as

v out = V outfinal (1 − e −t/τ ) where τ = 1 (32.53)

2πf u ⋅ β
where, for the DAI (see Fig. 32.41), the feedback factor is
CF
β= (32.54)
CF + CI
The feedback factor is 0.714 in the modulator of Fig. 32.37. The output of the DAI, vout,
must settle in a time, t (< Ts /2), to some percentage of an ideal value, Voutfinal. Solving for
this percentage using Eqs. (32.52), (32.53), and (32.54) and assuming T s /2 = t results in

× 100% = 1 − exp  − π ⋅
v out CF 
 × 100% (32.55)
V outfinal  2 CF + CI 
Chapter 32 Noise-Shaping Data Converters 189

CF
β ⋅ v out = v f = v out
CI + CF CF

vf
CI v out

Figure 32.41 The feedback factor in the DAI.

The output will only reach 67% of its ideal final value in the modulator of Fig. 32.37 when
the op-amp used has a unity gain frequency of fs /2.
In deriving Eq. (32.55) we used an op-amp unity gain frequency specified by Eq.
(32.52) to determine the settling response of the integrator. If the settling is linear then
incomplete settling will result in a constant DAI gain error (0.67 above). Every time the
output changes it will change by some constant percentage of its ideal value. Rewriting the
transfer function of our DAI to include this constant gain error results in
Settling gain error, G s
C V (z) ⋅ z −1/2 − V 2 (z)
V out (z) = I ⋅ (1 − e −πβ⋅(f u /f s ) ) ⋅ 1 (32.56)
CF 1 − z −1
Full, or complete, settling requires that the op-amp's unity gain frequency, fu , be much
larger than the sampling frequency, fs (in other words we can't use Eq. [32.52] to specify
the required bandwidth of the op-amp if settling time is important). The constant gain
error, resulting from incomplete settling, can be tolerated in the first-order modulator
because the integrator is directly followed by a comparator, as discussed earlier. In some
of the modulator topologies, though, the integrator is not followed by a comparator so
settling time becomes more important. To determine to what percentage the integrator
output must settle in these topologies, a gain term, say Gs, is added to the linearized block
diagram of the modulator (integrator). The transfer function of the modulator is then
evaluated to determine the allowable values of Gs for the application.
It's important to realize that we are assuming the op-amp doesn't experience
slew-rate limitations. If slewing is present, then the added gain term, in Eq. (32.56), will
not be a constant and will introduce distortion into the modulator's output spectrum
(whether a comparator follows the integrator or not).
Op-Amp Offset
The operation of the DAI is subject to the op-amp's offset. It can be shown that this offset
will effectively add (or subtract) from the common-mode voltage, VCM, and thus effectively
shift the input signals upwards or downwards. The resulting modulator output will then
show an offset equal to the op-amp's offset. To circumvent this problem, offset storage
can be used in the integrator.
190 CMOS Mixed-Signal Circuit Design

Op-Amp Input-Referred Noise

We'll discuss the calculation of the DAI input-referred noise (PSD of V 2n,DAI [ f ] ), at the
transistor level, in the next chapter. Here we discuss how the DAI's unwanted noise
contributions affect the SNR of the modulator, assuming we know V 2n,DAI ( f ) . Figure
32.42 shows the modulator's input-referred noise source, V n,ckt ( f ), in series with the input
signal. This noise source, with units of V/ Hz , includes both the integrator's and the
comparator's contributions. However, as discussed earlier, the noise contributions from
the comparator are usually negligible.

Modulator's input-referred noise, V n,ckt ( f ) = V2n,DAI ( f ) + V 2n,comp ( f )/A 2 ( f )

In Out
A( f )
Comparator
Integrator

Figure 32.42 The modulator's input-referred noise contributions from both the
comparator and the integrator.

Because the modulator's input-referred noise adds directly to the input signal, we
can use the derivations developed earlier in the chapter. As specified in Eq. (32.4), the
modulator's input, and thus its input-referred noise, pass through the modulator with a
delay of z-1. If we assume the modulator's input-referred noise is white and bandlimited to
fs /2 such that
Vn
V n,ckt ( f ) = for f < f s /2 (32.57)
fs
then passing the output of the modulator through an ideal lowpass filter with a bandwidth
of B ( = fs /[2K] ) results in
B
V 2n V
V ckt,RMS = 2 ⋅ ∫ ⋅ df = n (32.58)
0
fs K
Noting that not passing the output of the modulator through a lowpass filter results in an
RMS output noise of Vn, we see that the averaging filter (the lowpass filter) reduces the
noise by the root of K. We could also think of the filtering as reducing the PSD of the
modulator's input-referred noise by K. Remembering the jitter discussion from the last
chapter, we see a direct parallel in the derivations of how averaging affects the RMS value
of a random signal (noise or jitter).
Finally, as used in Ex. 31.15, we can estimate the finite SNR of a data converter
from quantization noise, jitter, and circuit noise using

V n,RMS = V 2Qe,RMS + V 2jitter,RMS + V 2ckt,RMS (32.59)

Chapter 32 Noise-Shaping Data Converters 191

and
Vp / 2
SNR= 20 ⋅ log (32.60)
V n,RMS
where Vp is the peak amplitude of an input sinewave, see Eq. (31.1), and

V jitter,RMS = P AVG,jitter (see Eq. [31.47]) (32.61)

Practical Implementation of the First-Order NS Modulator

As discussed in Ch. 27, switched-capacitor circuits suffer from the problems of capacitive
feedthrough and charge injection. To reduce these effects, fully-differential circuit
topologies are used. It could be stated that if reasonable size capacitors and dynamic range
are required, fully-differential topologies are a necessity simply because they subtract out,
to a first-order, the voltage changes on the switched-capacitors resulting from these
problems. In addition, again as discussed in Ch. 27, fully-differential topologies are used
because they improve power supply and substrate-coupled noise rejection and improve
distortion (even-order harmonics cancel).
Figure 32.43 shows the fully-differential implementation of the DAI of Fig. 31.78.
The inputs are now differential, that is, now v 1 = v 1+ − v 1− and v 2 = v 2+ − v 2− , as is the
output of the integrator, v out = v out+ − v out− . The fully-differential DAI has the same
transfer function as the single-ended DAI assuming the input signals are differential.

v 2+ CF
φ1 φ2
v 1+
CI
v out+
V CM
v out−
CI
v 1−

v 2− CF
C I V 1 (z) ⋅ z −1/2 − V 2 (z)
V out (z) = ⋅
CF 1 − z −1
Figure 32.43 Fully-differential discrete-analog integrator (DAI) implementation.

It's important to understand the signal levels in the fully-differential DAI. Let's
assume VCM = 0.75 V and the input voltages can range in amplitude from 0 to 1.5 V.
Assuming the input is balanced correctly if v 1+ = 0.85 V , then v 1− must equal 0.65 V. The
maximum input voltage is v1max= 1.5 − 0 = 1.5 V. The minimum input signal, on the other
hand, is v1min = 0 − 1.5 = −1.5 V. The range of inputs, or outputs, is then 3 V or twice the
range of the single-ended DAI.
192 CMOS Mixed-Signal Circuit Design

Figure 32.44 shows the implementation of a first-order NS modulation utilizing a

fully-differential DAI. Figure 32.45 shows the SPICE model used for a differential
input/output op-amp (see also, Fig. 26.29). We'll use this model to simulate the operation
of the modulator of Fig. 32.44 with the input signals and capacitor sizes used in Fig. 32.37
( fs = 100 MHz, CI = 0.4 pF, and CF = 1 pF, fin = 250 kHz, and a 0.7 V peak input
sinewave [the input sinewave, V in+ − V in− , has a peak amplitude of 2.8 V]).

V out
φ1 φ2 CF
V in+ φ1
CI

V CM V out

CI
V in−
CF
−V out

Figure 32.44 Fully-differential implementation of a first-order NS modulator.

v o+
v− E1
V CM
v− v o+

v+ v o−
v+ E2

v o−
Figure 32.45 SPICE modeling a differential input/output op-amp with common-mode voltage.

Figure 32.46 shows the simulation results for the outputs of the modulator of Fig.
32.44 after being passed through two RC filters with time constants of 100 ns. Passing a
single modulator output to the decimating filter would result in an output that is half the
input signal amplitude, which can be compensated for at the output of the filter by a
shift-left operation (multiply by two). Note, because the gain of the integrators is 0.4, the
integrator output's swing is at most 80% of the supply rails. Also note that the input
common-mode voltage of the op-amp remains at 0.75 V. This is important as the design
of the op-amp becomes more challenging if the common-mode voltage is not constant.
The finite op-amp common-mode rejection ratio (CMRR) can introduce distortion into the
output of the modulator. Because many input signals will not be fully-differential, we
briefly discuss differential modulator design with single-ended inputs next.
Chapter 32 Noise-Shaping Data Converters 193

Figure 32.46 Outputs of the fully-differential first-order modulator after RC filtering.

Fully-Differential Modulator with a Single-Ended Input

If we connect our modulator's minus input, V in− , to the common mode voltage, VCM , we
can apply a single-ended input to the modulator's Vin+ input. We need to note several
differences when the modulator is used with a single-ended input. The maximum input
signal is now half of the modulator's input range. This means that we can increase our
integrator's gain to 0.8 and still avoid DAI output saturation. It also means that our
modulator output range will be at most half of the full-scale range, Fig. 32.47a. Finally,
and probably most importantly, the op-amp's input common mode voltage now changes
with the input signal, Fig. 32.47b, which may result in the input diff-amp used for the first
stage in the op-amp shutting off (see also Eq. [34.8]).

(a) (b)

Figure 32.47 (a) Filtered modulator outputs with full-scale (1.5 V peak-to-peak) single-
ended input, and (b) how the input common-mode voltage of the op-amp changes.
194 CMOS Mixed-Signal Circuit Design

32.1.3 Second-Order Noise-Shaping

If we review Eq. (32.4), we might wonder if further filtering of the quantization noise,
E(z), can result in an improvement in the data converter's SNR over an input signal
bandwidth B. The second-order modulator's output shows a double differentiation of the
quantization noise
2
Y(z) = z −1 X(z) + (1 − z −1 ) E(z) (32.62)
The modulation noise may then be written, see Eqs. (32.10) and (32.11), as
2
V 2LSB  f
NTF( f ) 2 ⋅ V Qe ( f ) 2
= ⋅ 4 1 − cos 2π (32.63)
12f s  fs 
Figure 32.48 shows a comparison between the modulation noise of first- and second-order
NS modulators. Notice how the modulation noise is "flatter" in the bandwidth of interest.

V 2 /Hz ×10 −9 V 2 /Hz ×10 −9

Second-order modulation noise

f, Hz ×10 6 First-order modulation noise f, Hz ×10 6

f s = 100 MHz
Figure 32.48 Comparing first- and second-order NS modulator's modulation noise.

If we restrict our frequency range to frequencies less than fs /2, then we can rewrite
Eq. (32.63) as
V LSB f
NTF( f ) ⋅ V Qe ( f ) = ⋅ 4 sin 2 π (32.64)
12f s f s

Calculating the RMS quantization noise in a bandwidth B results in

V LSB π 2 1
V Qe,RMS ≈ ⋅ ⋅ 5/2 (32.65)
12 5 K
with an increase in the SNR of
SNR ideal = 6.02N + 1.76 − 12.9 + 50 log K (32.66)
Every doubling in the oversampling ratio results in an increase in SNR of 15 dB or 2.5
bits increase in resolution! Figure 32.49 shows a comparison between simple
oversampling, first-order NS, and second-order NS-based data converters. Note that, as
discussed earlier, the oversampling ratio is generally greater than or equal to eight.
Chapter 32 Noise-Shaping Data Converters 195

Improvement in resolution, N inc

(Bits added) Second-order noise-shaping, M = 2

16.6

13.3
First-order noise-shaping, M = 1
10.0

6.66

3.33 Simple oversampling, M = 0

0
1 10 100 1k 10k K , Oversampling ratio

Figure 32.49 Comparing improvement in modulator resolution.

Second-Order Modulator Topology

Consider the block diagram of a NS modulator shown in Fig. 32.50 (see Fig. 31.82). The
transfer function of this modulator may be written as
A(z) 1
Y(z) = ⋅ X(z) + ⋅ E(z) (32.67)
1 + A(z)B(z) 1 + A(z)B(z)
Comparing this equation to Eq. (32.62), we can solve for the forward and fed-back circuit
blocks, A(z) and B(z), by equating coefficients
A(z)
STF(z) = = z −1 (32.68)
1 + A(z)B(z)
and

NTF(z) = 1 = (1 − z −1 )
2
(32.69)
1 + A(z)B(z)

E(z)

ADC
In X(z) Y(z) Out
A(z)

B(z)

Figure 32.50 Block diagram of a feedback modulator.

196 CMOS Mixed-Signal Circuit Design

The results are

A(z) = z −1 (32.70)
2
(1 − z −1 )

and
B(z) = 2 − z −1 (32.71)
The second-order modulator can be implemented using the topology shown in Fig.
32.51a. The output of B(z) is the sum of the modulator output and the differentiated,
(1 − z −1 ) , modulator output. We can redraw the block diagram of Fig. 32.51a, as shown in
Fig. 32.51b, resulting in the implementation of a second-order NS modulator shown in
Fig. 32.51c.

E(z)
Comparator
A(z)
In X(z) 1 z −1 Y(z) Out
1 − z −1 1 − z −1

1 − z −1
B(z)

(a) E(z)

In X(z) 1 z −1 Y(z) Out

1 − z −1 1 − z −1

1
1 − z −1
1 − z −1

(b)
E(z)

In X(z) 1 z −1 Y(z) Out

1 − z −1 1 − z −1

(c)

Figure 32.51 Block diagrams of second-order modulators.

Chapter 32 Noise-Shaping Data Converters 197

The second-order (de) modulator topology of Fig. 32.51c can be used directly to
implement a NS DAC (see Figs. 32.11 and 32.12). However, this topology doesn't lend
itself directly to implementation using the DAI. The major concern, as discussed in the last
section, is the op-amp's output going to the power-supply rails (integrator saturation).
This is more of a concern in the second-order modulator since the output of the first
integrator isn't connected directly to a comparator.
Figure 32.52a shows how we can add an integrator gain to the block diagram of
Fig. 32.51c without changing the system's transfer function. Figure 32.52b shows pushing
the gain, 1/GI , through the second summer so that it is directly preceding the second
integrator. Notice how in Fig. 32.52b this (the second integrator's gain) is in series with
the comparator's gain (not shown; see Fig. 32.36 and the associated discussion). This
means we can arbitrarily change the second integrator's gain because of how the
E(z)
Comparator
X(z) Y(z)
In 1 1 z −1 Out
GI
1 − z −1 GI 1 − z −1

(a)

Can be selected arbitrarly because

of comparator gain (not shown). E(z)

X(z) Y(z)
In 1 1 z −1 Out
GI
1 − z −1 GI 1 − z −1

GI

(b)
E(z)
X(z) ⋅ z −1/2
X(z) 1 z −1 Y(z)
z −1/2 G1 G2 Out
1 − z −1 1 − z −1

(c)

Figure 32.52 Block diagrams of second-order modulator introducing integrator gains.

198 CMOS Mixed-Signal Circuit Design

comparator gain changes to force the loop gain to unity (see Fig. 32.38). Figure 32.52c
shows the resulting configuration where the second integrator has the a gain of G2 and the
first integrator has a gain of G1. Also notice how we have added a delay in series with the
input signal. This delay was added to show how using a DAI results in an added delay in
series with the input signal. The delay doesn't affect the magnitude of modulator's transfer
function but rather indicates the input signal arrives half a clock cycle later.
Figure 32.53 shows the DAI implementation of the second-order modulator of Fig.
32.52c. Note how the output of the modulator is fed back and immediately passes through
the first integrator and is applied to the second integrator (no delay as seen in Fig. 32.52c).
This is a result of switching the phases of the clock signals in the first integrator. We
should also see how the input signal sees an added half-clock cycle delay. Note that at this
point it should be trivial to sketch the circuit implementation of the fully-differential,
second-order modulator (see Fig. 32.44).

C F2
V CM C F1 V CM φ 1 φ2 V CM φ 1
φ2 φ1
C I2 V out
C I1
V CM
V CM

V in
C I1 C I2
f s = 100 MHz G1 = G2 =
C F1 C F2
Figure 32.53 Implementation of the second-order modulator of Fig. 32.52c.

Integrator Gain
As we showed in Eq. (32.41) for the first-order modulator, the forward gain of a second-
order modulator will be unity when the modulator is functioning properly. We now need
to discuss how to select the integrator gains to avoid harmful integrator saturation. If
noise and offsets were not a concern, as shown in Fig. 32.40 and the associated
discussions, then we could make our integrator gains very small (ultimately limited by
imperfections in the switches such as clock feedthrough and charge injection). In a
practical modulator, integrator saturation (the integrator's gain going to zero) can also
lead to modulator instability, as shown in Eq. (32.40), and the associated discussion.
Figure 32.54 shows the integrator outputs for the modulator of Fig. 32.53 if both
integrator gains are set to 0.4. Notice how both outputs go outside the supply voltage
range. If we replace the ideal op-amps in the simulation with transistor-based op-amps, the
integrator outputs will saturate at some voltage within the supply range. This saturation
can be thought of as noise and ultimately limits the data converter's SNR. Integrator
saturation can be avoided by limiting the input signal range, designing with small
integrator gain, and using op-amps that have a wide output swing.
Chapter 32 Noise-Shaping Data Converters 199

Output1
Output2 Supply voltage range

Figure 32.54 Showing integrator outputs using ideal components.

Example 32.12
Using SPICE simulations, show how an ideal second-order NS modulator can
become unstable if the integrator gain is too low.
Because the second integrator is directly followed by a comparator, its gain is
more tolerant to variations allowing it (the gain) to be made small. The first
integrator's gain, however, is isolated from the comparator by the second
integrator restricting its values. Figure 32.55a shows the (unstable) output of the
modulator in Fig. 32.53 if G1 = 0.01, while Fig. 32.55b shows the integrator
outputs. T

(a) (b)

Figure 32.55 (a) Modulator output, and (b) integrator outputs ifG 1 = 0.01
200 CMOS Mixed-Signal Circuit Design

For a more quantitative view of how the gains in a second-order NS modulator

affect performance, let's consider a couple of different topologies. Figure 32.56 shows the
block diagram of the second-order NS modulator topology of Fig. 32.50, with an
integrator gain coefficient, GI , and a comparator gain, Gc , added. Deriving the transfer
function of this linearized model with G F = G I ⋅ G c results in
2
G F ⋅ z −1 (1 − z −1 )
Y(z) = ⋅ X(z) + ⋅ E(z)
1 + z ⋅ 2(G F − 1) + z ⋅ (1 − G F )
−1 −2 1 + z ⋅ 2(G F − 1) + z −2 ⋅ (1 − G F )
−1

(32.72)
The poles of this transfer function are located at

z p1,p2 = (1 − G F ) ± (1 − G F) 2 − (1 − G F ) (32.73)
We know that for the modulator to remain stable the poles must reside within the unit
circle. This means that our values of forward gain are restricted to
0 ≤ G F ≤ 1.333 (32.74)
Again, if the modulator is functioning properly, GF = 1 (because of the comparator's gain
variation as seen in Fig. 32.28 and the associated discussion).

E(z)

In X(z) z −1 Y(z) Out

GI 2 Gc
(1 − z −1 )
GF = GI ⋅ Gc

2 − z −1

Figure 32.56 Block diagram of a second-order feedback modulator with gains.

We should make some observations at this point. Reviewing Eq. (32.40), we see
that the allowable range of forward gain, in the first-order modulator, is larger than the
allowable range in the second-order modulator. However, as long as the integrators don't
saturate (GI doesn't approach zero), stability for either modulator is easy to attain. An
analysis of the stability of higher order modulators show that the range of allowable
forward gains decreases with the order of the modulator. For example, a third-order
modulator can have a forward gain of at most 1.15. Finally, notice that the input signal
range is more restricted for the second-order modulator, in order to avoid integrator
saturation, as seen in Fig. 32.54. We'll discuss methods to attain wider input signal range
and more robust stability criteria by adjusting the feedback gains later in this section.
Chapter 32 Noise-Shaping Data Converters 201

Notice that we are treating our modulator as a linear system even though it isn't
linear; the comparator gain is a nonlinear variable. The linear approximation is useful to
give an idea of the stability of the modulator under certain operating conditions. Generally,
a DC input is applied to the modulator in the simulation, while lowpass filters are added to
determine the average comparator gain, Gc. Figure 32.57 shows this schematically.
Assuming we know GI (the gain coefficient of the integrators), we can then look at the
stability and forward gain of the modulator for varying DC input signal voltages.

DC input
v LPF LPF
G c = voutc
inc

v inc v outc
Figure 32.57 Simulating the gain of the comparator.

Next consider the more generic block diagram of the second-order NS modulator
shown in Fig. 32.58. In a moment we'll discuss how to implement the feedback gain, G3,
using the DAI. The transfer function of this topology can be written as
G 1 G 2 G c ⋅ z −1 X(z) + (1 − z −1 ) 2 ⋅ E(z)
Y(z) = (32.75)
1 + z −1 ⋅ (G 1 G 2 G c + G 2 G 3 G c − 2) + z −2 ⋅ (1 − G 2 G 3 G c )
Notice that if G 1 = G 2 = G 3 = G c = 1 (where G 1 G 2 G c = G F ), then this equation reduces
to Eq. (32.62). The poles of this equation are located at

2 − G 1 G 2 G c − G 2 G 3 G c ± (2 − G 1 G 2 G c − G 2 G 3 G c ) 2 − 4(1 − G 2 G 3 G c )
z p1,p2 =
2
(32.76)
When the modulator is functioning properly we require the (linearized) coefficient of the
input, X(z) in Eq. (32.75), to be unity
G1G2Gc
=1 (32.77)
(z − z p1 )(z − z p2 )
Again, if we set G 1 = G 2 = G 3 = 1 (and Gc = 1), then the poles are located at DC, that is,
z p1,p2 = 0 (32.78)
Equation (32.76) is useful to estimate the modulator's stability when scaling amplitudes by
adjusting the integrator gain coefficients, G1, G2, and G3.
202 CMOS Mixed-Signal Circuit Design

E(z)

X(z) G1 G 2 ⋅ z −1 Y(z)
Gc
In 1 − z −1 1 − z −1 Out

G3

GF = G1G2Gc

Figure 32.58 Generic block diagram of a second-order NS modulator.

Implementing Feedback Gains in the DAI

Consider the modified DAI shown in Fig. 32.59. Notice that if CI2 = CI3, this topology
reduces to the DAI shown in Fig. 31.78. Also note that some of the switches can be
combined to simplify the circuitry. Assuming that the output is connected through the φ 2
switches (or that there are no switches connected to the output of the op-amp, see Eq.
[31.136]) we can write the transfer function of the integrator as
C I2 z −1/2 C 1
V out (z) = V 1 (z) ⋅ ⋅ − V 2 (z) ⋅ I3 ⋅ (32.79)
C F2 1 − z −1 C F2 1 − z −1
The block diagram of this topology is shown in Fig. 32.60a. We want to implement a
block diagram like the one shown in Fig. 32.60b. Because we have already defined
C I2
G2 = (32.80)
C F2
we define our feedback gain, G3 , as
C I3 1 C
G3 = ⋅ = I3 (32.81)
C F2 G 1 C I2

C F2
φ1 φ2
V CM

C I2 V CM v out
v1

C I3
v2

Figure 32.59 Adding an additional gain setting to our DAI.

Chapter 32 Noise-Shaping Data Converters 203

V 1 (z) C I2 −1/2
⋅z
1 V out (z)
C F2 1 − z −1

C I3 V 2 (z)
C F2
DAI of Fig. 32.59
(a)

V 1 (z) G2 V out (z)

z −1/2
1 − z −1
C I2
G2 =
C F2

G3 =
C I3 G3 V 2 (z)
C I2
DAI of Fig. 32.59
(b)

Figure 32.60 Block diagram of a DAI.

Example 32.13
Sketch the circuit implementation of a second-order NS modulator based on the
topology of Fig. 32.58, where G 1 = G 2 = G 3 = 0.4 . Comment on the stability of
the resulting configuration. Simulate the design and show the integrator output
swing.
The block diagram of the modulator is shown in Fig. 32.61. We could dissect Eq.
(32.76) at this point to determine the transient properties of the modulator.
However, before discussing the transient characteristics of the modulator, let's
look at the integrator output swing.
φ1 φ2 1p φ1
φ2 φ1 1p
V CM V CM
V CM 0.4p V out
0.4p
V CM
V in V CM
0. 16p

Figure 32.61 Implementation of a second-order modulator with feedback gain.

204 CMOS Mixed-Signal Circuit Design

Figure 32.62 shows the output swing of the integrators. This figure should be
compared with Fig. 32.54. The output of the first integrator now falls within the
power supply range. The output of the second integrator is reduced but still
exceeds the power supply range. This, as discussed earlier, has less impact on
performance in the actual transistor-based modulator because the integrator is
followed by a comparator.

Output2

Figure 32.62 Integrator output signals in the modulator shown in Fig. 32.61.

Let's attempt to get an idea for the stability of the modulator by adding LPFs,
as seen in Fig. 32.57, to the simulation (with a DC input) to measure Gc. Figure
32.63 shows how we will implement the LPFs. The voltage-controlled voltage
source is used to keep from loading the modulator with the RC circuit when it is
added into the general simulation. In our ideal modulator shown in Fig. 32.61 both
the comparator output and integrator outputs are ideal voltage sources, so we
don't need the isolation (and therefore we can add the RC LPF directly into the
simulation).

Out
In 10k
1 100 pF RC >> 1/f s

Figure 32.63 SPICE implementation of a LPF for determining comparator gain.

Chapter 32 Noise-Shaping Data Converters 205

Figure 32.64 shows the comparator input and output, after lowpass filtering,
for the modulator of Fig. 32.61 when the input signal is 0.1 V (DC). Longer
simulation times reveal the average comparator input is 0.4 V. The resulting
comparator gain is then only 0.25. Using Eq. (32.76) to calculate the location of
the poles results in z p1.p2 = 0.96 ± j ⋅ 0.195 . These poles are very close to the unit
circle. Small shifts in the DAI gains can result in an unstable modulator. Increasing
the input signal amplitude makes the modulator more stable. Increasing G3 also
increases the modulator's stability.

Average comparator input voltage

Average modulator output

Figure 32.64 Average comparator input and output when using the modulator
of Fig. 32.61 with an input signal of 0.1 V.

The simulation that generated Fig. 32.64 can be very useful in understanding
basic second-order modulator's stability criteria. Changing the simulation variables
and looking at the resulting simulation outputs can be very instructional. Note that
increasing the simulation time in the netlist that generated Fig. 32.64 would reveal
that the comparator input actually has small amplitude oscillations. Also note how
Fig. 32.62 shows the output of the second integrator going way outside the power
supply limits when transitioning negative (going well below 0 V) while staying
bounded to the power-supply rail when transitioning positive (above 1.5 V). This
is related to the stability of the modulator being a function of the input voltage. T
Using Two Delaying Integrators to Implement the Second-Order Modulator
Consider the second-order modulator topology shown in Fig. 32.65. This topology can be
implemented using the circuits of Figs. 32.53 or 32.61 by simply switching the phases of
206 CMOS Mixed-Signal Circuit Design

E(z)

X(z) G 1 ⋅ z −1 G 2 ⋅ z −1 Y(z)
Gc
In 1 − z −1 1 − z −1 Out

G3

Figure 32.65 Second-order NS modulator using two delaying integrators.

the clocks in the first integrator (by making both integrators delaying). The transfer
function of this topology is
G 1 G 2 G c ⋅ z −2 X(z) + (1 − z −1 ) 2 ⋅ E(z)
Y(z) = (32.82)
1 + z −1 ⋅ (G 2 G 3 G c − 2) + z −2 ⋅ (1 − G 2 G 3 G c + G 1 G 2 G c )
The poles are located at

2 − G 2 G 3 G c ± (2 − G 2 G 3 G c ) 2 − 4(1 − G 2 G 3 G c + G 1 G 2 G c )
z p1,p2 = (32.83)
2
This equation should be compared to Eq. (32.76). Remembering that for a stable
modulator the poles must be inside the unit circle, we see that using two delaying
integrators will not result in a modulator that has as robust stability criteria as the general
implementation of Fig. 32.58. Figure 32.66 shows the implementation of a second-order
NS modulator using two delaying integrators. One advantage of this topology over the
topology of Fig. 32.58 is the reduced slew-rate requirements of the op-amps since neither
op-amp in Fig. 32.66 has to drive both the feedback capacitance and the switched input
capacitance of the next stage during the same clock phase.

Note the change in clock phases

C F2
V CM C F1 V CM φ 1 φ2 V CM φ 1
φ1 φ2
C I2 V out
C I1
V CM
V CM

V in
C I1 C I2
f s = 100 MHz G1 = G2 = G3 = 1
C F1 C F2

Figure 32.66 Implementation of a delaying second-order NS modulator.

Chapter 32 Noise-Shaping Data Converters 207

Selecting Modulator (Integrator) Gains

Before leaving this section, let's discuss the general selection of modulator gains. In
general, for good stability, the inner loop feedback gain, G3, should be made as large as
possible. For general design, set G3 = 1. This simplifies the design of the modulator
circuitry and provides good flexibility when selecting the values of G1 and G2. If G3 = 1,
then Eq. (32.76) may be rewritten to show the location of the poles as

2 − G 1 G 2 G c − G 2 G c ± (2 − G 1 G 2 G c − G 2 G c ) 2 − 4(1 − G 2 G c )
z p1,p2 = (32.84)
2
Keeping in mind that the reason we are not setting all gains to one is to avoid integrator
saturation, we can look at Eq. (32.84) as a guide to determine how we can reduce G1 and
G2. Since G2 is directly followed by the comparator, we can set its gain to 0.4 as discussed
earlier. Practically then, we can reduce the value of G1 to a very small number and still
have a stable modulator (see Ex. 32.12). At the same time using small G1 avoids integrator
saturation. The practical problem with small G1, as discussed earlier, is the increase in the
input-referred noise. Again trade-offs must be made for given design criteria. Figure 32.67
shows the integrator outputs for the modulator of Fig. 32.58 when G1 = 0.2, G2 = 0.4, and
G3 = 1. Note how, when compared to Figs. 32.54 and 32.62, the outputs are very well
behaved. We don't have the abnormal transitions above the power-supply rails indicating
that the modulator stability is becoming marginal with input signal values close to the
power-supply rails.
G 1 = 0.2
G 2 = 0.4
G3 = 1

Second integrator output.

Figure 32.67 Integrator outputs for a modulator with first integrator gain of 0.2.
208 CMOS Mixed-Signal Circuit Design

Understanding Modulator SNR

Figure 32.68 shows the output spectrum of a first-order NS modulator clocked at 100
MHz. This spectrum should be compared to the spectrum of the second-order NS
modulator shown in Fig. 32.69. Note how the spectrum of the first-order modulator
appears to contain more tones in the base spectrum of interest than the spectrum of Fig.
32.69. As discussed earlier, unwanted tones are less of a problem in second-order
modulators.

G = 0.4
Volts
V in = 0.75 + 0.5 sin (2π ⋅ 500kHz ⋅ t)
Voltage, peak

Figure 32.68 Output spectrum of a first-order modulator.

We know that for the modulator to be useful its output must be passed through a
lowpass filter to remove the modulation noise. In simulations we can approximate a
lowpass filter with a bandwidth B by limiting the spectral analysis range. To estimate the
SNR from the simulations of Figs. 32.68 or 32.69, with K = 16, we perform the spectral
analysis up to 50 MHz/16 or 3.125 MHz. The quantization noise plus distortion is
calculated as discussed in the last chapter and shown in the SPICE netlists.
To demonstrate the calculation of a modulator's SNR let's use the second-order
modulator simulation used to generate Fig. 32.69. Using Eq. (32.65) with VLSB = 1.5 V
and K = 16 results in an RMS quantization noise of 1.86 mV. The SNRideal is calculated,
using Eq. (32.66) as 55 dB. However, Eq. (32.66) was derived assuming Eq. (32.9) was
valid. For the 1-bit ADC/DAC it is not. For the 1-bit DAC/ADC VLSB is twice the value
given by Eq. (32.66) or VREF+ − VREF−. The doubling in VLSB results in a subtraction of 6 dB
from Eq. (32.66). The SNRideal is 49 dB. To discuss this further consider a sinewave with a
peak-to-peak amplitude of VLSB (= 1.5 here). We can write the SNR of the modulator as
Chapter 32 Noise-Shaping Data Converters 209

Volts G 1 = 0.2 G 2 = 0.4 G 3 = 1

V in = 0.75 + 0.5 sin (2π ⋅ 500kHz ⋅ t)
Voltage, peak

Figure 32.69 Output spectrum of a second-order modulator.

SNR ideal = 20 log   [1.5/2]/ 2  /(1.86 mV)  = 49 dB (32.85)

 
Modifying Eq. (32.66) for the 1-bit case and the increase in VLSB results in
SNR ideal = 50 ⋅ log K − 8.3 = 49 dB (32.86)
In practice the SNR (SNDR) is considerably worse than the ideal value. This
variation comes from the fact that our assumed quantization noise spectrum isn't white and
the modulator output can contain unwanted tones at multiples of the input sinewave signal
frequency. Figure 32.70 shows the output of the second-order modulator of Fig. 32.69
when we limit the spectral analysis to B (= 3.125 MHz). Calculating the SNR using Eq.
(32.85) with a peak input sinewave amplitude of 0.5 V gives 45.6 dB. Simulations using
ideal components, however, give a 37 dB SNDR. Zeroing out the tones (see the
commands in the netlist where we have already zeroed out the DC term and the
fundamental at 500 kHz) will obviously increase the SNR. Note also that we didn't use a
full-scale input sinusoid (peak amplitude of 0.75 V). Full-scale inputs inherently result in a
reduction in SNR because our modulator has less output signal range to average over. For
example, an input signal approaching the supply rails causes the output of the modulator
to remain high most of the time, while a mid-scale signal results in more modulator output
variation allowing better averaging. The reduction in SNDR with input signal amplitude
was shown back in Fig. 31.5. Finally, note that by using a high-frequency input signal,
which has the same effect as an added dither signal, the output modulation noise becomes
more random and the SNR increases. To illustrate this we could resimulate the netlist used
for Fig. 32.70 with an input frequency of 5 MHz (outside our signal band of interest).
210 CMOS Mixed-Signal Circuit Design

Volts
0.75 DC
0.5 V peak input sinewave

Second harmonic

Third harmonic

Figure 32.70 Same as Fig. 32.69 but with limited spectral range.

32.2 Noise-Shaping Topologies

The last section presented the fundamentals of NS data converters. It's important to
understand this fundamental material before proceeding with the topics presented in this
section.
In this section we cover (1) higher order NS modulators, (2) NS modulators using
multibit ADCs and DACs (multibit modulators), (3) cascaded modulators (higher-order
modulators built with a cascade of first- and/or second-order modulators), and (4)
bandpass modulators (modulators that perform data conversion over a band of frequencies
that doesn't include DC).
32.2.1 Higher-Order Modulators
We can take the theory developed for our first- and second-order modulators in the last
section and generalize it for an Mth-order modulator (a modulator having M integrators
and M feedback loops). Rewriting Eqs. (32.11) and (32.64) for the general Mth-order
modulator results in
M
V LSB  f
NTF( f ) ⋅ V Qe ( f ) = ⋅  2 sin π  (32.87)
12f s  f s

The RMS noise in a bandwidth, B, can be written, see Eqs. (32.25) and (32.65), as

V Qe,RMS =
V LSB
⋅ πM ⋅ M1+ 1/2 (32.88)
12 2M + 1 K
Chapter 32 Noise-Shaping Data Converters 211

The ideal increase in the SNR can be written as

 
SNR ideal = 6.02N + 1.76 − 20 log  π
M
 + [20M + 10] ⋅ log K (32.89)
 2M + 1 
or
SNR ideal = 6.02(N + N inc ) + 1.76 (32.90)
The increase in resolution, Ninc, is given by
  
N inc = 1  (20M + 10) ⋅ log K − 20 log  π
M
 (32.91)
6.02   2M + 1  
This equation shows that for every doubling in the oversampling ratio, K, the resolution
increases by M + 0.5 bits. In practice, as we have seen already, this equation results in an
overestimate for the increase in resolution because the quantization noise is not truly white
(because of the 1-bit ADC) and the modulation noise contains unwanted spectral tones (as
seen in Fig. 32.70).
M th-Order Modulator Topology
Reviewing the general NS modulator topology of Fig. 32.50 we want to determine the
forward transfer function, A(z), and the feedback transfer function, B(z), for an Mth-order
NS modulator. The transfer function of a general Mth-order modulator is
M
Y(z) = X(z) ⋅ (z −1 ) + E(z) ⋅ (1 − z −1 ) (32.92)
Using this equation together with Eq. (32.67) results in a forward modulator transfer
function of

A(z) = z −1 (32.93)
M
(1 − z −1 )
and a feedback filter transfer function of
M
1 − (1 − z −1 )
B(z) = (32.94)
z −1
The block diagram of an Mth-order NS modulator is shown in Fig. 32.71.
E(z)
Nondelaying integrators Delaying integrator

X(z) 1 1 z −1 Y(z)
In 1 − z −1 1 − z −1 1 − z −1 Out

th
Figure 32.71 Generic block diagram of an M -order NS modulator.
212 CMOS Mixed-Signal Circuit Design

Decimating the Output of an M th-Order NS Modulator

Let's revisit the derivation of Eq. (32.20). This equation states that the number of sinc
stages, L, used in cascade, for near optimum removal of the modulation noise, is one more
than the order of the modulator (L = M + 1). Rewriting Eq. (32.22)
f s /2

V 2Qe,RMS = 2 ∫ NTF( f ) 2 ⋅ V Qe ( f ) 2 ⋅ H( f ) 2 ⋅ df (32.95)

0

where the decimation filter's transfer function is given by

2(M+1)
  f 
 1 sin  Kπ f s  
H( f ) 2
= ⋅  (32.96)
 K sin  π f  
  fs  
The mean-squared quantization noise is calculated by evaluating
VQe ( f ) 2 NTF( f ) 2
2(M+1)
  f 
 1 sin  Kπ f s 
f s /2
V 2LSB  f
2M

V 2Qe,RMS = 2 ⋅ ⋅ ∫  2 sin π  ⋅ ⋅  ⋅ df (32.97)
12f s 0  f s  K sin  π f  
  fs  
or

sin2(M+1)  Kπ fs 
f
fs /2
V2 2(M+1)
V 2Qe,RMS = 2 ⋅ LSB ⋅ 2 2M ⋅  1  ⋅ ∫0 ⋅ df (32.98)
K
sin2M  π fs 
12f s f

f
If we let θ = π , then we get
fs
M
= K2 π⋅ Π
m=1
2m−1
2m

V2 sin 2(M+1) (Kθ)

2(M+1) 2
fs
V 2Qe,RMS = LSB ⋅  2  ⋅π⋅ ∫ ⋅ dθ (32.99)
12f s  K  0 sin 2M θ
Finally, the RMS quantization noise associated with an Mth-order modulator followed by
an M + 1 (= L) sinc averaging filter is
V LSB  2  M+1/2 M 2m − 1
V Qe,RMS = ⋅ ⋅Π (32.100)
12  K  m=1 2m

The change in SNR, when using the sinc averaging filter decimator instead of the ideal
filter with bandwidth, B, is given by looking at the ratio of Eq. (32.88) to Eq. (32.100)
 M
2M + 1 
Increase in SNR = −20 log  2 M+1/2 ⋅ Π 2m − 1 ⋅  (32.101)
 m=1 2m πM 
Chapter 32 Noise-Shaping Data Converters 213

For first-, second-, and third-order modulators, the difference in the SNRs is 2.16, 6.35,
and 10.39 dB, respectively. This shows that using a sinc averager, theoretically, increases
the SNR if we neglect the decrease in the desired signal amplitude because of the droop,
Figs. 31.43 or 31.46. To avoid the droop, as discussed earlier, the desired signal content is
often limited to frequencies well below fs/2K (= B). When the droop (reduction in the
desired signal amplitude) is taken under consideration, the SNR, when using the sinc
averaging filter, is worse than the ideal filter with bandwidth B.
Implementing Higher Order, Single-Stage Modulators
The single-stage, higher order modulator of Fig. 32.71 can be difficult to implement
directly. It is impossible to implement a higher order modulator, when using DAIs, where
all but the last integrator are nondelaying. However, as we saw with the second-order
modulator using two delaying integrators in Fig. 32.65 and Eqs. (32.82) and (32.83), the
stability criteria of a modulator using only delaying integrators is poorer than the criteria
of the topology shown in Fig. 32.71 (where only the last integrator is delaying). While we
can help the situation by staggering delaying and nondelaying integrators in a modulator,
the point is that implementing a higher order modulator without modifying our basic NS
topology will result in an unstable circuit. Intuitively, we can understand this by noting
that if the modulator's forward gain is too high and the delay through the forward path is
too long (because of the large number of integrators), the signal fed back may add to the
input signal instead of subtracting from it.
To help with the stability of a higher order modulator a topology that feeds the
input signal forward into additional points in the modulator (thereby reducing the forward
gain and delay) and feeds the output signal back as discussed earlier (allowing scaling of
amplitudes) is needed. Towards this goal, consider the modified NS topology for higher
order modulators shown in Fig. 32.72. The forward and feedback transfer functions can be
written as
M−i+1
a 1 ⋅ z −M a 2 ⋅ z −(M−1) a ⋅ z −(M−2) a ⋅ z −1 M −1
A(z) = + + 3 + ... + M −1 = Σ a i ⋅  z −1 
(1 − z −1
)
M
(1 − z −1 )
M−1
(1 − z −1 )
M−2 1−z i=1 1−z

(32.102)
or
A(z) = (z − 1) −M ⋅  a 1 + a 2 (z − 1) 1 + a 3 (z − 1) 2 + ... + a M (z − 1) M−1  (32.103)
and
b 1 ⋅ z −M b 2 ⋅ z −(M−1) b 3 ⋅ z −(M−2) b M ⋅ z −1 M  1 
M−i+1
−A(z)B(z) = M
+ M−1
+ M−2
+ ... + =
1 − z −1 i=1
Σ b i ⋅
z −1
(1 − z −1 ) (1 − z −1 ) (1 − z −1 )
(32.104)
or
−A(z)B(z) = (z − 1) −M ⋅  b 1 + b 2 (z − 1) 1 + b 3 (z − 1) 2 + ... + b M (z − 1) M−1  (32.105)
214 CMOS Mixed-Signal Circuit Design

E(z)
In
X(z) a1 a2 aM
z −1 z −1 z −1 Y(z)
1 − z −1 1 − z −1 1 − z −1 Out
bM
b2
b1

th
Figure 32.72 Block diagram of a modified M -order NS modulator.

Before going any further, let's explain what we are trying to do with the modified,
higher-order, NS topology of Fig. 32.72. We know that the NTF(z), for a general
modulator, is of the form (1 − z −1 ) M with a shape seen in Fig. 32.73. At high frequencies
the modulation noise will get very large. At fs /4, for example, the magnitude of the noise
M
transfer function, NTF( f ) , is  2  (see Fig. 31.51). For the modified NS modulator
we will try to reduce the modulation noise at higher frequencies by changing the shape of
the NTF(z). Our modified NTF(z) will be of the form
M
NTF(z) = LPF(z) ⋅ (1 − z −1 ) = LPF(z) ⋅  z −z 1 
M
= HPF(z) (32.106)

where LPF(z) [HPF(z)] is a lowpass [highpass] filter implemented with the feedback
coefficients bx. The goal is to flatten out the higher frequency modulation noise (keep the
noise from getting too large) thereby reducing the NTF( f ) at high frequencies and
keeping the modulator stable. One drawback of using this technique is that the signal no
longer sees just a delay in its transfer function but rather it sees the lowpass response. The
modified STF will be of the form
M
STF(z) = NTF(z) ⋅ A(z) = LPF(z) ⋅ Σ a i ⋅ (z − 1) i−1 (32.107)
i=1

NTF( f )
An example shape of a
higherorder NTF.
(1 − z −1 ) M
LPF(z) ⋅ (1 − z −1 ) M

(Less gain at high frequnencies)

f
B
Figure 32.73 Showing the change in the NTF in a higher order modulator.
Chapter 32 Noise-Shaping Data Converters 215

so that the feed forward coefficients, ax , can be used to help make the STF( f ) constant
over the region of interest (the STF can be made to have an overall lowpass response).
The NTF is given by

NTF(z) = 1 (32.108)
1 + A(z)B(z)
or

NTF(z) = 1 = HPF(z) (32.109)

M
1 − (z − 1) −M
⋅ Σ b i ⋅ (z − 1) i−1

i=1

The coefficients, bx, are selected for a highpass response. Note also that our coefficients
are positive since the feedback paths, as seen in Fig. 32.72, are subtracting. The design of
the modulator at this point is to determine the feed-forward and feedback coefficients
using basic digital-signal processing filter design (and, to keep the algebra simple, a
computer program of some sort), then to simulate the design to see if it exceeds
specifications. One challenge, among others, is to meet a given SNR without causing
harmful integrator saturation.
Other topologies have been developed to implement higher-order NS modulators.
The reader is referred to Chs. 4 and 5 of [2] for further information.
32.2.2 Multi-Bit Modulators
Throughout this chapter we have assumed N = 1; that is, we have used a comparator for
our quantizer in the forward path of our NS modulator. The main advantage of single-bit
modulators, as discussed earlier, is the inherent linearity of the 1-bit feedback DAC.
Feedback DAC linearity is important because the output of the DAC is directly subtracted
from the input signal. Any distortion or nonlinearity (or noise) in the output of the DAC
will directly affect the modulator's performance and, ultimately, limit the modulator's SNR.
The benefits of using a multibit (N > 1) quantizer in a NS modulator are increased SNR
(see Eq. 32.89), better stability (the modulator behaves closer to the linearized theory
developed in this chapter), fewer spectral tones, and simpler digital-decimation filter. The
drawbacks of using multibit topologies, are the increase in ADC complexity (the ADC
must be a flash converter) and the need for the DAC to be accurate to the final accuracy
of the modulator. The ADC errors, like gain errors in the integrators, are less important
since they are in the forward, high-gain path of the modulator.
Simulating a Multibit NS Modulator Using SPICE
Figure 32.74 shows a circuit-level implementation of a first-order, multibit, NS modulator
using a 4-bit ADC and DAC. Figure 32.75 shows the SPICE simulation outputs of this
modulator in the time and frequency domains with the same input sinewave used in
generating Fig. 32.68. Comparing Fig. 32.75 to Fig. 32.68 the decrease in modulation
noise is obvious. Note that (a) of the figure shows both the input to the modulator and the
output of the ideal DAC while (b) is the DAC's output spectrum. Looking at the output of
the DAC avoids the need for a Fourier transform on the modulator's output digital data.
216 CMOS Mixed-Signal Circuit Design

φ1 φ2
V REF+ = VDD
1p φ1
Clk
V CM 4-bit Out V out
V CM ADC
In 4-bits
0.4p V REF− = 0
V in Out 4-bit In
f s = 100 MHz DAC

Figure 32.74 Circuit implementation of a first-order multi-bit NS modulator.

(a) (b)
Figure 32.75 Output of the (a) multbit modulator and (b) its spectrum.

Most of the design effort, when developing multi-bit modulators, goes into the
design of the feedback DAC. Because it is nearly impossible to design highly accurate
DACs without trimming, or some sort of error correction, methods have been developed
that attempt to randomize DAC errors. If the errors appear as a random variable, they may
appear as white noise in the output spectrum and not affect the SNR of the data converter.
Figure 32.76 shows one possible implementation of a DAC that utilizes resistive
unit elements. While this figure is busy, let's attempt to explain how the DAC functions.
The DAC is based on unit-element (equal value) resistors. In one case we connect VDD to
one corner of the resistor cube and ground to the opposite corner (assuming VREF+ = VDD
and VREF− = 0). There exist two voltage dividers along each of the sides of the resistor
square. The output of the DAC can change from zero, to (1/8)VDD, to (2/8)VDD, ... up
to (8/8)VDD. Depending on the output of the decoder, one tap from each side is fed to the
analog output. Because there are two sides, the outputs from each side are combined and
effectively averaged.
The purpose of the counter is to vary the connections of VDD and ground around
the outside of the resistive divider to randomize variations in the output voltage due to
resistor mismatch. To understand this in more detail consider a constant DAC output
Chapter 32 Noise-Shaping Data Converters 217

Connected to VDD when counter output is 8

and connected to ground when counter output 0
VDD
4,12 5,13 6,14 7,15 8,0

3-bit DAC inputs 3,11 9,1

b0
Decoder

8 Analog
b1 10,2 Output
b2
2,10 11,3
Counter

Clock 16
1,9 Switch

VDD bus
0,8 15,7 14,6 13,5 12,4
Ground bus
Connected to VDD when counter output is 0
and connected to ground when counter output is 8

Figure 32.76 Implementation of a DAC for use in a multibit NS modulator.

voltage of VDD/2. As the counter changes output values, so do the connections to VDD
and ground in the resistor string. To keep a constant output voltage of VDD/2 the
switches in the center of the DAC move accordingly based on the output of the counter
and the input to the decoder. In this way variations in the resistors, hopefully, average out
to a constant value.
Multibit Demodulator (Used in a NS DAC) Implementation (Error Feedback)
The NS topologies we've discussed so far are sometimes called interpolative modulators
since the signal fed back is the average of the input signal interpolated between known
values of the modulator output (the average of the modulator outputs should be the input
signal). However, NS modulators were first introduced (see C. C. Cutler, "Transmission
systems employing quantization," 1960, U.S. Patent No. 2,927,962 [filed 1954]) using the
error feedback topology shown in Fig. 32.77. Error feedback topologies are not used in
analog input modulators because errors in the analog subtraction directly add to the input
signal. We can use this topology, however, in the implementation of a digital input
demodulator (sometimes also called a modulator), as the subtraction is digital.
218 CMOS Mixed-Signal Circuit Design

E(z)

In X(z) In Out Y(z) Out

Quantizer
F(z)
E(z)
z −1

Figure 32.77 Block diagram of an error feedback modulator.

Looking at Fig. 32.77 we note that by definition the difference between the input
and the output of the quantizer is the quantization noise, E(z). This noise is subtracted
from the input after a delay (for a first-order modulator) resulting in
Y(z) = X(z) − F(z) ⋅ E(z) + E(z) = X(z) + E(z)[1 − F(z)] (32.110)
Note that the signal transfer function for an error feedback-based modulator is simply one;
that is, STF( f ) = 1. For a first-order NS modulator we set F( z ) = z−1 (a register), which
results in
Y(z) = X(z) + E(z) ⋅ (1 − z −1 ) (32.111)
2
A second-order modulator with a NTF( f ) = (1 − z −1 ) would use a feedback filter,
noticing from Eq. (32.110) that NTF( f ) = 1 − F(z) , of
2
F(z) = 1 − (1 − z −1 ) = z −1 ⋅ (2 − z −1 ) (32.112)
Implementation of a second-order NS modulator is shown in Fig. 32.78. Note that when
trying to implement higher-order modulators using error feedback we run into the same
problem we encountered when using an interpolative modulator, namely, instability
resulting from a NTF that is too large at higher-frequencies. As with interpolative
modulators, we can design the NTF to be a highpass response.
E(z)

In X(z) In Out Y(z) Out

shift-left
Quantizer
×2
z −1
z −1

Figure 32.78 Block diagram of a second-order error feedback modulator.

Chapter 32 Noise-Shaping Data Converters 219

We've introduced the error feedback topology with the idea that it can be used in a
modulator (demodulator) that performs digital-to-analog conversion. We first introduced
a modulator for use in a DAC back in Fig. 32.12. At this point we need to answer the
question, "Why is the NS topology of Fig. 32.77 a better choice for DAC implementation,
in general, then the topologies of Figs. 32.12 and 32.71?" The answer to this comes from
the realization that the quantizer and difference block in Fig. 32.77 can be implemented by
simply removing lower bits from the digital input words. This is illustrated in Fig. 32.79.
The resulting error feedback modulator will be simpler to implement than the modulators
based on interpolative topologies. Figure 32.80 shows Fig. 32.77 redrawn to show the
simpler implementation.

E(z)

N bits In Out Y(z) Out

N bits N − F bits Y(z)
N − F bits
Quantizer
F bits

F bits This is implemented using

Figure 32.79 Showing how quantizer and difference block are implemented.

The number of bits used in the modulator, N, is selected to avoid overflow when
the maximum input signal and fed-back signal are subtracted. When using two's
complement numbers, the words input to the adder must be the same length. The smaller
word's MSB is used to increase the smaller word's size until the word lengths match. We'll
comment more on this important concern in a moment.

In X(z) N bits Y(z) Out

N − F bits
F(z) F bits

Figure 32.80 Block diagram of an error feedback modulator.

Figure 32.81 shows the block diagram of an NS-based DAC. As we saw in Fig.
32.11, if a 1-bit output is used, the modulator can be connected directly to the
reconstruction filter (RCF). The 1-bit DAC is perfectly linear so distortion concerns are
reduced. Using a multibit modulator and DAC gives a better SNR, for a given
oversampling ratio and modulator order, as well as easing the requirements placed on the
RCF. The drawback, as discussed earlier, is that the DAC must be accurate to the final
desired output resolution since it is in series with the output signal path.
220 CMOS Mixed-Signal Circuit Design

Interpolation filter
Digital input Digital Analog output
NS (de)modulator DAC RCF
filter

Figure 32.81 DAC using a NS modulator and digital filter.

Let's comment on how to estimate the quantization noise added to the signal from
the error feedback quantization process. Assuming we are using two's complement
numbers we know
1 LSB
N bits
V REF+ − V REF−
0111111... = V REF+ − (32.113)
2N
and
1000000... = V REF− (32.114)
For the DAC to function properly we must change the numbers back to binary offset
(complement the left-most or most-significant bit) unless the DAC input uses two's
complement format. This is easy to see if the output of the modulator is a single bit
(N − F = 1) since an MSB of 1 = V REF+ and a 0 = V REF− where V LSB = V REF+ − V REF− . By
dropping F bits the voltage weighting of an LSB in the modulator output can be written as
V REF+ − V REF−
V LSB = if N − F > 1 (32.115)
2 N−F
(See question 30.14 or Ex. 35.21 for further discussions.) This result is used in Eq. (32.8)
to estimate the quantization noise spectrum in a NS modulator.
Implementation Concerns
We know from our discussions in the last chapter that most digital additions and
subtractions utilize two's complement numbers because of the simplicity (see Fig. 31.55
and the associated discussion) in implementing the hardware. However, consider the two's
complement N-bit input in Fig. 32.79. If we drop the lower F bits, the resulting number
fed back to F(z) (the quantization noise) is not in two's complement format.
To circumvent these types of problems, the topology shown in Fig. 32.82 can be
used. The input to the quantizer/subtractor is changed from two's complement format into
binary offset format. (See Figs. 31.36 and 31.37 for a comparison of the formats.)
Quantization is then performed; the lower bits are dropped from the output and fed back.
The fed-back word (the quantization error) is then changed from a binary offset number
back into a two's complement number. The size of the word fed back is adjusted to match
the size of the modulator's input (knowing that the words used in two's complement
arithmetic must be the same size so that the sign bit is in the same location in each word,
see also Fig. 31.55).
Chapter 32 Noise-Shaping Data Converters 221

MSB
N bits N bits N − F bits Y(z)
In
Two's complement Binary offset Binary offset
select MSB
Two's complement 1 0000... F bits
MUX
0 1111... Binary offset

Adjust, using the MUX, the output word size so that

it matches the modulator's input word size. The adder,
on the input of the modulator, should see the same size words.

Figure 32.82 Implementation of the quantizer and difference blocks.

32.2.3 Cascaded Modulators

The NS modulators discussed up to this point, in this chapter, have been single feedback
loop topologies with the general form seen in Fig. 31.81. This includes the higher order
topologies discussed in Sec. 32.2.1 and the error-feedback topologies of the last section.
In this section we discuss cascaded or multistage NS modulators. The cascaded
modulators discussed here are sometimes called MultistAge noise SHaping or MASH
modulators. While our focus in this section is on modulators for ADCs, it is easy to
extend the theory developed to modulators used in DACs.
We indicated, in the last section, that feeding back the quantization noise, E(z), to
the input isn't practical in analog implementations of NS modulators. The output of the
analog subtraction (E[z]) would be added directly to the input signal. Instead of feeding
E(z) back to the input, cascaded modulators feed it forward to the input of another
modulator. The second modulator's output is then a delayed version of E(z) as well as its
own unwanted modulation noise. If this output is subtracted from the output of the first
modulator, we can effectively reduce the resulting overall quantization noise.
The major benefit of a cascaded topology is stability. Unconditionally stable first-
and second-order loops can be cascaded to implement higher order modulators. In
addition, as we'll briefly discuss, modulators consisting of a first-stage modulator using a
1-bit ADC and DAC followed by a multibit modulator can provide reasonable resolutions
with low oversampling ratio K.
Second-Order (1-1) Modulators
A second-order NS modulator can be implemented using a cascade of two first-order
modulators (called a 1-1 modulator), as seen in Fig. 32.83. The output of the first
modulator is given by
Y 1 (z) = z −1 X(z) + (1 − z −1 )E 1 (z) (32.116)
222 CMOS Mixed-Signal Circuit Design

E 1 (z)

In X(z) z −1 O 1 (z) Y 1 (z)

1 − z −1 z −1
Delay
Out
− E 1 (z) Y(z)
E 2 (z)

− E 1 (z) z −1 Y 2 (z)
1 − z −1
1 − z −1
Differentiator
see Fig. 31.51

Figure 32.83 Second-order (1-1) cascaded modulator.

while the output of the second modulator is

Y 2 (z) = −z −1 E 1 (z) + (1 − z −1 )E 2 (z) (32.117)
The overall modulator output is given by
Y(z) = z −1 Y 1 (z) + (1 − z −1 )Y 2 (z)
2
= z −2 X(z) + z −1 (1 − z −1 )E 1 (z) − z −1 (1 − z −1 )E 1 (z) + (1 − z −1 ) E 2 (z)
= z −2 X(z) + (1 − z −1 ) 2 E 2 (z) (32.118)
Note how the second modulator is used to subtract the first's quantization noise, E1(z),
from the final output. If all of the components are ideal, the resulting modulator has
second-order noise shaping. In practice, however, the coefficients of E1(z) in Eq. (32.118)
will not exactly cancel. When this occurs, E1(z) is said to leak to the output of the
modulator. Differences in the coefficients are caused by gain errors in the first modulator's
analog integrator when compared to the output of the digital differentiator.
Let's attempt to characterize the performance of the 1-1 modulator if the
integrators have gain coefficients, GI , other than one as seen in Fig. 32.36. We can write
the output of the first modulator's integrator in Fig. 32.83 as
G I1 ⋅ z −1 G I1 ⋅ z −1
O 1 (z) = ⋅ X(z) − ⋅ E 1 (z) (32.119)
1 + (G F − 1)z −1 1 + (G F − 1)z −1
Using Eq. (32.39) with this equation we can write
(G F − G I1 ) ⋅ z −1 1 − (1 − G I1 ) ⋅ z −1
E 1out (z) = Y 1 (z) − O 1 (z) = ⋅ X(z) + ⋅ E 1 (z) (32.120)
1 + (G F − 1)z −1 1 + (G F − 1)z −1
Chapter 32 Noise-Shaping Data Converters 223

where, ideally, the output quantization noise of the first modulator, E1out(z) , is E1(z). If the
modulator is functioning properly, then GF = 1 independent of GI as discussed earlier.
Equation (32.120) can then be written as
E 1out (z) = (1 − G I1 ) ⋅ z −1 ⋅ X(z) + [1 − (1 − G I1 ) ⋅ z −1 ] ⋅ E 1 (z) (32.121)
Using this equation in Eq. (32.117) while assuming the second modulator uses an
integrator scaling factor, GI2, and GF2 is one results in (rewriting Eq. [32.118])
2
Y(z) = z −2 X(z) + z −1 (1 − z −1 )E 1 (z) − z −1 (1 − z −1 )E 1out (z) + (1 − z −1 ) E 2 (z)
Desired output Unwanted term
−1 2
= z X(z) + (1 − z ) E 2 (z) + [E 1 (z) − X(z)] ⋅ z −2 (1 − z −1 ) ⋅ (1 − G I1 )
−2
(32.122)
While we can set the second modulator's integrator gain coefficient, GI2, to 0.4 to avoid
integrator saturation, as discussed earlier, we must set GI1 as close to unity as possible.
Using a unity gain coefficient results in a reduction in the modulator's overall dynamic
range (see Fig. 32.35 and the associated discussion). Note how the input signal appears in
the unwanted term in Eq. (32.122). It should be obvious at this point that we can add
scaling parameters at various points in the modulator to attempt to maximize the
modulator's dynamic range. Also note how the number of bits in the 1-1 modulator's
output will be more than one bit (two bits if comparators are used in each first-order
modulator).
Third-Order (1-1-1) Modulators
By adding a third first-order modulator to our 1-1 modulator of Fig. 32.83 we get a 1-1-1
or third order modulator, Fig. 32.84. The output of the added third modulator can be
written as
Y 3 (z) = −z −1 E 2 (z) + (1 − z −1 )E 3 (z) (32.123)
while the ideal output of the 1-1-1 cascade is given by
3
Y(z) = Y 1 (z) + Y 2 (z) + Y 3 (z) = z −3 X(z) + (1 − z −1 ) E 3 (z) (32.124)
Again, as we saw in Eq. (32.122), noise from the first modulator can leak through to the
output and spoil the overall cascade's SNR. Indeed, if the leakage from the first modulator
is large enough, we get no benefit from adding the third modulator. Notice, in Eq.
(32.122), that the unwanted term exhibits first-order differentiation, (1 − z −1 ) . We might
expect better overall performance, that is, less leakage if the first modulator is second
order. The unwanted term would then exhibit second-order differentiation.
Third-Order (2-1) Modulators
A third-order modulator formed by using a second-order modulator followed by a first-
order modulator is shown in Fig. 32.85. The output of the first modulator is given by
2
Y 1 (z) = z −1 X(z) + (1 − z −1 ) E 1 (z) (32.125)
224 CMOS Mixed-Signal Circuit Design

E 1 (z) Y 1 (z) = O 1 (z) + E 1 (z)

In X(z) z −1 O 1 (z) Y 1 (z)

1 − z −1 z −2

Out
Y(z)
E 2 (z)
− E 1 (z)
z −1 Y 2 (z)
1 − z −1 z −1 (1 − z −1 )

E 3 (z)

− E 2 (z)
z −1 Y 3 (z) 2
(1 − z −1 )
1 − z −1

Figure 32.84 Third-order (1-1-1) cascaded modulator.

E 1 (z)

In 1 z −1 O 1 (z) Y 1 (z)
z −1
X(z) 1 − z −1 1 − z −1

Out
Y(z)
E 2 (z)
− E 1 (z)
z −1 Y 2 (z) 2
(1 − z −1 )
1 − z −1

Figure 32.85 Third-order (2-1) cascaded modulator.

Chapter 32 Noise-Shaping Data Converters 225

while the output of the second modulator is

Y 2 (z) = −z −1 E 1 (z) + (1 − z −1 )E 2 (z) (32.126)
The output of the 2-1 modulator is then, ideally,
2 3
Y(z) = Y 1 (z)z −1 + (1 − z −1 ) Y 2 (z) = z −2 X(z) + (1 − z −1 ) E 2 (z) (32.127)
Let's attempt to characterize the leakage to the output by first determining the
output of the second integrator O1(z) (the input to the comparator). We'll use the topology
shown in Fig. 32.58, with G3 = 1, to define our gains. The output, O1(z), is (assuming that
GF = G1G2Gc = 1 )
G 1 G 2 ⋅ z −1 X(z) − [(G 1 G 2 + G 2 ) − G 2 z −1 ] ⋅ z −1 E 1 (z)
O 1 (z) = (32.128)
1 + z −1 ⋅ (G 2 G c − 1) + z −2 (1 − G 2 G c )
Again writing the input to the second modulator as (using Eq. [32.75])
E 1out (z) = Y 1 (z) − O 1 (z)
(1 − G 1 G 2 ) ⋅ z −1 X(z) +  (1 − z −1 ) 2 + (G 1 G 2 + G 2 ) ⋅ z −1 − G 2 z −2  E 1 (z)
= (32.129)
1 + z −1 ⋅ (G 2 G c − 1) + z −2 (1 − G 2 G c )
noting that if G 1 = G 2 = G c = 1 then E 1out (z) = E 1 (z) . If we write the output of the
cascade as
3
Y(z) = z −2 X(z) + z −1 (1 − z −1 ) 2 E 1 (z) − z −1 (1 − z −1 ) 2 E 1out (z) + (1 − z −1 ) E 2 (z) (32.130)
then
Desired output

3
Y(z) = z −2 X(z) + (1 − z −1 ) E 2 (z) +
Undesired term
−1 −1 2 
(1 − G 1 G 2 ) ⋅ z −1 X(z) + [(1 − G 2 ) − (G 2 G c − G 2 )z −1 ] ⋅ z −1 E 1 (z) 
z (1 − z )  
 1 + z −1 ⋅ (G 2 G c − 1) + z −2 (1 − G 2 G c ) 
(32.131)
When this equation is compared to Eq. (32.122), we see that the undesired term is second-
order differentiated. Also, we have more control over the integrator gains. Third-order
modulators using the 2-1 topology are much more robust than the 1-1-1-based topology
and can provide output signals free of unwanted tones. Again, if integrator saturation (and
thus dynamic range) isn't a concern, then we can set G 1 = G 2 = 1 .
One of the interesting uses of the 2-1 modulator is the configuration where the first
(second-order) modulator utilizes a 1-bit ADC and DAC, while the second (first-order)
modulator utilizes a multibit ADC and DAC. The overall linearity of this topology is
dominated by the second-order modulator, while the multibit modulator provides an
enhancement in dynamic range for a given oversampling ratio. These very interesting, and
potentially ubiquitous, data converters are discussed in greater detail in Ch. 7 of [2].
226 CMOS Mixed-Signal Circuit Design

Implementing the Additional Summing Input

Before leaving our introduction to cascaded converters, let's discuss the implementation of
the extra summing block used to generate the quantization noise, E(z). Figure 32.86
shows the topology of the two summing blocks and how they can be combined.

O 1 (z) Y 1 (z) = O 1 (z) + E 1 (z)

Y 1 (z) O 1 (z)
− E 1 (z)
Y 1 (z)
Out
Out to integrator
Y 2 (z)
Y 2 (z)

Figure 32.86 Showing implementation of the dual summing block as a single block.

One way to implement the extra subtracting input and the integrator is shown in
Fig. 32.87. This DAI is a modification of the DAI shown in Fig. 32.59. The output of this
integrator is related to the inputs by
C I2 z −1/2 C 1 C 1
V out (z) = O 1 (z) ⋅ ⋅ − Y 2 (z) ⋅ I2 ⋅ − Y 1 (z) ⋅ I22 ⋅ (32.132)
C F2 1 − z −1 C F2 1 − z −1 C F2 1 − z −1
If we set CI2 = CI22 = CF2 and we realize that the comparator in the second modulator,
assuming it is clocked with the rising edge of φ 1 (or the falling edge of φ 2 ), adds a
half-clock cycle delay in series with the Y1(z) input and a full clock cycle delay in series
with O1(z) and Y2(z), then we can write
−1
V out (z) = [O 1 (z) − Y 1 (z) − Y 2 (z)] ⋅ z −1 (32.133)
1−z
Figure 32.88 shows the implementation of a 2-1 modulator.
C F2
φ1 φ2
V CM

C I2 V CM V out (z)
O 1 (z)
V CM C I22 Y 2 (z)

Y 1 (z)

Figure 32.87 Implementing the dual summing block for a cascaded modulator.
Chapter 32 Noise-Shaping Data Converters 227

φ1 φ2 φ1
φ2 φ1
Y 1 (z)

V in

φ1 φ2 φ1

Y 2 (z)
O 1 (z)

Y 1 (z)

Figure 32.88 Implementation of a 2-1 NS modulator.

We could also use the topology shown in Fig. 32.89 to implement the summing
block of Fig. 32.86. This topology has the benefit of using a single capacitor for a simpler
circuit and no matching differences between CI2 and CI22 . Unfortunately, as discussed in
Ch. 27, the topology is no longer insensitive to the parasitic capacitance on the top plate
of the switched capacitor. In the parasitic insensitive topologies, Fig. 32.87 for example,
the top plate of the capacitor is always held at the common-mode voltage, VCM. In the
topology of Fig. 32.89 the top plate is charged to y1(t) when the φ 1 switches are closed
and discharged to VCM when the φ 2 switches are closed. The difference between these
voltages combined with the value of the unwanted parasitic capacitance to ground on the
top plate causes unwanted charge to transfer to the feedback capacitor and a gain error.
This by itself isn't too bad. However, the unwanted capacitance can have a large depletion
capacitance component, resulting in a voltage-dependent capacitance and thus nonlinear
gain. Nevertheless, in some applications this topology may still prove useful.

φ1 φ2

Y 1 (z)
V out (z)
V CM
O 1 (z)

Y 2 (z)

Figure 32.89 Implementing the dual summing block with a single capacitor
results in sensitivity to the top plate parasitic capacitance.
228 CMOS Mixed-Signal Circuit Design

32.2.4 Bandpass Modulators

The modulators we've discussed so far in this chapter have been lowpass topologies; that
is, the desired signal resides from DC to B. In this section we briefly discuss the idea that
we can perform data conversion on a range of frequencies that doesn't include DC. A
bandpass modulator is one that pushes the modulation noise away from some desired
bandwidth of interest.
In Sec. 31.2.4 we discussed the idea that we can implement a sinc-shaped
averaging bandpass filter centered around fs /4 (or fs /6) having a transfer function of
−K
H(z) = 1 − z −2 (32.134)
1+z
Comparing this equation to the equation for the equivalent lowpass averaging filter, Eq.
(31.99), we can see that transforming our low pass modulator topologies into bandpass
modulator topologies with bandpass responses centered at fs /4 can be accomplished by
Substituting z −2 for −z −1 (32.135)
Figure 32.90 shows the result of a lowpass second-order modulator transformed into a
fourth-order bandpass modulator. It's now called a fourth-order modulator because the
number of poles in the NTF is now four. The transfer function for this, fs /4, bandpass
modulator is
STF NTF

Y(z) = X(z)⋅(−z −2 ) + E(z)⋅(1 + z −2 )

2
(32.136)
Writing the modulation noise for a bandpass modulator results in
4
V 2LSB  f
NTF( f ) 2 ⋅ V Qe ( f ) 2 = ⋅  2 cos 2π  (32.137)
12f s  fs 

E(z)

X(z) 1 −z −2 Y(z)
G1 G2 Out
1 + z −2 1 + z −2

Figure 32.90 Block diagram of a fourth-order bandpass modulator.

Chapter 32 Noise-Shaping Data Converters 229

Figure 32.91 shows the modulation noise spectrum of a fourth-order modulator, Eq.
(32.127). Notice how, at fs /4, the modulation noise goes to zero. The oversampling ratio
is, once again, defined as
fs
K= (32.138)
2B
If fs /4 = 25 MHz and the desired bandwidth is 50 kHz, then K = 1,000.

V 2 /Hz

f s /4 f s = 100 MHz
Figure 32.91 Modulation noise in a bandpass modulator.

Implementing a Bandpass Modulator

Toward implementing a bandpass modulator, consider the circuit shown in Fig. 32.92. The
top portion of the circuit is simply the DAI discussed in Sec. 31.3.1. The bottom portion
provides the positive feedback needed for the addition (instead of subtraction) of the
delayed output. We've adjusted the values of the capacitors so that the resulting transfer
function of the DAI is (see question 31.51 in the last chapter)
V1 (z) ⋅ z −1/2 − V 2 (z) C I
V out (z) = ⋅ (32.139)
1 + z −1 CF
To change the denominator in this equation to 1 + z −2 , we can use a clocking frequency of
f
j2π⋅
fs,new = 2fs, effectively changing the z−1 to z−2 where z is still e f s . In most practical
implementations fully-differential integrators are used [6]. The inverting block in Fig.
32.92 is implemented with the inverting output of the fully-differential op-amp.
230 CMOS Mixed-Signal Circuit Design

CF
φ1 φ2
V CM

CI V out (z)
V CM
V 1 (z)

V 2 (z)

V CM

2C F V CM
−V out (z)
1

Figure 32.92 Implementing a DAI for use in a bandpass modulator.

In a bandpass modulators 1/f noise isn't a concern since it is filtered out with the
digital filter. If the modulator is used in a wireless application where the intermediate
frequency (IF) is fs /4, extracting the real (I, or in-phase component) and imaginary (Q, or
quadrature component) becomes trivial (see Fig. 32.93). Since a single modulator is used,
and the I/Q extraction is digital, the channel mismatch encountered in typical baseband
demodulators is absent.
We might wonder, after looking at this figure, how we multiply the modulator
output, a 1-bit word, by 1, 0, and −1. We know that a 1 coming out of the modulator
corresponds to VREF+ and a 0 corresponds to VREF−. After reviewing Fig. 31.37 in the last

fs cos 2πf IF ⋅ nT s = cos n π = 1, 0, −1, 0...

Centered at f IF = 2
4

LPF I output
IF Bandpass
Multipliers
In modulator

LPF Q output
f s = 4 ⋅ f IF

sin 2πf IF ⋅ nT s = sin n π = 0, 1, 0, −1...

2

Figure 32.93 Digital I/Q demodulation.

Chapter 32 Noise-Shaping Data Converters 231

chapter, we can convert these 1-bit outputs to 2-bit words in two's complement format. A
1 output is changed to 01 (+1) and a modulator output of 0 becomes 11 (−1) in two's
complement prior to multiplication. Multiplication results in 01 × 1 = 01, 01 × 0 = 00, 01
× −1 = 11, 11 × 1 = 11, 11 × 0 = 00, or 11 × −1 = 01. A simple MUX with some logic for
output selection can be used to implement the multiplier.
REFERENCES
[1] J. C. Candy and G. C. Temes (eds.), Oversampling Delta-Sigma Data Converters,
IEEE Press, 1992. ISBN 0-87942-285-8
[2] S. R. Norsworthy, R. Schreier, and G. C. Temes (eds.), Delta-Sigma Data
Converters: Theory, Design, and Simulation, IEEE Press, 1996. ISBN
0-7803-1045-4
[3] R. K. Hester, Introduction to Oversampled Data Conversion, Notes from a
tutorial at the 1995 International Solid-State Circuits Conference (ISSCC-95).
[4] P. A. Lynn and W. Fuerst, Introductory Digital Signal Processing, Second
Edition, John Wiley and Sons, 1998. ISBN 0-471-97631-8
[5] E. P. Cunningham, Digital Filtering: An Introduction, John Wiley and Sons, 1995.
ISBN 0-471-12475-3
[6] A. K. Ong, and B. A. Wooley, "A Two-Path Bandpass SD Modulator for Digital
IF Extraction at 20 MHz," IEEE Journal of Solid-State Circuits, Vol. 32, No. 12,
pp. 1920-1934, December 1997.
QUESTIONS
32.1 Show the details and assumptions leading to Eq. (32.1).
32.2 Would it be possible to operate the DAI of Fig. 32.3 without a 0.75 V supply?
Give an example. Show simulation results with the output initially at 0.75 V and
the same input used to generate Fig. 32.4. Are the DAI outputs the same?
32.3 Show the derivation of Eq. (32.4) from the block diagram shown in Fig. 32.6.
32.4 In the basic NS modulator shown in Fig. 32.7, what component serves as the
ADC? What component serves as the DAC?
32.5 Show, using timing diagrams, how Eq. (32.5) is correct.
32.6 Show, using SPICE simulations, how increasing the RC circuit's time constant in
Fig. 32.10 removes additional modulation noise making the output smoother.
What happens to the amplitude of the desired signal?
32.7 Show the spectrums (modulator input, output, and output after filtering) of the
signals in question 32.6. Discuss what the spectrums indicate.
32.8 Explain how the quantizer in Fig. 32.12 functions.
232 CMOS Mixed-Signal Circuit Design

32.9 What are we assuming about an input signal if the modulation noise follows Eq.
(32.7)?
32.10 What is the magnitude of Eq. (32.7)?
32.11 What is the difference between quantization noise and modulation noise?
32.12 Show the steps and assumptions leading to Eq. (32.15)?
32.13 Is the statement that on page 163 that "every doubling in the oversampling ratio
results in 1.5 bits increase in resolution" really true if K is small (say 8 or 16)?
Explain.
32.14 Does noise-shaping work for DC input signals? If so, how?
32.15 Show the steps leading up to Eq. (32.25).
32.16 What is the impulse response of the following z-domain transfer function?
−16 2
H(z) =  1 − z −1 
 1−z 

32.17 Regenerate Fig. 32.23 if L = 3. What is the droop at B?

32.18 Is it possible to eliminate the op-amp in Fig. 32.24 and use the following topology?
Comment on the problems associated with this topology.

R φ

R V CM
V in V out
C

−V out

Figure 32.94 First-order NS modulator for question 32.18.

32.19 Simulate the operation of the circuit shown in Fig. 32.94.

32.20 Sketch a modulator output, similar to Fig. 32.27, if the input is 0.2 V.
32.21 In your own words, describe ripple in the output of a digital filter connected to an
NS modulator.
32.22 Does adding a dither signal to the input of a NS modulator help reduce the
peak-to-peak ripple in the digital filter output? Does it help to break up tones in
the filter's output?
32.23 Derive Eq. (32.39).
Chapter 32 Noise-Shaping Data Converters 233

32.24 Repeat Ex. 32.11 if the integrator's gain is set to 0.5.

32.25 Verify that Eq. 32.43 is correct. Use pictures if needed.
32.26 Would large parasitic op-amp input capacitance affect the settling time of a DAI?
32.27 Determine the transfer function of the DAI shown in Fig. 32.43.
32.28 Derive Eq. (32.65).
32.29 Sketch the implementation of the full-differential second-order NS modulator.
32.30 Derive Eq. (32.75)
32.31 Sketch the fully-differential equivalent of Fig. 32.59.
32.32 Resimulate the modulator in Ex. 32.13 if the gains are set to one. Comment on the
stability of the resulting circuit.
32.33 Resimulate the modulator in Ex. 32.13 if the input is only 50 mV. Comment on the
stability of the resulting circuit.
32.34 Regenerate Fig. 32.67 by selecting integrator gains so that the maximum output
swing of any op-amp is 1.3 V.
32.35 Comment, in your own words, on why the actual SNR of a NS-based data
converter can be worse than the ideal values calculated in the chapter.
32.36 Derive Eq. (32.91). Make sure each step of the derivation includes comments.
32.37 Resimulate Fig. 32.74 using two-bit ADC and DAC.
32.38 Sketch a possible implementation of a quantizer for the error feedback modulator
shown in Fig. 32.78.
32.39 What transfer function does the following block diagram implement?

shift left
×2
X(z) z −2 Y(z)

z −1

Figure 32.95 Circuit for Question 32.39.

32.40 In Fig. 32.84 sketch the block diagram implementation of the circuit in series with
the Y2(z) output.
2
32.41 Sketch the block diagram implementation of the transfer function (1 − z −2 ) . What
kind of filter does this transfer function implement?
234 CMOS Mixed-Signal Circuit Design

32.42 Sketch the implementation of the multipliers in Fig. 32.93.

32.43 Would clock jitter be a concern in a bandpass modulator? (Hint: Review Fig. 31.14
in the last chapter and the associated discussion.)
 Chapter

33
Submicron CMOS Circuit Design

In this chapter we turn our attention toward transistor-level circuit design using a
submicron CMOS process, that is, a CMOS process with a minimum channel length, Lmin,
less than 1 µm. We divide the chapter up into three sections. The first section covers basic
submicron CMOS processes and device models. The second and third sections provide
digital and analog circuit design examples and discussions, respectively. We assume
throughout the chapter, that the reader is well grounded in the material presented in
CMOS: Circuit Design, Layout, and Simulation [1] (the first CMOS book).
Before getting too far into this chapter, let's discuss how we distinguish the
material presented here from the material presented in the first CMOS book. If we recall,
in the first CMOS book, an older CMOS process was used to illustrate the fundamental
design ideas, methods, and procedures and to provide practical models for comparing
hand-calculations and simulation results. The older CMOS devices followed the
"square-law" MOSFET model. While one can argue that the older CMOS processes will
never be obsolete because of their inherent higher voltage handling capability (a modern
CMOS process generally limits VDD, with VSS = 0, to between 1 and 3.3 V), this isn't the
main reason for using them to illustrate design fundamentals. The main reason comes from
the fact that hand-calculation parameters (transconductance and output resistance, for
example) are derived from the SPICE level 1 square-law model. An older MOSFET that
can then be modeled relatively well using the level 1 model yields simulation results that
match hand-calculations and provides immediate feedback to the designer that "I know
what I'm doing." The level 1 model can accurately model devices with an Lmin > 5 µm.
Reasonable hand-calculation accuracy, say within 20%, can be achieved in a process with
Lmin between 1 and 5 µm (in any case, though, the most accurate SPICE MOSFET model
available should be used). However, if hand-calculations, based on the level 1 square-law
model, are used in a submicron CMOS process, the error is generally well above 100%!
As an example, Fig. 33.1a shows an IV plot of a typical 0.5 µm (= Lmin ) NMOS transistor,
while Fig. 33.1b shows the level 1 SPICE results.
236 CMOS Mixed-Signal Circuit Design

ID ID

V GS = 3 V V GS = 3 V

(a)
V DS (b) V DS
L = 0.5 µm and W = 3 µm
Figure 33.1 (a) IV characteristics of a submicron MOSFET, and (b) its level 1
SPICE representation.

Looking at Fig. 33.1, we should make several key observations. To begin, notice
how the drain current, ID , varies as the square of the gate-source voltage, VGS , in the level
1 model (b), while the variation in the actual curves (a) is more or less linear with VGS.
Next, notice how the point the MOSFET enters the saturation region, VDS,sat , is defined by
VGS − VTHN (the gate-source voltage minus the NMOS threshold voltage) in the level 1
model (b). This, as was discussed in Chs. 5 and 6, results in an overestimate of VDS,sat and is
one reason body-effect is neglected so often in DC hand-calculations. Finally, notice how
the slope of the curves, when the MOSFET is operating in the saturation region, is larger
in (b) then in (a). We know that the small-signal output resistance of the MOSFET is the
reciprocal of this slope. Further then, we would expect the level 1 model to provide lower
values of gain in simulations than a model that more exactly matches part (a).

33.1 Submicron CMOS: Overview and Models

In this section we discuss the CMOS process flow [2] for devices with Lmin less than 0.35
µm, implementation of capacitors and resistors, and lastly the EKV MOSFET model [3-5]
and why we'll use this model to illustrate circuit design techniques in this book.
33.1.1 CMOS Process Flow
Figure 33.2 shows the basic CMOS process flow for a sub-0.35 µm process. This process
flow illustrates the differences between a submicron process and the older process flows
discussed in Chs. 2−4. In particular, (1) shallow trench isolation (STI) is used instead of
the local oxidation of silicon (LOCOS) for device isolation, (2) n+ poly is used for NMOS
formation while p+ poly is used in PMOS formation, (3) lightly doped drains are used to
reduce short channel effects, (4) silicided source/drains/gates are used to reduce parasitic
resistances, and (5) both devices are surface devices (the PMOS is no longer a buried
channel device).
We can summarize the process steps, shown in Fig. 33.2, as follows:
Chapter 33 Submicron CMOS Circuit Design 237

Part (a) starts with a p-type wafer or a p+ wafer with a p− epitaxial layer as
discussed in Ch. 2. The active areas are patterned by first depositing a thin oxide and a
nitride. A photoresist is deposited and patterned on the top of the nitride. The exposed
areas of nitride are removed
Part (b) shows the result of etching down into the silicon areas that are exposed,
that is, those not covered with the photoresist (or nitride after the nitride is etched off).
Part (c) shows the cross-section of the wafer after a thick oxide has been deposited
over the entire wafer and the top of the wafer has undergone polishing using chemical-
mechanical polishing (CMP). Notice how the top of the wafer is flat. Also notice the
shallow trenches are filled with a chemical vapor deposited (CVD) oxide (called STI).
STI is used in place of LOCOS because of the ability to define smaller openings in the
top of the wafer (smaller active area windows). The effective encroachment on the
devices' width is reduced and the MOSFETs can be placed closer together.
Part (d) shows the implant used for making the body of the PMOS transistors (the
n-well) and the implants used to adjust the threshold voltage.
Part (e), at the top of the next page, shows the result of patterning the polysilicon
gates on the top of the wafer.

Nitride
Pad oxide
Photoresist (after patterning)
p-type (a)

After etching
p-type (b)

STI STI STI

Isolation
p-type (c)

STI STI STI

p-doping n-well Implants
Threshold voltage implant n-doping p-type (d)

Figure 33.2 CMOS process flow.

238 CMOS Mixed-Signal Circuit Design

Undoped polysilicon

STI STI STI Gate oxide

n-well w/ nitride
Threshold voltage implant not shown p-type (e)

STI STI STI

n- implant LDD implant
p- implant p-type (f)

n+ p+
STI n+ n+ STI p+ p+ STI
n+/p+ implants
p-type (g)

silicide p+
n+
STI STI STI
Add silicide
NMOS
PMOS (h)
p-type

Figure 33.2 (cont'd) CMOS process flow.

In part (f) light, and shallow, implants are shown which are used in lightly doped
drain, or LDD, MOSFET formation.
Part (g) shows formation of the lateral oxide spacer adjacent to the gate poly (used
for LDD MOSFET formation) and the results of using implants to heavily dope the
gates, sources and drains. Implanting the gate polysilicon is important. The p+ poly
used in the PMOS formation here results in a surface device (conduction between the
drain and source occurs along the oxide/semiconductor interface) rather than a buried
device (conduction occurs through a buried channel). The threshold voltage of the
PMOS is easier to set precisely (because we don't have to counter dope the channel)
and the short channel effects become less severe. The drawbacks of switching from a
buried-channel PMOS to a surface-channel PMOS are the reduction in mobility and the
increase in flicker (1/f ) noise.
Finally, part (h) shows the cross-sectional view of the resulting NMOS and PMOS
devices after a silicide (combination of silicon and a refractory metal such as tungsten)
has been deposited. The addition of the silicide complicates the process but produces
devices that have significantly less parasitic series gate and source/drain resistance.
Chapter 33 Submicron CMOS Circuit Design 239

33.1.2 Capacitors and Resistors

As we saw in the last chapter, capacitors are an important component when implementing
a mixed-signal integrated circuit (IC). In this section we briefly discuss implementing
capacitors and resistors in a submicron CMOS process. While in some of these processes
(for example, a flash memory process) two layers of poly are available for capacitor
formation, here we assume that poly-poly capacitors (discussed in Ch. 7) are not available.
Using a MOSFET as a Capacitor
Figure 33.3 shows the CV curve for an NMOS transistor with source, drain, and body
connected to ground. We might try to use this device in one of the discrete-analog-
integrators (DAIs) of the last chapter. However, the capacitors used in the DAI are
"bipolar" (the voltage across them can be positive or negative). We see in the Fig. 33.3
that VGS should be much greater than 400 mV (the threshold voltage) for the device to
behave as a capacitor. If VGS falls close to the knee slightly above VTHN, then the
capacitance can become nonlinear and distortion can appear in a circuit's output. Note that
this curve shifts to the right with a nonzero VSB.

Cg
ε ox
C ox = Cg
t ox
Accumulation Strong inversion
Depletion

VX 400 mV = V THN VG

Figure 33.3 Using a MOSFET as a capacitor.

Using a Native or Natural MOSFET Capacitor

Figure 33.4 shows the layout, CV curves, and schematic symbol of the native, or also
sometimes called the natural, MOSFET capacitor. The native MOSFET capacitor is
formed by laying out poly over n+ active in an n-well. The result is a shift in the
MOSFET's threshold voltage, VTHN. While the native MOSFET still cannot be used as a
bipolar capacitor, it does find uses in many applications where low voltages are a concern.
Note that we might be tempted to use this MOSFET in an amplifier (not as a
capacitor) as a near-depletion mode device. However, since the source and drain are
shorted together through the resistive n-well, the resulting device may not be too useful.
The Floating MOS Capacitor
A novel method of implementing a capacitor using regular PMOS transistors is shown in
Fig. 33.5 [6]. Two PMOS devices are laid out either adjacent or interdigitated in the same
n-well. For the moment let's not concern ourselves with the exact voltage of the n-well,
240 CMOS Mixed-Signal Circuit Design

poly
n+ active

n-well
(a) Layout view

n+
STI n+ n+ STI
n-well
p-type

(b) Cross-sectional view

Cg
ε ox Cg
C ox =
t ox

100 mV VG

(c) CV curves for the native MOSFET

Figure 33.4 The native or natural MOSFET.

but rather assume that the capacitor and resistor time constant is so large compared to the
signal frequencies of interest that little charge, ideally zero on average, flows in the big
resistor. An increase in voltage on A, in the figure, will cause an accumulation of charge
under the left MOSFET's gate oxide. At the same time an equal and opposite charge will
appear under the right MOSFET's gate oxide. The result is that the charge accumulated on
B will be equal and opposite to the charge accumulated on A. Since the capacitors are in
series the overall capacitance seen between A and B, CAB is the series connection of each
MOSFET's own gate-oxide capacitance as seen in the figure.
VA
VDD A B

C AB = C ox /2 C AB = C ox WL/2 = C ox /2
Big (assuming each MOSFET
C AB < C ox /2 resistor is the same size)
VX
VB
VX VDD
Figure 33.5 A floating MOS capacitor.
Chapter 33 Submicron CMOS Circuit Design 241

To implement the big resistor in Fig. 33.5, a topology like the one seen in Fig. 33.6
can be used [6]. The long L PMOS device is used to generate a very small current. This
current is mirrored across and used to hold the n-well and p+ active areas at ground (on
average). Because the current is so small, the actual voltages seen in the n-well and active
areas can be considerably different than ground over short periods of time allowing the
capacitor action discussed above to occur. Finally, notice that the MOSFETs used in the
capacitor operate in accumulation as long as the voltage on either side of the capacitor is
greater than VX. For the PMOS equivalent of Fig. 33.3, VX is positive and VTHP is negative
with the source/drain and body grounded.

VDD

Long L Floating capacitor

Very small current

Figure 33.6 Implementing a large resistor for the floating MOS capacitor.

Metal Capacitors
Probably the most common method of making capacitors in a submicron CMOS process is
using the metal layers. Consider the cross-sectional view of a parallel plate capacitor
shown in Fig. 33.7. If the plate capacitance between the metal1 and metal2 dominates
because the metals have a large layout area (that is, the fringe capacitance contribution is
small), then the capacitance can be estimated using
C 12 =Area ⋅ (capacitance per area) (33.1)
If the capacitance per area is 50 aF/µm2, then it would take an area of 100 µm by 200 µm
to implement a 1 pF capacitor. While large area is a problem, it isn't the main problem with
a metal parallel-plate capacitor. The main problem occurs from the extremely large bottom

Metal2

Metal1 Insulator
Insulator

Substrate (p-type)

Figure 33.7 Parallel-plate capacitor using metal1 and metal2.

242 CMOS Mixed-Signal Circuit Design

plate parasitic capacitance, that is, the capacitance from metal1 to substrate. This parasitic
capacitance can be anywhere from 80 to 100% of the desired capacitance. Further it
usually slows the circuit response and results in a waste of power.
To help decrease the bottom plate's percentage of the desired capacitor value,
consider the cross-sectional view shown in Fig. 33.8, where four layers of metal
implement a capacitor. The capacitance of this structure can be estimated using
C = C 12 + C 23 + C 34 (33.2)
2
If plate capacitance between each metal layer is, again, 50 aF/µm , then the area required
to implement a 1 pF capacitor is 100 µm by 66 µm. The area needed is reduced by
one-third of the area used in the metal1/metal2-only capacitor. While we used the same
plate capacitance value in between each level, we know that this will vary because of the
differing thickness in between the metals. The absolute value of the capacitors, in most
situations, isn't important but rather the ratio of capacitors is the important parameter, as
seen in the last chapter. Also notice how, in a modern CMOS process, the thickness of the
metals (made most often now with copper) increases as we move away from the substrate.

Metal4

Metal3
Tungsten plugs

Substrate (p-type)

Figure 33.8 Cross-sectional view of a parallel plate capacitor using metal1-metal4.

The value of the capacitors in Figs. 33.7 and 33.8 was set by the areas of the
metals and the corresponding plate capacitance. We assumed the perimeter of the metals
and the resulting fringe capacitance was a small contributor. Figure 33.9 shows typical
minimum sizes and distances between pieces of metal1 where the fringe capacitance
dominates. We can make a capacitor using the two pieces of metal1 shown in this figure.
A typical value of capacitance per length is 25 aF/µm. The parasitic bottom plate
capacitance is half of this value or 12.5 aF/µm. Since, as seen in Fig. 33.9, the electric
fields can terminate on the close adjacent metal, the bottom component is a smaller
percentage than it was when the plate capacitance dominated.
Chapter 33 Submicron CMOS Circuit Design 243

Layout view
Cross-sectional view with field lines

Metal1

0.5 µm width and distance. substrate

Figure 33.9 Typical size when fringing capacitance dominates.

Example 33.1
Estimate the size of a metal1 only 1 pF capacitor. Also estimate the bottom
parasitic capacitance.
If we look at the layout of the capacitor shown in Fig. 33.10, we can estimate the
capacitance of a 1 µm by 2 µm section as 25 aF/µm2. This would mean that we
need an area of metal1 that measures 200 µm by 200 µm to implement a 1 pF
capacitor. The bottom plate capacitance can be estimated as 0.5 pF.
Note that while this capacitor results in twice the area af the metal1/metal2
capacitor of Fig. 33.7 and the associated discussion, it only uses one layer of metal
and the bottom parasitic is smaller. One might wonder if further benefits can be
achieved by using the fringe capacitance and multilevels of metal. T
Consider the use of metal2 and via1 in the implementation of a capacitor shown in
Fig. 33.11. While the fringe capacitance is still a major component in this capacitor
because of the addition of the via between the metals, it is sometimes called a lateral
capacitor (there exists a "plate" capacitance between the vias). A typical value of

25 aF 25 aF

1 µm

2 µm

Layout view (section)

Figure 33.10 Layout of a 1 pF capacitor using only metal1.

244 CMOS Mixed-Signal Circuit Design

Layout view Cross-sectional view

Via1
Metal2
Tungsten plug
Metal1, Metal2, Metal1 (Via1)
and Via1

0.5 µm width and distance. Substrate

Figure 33.11 Using two layers of metal and the via to implement a lateral capacitor.

capacitance for this structure is 200 aF/µm. The bottom plate capacitance remains
approximately 15 aF/µm. Using additional vias and metal layers will increase the
capacitance but generally not linearly. The higher levels of metal, e.g. metal4 or metal5,
generally have larger spacing and width design rules than do the lower levels of metal.
Nonetheless, using the lateral capacitor with several layers of metal and vias is the most
common way to implement a capacitor in a mixed-signal circuit.

Example 33.2
Repeat Ex. 33.1 using the lateral capacitor of Fig. 33.11.
Since the capacitance per length is now 200 aF/µm, the area required for a 1 pF
capacitor, keeping in mind that both metal1 and metal2 are used, is 50 µm by 100
µm. The bottom plate capacitance becomes 0.15 pF.
It's interesting to note that if we used four layers of metal with three vias and a
lateral capacitance value of 500 aF/µm, the area drops to 50 µm by 40 µm. T
An Important Note
While we've concentrated on the bottom plate parasitic, it is also possible to have a top
plate parasitic. Often, to avoid coupling noise into the relatively large area occupied by the
capacitor, a ground plate is placed above the capacitor. This would allow noisy digital
signals to be routed above the capacitor, as seen in Fig. 33.12.

Metal4 Digital signals

Metal3

Metal2 Connected to analog ground

(shield for the capacitor)
Metal1

Figure 33.12 Using a metal3 shield to isolate the lateral capacitor.

Chapter 33 Submicron CMOS Circuit Design 245

Resistors
Using a large number of capacitors in a circuit can result in large layout area, as just
discussed. Because of this, resistors are used whenever and wherever possible. For
example, a DAC may have been implemented using a charge redistribution topology in the
past. Now, however, it can be implemented using an R-2R topology and in considerably
less space. Table 33.1 shows the various characteristics of resistors available in a
submicron CMOS process. In the following discussion we assume that we are concerned
with implementing an R-2R DAC (see Chs. 29 and 34).

Rs TCR1 TCR2 VCR1 VCR2 Mis-

Silicide Resistor (ohms/sq) (ppm/C) (ppm/C2) (ppm/V) (ppm/V2) match %
Type AVG. AVG. AVG. AVG. AVG. ∆R/R

n-well 500 ± 10 2400 ± 50 7 ± 0.5 8000 ± 500 ± 50 < 0.1

n+ 120 ± 1 21± 10 0.6 ± 0.03 700 ± 50 150 ± 15 < 0.5
p+ 300 ± 5 160 ± 10 0.8 ± 0.03 600 ± 50 150 ± 15 < 0.2
n+ diff 100 ± 2 1500 ± 10 0.04 ± 0.1 2500 ± 50 350 ± 20 < 0.4
p+ diff 125 ± 3 1400 ± 20 0.4 ± 0.1 80 ± 80 100 ± 25 < 0.6
* n+ 3 ± 0.3 3300 ± 90 1.0 ± 0.2 2500 ± 125 3800 ± 400 < 0.4
* p+ 2 ± 0.1 3600 ± 50 1.0 ± 0.2 2500 ± 400 5500 ± 250 < 0.7
* n+ diff 3 ± 0.1 3700 ± 50 1.0 ± 0.2 350 ± 150 600 ± 60 < 1.0
* p+ diff 2.5 ± 0.1 3800 ± 40 1.0 ± 0.2 150 ± 50 800 ± 40 < 1.0

Table 33.1 Properties of resistors in a submicron CMOS process.

At first glance after reviewing Table 33.1, it may appear as though the n-well
offers the best choice for a resistor in a data converter since it has < 0.1% matching
characteristic. However, after reviewing the voltage coefficient specification for the
n-well, i.e., 0.008/V, we see a problem. If the voltage across one resistor in the R-2R
string is 2 V, while the voltage across another resistor is 0 V, we will see a mismatch
between the two resistors of 1.6%. Such a large voltage-varying mismatch can cause
severe linearity problems. It should be mentioned in passing that the origin of the n-well
voltage coefficient comes from the extension of the depletion region into the n-type
material used in the n-well (a problem not found in polysilicon resistors).
The polysilicon resistors available depend on the process steps. In one scenario the
poly is doped in situ while it's being deposited. Since the poly is silicided (called a
polycide) the possible pn-junction between the p+ and n+ poly isn't a concern. If the poly
is doped with an implant after it has been deposited, then a nitride layer above the gate
oxide is required to keep the implant from penetrating into the MOSFET's channel. In
either case, a silicide blocking mask is generally available to block out the siliciding of poly
(or active.)
246 CMOS Mixed-Signal Circuit Design

The p+ and n+ diffusions (the source and drain areas) can also be used for resistor
implementation. Again, the silicide block can be used to keep from siliciding the diffusions
(a silicided diffusion is called a salicide). Since the matching characteristics, temperature
behavior, and voltage coefficient are, overall, better for the polysilicon resistors, they are
generally preferred in the implementation of precision circuits such as data converters.
In general, the resistor’s width and length should be at least 10 and 100 times the
minimum feature size of the process, respectively. For example, if Lmin is 0.15 µm, then the
minimum width of the resistor should be 1.5 µm. Requiring minimum widths and lengths
for the resistors is important both for matching and to ensure that the self-heating, which
occurs because of the different current densities flowing in the R-2R resistors, doesn't
cause any noticeable differences in DAC linearity. In simple terms, the larger resistor area
dissipates heat better than the same valued resistor in a smaller area.
Figure 33.13a shows the conceptual layout of an R-2R resistor string in a minimum
area. Figure 33.13b shows the actual layout of the resistors having large width and length
along with a large number of contacts to reduce metal/resistive material contact resistance.
Figure 33.13c shows the problem of laying out metal over the resistive material, that is,
resistor conductivity modulation. The figure shows what happens when a metal, having a
potential greater than the potential of the underlying resistor is laid out directly over a
resistor. Electrons are attracted towards the surface of the resistor causing spots of lower
resistivity. The solutions to avoiding or reducing conductivity modulation are (1) avoiding
running metal over the resistors, (2) using higher levels of metal to route the resistive
signals so as to increase the distance between the resistor and the overlaying metal
(remembering vias and contacts must be plentiful to avoid adding unwanted series
resistance), or (3) inserting a conducting “shield” connected to analog ground and made
with metal1 between the resistors and the routing wires above the R-2R resistor array.
Finally, to conclude this subsection, we ask, “What is the best method of laying out
the resistors in an R-2R string to avoid process gradients and achieve good matching?”
While there are no absolute answers, we will discuss a possibility where layout area is a
concern. In other words, we won't discuss methods that use a large amount of layout area
to average out process variations but will limit our averaging to at most twice the layout
area of the R-2R string shown in Fig. 33.13.
Figure 33.14 shows one possibility for averaging process gradients using a
common-centroid configuration (see Ch. 7) with two R-2R strings connected in series. In
this figure we are assuming that the process variations change linearly with position. For
example, the first resistor in the string may have an effective value of 1k, while the
second's value may be 1.01k, and the third's value is 1.02k, etc. The normalized change in
the resistance value is shown in the figure using numbers. However, we could show that
the process gradients average out no matter what numbers are used, when using this
layout topology, as long as the sheet resistance varies linearly with position. For example,
the MSB 2R in the top string of Fig. 33.14 (on the left) has a value of 14 (6 + 8). The
MSB 2R in the bottom string (on the right) has a value of 24. Adding the values of the
two resistors, by connecting them in series, results in a resistor value of 38 (2R = 38 while
R = 19). The middle resistor value in the top string has a value of 12, while the bottom
Chapter 33 Submicron CMOS Circuit Design 247

dummy

dummy
(a)

Simplified layout
view of a resistor.
Layout of actual resistor with large
width and length for better matching
and power dissipation.
(b)
Metal at a potential higher than
the resistor will attract electrons
here
Metal

Resistor

Cross sectional view of metal over resistor.

(c)

Figure 33.13 (a) Minimal layout of R-2R string, (b) actual layout of resistor, and (c)
conductivity modulation of the resistor value.
248 CMOS Mixed-Signal Circuit Design

resistor has a value of 7. Again, adding the two resistors results in a value of 19.
Fundamentally, the limiting factor in matching then becomes the voltage and temperature
(because of the different current densities through the resistors) coefficients of the
resistors and the finite resistance of the MOSFET switches used in the DAC (discussed in
more detail in the following chapter).

Remaining metal connections not shown

Dummy

Dummy
6 7 8 9 10 11 12 13 14 15 16 17 18 +5

Process gradient
Dummy

Dummy
+0

1 2 3 4 5 6 7 8 9 10 11 12 13

+1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13

Process gradients

Figure 33.14 Two-string layout for improving matching of R-2Rs. Assumes the
resistors are connected together on higher levels of metal to avoid
conductivity modulation.

33.1.3 SPICE MOSFET Modeling

In this section we discuss using the EKV MOSFET model [4] in SPICE mixed-signal
simulations. We present a basic overview of the model and why we have selected it for our
example simulations.
Model Selection
In general, selecting a SPICE MOSFET model for submicron CMOS circuit design begins
with comparing simulated DC curves against measured curves, for example, ID vs. VDS or
Chapter 33 Submicron CMOS Circuit Design 249

ID vs VGS. While this is an important concern, and any SPICE model used for simulating
submicron circuits should show good agreement, it won't be what we focus on here. Here
we focus on the ability of the model to transition continuously from weak to strong
inversion. While we might think that looking at the DC curves of a device (e.g., ID vs. VGS )
would show the discontinuities (kinks) between weak and strong inversion, a much better
indication is to look at several devices operating under similar, related conditions.

VDD

I REF I REF I REF I REF

I REF I REF
2 4 8 16

W
L W 1W 1W 1W 1W
L 2L 4L 8L 16 L

Figure 33.15 Binary weighted current mirror.

Consider the binary weighted current mirror shown in Fig. 33.15. In the following
discussion we assume the lengths and widths of the devices are so large that oxide
encroachment and lateral diffusion are not an issue. Clearly, in Fig. 33.15, the MOSFETs
will all be operating in the same region, for example, strong inversion. What we are going
to do, with the binary weighted current mirror, is utilize the fact that MOSFETs in series
and parallel can be combined, as seen in Fig. 33.16, to implement a test circuit to evaluate
the performance of our submircon SPICE model. Note that our test circuit will have
nothing to do, directly, with short-channel behavior, but rather it will evaluate the
fundamental implementation of the model.

Drain
Drain
Drain Drain
W
L
Gate Gate 2W Gate Gate W
W
W L L 2L
W
L L
Source Source
Source
Equivalent Source Equivalent

Figure 33.16 Combining parallel and series MOSFETs.

250 CMOS Mixed-Signal Circuit Design

Figure 33.17 shows the implementation of the binary-weighted current mirror

using a W-2W topology (based on the R-2R divider discussed in the last section). To
understand the operation of this circuit first note that currents in M1 and M2 have the
same value. Next, notice that the currents flowing in the remaining MOSFETs should sum
to IREF. In fact, using the information shown in Fig. 33.16, the remaining MOSFETs can be
combined into a MOSFET with the same size as M1 or M2 (and, again, having a drain
current of IREF). Each stage we add to this topology essentially divides the reference
current by two keeping the overall sum of the currents at IREF.

VDD

I REF I REF I REF I REF I REF I REF

2 4 8 8
W W W W W
W L L L L L
L M3
M1 M2
2W 2W 2W
L L L

I REF I REF I REF

2 4

Figure 33.17 W-2W current mirror.

This circuit is useful because it now relates the current flowing in a strongly
inverted device, say M1 or M2 in Fig. 33.17, to a weakly inverted device, say M3. If the
MOSFET model is operating with a truly continuous change from one region to another
the currents will be binary-related and sum to IREF. Figure 33.18 shows the simulation
results for an eight-stage W-2W current mirror modeled with the EKV model. The 1 to
2% error in the binary currents is related to the differing drain-to-source voltages, VDS , of
the devices. The minimum length of the device modeled by the EKV model in this
simulation is 0.15 µm while the actual length used in the simulation is 5 µm (33 times
minimum). The widths of the devices used in the simulation are 20 µm and 40 µm.
Figure 33.19 shows the simulation results using a MOSFET model that doesn't
model these transitions well. If one were to use this model where the W-2W section is
used in a DAC, the designer might think the DAC performance is circuit-limited and not
matching-limited (keeping in mind that all MOSFETs are perfectly matched in a SPICE
simulation). This also points out an important point: Simulations don't always tell the
truth! The good design engineer knows the limitations of the models and the simulator.
While there are other reasons for using the EKV model (simulation speed, scaling,
well-behaved, etc.), the topic of MOSFET modeling is outside the scope of this book [5].
Chapter 33 Submicron CMOS Circuit Design 251

% Error from ideal value

Figure 33.18 Simulated W-2W current mirror using EKV model.

% Error from ideal value

Figure 33.19 Simulated W-2W current mirror showing model problems.

252 CMOS Mixed-Signal Circuit Design

Model Parameters
The EKV model parameters are listed below for both NMOS and PMOS devices. Notice
that the minimum length is 0.15 µm and the minimum width is 1.05 µm. Also note that the
level used depends on the simulator. For the simulations in this book, again, we will utilize
WinSPICE. While some of the model names are discussed in Ch. 5, information
concerning the remaining names can be found in [4]. Also note that these models are
located in the file models.txt in the zip file chap33_spice.zip located at cmosedu.com.
*** SPICE Models

*** Models created by Daniel Foty.

*** (c) 2001, Gilgamesh Associates and EPFL - All rights reserved.
*** These models are provided without warranty or support.
*** These models represent a completely fictitious 0.15um process, and do
*** NOT correspond to any real silicon process. They are provided expressly for
*** use in the examples provided in this text, and should not be used for any
*** real silicon product design.

*** NMOS EKV MOSFET Model ***************************************************

*** Level=44 in WinSPICE and ELDO, Level=55 in ADM/HSPICE, Level=5 in PSPICE,
*** Level=EKV in Spectre
*** Lmin=0.15u Wmin=1.05u (If Scale=0.15u then Lmin=1 and Wmin=7)
*---------------
.MODEL nmos nmos
+ LEVEL=44

*** Setup Parameters

+ UPDATE=2.6

*** Process Related Model Parameters

+ COX=9.083E-3 XJ=0.15E-6

*** Intrinsic Model Parameters

+ VTO=0.4 GAMMA=0.71 PHI=0.97 KP=453E-6
+ E0=88.0E6 UCRIT=4.0E6
+ DL=-0.05E-6 DW=-0.02E-6
+ LAMBDA = 0.30 LETA=0.28 WETA=0
+ Q0=280E-6 LK=0.5E-6

*** Substrate Current Parameters

+ IBN=1.0 IBA=200E6 IBB=350E6

*** Intrinsic Model Temperature Parameters

+ TNOM=27.0 TCV=1.5E-3 BEX=-1.5 UCEX=1.7 IBBT=0

*** 1/f Noise Model Parameters

+ KF=1E-27 AF=1

*** Series Resistance and Area Calculation Parameters

+ HDIF=0.24e-6 ACM=3 RSH=5.0 RS=1250.526
+ RD=1250.526 LDIF=0.07e-6
Chapter 33 Submicron CMOS Circuit Design 253

*** Junction Current Parameters

+ JS=1.0E-6 JSW=5.0E-11 XTI=0 N=1.5

*** Junction Capacitances Parameters

+ CJ=1.0E-3 CJSW=2.0E-10 CJGATE=5.0E-10
+ MJ=0.5 MJSW=0.3 PB=0.9 PBSW=0.9 FC=0.5

*** Gate Overlap Capacitances

+ CGSO=3.0E-10 CGDO=3.0E-10 CGBO=3.0E-11

*** PMOS EKV MOSFET Model ***************************************************

*** Level=44 in WinSPICE and ELDO, Level=55 in ADM/HSPICE, Level=5 in PSPICE,
*** Level=EKV in Spectre
*** Lmin=0.15u Wmin=1.05u (If Scale=0.15u then Lmin=1 and Wmin=7)
*---------------
.MODEL pmos pmos
+ LEVEL = 44

*** Setup Parameters

+ UPDATE = 2.6

*** Process Related Model Parameters

+ COX=9.083E-3 XJ=0.15E-6

*** Intrinsic Model Parameters

+ VTO=-0.4 GAMMA=0.69 PHI=0.87 KP=92.15E-6
+ E0=51.0E6 UCRIT=18.0E6
+ DL=-0.05E-6 DW=-0.03E-6
+ LAMBDA=1.1 LETA=0.45 WETA=0
+ Q0=200E-6 LK=0.6E-6

*** Substrate Current Parameters

+ IBN=1.0 IBA=0.0 IBB=300E6

*** Intrinsic Model Temperature Parameters

+ TNOM=25.0 TCV=-1.4E-3 BEX=-1.4 UCEX=2.0 IBBT=0.0

*** 1/f Noise Model Parameters

+ KF=1.0E-28 AF=1

*** Series Resistance and Area Calculation Parameters

+ HDIF=0.24E-6 ACM=3 RSH=5.0 RS=3145.263
+ RD=3145.263 LDIF=0.07e-6

*** Junction Current Parameters

+ JS=1.0E-7 JSW=5.0E-12 XTI=0 N=1.8

*** Junction Capacitances Parameters

+ CJ=1.3E-3 CJSW=2.5E-10 CJGATE=5.5E-10
+ MJ=0.5 MJSW=0.35 PB=0.9 PBSW=0.9 FC=0.5

*** Gate Overlap Capacitances

+ CGSO=3.2E-10 CGDO=3.2E-10 CGBO=3.0E-11
254 CMOS Mixed-Signal Circuit Design

An Important Note
We will be using the "scale" option available in WinSPICE with the EKV model. This
option is added to a netlist as follows
.option scale=0.15u

A MOSFET specified by
M1 1 2 3 4 NMOS L=1 W=10

would indicate that the MOSFET has a length of 0.15 µm and a width of 1.5 µm. A
possible mistake, when writing a netlist manually, would be to forget to add the scale
parameter.
Figures 33.20 and 33.21 show example IV plots for both NMOS and PMOS
devices. The NMOS device is sized 10/1 (actual width 1.5 µm and length 0.15 µm). The
PMOS device is sized twice as large as the NMOS, that is, 20/1 so that its current levels
are similar to the NMOS device. In our example process used in the book VDD is 1.5 V.

ID ID

V SB = 0 V GS = 1.5 V DS = 1.5 V
V GS = 1.25
V SB = 0

V SB = 1.25

V DS V GS
ID
10/1
D
G B
V DS
S
V GS V SB

Figure 33.20 NMOS curves for L = 1 and W=10.

Chapter 33 Submicron CMOS Circuit Design 255

ID ID

V BS = 0 V SG = 1.5 V SD = 1.5 V
V SG = 1.25
V BS = 0

V BS = 1.25

V SD V SG
ID
20/1
D
G B
V SD
S
V SG V BS

Figure 33.21 PMOS curves for L = 1 and W=20.

A Note Concerning "Long L MOSFETs"

We might think that with the terminology "long L" simply by making the MOSFET's
length very long we can avoid short-channel effects. Further, we might believe that using a
long length would result in a device that follows the square-law model. Unfortunately,
though, as the process dimensions shrink the devices are designed to drop large voltages
over small distances. A 5 µm length device in a 0.15 µm process will have significantly
different characteristics than a 5 µm device in a 2 µm process. Increasing the channel
length will not significantly affect the depletion width between the channel and the drain
(assuming the MOSFET is in saturation) for a fixed VDS .

33.2 Digital Circuit Design

In this section we discuss digital circuit design using a CMOS submicron process. Our
focus will be on the digital building blocks used in the last two chapters, that is, switches,
delay elements, counters, and adders. We assume the MOSFET models discussed in the
last section accurately model the fictitious submicron process used in the design examples
presented in this chapter.
256 CMOS Mixed-Signal Circuit Design

33.2.1 The MOSFET Switch

In this section we assume the reader is familiar with the material concerning the switches
discussed in Chs. 10 and 27. Figure 33.22 shows a basic NMOS switch in a test
configuration for determining its effective digital switching resistance. From the simulation
results shown in Fig. 33.23 we can relate the length and width of a MOSFET to the
effective digital resistance in our submicron process using
1 + K n ⋅ (VDD − VTHN ) L
R n = 10 kΩ ⋅ L ≈ ⋅ (33.3)
W KP n W
where the term 1 + K n ⋅ (VDD − VTHN ) (Kn is a constant dependent on the process) is used
to model the reduction in the mobility because of the thin oxide used in the MOSFET
formation. Notice that this is an average estimate for the resistance in all cases.

1.5

W/L
V DS
S D Rn =
ID
ID
V DS

Figure 33.22 Determining resistance of an NMOS switch.

W/L = 10/1
Rn
20/1

50/1

V DS
Figure 33.23 NMOS effective resistance from Fig. 33.22.
Chapter 33 Submicron CMOS Circuit Design 257

Example 33.3
Estimate, and verify with a SPICE simulation, the delay time in the following
circuit (Fig. 33.24).

Vout Initially at 1.5 V

1.5
10/1 1 pF
0

Figure 33.24 Circuit used in Ex. 33.3.

Using Eq. (33.3) the effective digital resistance of the MOSFET is 1k. The
propagation delay (input going high and output going low) can then be estimated,
knowing the load capacitance is much larger than the MOSFET capacitances,
using
t PHL = R n ⋅ C L = 1k ⋅1 pF= 1 ns
The SPICE simulation results are shown in Fig. 33.25. T

V in
V out

t PHL

Figure 33.25 Simulation results for Ex. 33.3.

Figure 33.26 shows the test circuit used to determine the PMOS effective digital
switching resistance, Rp. From the simulation results shown in Fig. 33.27 we can write
1 + K p ⋅ (VDD − V THP ) L
R p = 20 kΩ ⋅ L ≈ ⋅ (33.4)
W KPp W
Again this is an average estimate for the resistance for all source-to-drain voltages. Also
note how it doesn't matter if we use actual device sizes or scaled sizes in this equation
because of the ratio.
258 CMOS Mixed-Signal Circuit Design

W/L
1.5 − VD
D S Rp =
ID
VD ID 1.5

Note: Body of PMOS is

tied to 1.5 V

Figure 33.26 Determining resistance of an PMOS switch.

Rp W/L = 20/1

40/1

100/1

VD
Figure 33.27 PMOS effective resistance from Fig. 33.26.

Bidirectional Switches
The NMOS and PMOS switches shown in Figs. 33.22 and 33.26 make use of the fact that
the NMOS source is connected to ground and the PMOS source is connected to VDD.
For complementary static CMOS logic design we can rely on Eqs. (33.3) and (33.4) to
estimate the MOSFET sizes for a particular drive strength. However, if the MOSFET is
used as a pass gate where current can flow bidirectionally, the effective switching
resistance can become very large. This is related to the fact that the PMOS switch can't
pass a logic low (0 V) well and an NMOS switch can't pass a logic high well (VDD). Of
course, combining the NMOS and PMOS into a transmission gate (TG) eliminates this
concern at the price of larger layout area and the need for two complementary clocks.
Chapter 33 Submicron CMOS Circuit Design 259

Figure 33.28 shows the NMOS device used as a switch with the input at VDD (=
1.5 V here). Figure 33.29 shows how the effective switching resistance of this device
changes with size under various output voltages. Notice that, as we would expect, Rn gets
very large as the output approaches VDD − VTHN (with body effect).

1.5
1.5 − V out
W/L Rn =
ID
In Out

ID
1.5 V out

Figure 33.28 Determining resistance of a bidirectional NMOS switch.

W/L = 10/1
Rn

20/1 50/1

V out
Figure 33.29 NMOS effective resistance from Fig. 33.28.

Another application where a switch can be used bidirectionally was in the DAI
discussed in the last chapter. If the switches used in the DAI can be replaced with NMOS
devices the implementation is simpler. If we increase the voltage of the gate signal, it is
possible to turn the MOSFET all the way on and pass VDD from the switch input to its
output. Figure 33.30 shows the results if the gate signal in Fig. 33.28 is increased to a
value of 2.3 V.
260 CMOS Mixed-Signal Circuit Design

W/L = 10/1
Rn

20/1

50/1

V out

Figure 33.30 NMOS effective resistance from Fig. 33.28 with gate at 2.3 V.

Toward the goal of increasing the amplitude of the clock signal controlling the
switches consider the bootstrapped clock driver circuit shown in Fig. 33.31. This circuit is
a simple implementation of a voltage (charge) pump discussed in Ch. 18. The output
amplitude of the circuit approaches 2VDD so concern for oxide damage or long-term
failure is warranted as discussed in Ch. 6. The inverters are sized with 100/1 PMOS and

In Out 1.5 1.5

P
M1 M2
Schematic symbol 20/1 100/1
for this

100f 1,000f
100/50
100/50 100/1
Clock in Clock out
100/1

Figure 33.31 Charge-pump clock driver. Peak output is around 2.8 V.

Chapter 33 Submicron CMOS Circuit Design 261

50/1 NMOS devices. The other devices are sized to minimize power while supplying a
reasonable level of output drive. For example, the 100 fF capacitor only has to supply
charge to the gate of M2, but the 1,000 fF capacitor supplies charge to both the gate of
M1 and the load. Further scaling is possible to further reduce power and enhance output
drive. Note this circuit is noninverting and can be used in a nonoverlapping clock
generator, as shown in Fig. 33.32.

φ1
CLK
P P φ 1D

P P φ 2D

φ2

Figure 33.32 Nonoverlapping clock generation circuit with pumped outputs.

The clock generator of Fig. 33.32 provides the two phases of a clock signal as well
as slightly delayed clocks for use in a sample-and-hold, see Ch. 27. As the simulation
results show in Fig. 33.33, the output amplitude is approximately 2.5 V when a 100 fF
load is connected to each phase of the output. The time that all four clock signals are low,
the nonoverlap time (dead time), can be increased by increasing the delay in series with the
output of the NOR gates. Adding inverter pairs to the outputs of each NOR gate is a
common method of increasing the dead-time. Also note that the capacitors in Fig. 33.31
can be implemented using NMOS devices since they will always be in strong inversion.
A Clocked Comparator
One of the circuits that we used often in Ch. 32, in NS data converters, was a clocked
comparator. Let's develop a clocked comparator using inverters and switches. Examine
the evolution of circuits shown in Fig. 33.34. In parts (a) and (b) the basic inverter- based
latch is shown. In order to reduce power and make the comparator clocked, we add the
NMOS switch shown in part (c). Before each comparison, we want to ensure the
comparator is equilibrated. To erase the memory of the previous comparison, the PMOS
switch in part (d) is added to our circuit. When the clock, φ, goes high, the PMOS device
turns off and the NMOS device turns on allowing the inverters to latch in a stable
condition. The only thing we need to add to this circuit is circuitry to somehow create an
imbalance across the inverters when φ goes high. We can do this several ways. One
possibility is shown in Fig. 33.34e.
262 CMOS Mixed-Signal Circuit Design

Figure 33.33 Typical output of Fig. 33.32.

(a) Basic inverter-based latch.

(b) Transistor implementation of (a).

φ
φ

(c) Addition of switch to reduce power. (d) Erasing comparator memory.

Figure 33.34 Implementation of a clocked comparator.

Chapter 33 Submicron CMOS Circuit Design 263

NMOS are 10/1 Used if both outputs can't go

PMOS are 20/1 high over half of the clock cycle.

out−
V out+
V out−
out+

V in+ V in−

(e) Complete clocked comparator.

Figure 33.34 (cont'd) Implementation of a clocked comparator.

In Fig. 33.34e we connect our inputs to two common-source amplifiers which

have two purposes: (1) to amplify the input signals and create an imbalance in the latch,
and (2) to isolate the inputs from the switching noise resulting from the latch positive
feedback. (Kickback noise was discussed in Ch. 27.) The two switches we add in series
with our common-source amplifiers are not, in all cases, necessary. We add them here to
reduce power dissipation when φ is low. The clocked comparator doesn't draw any current
when φ is low. It does, however, draw current when φ is high. The amount is dependent
on the voltage applied to the comparator's inputs. Note also that when φ is low, both Vout+
and Vout− are equilibrated to a voltage of VDD − VTHP. This means that the output of the
comparator is essentially a logic high whenever φ is low. In order to make the circuit
appear as a truly rising edge comparator, where the comparison from a rising edge is valid
until the next rising, edge of an SR flip-flop (see Ch. 13) can be added to the output of the
clocked circuit.
Figure 33.35 shows simulation results with a typical input waveform. Note how,
when φ is low, the outputs of the latch go to VDD − VTHP. Also note how the final outputs
remain valid until the next rising edge of the clock. One thing that this simulation doesn't
reveal is the comparator's random offsets. Since the comparator is simulated using
perfectly matched devices, we will only see the comparator's systematic offset (see Ch.
25). While comparator offset wasn't a concern in a noise-shaping data converter, it is a
major concern in a Nyquist-rate data converter. We will revisit comparator and op-amp
offsets in Ch. 34.
264 CMOS Mixed-Signal Circuit Design

V in+ = 20 mV⋅sin 2π ⋅ 40 MHz+0.75

V in− = 0.75 V

φ
out−

out+

V out−

V out+

Figure 33.35 Simulation results for the comparator of Fig. 33.34.

One last comment before leaving this topic: Notice, after reviewing the simulation
netlist, how we used voltage sources for our comparator inputs. In any practical
simulation it is a better idea to add some series resistance between the comparator inputs
and the voltage sources to simulate finite source impedance. Resistors with 10k values are
typical for simulations of this nature. Using these resistors shows kickback noise on the
inputs to the comparator. This noise is often the fundamental limitation of the
comparator's performance in an actual circuit. Methods to reduce this kickback, such as
cascoding the input common-source amplifiers or using an additional amplification stage
such as a diff-amp, should be used in a general application. Note that kickback noise
shouldn't be a problem in the comparator used in a noise-shaping data converter due to the
large capacitance connected to the input of the comparator (the DAI's integrating
capacitance).
Common-Mode Noise Elimination
High-speed digital signals can often appear more like a sinewave than a square wave.
When these sinewave-like signals are applied to the inputs of a digital gate, the timing
delay between the gate's inputs and output can vary. This delay variation can be the result
of noise coupled onto the wires used to connect the circuits together or because of
power-supply fluctuations. To avoid these problems in analog circuits, as discussed on
page 191 and in Chs. 25 and 27, fully-differential outputs are used. Using fully differential
outputs in a digital system, however, can result in large layout area. The gates must have
both differential inputs and outputs. Because of this and the large noise margin of digital
signals, generally only signals that propagate over long distances will experience
Chapter 33 Submicron CMOS Circuit Design 265

detrimental noise corruption. However, any digital signal can be corrupted because of
power-supply fluctuations. In this section we discuss the idea of common-mode noise
elimination, CMNE. The CMNE circuit will, ideally, eliminate common-mode noise on a
wire pair while, at the same time, not affect the differential component. The technique can
be used to "square-up" digital signals. We apply this technique to the design of a
high-speed digital buffer.
Toward the design of a CMNE circuit, examine Fig. 33.36a. This circuit was the
heart, or decision circuit, of our comparator in Ch. 26. Assuming for the moment that all
transistors are sized equally we know that when io+ is greater than io−, the output vo+ is
greater than vo−. Any common signal to both io+ and io− will not be a factor in which signal,
vo+ or vo−, is larger. This circuit can only function if both io+ and io− are positive. Figure
33.36b shows the decision circuit of part (b) where we've added a PMOS decision circuit
so that the currents io+ and io− can be positive or negative. The schematic representation of
this circuit using inverters is shown in Fig. 33.36c.

VDD

i o+ i o−
i o+ i o−
v o+ v o−
v o+ v o−

(a) Basic decision circuit

(b) CMOS decision circuit

i o+
v o+

v o−

i o−

(c) Schematic diagram of part (b)

Figure 33.36 Common-mode noise elimination circuit.

266 CMOS Mixed-Signal Circuit Design

To determine quantitatively how this circuit functions, consider the inverter output
vs. input plot shown in Fig. 33.37. The switching point, VSP , is defined as the point where
the inverter's input and the output voltages are equal. This is also the DC operating point
of the CMNE circuit in Fig. 33.36c with zero input current. The inverter's model is also
shown in this figure. When vIN increases, vOUT ( = g m ⋅ v IN ⋅ r o ) decreases. The actual
values of gm and ro are not needed to understand the operation of the CMNE circuit.

20/10
v IN v OUT v OUT

v OUT V SP

v IN g m ⋅ v IN ro

Inverter model v IN
V SP

Figure 33.37 Modeling an inverter.

Consider the CMNE circuit shown with the inverter currents in Fig. 33.38. In this
circuit the input current is made up of a common-mode component, ICM , and a difference-
mode component, idiff, so that
i o+ = i CM + i diff (33.5)

g m ⋅ v o+

v o+
g m ⋅ v o− ro
i CM i diff g m ⋅ v o+ 2
v o−
ro
i CM 2
i diff g m ⋅ v o−

Figure 33.38 Analysis of a CMNE circuit.

Chapter 33 Submicron CMOS Circuit Design 267

and
i o− = i CM − i diff (33.6)
The resistors with values ro/2 connected to the two signal nodes model the parallel
combination of the two inverters' output resistance at each node. The fact that there are
only two signal nodes in this circuit is an important point since we don't want the CMNE
circuit to affect the desired, fully-differential signals. We want the desired signal to pass
through the CMNE circuit without any delay. If we sum the currents at each node, we get
v
i diff = g m v o− + g m v o+ + o+ + i CM (33.7)
r o /2
and
v o−
−i diff = g m v o− + g m v o+ + + i CM (33.8)
r o /2
Taking the difference in these two equations results in
v −v
i diff = o+ r o o− (33.9)

If we write the outputs as

v o+ = v cm + v diff (33.10)
and
v o− = v cm − v diff (33.11)
we notice the common-mode component subtracts leaving
r
v diff = i diff ⋅ o (33.12)
2
This equation shows that the input signal, idiff, generates an output voltage, vdiff , and that
any common-mode noise, vcm , is removed from the output signal.
A simple, yet useful, application of CMNE is shown in Fig. 33.39. Here the
CMNE circuit is placed in between two inverters. This circuit essentially behaves like a
diff-amp, or a comparator, amplifying the difference in the input signals and rejecting the
common-mode component. To be more correct, the common-mode component is shorted
to an inverter switching-point voltage, VSP, so that the difference-mode signals swing
around VSP. The inverters added at the end of the circuit ensure that good, solid CMOS
logic levels are output from the circuit.
Figure 33.40 shows a plot of the buffer's output against its input for reference
voltages, VREF, of 0.7 and 0.9 V. As we would expect, the buffer switches states only after
the input exceeds the reference voltage. This buffer can also be used if the input signals are
complementary logic signals. The delay through the buffer is only two inverter delays.
Because of the two inverters with their inputs shorted to their outputs the power
dissipation in this basic example can be excessive (approximately 1 mA for the example
given here). To reduce the current draw the CMNE circuit can be scaled.
268 CMOS Mixed-Signal Circuit Design

NMOS 10/1
PMOS 20/1

v in v out

V REF or v in
v out

Figure 33.39 A digital buffer (comparator) using CMNE.

v out and v out

V REF = 0.9 V
V REF = 0.7 V

v in

Figure 33.40 Simulating the circuit in Fig. 33.39 showing switching points
for references of 0.7 and 0.9 V.

One might wonder, after reviewing Fig. 33.40, if it's possible to increase the gain
of the buffer by adjusting the sizes of the inverters. We see that it takes over 300 mV input
signal to cause a full logic transition on the buffer's output. Also, it would be nice if the
buffer could be designed to have hysteresis, as discussed in Ch. 26. While we can increase
the length of the devices used in the inverters to both increase the gain and decrease the
power dissipation, the trade-offs are decreases in speed (the delay through the buffer) and
frequency response of the CMNE circuit. At very high frequencies the inverters aren't fast
enough to eliminate common-mode noise.
After reviewing how we introduced hysteresis into our decision circuit back in Ch.
26, we see that by increasing the length of the MOSFETs used in the shorted input/output
inverter we can achieve the same results in the buffer of Fig. 33.39. Consider Fig. 33.41, a
redrawn version of Fig. 33.38, with weak inverters. By weak we mean that the W/L ratio
Chapter 33 Submicron CMOS Circuit Design 269

Make a weak inverter

g mw ⋅ v o+

v o+
g m ⋅ v o− ro
i CM i diff 2
g m ⋅ v o+
v o−
ro
i CM 2
i diff g mw ⋅ v o−

Make a weak inverter

Figure 33.41 Figure 33.38 redrawn with weak inverters for hysteresis.

of the transistors used in this inverter is smaller than the other W/Ls used in the circuit.
We indicate that the modified inverter's gm is now weak, and thus less than the other
inverter's gm, by relabeling it gmw. We can rewrite Eq. (33.9) as
v −v v −v
i diff = o+ r o− + (g mw − g m ) ⋅ o+ o− (33.13)
o 2
or
2v diff
 
i diff = (v o+ − v o− ) ⋅  r1 + 1
 (33.14)
 o 2/(g mw − g m ) 
This equation can be written as

v diff = i diff ⋅  o g 1− g 
r
(33.15)
2 mw m

Since gmw is less than gm, the effective resistor added in parallel with ro is negative having
the effect of increasing the resistive loading of the CMNE circuit. This increase has the
effect of boosting the differential gain of the buffer of Fig. 33.39 and introducing
hysteresis into the switching point. Note that if gmw is equal to gm, then Eq. (33.15) reduces
to Eq. (33.12).
The allowable range of VREF is set by the threshold voltages and the power
supplies. For example, VREF can be no larger than VDD − VTHP. In reality VREF is limited to
voltages less than this because the drive of the inverter connected to VREF decreases.
Notice, in Fig. 33.40, how the final output crossover point is creeping toward VDD.
The CMNE technique can be used in a variety of places including delay-locked
loops or input and output buffers or simply to balance two differential digital signals.
While we used CMOS inverters here the technique can be extended to use inverting
amplifiers. We will extend this technique to balancing the outputs of fully-differential
op-amps later in the chapter.
270 CMOS Mixed-Signal Circuit Design

Example 33.4
Resimulate the buffer shown in Fig. 33.39 if the length of the MOSFETs is
increased to 2. Rerun the simulation if weak inverters, Fig. 33.41, are used with
their Ls increased from 2 to 2.1.
Figure 33.42 shows the simulation results. In part (a) the increase in gain with the
increase in L from 1 to 2 is evident. The current drawn from VDD decreases from
1 mA to 0.5 mA. Note in this figure we show VREF = 0.5, 0.7, and 0.9 V. The
references at 0.5 and 0.9 are at the edge of the allowable reference voltages, VREF.
In part (b) the small increase in the weak inverter's length (only 5%) shows that the
gain is improved further. This small increase introduces little hysteresis into the
input buffer. Increasing the weak inverter's length further, say to 3, causes both the
gain and hysteresis to further increase. T

V REF = 0.9 V
v out and v out V REF = 0.7 V

V REF = 0.5 V

(a)

v in

v out and v out V REF = 0.7 V V REF = 0.9 V

V REF = 0.5 V

(b)

v in
Figure 33.42 Simulation results for the buffers described in Ex. 33.4.
Chapter 33 Submicron CMOS Circuit Design 271

33.2.2 Delay Elements

Delay elements were used to implement our digital averaging or comb filters in Ch. 31.
We used these filters on the output of our noise-shaping, modulator-based ADCs or on
the input of a NS DAC in Ch. 32. Since the delay elements are continuously clocked, we
discuss the use of dynamic circuits in this section. Dynamic elements are used because they
result in lower power and smaller-layout area than static CMOS circuits. Low power and
small-layout area become extremely important when we realize that a filter may employ
hundreds, or even thousands, of delays.
Figure 33.43 shows a basic cascade of pass transistors and inverters first shown
and discussed in Ch. 14. When clk goes high, the output of the master is transferred to the
slave. When clock goes back low, the input capacitance of the slave inverter remains
charged and the output is unchanged. We can think of this circuit as a rising-edge
triggered D flip-flop. The pass transistors don't pass a logic high well, so the input voltage
to the inverters will be at most VDD − VTHN (with body effect). This can result in the
inverter having a significant crossover current and large power dissipation. The average
current pulled from VDD by the circuit of Fig. 33.43 while clocked at 100 MHz and
having equally sized devices (both 10/1) is 50 µA. To avoid excess current draw, the
switching point of the inverter can be decreased toward ground by making the PMOS
device weak. The output rise time, with a weak PMOS device, can become very long.

Master Slave
In Out Out

In
clk clk

clk

Figure 33.43 Simple delay element using pass transistors and CMOS inverters.

Figure 33.44 shows a positive edge-triggered delay using clocked-CMOS logic.

The problem of having excess power-supply current because of marginal logic levels is
absent in this configuration. However, the layout area will be larger than the delay in Fig.
33.43. When the delay of Fig. 33.44 is clocked at 100 MHz, the average current pulled
from VDD is well below 10 µA. It is easy to implement a reset using this delay cell
because we have a high-impedance node, that is, the node connecting the master and the
slave is never connected directly to ground or VDD. We can implement a reset, or set, in
the circuit in Fig. 33.43 by adding an additional switch in series with the input and two
additional switches on both inverters' inputs.
272 CMOS Mixed-Signal Circuit Design

Reset

Out
clk clk
In Out
In
clk
clk
clk

Master Slave

Figure 33.44 Simple delay element using clocked CMOS logic.

Both cells in Figs. 33.43 and 33.44 require the use of two clock signals. Figure
33.45 shows a delay element [7] that functions as an edge-triggered D flip-flop with a
single clock signal. The circuit technique used to implement this delay is termed true
single-phase clocking (TSPC). As seen in Fig. 33.45, both true and complement outputs
are available (the true output being buffered). The current pulled by this delay cell, when
clocked at 100 MHz, is below 10 µA. The layout area is comparable to the layout area
used by the clocked CMOS delay in Fig. 33.46.

Out Out
clk
Out
clk clk (Q) In

In clk
(D)

Figure 33.45 Delay element using TSPC.

By having a complementary output available, and requiring only a single-phase

clock signal, a divide-by-two circuit can be implemented, Fig. 33.46, using TSPC. We
used clock frequency dividers in the implementation of both decimating and interpolating
filters (see Fig. 31.63, for example). A divide-by-four is implemented by cascading two
divide-by-two circuits. In the general case, we can implement up- or down-ripple counters
by cascading TSPC delays as seen in Fig. 33.47. Also shown in this figure is a
synchronous up counter.
Chapter 33 Submicron CMOS Circuit Design 273

clk clk/2
clk/2
clk clk Q

clk
D

Figure 33.46 Divide-by-two circuit using TSPC.

D Q b2 D Q
clk Q clk Q b2

D Q b1 D Q
clk Q clk Q b1

D Q bo D Q
clk Q clk Q bo
Ripple up counter Ripple down counter

TSPC cell in Fig. 33.46

D Q
clk Q D Q
clk Q b2
D Q
clk Q D Q
clk Q b1
D Q
In
clk Q D Q
clk Q bo

Synchronous up counter

Figure 33.47 Counters using edge-triggered latches.

274 CMOS Mixed-Signal Circuit Design

Example 33.5
Sketch the implementation of a synchronous up/down counter. Discuss its
operation.
Figure 33.48 shows the basic block diagram of the counter. An adder is used to
either add or subtract one from the contents of the register. Two's complement
numbers are used in the adder to avoid overflow problems (see Ex. 31.22). The
MUX selects either +1 (= 0000...1) if UP is high or −1 (= 1111...1) if UP is low to
add to the contents of the register. T

D Q bn
clk
select, UP
000...1 UP
MUX D Q b1
111...1 clk
UP

D Q bo
clk
clk

Figure 33.48 Synchronous up/down counter using an adder.

33.2.3 An Adder
The last digital building block we will look at in this chapter is the adder. An adder was
used in all of our digital filters discussed in Chs. 31 and 32. While there are many ways to
implement adders, here we discuss ripple adders using dynamic logic. Again these designs
result in low power and a small layout area. If the delay through the adder is too long, for
a specific application, we use pipelining, Fig. 33.49, to segment the adder's internal delays.
Note that using pipelining results in a delay in series with the adder. The adder in Fig.
33.49 would have a z−3 delay in series with the output signal. In a practical circuit we
would segment 4-bit, or more, adders instead of the single bit adders shown in the figure.
The output of a 1-bit adder can be written as
s out = a in ⋅ b in ⋅ c in + (a in + b in + c in ) ⋅ c out (33.16)
where ain and bin are the adder's inputs, while cin is the carry input. The carry output can be
written as
c out = a in ⋅ b in + c in ⋅ (a in + b in ) (33.17)
Chapter 33 Submicron CMOS Circuit Design 275

1-bit
b4 c out

Latch

Latch

Latch
a4 s4
c4
1-bit
b3
Latch

Latch

Latch
a3 s3
c3
1-bit
b2
Latch

Latch

Latch
a2 s2
c2
1-bit
b1 Carry out
Latch

Latch

Latch
a1 s1
Carry in c1
0

Figure 33.49 A 4-bit pipelined adder. The latches (clocked) behave as delay elements.

Figure 33.50 shows the implementation of a dynamic adder. The first stage generates the
carry out and is implemented in NMOS precharge-evaluate (PE) logic. The second stage is
implemented using PMOS PE logic. The overall gate can be thought of as a domino gate.
The output of the adder is valid when clk is high.

c out
a in
a in c in b in c in
b in a in
a in
b in b in
c in
clk clk

c out
s out

Figure 33.50 Full-adder bit implemented using dynamic logic.

276 CMOS Mixed-Signal Circuit Design

33.3 Analog Circuit Design

In this section we discuss analog circuit design using a submicron CMOS process. We
assume the reader is familiar with the fundamentals of analog design presented in Chs.
20-25 of [1]. The first subsection presents a discussion of biasing concerns, the second
subsection discusses op-amp design, and the third subsection covers circuit noise.
33.3.1 Biasing
When starting an analog design we begin by selecting the excess gate voltage, ∆V, also
known as the overdrive voltage, and the biasing current level. Selecting these two
parameters sets the width and length of the MOSFETs. While using large area devices (L⋅
W) that are placed close together results in the best device matching [8], our focus here
will be on speed and power.
Selecting the Excess Gate Voltage
Figure 33.51 shows the basic source cross-coupled diff-amp first discussed in Ch. 24. For
the moment we will assume the minimum voltage across the drain and source of a
MOSFET, VDS,sat , is ∆V. Further, we know that the gate-to-source voltage of a MOSFET,
VGS , can be written as ∆V + VTHN . In our 0.15 µm process the NMOS and PMOS devices

VDD VDD

V ot2 M7 M8 V ot1

VDD VDD

V biasp V biasp
VDD VDD
M1 M2

V inp V inm
M3
M4
V biasn V biasn

M5 M6
V ob2 V ob1

Figure 33.51 Op-amp input diff-amp without slew-rate limitations.

Chapter 33 Submicron CMOS Circuit Design 277

have the same threshold; 0.4 V at room temperature in a typical process run. We will
design our circuits so the PMOS and NMOS devices have the same gate-to-source
voltage. Writing KVL from VDD to ground through M8, M2, M3, and M5 results in
VDD = V SG8 + V DS2 + V SD3 + V GS5 (33.18)
or
VSG8 VDS2 VSD3 VGS5

VDD = ∆V + VTHP + ∆V + ∆V + ∆V + VTHN (33.19)

noting, in Fig. 33.51, we've eliminated the body effect in M3 and M4 by placing them in
their own well. Because VDD = 1.5 and VTHP = VTHN = 0.4, we can set our ∆V to at most
175 mV. We know that the threshold voltage will change with process runs and with
temperature so we will select our ∆V as 100 mV to provide some margin for these shifts.
This means our nominal VGS (or VSG for the PMOS) in the designs presented here is 0.5 V
and the drain-to-source voltages are 250 mV.
Selecting the Channel Length
The small-signal output resistance decreases with decreasing channel length. Because of
this we might just select a channel length, for analog applications, ten times the minimum
length and be finished. However, as we'll show in a moment, the speed of the MOSFET is
inversely proportional to the channel length and, so, long L equates to slow speed. Also,
layout area is always premium real-estate; therefore, using the smallest possible devices is
usually desirable.
Consider the test circuit shown in Fig. 33.52. We've applied 0.5 V DC to the gate
of the NMOS device and swept the drain-to-source voltage of the MOSFET. This circuit
was simulated for four different device sizes: 40/4, 30/3, 20/2, and 10/1. Figure 33.52a
shows how the drain current changes with changing VDS. More interesting is the plot in
33.52b showing the MOSFET's output resistance, ro. Notice, as we would expect, the
output resistance increases with increasing L. The key point here is that we can increase
the output resistance and thus gain by increasing L. Unfortunately, this results in a
decrease in speed. For the designs presented here we will use an L of 2 (a 20/2 NMOS
device) as a reasonable trade-off between gain and speed. The nominal drain current that
flows in a 20/2 NMOS device with a VGS of 0.5 V is 20 µA. Also note from Fig. 33.52b
that the MOSFET appears to enter the saturation region at approximately 250 mV (not
the 100 mV we assumed earlier for VDS,sat ).
Figure 33.53 shows the output resistance plots for the PMOS device. Because of
the weaker drive of the PMOS, we used 20/1, 40/2, 60/3, and 80/4 device sizes in an
attempt to match the PMOS and NMOS drive strengths. Note that the gate of the PMOS
device is connected to a 1 V supply to set the VSG of the PMOS device to 0.5 V. We use a
40/2 PMOS device for the designs presented here.
It should be clear, after looking at Figs. 33.52 and 33.53, that we will often not be
operating our devices deep in saturation (and so our gain will suffer). If our device's
drain-to-source voltage is 100 mV, we will be operating our amplifiers in the triode
278 CMOS Mixed-Signal Circuit Design

10/1 40/4
30/3
20/2
20/2
40/4
10/1

(a) Drain current vs. drain-source voltage (b) Output resistance vs. drain-source voltage

V DS
0.5 V

Figure 33.52 NMOS curves for 40/4, 30/3, 20/2, and 10/1 devices.

20/1 80/4
60/3
40/2 40/2
80/4 20/1

(a) Drain current vs. drain voltage (b) Output resistance vs. drain voltage

1.5 V
V SG = 0.5 S

1.0
VD

Figure 33.53 PMOS curves for 80/4, 60/3, 40/2, and 20/1 devices.
Chapter 33 Submicron CMOS Circuit Design 279

region. The circuit-design techniques that we use for submicron circuit design should
allow reasonable gains even if our transistors move into the triode region with temperature
or process variations.
Small-Signal Transconductance, gm
Figures 33.54 and 33.55 show the test circuits and simulation results used to determine
each device's small-signal transconductance, gm. Note how we adjusted the DC drain-to-
source voltage so that the devices are operating in the triode region (see Figs. 33.52 and
33.53). Note also how we've tried to size the PMOS device to have similar characteristics
as the NMOS but the gm is still half that of the NMOS device.

i d = g m v gs g m , µA/V

20/2
0.1 V
v gs

0.5 V

Figure 33.54 NMOS small-signal transconductance.

g m , µA/V
1.5 V

40/2
v sg
i d = g m v sg

1.0 1.4

Figure 33.55 PMOS small-signal transconductance.

MOSFET Transition Frequency, fT

The MOSFET's transition frequency, fT , is defined as the frequency where the AC gate
current is equal to the AC drain current, or, i d /i g = 1 = 0 dB . This figure-of-merit was
280 CMOS Mixed-Signal Circuit Design

discussed back in Chs. 9 and 25. Figures 33.56 and 33.57 show how fT is determined from
simulation results. Large fT indicates high speed. From a circuit point of view
V GS
fT ∝ (33.20)
L
Using minimum-length devices with large gate-to-source voltages results in high-speed
operation with low gain (because of the small output resistance, as seen in Figs. 33.52 and
33.53) and reduced output swing (using a large VGS results in devices that enter the triode
region with relatively large drain-to-source voltages).

id
id
ig ig
20/2
1.5 V
v gs

0.5 V
fT

Figure 33.56 NMOS transition frequency.

1.5 V
id
ig ig
40/2
v sg
id

1.0

fT

Figure 33.57 PMOS transition frequency.

The Beta-Multiplier Self-Biased Reference

Figure 33.58 shows the schematic diagram of a beta-multiplier self-biased reference
designed to provide nominally 10 µA of current through a 20/2 NMOS or 40/2 PMOS.
We select the beta-multiplier because of its robust temperature characteristics. The
increase in the resistor with temperature is compensated for by the decrease in the
Chapter 33 Submicron CMOS Circuit Design 281

MOSFET's threshold voltage. The 80/1 device, M2, is large relative to M1 so that its VGS
is approximately 0.4 V (the threshold voltage). Because M2's VGS is 0.5 V, there is 100
mV dropped across the 10k resistor (and this sets the current). In a practical circuit,
subject to process variations, we can adjust the resistor value by adding series-shorted and
parallel resistors to the source of M2. This makes adjusting the current to a specific value
possible. Note, as discussed in the homework problems of Ch. 21, adding a capacitance to
ground at the source of M2 can result in an unstable circuit. The reference can actually
oscillate. This may be a problem if the resistor is bonded out to set the current value.
Adding capacitors to ground or VDD at Vbiasn and Vbiasp, however, can often be useful to
reduce coupled noise to the bias voltages.

VDD
M5
M3 M4 40/2
10/20 40/2 V biasp
10/1

M7
10/5 80/1
20/2 V biasn
M6
M1 M2
Start-up circuit 10k

Figure 33.58 Beta-multiplier self-biased reference circuit.

The temperature behavior of the beta-multiplier reference self-biased circuit of Fig.

33.58 is shown in Fig. 33.59. The temp-co of the resistor is set to 2,400 ppm/C. VDD is
swept on the x-axis while the current flowing in M2/M4 is shown on the y-axis. While we
might think that we can get better power-supply rejection by cascoding the MOSFETs, we
would find that many of the MOSFETs would operate in the triode region.
Figure 33.60 shows a general biasing circuit for analog design. The voltages Vbiasn
and Vbiasp are the inputs to the bias circuit and are supplied by the beta-multiplier of Fig.
33.58. The reader who doesn't understand the origin of this circuit is referred back to Ch.
20. Note, in this biasing circuit, how we have made an effort to reduce the number of
MOSFET gate-source voltages in between VDD and ground. This is necessary for
low-voltage operation. In the general design, as discussed back in Ch. 20, the size of the
⋅ device can be reduced (to, say, 15 ⋅ WL ) to bias the device closest to the power supply
1 W
4 L
rails further into the saturation region. This will generally provide higher gains at the cost
of slightly reduced output swing. Figure 33.61 shows the output current through both
NMOS and PMOS cascode current mirrors biased with Vbias1 through Vbias4.
282 CMOS Mixed-Signal Circuit Design

T=0C
T = 25 C
Reference current

T = 100 C

Figure 33.59 Temperature behavior of the reference of Fig. 33.58.

VDD VDD VDD VDD VDD VDD

V biasp V bias1 V biasp

V biasn2 V high
V bias2 V bias3
40/8 20/8
V biasp2 V low
V biasn V biasn V bias4

All unlabeled PMOS are 40/2

All unlabeled NMOS are 20/2

Figure 33.60 General biasing circuits for analog design.

Chapter 33 Submicron CMOS Circuit Design 283

T=0C

Current through vtest.

V bias3
20/2 T = 100 C
vtest
V bias4
20/2

VDD

V bias1
Current through vtest.

40/2 T=0C

V bias2 T = 100 C
40/2

vtest

Figure 33.61 Using the general purpose biasing circuit of Fig. 33.60.

Figure 33.62 shows how the currents in each leg of the diff-amp of Fig. 33.51
change as we sweep Vinp with Vinm held at 0.75 V. Note how, with Vinp = Vinm = 0.75 V, the
current in each leg of the diff-amp is 6 µA or less than the current in the biasing circuits.
This is the result of the body effect experienced by the MOSFETs in the diff-amp.

T=0C
T = 25 C
T = 50 C
T = 75 C
T = 100 C

Figure 33.62 DC sweeps showing the currents in each leg of the diff-amp of Fig. 33.51.
284 CMOS Mixed-Signal Circuit Design

33.3.2 Op-Amp Design

In this section we present the design of general-purpose, mixed-signal op-amps. Once
again we assume the reader is familiar with the material in Ch. 25. In particular,
compensating two-stage op-amps, floating current sources, output buffers, and fully-
differential op-amps. We use the biasing circuits developed in the last section in the
designs presented in this section. The goals of the designs presented here are robust
operation over wide process variations and temperatures.
Output Swing
Let's begin our op-amp development by considering the inverter shown in Fig. 33.63. In
order for our op-amp to have the widest possible output swing we must use this structure
on the output of the op-amp. (Sometimes this output structure is called a push-pull
amplifier because it can both source [push] and sink [pull] a current from the load.) Notice
how we've increased the size of the MOSFETs used in this structure from our standard
40/2 and 20/2 devices. This was to both increase the output drive of the op-amp and to
increase the output stage's input capacitance. This capacitance will be used to compensate
the op-amp. Also, because op-amp open-loop gain, AOL, is always important, using an
output stage with gain increases the op-amp's AOL.

VDD = 1.5 V

400/2
vout

vin vout

200/2

vin

Figure 33.63 Using an inverter on the output of an op-amp.

Looking at the transfer curve shown in Fig. 33.63, we see that the gain of the
inverter (the slope of the curve) is largest when the output falls between 0.25 and 1.25 V
(an output swing of 1 V). Throwing away 0.5 V, or 33%, of the power-supply voltage on
a MOSFET operating in the triode region is, of course, highly undesirable. Thinking about
this for a moment we may realize that if this (second) stage is preceded by a high-gain
(first) stage the op-amp may still function within specifications when the second stage gain
is dropping. (Though the distortion introduced by the output stage may be too high
because of this nonlinearity.) A more important concern then is the quiescent current
pulled through this stage. For the inverter in Fig. 33.63 this current is > 1 mA. For both
gain and power reasons we need to modify this basic output circuit.
Chapter 33 Submicron CMOS Circuit Design 285

To lower the quiescent current pulled from VDD and to increase the linear output
swing of the output stage consider adding batteries to the circuit as seen in Fig. 33.64.
We've selected the batteries so that when vin is 0.75 V the gate-source voltages of the
MOSFETs are 0.5 V. From Figs. 33.52 and 33.53 we can estimate the quiescent current in
the output stage as 150 µA (simulation results verify this estimate). Clearly, increasing the
battery voltages will make the output swing approach the power supply rails before the
MOSFETs enter the triode region. This increase in linear output swing comes at the cost
of speed, as indicated by Eq. (33.20).

VDD = 1.5 V

400/2
0.25
vout

vin vout

0.25
200/2

vin

Figure 33.64 Biasing a push-pull amplifier.

The next question becomes, "How do we implement the batteries in Fig. 33.64?"
The batteries must track both process and temperature changes. What we want is
something like what is seen in Fig. 33.65. Using Vbiasn2 from the circuit of Fig. 33.60, we
can precisely set the current in the output stage. Looking at this figure for a moment, we

VDD = 1.5 V

400/2
V biasp2
VDD MC1
vout
V biasn2
MC2
200/2
Two ga
te-sourc
e voltag
es

Figure 33.65 Conceptual biasing of a push-pull amplifier with current mirrors.

286 CMOS Mixed-Signal Circuit Design

see that we need to somehow couple our input signal to the gates of the output MOSFETs
and we need to provide a path for current flow in the added transistors. As drawn MC1
and MC2 are off.
Figure 33.66 shows the use of a floating current source (discussed in Ch. 25) to set
the bias current in the output stage. Note that since the current in the cascoded transistors
splits between MC1 and MC2, we have reduced their size by one-half in order to set the
current in the output MOSFETs to precisely ten times the current in the remaining
MOSFETs. By further reducing the size of MC1 and MC2 (reducing W or increasing L),
we can choke off the current flowing in the output transistors. While this will push the
frequency of the pole located on the output of the op-amp downwards, ultimately making
stability a concern, it may be used to reduce the quiescent power of the op-amp. The input
signals, Vot1 and Vob1, come from the diff-amp shown in Fig. 33.51. The cascode transistors
provide the "first stage gain" so that the circuit shown in Fig. 33.66 is an op-amp minus
the diff-amp. The structure is biased so that it can function with very low power supply
voltages. The limitation on how low the power-supply voltages can go is set by the
diff-amp of Fig. 33.51.

VDD

V ot1

VDD
V bias2
400/2
V biasp2
20/2
MC2 MC1
V biasn2 10/2
200/2
V bias3
M12

V ob1
M11
All unlabeled PMOS are 40/2
All unlabeled NMOS are 20/2

Figure 33.66 Biasing a push-pull output stage with floating current source.

Example 33.6
Consider the AC small-signal simplification of the floating current source shown in
Fig. 33.67. Assuming the NMOS cascode output resistance is labeled Rncas, what is
the small-signal resistance seen by the test voltage, vtest?
Chapter 33 Submicron CMOS Circuit Design 287

To PMOS cascode
i test
S
i dmc2
MC2 MC1
v test r on r op
i dmc1
S

R ncas i test

Figure 33.67 Small-signal AC circuit for Ex. 33.6.

What we are going to show is that the floating current source will not load, or
decrease, the resistance seen by the cascode structures. Writing a KVL from vtest to
ground results in
v test = (i test − i dmc1 − i dmc2 ) ⋅ r on r op + i test ⋅ R ncas
where the drain currents of MC1 and MC2 are idmc1 and idmc2, respectively, and their
output resistances are ron and rop. The drain currents can be written as
i dmc1 = g mn ⋅ v gs = g mn ⋅ (−i test ⋅ R ncas )
and
i dmc2 = g mp ⋅ v sg = g mp ⋅ v test
Combining these equations
≈ g mp ⋅r on r op ≈ g mn ⋅r on r op ⋅R ncas

v test ⋅(1 + g mp ⋅ r on r op ) = i test ⋅(1 + g mn R ncas ⋅ r on r op + R ncas )

or
v test
≈ R ncas
i test
This shows that adding the floating current source to our cascode stack in Fig.
33.66 will not affect the gain of the circuit. T
Slew-Rate Concerns
We know from our discussion in the last chapter that slew rate can be a big concern when
designing a mixed-signal system. For example, the drain of the NMOS device, M11, at the
bottom of Fig. 33.66 will be at a voltage of approximately 150 mV. If the voltage Vob1
increases, the maximum amount this device (M11) can turn on is very limited. If we were
able to hold its drain voltage constant, then an increase Vob1 would result in an increase in
288 CMOS Mixed-Signal Circuit Design

drain current. Now, however, the current through M12 is constant (its gate is held at Vbias3,
while its source is held at a fixed potential). What we need to add to this basic circuit is a
circuit that will hold the drain of M11 at a fixed potential while at the same time adjust the
gate voltage of M12 so that it can turn on.
Figure 33.68 shows adding N and P diff-amps to help with adjusting the biasing so
that slewing isn't a concern. Figure 33.69 shows the circuit implementation of the
amplifiers. The source followers were added in Fig. 33.69 so the inputs can go to the
power supply rails and to reduce the input capacitance. Adding the N and P amplifiers to
the amplifier of Fig. 33.66 (called gain-enhancement back in Ch. 25) also increases the
output resistance of the cascode stack. This is important because we want the pole
associated with this node (the output of the first stage or the input to the second stage) to
be dominant so that it compensates the op-amp. The voltages Vhigh and Vlow are generated
with the bias circuit of Fig. 33.60 for, once again, the widest possible operating range. As
discussed in Ch. 25, we can increase the gain of the op-amp by increasing the gains of
these added amplifiers.

VDD

V ot1

VDD

V high N

V biasp2

V out
V biasn2

V low
P

V ob1
Device sizes as seen in
Fig. 33.66

Figure 33.68 Adding amplifiers to our op-amp to boost gain and help slew-rate.

Reviewing Fig. 33.62 we see that the current sourced by our diff-amp is very
limited. Let's say that there is 5 µA of current available to charge the output transistors in
Fig. 33.68. We can estimate the input capacitance of these two transistors using
Chapter 33 Submicron CMOS Circuit Design 289

VDD VDD VDD

V biasp

out
P

Out

VDD
VDD VDD

Out
out
N

V biasn

Figure 33.69 Diff-amps with source-follower level shifters for use in Fig. 33.68.

C ox
 Wp Wn
 L
ε
C 1 =  400 + 200  ⋅ 2 ⋅(scale) 2 ⋅ ox = 1, 200 ⋅ (0.15 µ) ⋅
 2 35.13 aF/µm
= 237 fF
  t ox 0.004 µm
 
(33.21)
The rate we can charge this input capacitance is
5 µA dV
= = 21 mV/ns (33.22)
237 fF dt
At first glance this may appear to be a significant limitation if the output of our op-amp
has to change by 1 V or more during a 10 ns clock cycle. However, after reviewing Fig.
33.64 we see that well under 50 mV change on the input of these output transistors is
needed to cause the output to change from rail to rail. One final comment: To balance the
drive to the output transistors, a capacitor can be added in between each of the gates of
290 CMOS Mixed-Signal Circuit Design

the two transistors. This capacitor doesn't affect the compensation or the speed, it simply
makes the biasing appear more battery-like, as seen in Fig. 33.64. We also added
capacitors in the diff-amp of Fig. 33.51 so that the source-followers used for biasing
appear more battery-like (as discussed in Ch. 24).
Now that we've calculated the capacitance on the output of the first stage, C1, we
can estimate the location of the dominant pole. The voltage gain of the cascode section is
approximately (gmro)2. When the gain enhancement amplifiers (N and P in Fig. 33.69) are
added the voltage gain increases to (gmro)3 noting this is the gain to the output of the first
stage and not the final gain of the op-amp. If we pull the transconductance of the diff-amp
out of this equation, we estimate the cascode output resistance as g 2m r 3o (= R1). Using Figs.
33.52 - 33.55 we can estimate R1 as 150 MΩ. The location of the dominant pole is then
estimated as f 1 = 1/(2π ⋅ 150 MΩ ⋅ 237 fF) = 4.4 kHz . This pole can be pushed lower in
frequency, further compensating the op-amp, by adding capacitance from the gates of the
output MOSFETs to AC ground (ground or VDD).
The observant reader may ask, "If we can get away with only 5 µA of bias current
in our amplifier and avoid slew-rate limitations, why use the diff-amp of Fig. 33.51?" As
we discussed earlier, this diff-amp represents the weak link in the minimum power supply
voltage we can use with our op-amp and it dissipates more power than an equivalently
biased regular diff-amp. Also, the input common-mode range of this diff-amp is very
limited. We won't be able to use the op-amp as a simple voltage follower. Because of
these concerns/reasons we won't use this topology for our basic op-amp design. (The
noise performance, discussed in the next section, is also poorer for this diff-amp mainly
because the source followers used for biasing are in series with the input signal.)
Figure 33.70 shows one possible mixed-signal op-amp topology. We used diode
connected, cascoded MOSFETs to generate Vot1 and Vob1 in the diff-amp in an effort to
equalize all drain-source voltages. The minimum supply voltage, because of the diff-amp
used, can be significantly less than 1.5 V (approaching 1 V for a typical process run). One
potentially important concern is the negative common-mode range of the diff-amp. If the
inputs are held at 0.75 V, with the gate-source voltage of the diff-amp pair at 0.5 V, there
will be only 0.25 V left to drop across the diff-amp's current sink. The result is the
diff-amp's biasing current may decrease (and so will the common-mode rejection ratio).
Using a single MOSFET to bias the diff-amp or increasing the widths of the diff-pair can
improve this situation.
The gain of this topology is very high. This can lead to simulation problems (which
has led us to use HSPICE in the following simulation results). Figure 33.71 shows the
output of the op-amp as a function of the noninverting input voltage of the op-amp with
the inverting input held at 0.75 V. The systematic offset voltage is approximately 3 mV.
Not cascoding the diode-connected loads of the diff-amp can result in a significantly larger
offset voltage. Increasing the widths of the diff-amp pair reduces the systematic offset,
and, if laid out properly, reduces the random offsets.
Figure 33.72 shows the open-loop gain of the op-amp (approximately 110 dB at
DC). As is, the op-amp will be unstable if used in a unity gain configuration. The dominant
Chapter 33 Submicron CMOS Circuit Design 291

VDD VDD VDD VDD

V ot1

V bias2 VDD
V high N
400/2
V biasp2
20/2
V out
V biasn2
10/2
V low 200/2
P
V bias3 40/2

V bias4 V ob1
40/2

All unlabled PMOS are 40/2

All unlabled NMOS are 20/2

Figure 33.70 Mixed-signal op-amp.

pole, as discussed above, is at the output of the first stage (input to the second stage). We
might think that using different N and P diff-amps (or some other operational
transconductance amplifier) with a higher gain will help improve the stability. While
increasing the gain of these amplifiers will push the dominant pole to a lower frequency, it
will also increase the low-frequency gain having little effect on the stability.
Figure 33.73 shows how adding two 250 fF capacitors to the output stage pushes
the dominant pole downwards and makes the op-amp stable. The unity gain frequency of
the op-amp is approximately 70 MHz. Unfortunately, the settling time of the op-amp
increases. Figure 33.74 shows a test configuration where the op-amp, driving a relatively
large 5 pF capacitor, has a settling time of approximately 50 ns. (Figures 33.72 and 33.73
were generated without a load; so the unity gain frequency with a load will be less than
what is shown in these figures.)
While reducing the capacitive load decreases the settling time, we may not have
this option available. Let's discuss the design of an op-amp and the trade-offs if we use the
basic topology of Fig. 33.70 to implement a mixed-signal op-amp.
1. The load is purely capacitive. We may consider eliminating the floating current
source and the push-pull output stage (and note that the inverting and noninverting input
292 CMOS Mixed-Signal Circuit Design

1.5 V

VDD
V in
V out

V out 0.75

0V

V in
122 nV

Figure 33.71 DC behavior of the op-amp of Fig. 33.70.

V out

600 MHz

V out

0.75

∠V out 1 100MEG

Unstable!

Figure 33.72 Showing open-loop response of the op-amp of Fig. 33.70.

Chapter 33 Submicron CMOS Circuit Design 293

VDD

250 fF
Out
250 fF

Adding capacitors to
the output stage

70 degree phase margin

Figure 33.73 Compensating the op-amp of Fig. 33.70.

In

Out 0.75 Out

10k
10k
C load
1.0 5 pF
In
0.5

Figure 33.74 Showing settling time of the op-amp in Fig. 33.70 with the compensation
capacitors shown in Fig. 33.73.
294 CMOS Mixed-Signal Circuit Design

terminals switch places). While the output range is reduced when not using the push-pull
output buffer, the stability is almost guaranteed with a reasonable-sized load capacitance.
The biasing current is increased so that it can drive the capacitive load in the time
required. A scaling increase in the biasing currents is followed by an increase in the size of
the devices. For example, if we increase our biasing current from nominally 15 µA (see
Figs. 33.52 and 33.53) to 150 µA, then our NMOS size is increased to 200/2 and the
PMOS size is increased to 400/2. Not scaling devices, as discussed earlier, can result in
too small of an fT or too large of a ∆V.
2. We use the circuit as seen in Fig. 33.70 but the settling time is too long. By
reducing the lengths of the push-pull output stage, the frequency of the second pole gets
pushed out (increases) and the gain of the output stage decreases (both helping with
stability). However, the current in the output stage increases, resulting in higher power
dissipation. This, in most situations, isn't enough alone to guarantee a stable op-amp.
3. Increasing the biasing current lowers the gain and improves the speed (and thus
decreases the settling time). The linear output range decreases (perhaps by too modest an
amount to be a concern because of the large first-stage gain) and the input diff-amp
minimum common-mode range may become too large, causing the diff-amp to shut off
when VDD/2 is applied to the op-amp input. This latter concern was discussed earlier.
This fix for the settling time is trivial to simulate by changing the resistor value in the
beta-multiplier biasing circuit used in the op-amp.
4. Increasing both the biasing current and the size of the devices in Fig. 33.70 so
that a given load capacitance becomes, effectively, less difficult to drive. This is the same
fix as 1), above, except that we still have the floating current source and output buffer
(and so the current needed to charge the load is supplied by the push-pull amp and is not
directly related to the biasing current in the diff-amp).
Before listing number 5, let's review from Ch. 27 how the op-amps unity gain
frequency, fu, is related to settling time. Assuming no slew-rate limitations, the op-amps
time constant can be written (assuming the op-amp has only a single dominant pole) as

τ= 1 (33.23)
2πf u ⋅ β
β is the feedback factor. Here we assume β = 1, where all of the output is fed back to the
input. For our op-amp response of Fig. 33.73 τ = 2.3 ns. The output signal for our
single-time constant dominant-pole op-amp circuit can be written as
V out = V outfinal (1 − e −t/2.3ns ) (33.24)
For 0.1% settling accuracy (Vout /Voutfinal = 99.9%), it takes
t = 15.9 ns (33.25)
While we used 70 MHz for fu, including the 5 pF load drops the unity gain frequency and
increases the bandwidth-limited settling time.
Chapter 33 Submicron CMOS Circuit Design 295

5. Use minimum channel lengths for any high-speed design. This increases the
device's fT while also increasing the drive current strength of the MOSFETs. Using
minimum channel lengths with a larger biasing current can push the settling time down to
under 10 ns. The decrease in the gain resulting from using minimum length devices and a
larger biasing current (larger ∆V) in the topology of Fig. 33.70 shouldn't be too much of a
concern since we are starting with 110 dB gain.
Differential Output Op-Amp
Let's build on our basic op-amp of Fig. 33.70 to implement a high-speed, low-power
fully-differential op-amp. Consider the gain and output stage shown in Fig. 33.75 and the
associated simplified schematic representation. Notice how the inputs labeled "Top" and
"Bottom" are low-impedance, cascode-connected current mirrors (with node voltage
labels, Vot1 and Vob1). Using the simplified model, Figure 33.76 shows the schematic of a
fully-differential op-amp (minus the common-mode feedback circuit).

VDD VDD

V ot1

V bias2 VDD
Top V high N

V biasp2
V out
V biasn2

Bottom V low
P
V bias3

V ob1

V ot1
Top

Out V out
V ob1 Bottom Simplified schematic symbol

Figure 33.75 Mixed-signal op-amp building block.

296 CMOS Mixed-Signal Circuit Design

VDD VDD

Top Top

V out− V bias2 V out+

Out Out

Bottom Bottom

V bias3

V bias4

Figure 33.76 Fully-differential op-amp.

An important component of any fully-differential op-amp is the common-mode

feedback circuit as discussed back in Ch. 25. While we won't repeat the material in Ch. 25
here, we will comment on two additional methods to balance the op-amp outputs.
Figure 33.77 shows the addition of two weak transistors to the input of the
diff-amp of the op-amp. If the op-amp's inputs are not at the common-mode voltage, VCM ,
the additional transistors either conduct more or less current causing the average of the
outputs of the op-amp to move upwards or downwards. This, of course, assumes the
output of the diff-amp is single-ended. This would require connecting the "Bottom" input
node in the building block stage to Vbias4 and removing the diode-connected MOSFETs on
the input of this stage.
Earlier we discussed using common-mode noise elimination to balance the outputs
of a digital input buffer, Fig. 33.39. We can use the same technique to balance the output
of our op-amp, Fig. 33.78. We will use inverters to illustrate the technique; however, we
must ensure that whatever inverting amplifier we place on the output of the op-amp
doesn't load the op-amp's outputs. Adding resistors in series with the inverter outputs will
help ensure loading isn't a problem. Since our op-amp outputs are buffered, the op-amp
can drive the resistors directly. Using diff-amps in place of the inverters may be necessary
to precisely set the common-mode output voltage to VCM . The inverters, as shown in Fig.
33.78, will try to balance the outputs to their switching point voltage, VSP. When a
diff-amp is used in place of the inverters, one input is tied to the resistors and the other
input is tied to VCM. Also note, for high-frequency operation, the averaging resistors
Chapter 33 Submicron CMOS Circuit Design 297

VDD VDD
V CM

V bias3
Circuit useful with Long L devices
DC feedback around V bias4
the op-amp Adjust current as needed

Figure 33.77 Adding auxilary input to the diff-amp to balance the op-amp's outputs.

v o+

R
v o+ + v o−
2

R
v o−

Figure 33.78 Using common-mode noise elimation to balance the outputs of an op-amp.

should have small shunt capacitors placed across their terminals to compensate for the
inverters' input capacitance.
We can analyze the operation of the circuit shown in Fig. 33.78 using the steps
shown in Eqs. (33.5)-(33.12). Assuming the output resistance of the inverter is large
compared to the resistors R, we get
v o+ + v o− v o+ − (v o+ − v o− )/2
i diff = g m ⋅ + + i CM (33.26)
2 R
and
v o+ + v o− v o− − (v o+ − v o− )/2
−i diff = g m ⋅ + + i CM (33.27)
2 R
Taking the difference in these equations shows, once again,
v −v
2i diff = o+ o− (33.28)
R
and that the common-mode component of the signal is removed (set to VSP).
298 CMOS Mixed-Signal Circuit Design

33.3.3 Circuit Noise

In this section we discuss and review circuit noise. We will repeat discussions of some of
the topics we've already covered in Chs. 7, 9, and 22 to provide further, intuitive
understanding of random processes (such as the quantization noise and clock jitter
discussed in Chs. 30 and 31).
Thermal Noise
Consider the voltage divider shown in Fig. 33.79a. In this figure the ideal voltage out, Vout,
is 0.75. However, because of the random motion of the electrons making up the current
flowing in the circuit (because of lattice vibrations or heat), the voltage Vout has a random
variation. The effects of this variation are termed thermal noise. As seen in Fig. 33.79b,
the variation in the output voltage can be characterized with a Gaussian probability density
function (PDF). Notice that time is not indicated in this figure. We can't determine
directly, from the information shown in the figure, the spectral characteristics of the noise
unless we make some assumptions (like we did with the quantization noise in the previous
chapters where we assumed it was bandlimited to the Nyquist frequency). Reviewing Figs
31.12 and 31.13 and the associated discussions in Ch. 31 we can make the following
comments:
1. The RMS value of the thermal noise in Fig. 33.79 is 1 µV. We could also say
that the standard-deviation, σ, is 1 µV since the RMS value and the standard deviation are
equal when the noise has a Gaussian PDF.

0.750003
VDD = 1.5 V

R
V out 0.75 V

σ
R 6σ ≈ 6 µV
2σ
0.749997

(a)
(b) Volts

RMS voltage = σ ≈ 1 µV

Figure 33.79 (a) A voltage divider and (b) the variation of the output voltage because of
thermal noise (an example PDF).
Chapter 33 Submicron CMOS Circuit Design 299

2. The mean-squared value (squaring the RMS value) indicates the average power
of the thermal noise. We could also say that the variance, σ2, indicates the average power
of the noise. Sometimes this is more correctly called the total average normalized power
because we assume a 1 Ω resistor when converting from RMS voltage or current to power
and we sum the total power in the spectrum, see Eq. (31.37).
3. The power (variance) in uncorrelated noise sources (random variables) can be
added directly, but the RMS voltage or current values (standard-deviation) cannot. For
example, if we have an RMS thermal noise voltage, σtherm, an RMS quantization noise
voltage, VQe,RMS, and a sampling error power due to jitter of PAVG,jitter (see Ex. 31.15)
corrupting a sinewave signal with a peak amplitude of Vp, then we would determine the
signal-to-noise ratio of the signal using
Vp / 2
SNR = 20 ⋅ log (33.29)
σ 2therm + V 2Qe,RMS + P AVG,jitter

The numerator is, of course, the RMS value of the desired signal while the denominator is
the square root of the total error power from each error source, i.e., thermal noise,
quantization noise, and clock jitter. It's interesting to note that averaging K samples of a
random variable, say thermal noise, results in a reduction of its RMS value
σ therm σ2
σ K,therm = or σ 2K,therm = therm (33.30)
K K

The shape of the Gaussian PDF gets taller and narrower as we average the random signal.
The area, however, remains constant and equal to one. Rewriting Eq. (33.29) and
including the effects of averaging the signal and noise results in
Vp / 2
SNR= 20 ⋅ log + 10 ⋅ log K (33.31)
σ 2therm + V 2Qe,RMS + P AVG,jitter

which shows, once again, that averaging can be employed to increase SNR.
The Spectral Characteristics of Thermal Noise
Examine Fig. 33.80 where we've eliminated the DC bias and have shown the random
current sources used to model each resistor's thermal noise contributions to Vout. The RMS
noise current has a value (as given in Ch. 7) of
4kT
i2 = ⋅B (33.32)
R
where k is Boltzmann's constant (1.38 × 10−23 Watt⋅sec / K ), T is the temperature in
Kelvin, and B is the bandwidth over which the noise is measured. For the circuit shown in
Fig. 33.80, the RMS output noise voltage is
4kT 4kT
σ therm = V out,RMS = (R 1 R 2 ) ⋅ ⋅B+ ⋅B (33.33)
R1 R2
300 CMOS Mixed-Signal Circuit Design

V out

4kT ⋅ B R1 4kT ⋅ B R2
R1 R2

RMS noise sources

Figure 33.80 Modeling thermal noise in a resistor.

As indicated in Ch. 7, to perform a noise analysis we (1) add RMS noise voltages to the
circuit, (2) determine the RMS output noise from each contribution using superposition
(i.e., with only one noise source in the circuit at a time), and (3) square each contribution
followed by summing and taking the square-root to get the output noise (as a function of
the bandwidth B).
Note that even with both sides of a resistor connected to ground (no DC current),
a noise current (electrons) will move back and forth from the ground to the resistive
material at each connection as long as T > 0 K . In other words, a noise current will still
be present in the circuit.
Reviewing Eq. (33.32) for a moment would reveal that if we reduce the bandwidth
of a measurement (pass the signal plus noise through a narrow band filter) we get a
corresponding reduction in the RMS noise present in the signal. Spectrum analyzers use
narrow band filtering for this reason: to get extremely large dynamic range. The PSD of
the thermal noise voltage specified by Eq. (33.33) is plotted in Fig. 33.81. The output
noise power is given by
fH

P AVG = σ 2therm = V 2out,RMS = ∫ P therm ( f ) ⋅ df = 4kT ⋅ (R 1 R2) ⋅ B (33.34)

fL

where
B = fH − fL (33.35)
We now need to discuss how to determine the bandwidth, B.

P therm ( f ), V 2 /Hz

4kT ⋅ (R 1 R 2 )

Figure 33.81 Thermal noise power spectral density for Eq. (33.33).
Chapter 33 Submicron CMOS Circuit Design 301

Noise Equivalent Bandwidth

Any real circuit will not operate over the infinite bandwidth indicated in Fig. 33.81.
Consider the simple RC lowpass filter shown in Fig. 33.82. The noise circuit, after using
superposition (shorting the input voltage source, Vin , to ground) is also seen in this figure.
Note that a capacitor doesn't generate noise (although, as we'll see in a moment, it does
limit the RMS output noise in the circuit).

R
V in V out V out

C 4kT R C
R

Noise circuit

Figure 33.82 Circuit used to determine NEB.

The output noise power for the circuit of Fig. 33.82 can be determined using
∞
V 2out,RMS = ∫ 4kTR ⋅ 1 ⋅ df (33.36)
0
1 + (2πf ⋅ RC) 2
Knowing
du 1 u
∫ a 2 + u 2 = a tan −1 a + C (33.37)

then
f 3dB

1 ∞
V 2out,RMS = 4kTR ⋅ ⋅[tan −1 2πf ⋅ RC] 0 (33.38)
2π ⋅ RC
or
V 2out,RMS = 4kTR ⋅ f 3dB ⋅ π (33.39)
2
The noise equivalent bandwitdth (NEB) is then
NEB = f 3dB ⋅ π (33.40)
2
Figure 33.83 shows the interpretation of this equation. The area from DC to the NEB is
equal to the area under the actual response. Note that Eq. (33.39) reduces to

V 2out,RMS = kT (33.41)
C
which is our familar result for the RMS thermal output noise power of an RC circuit (kay
tee over cee noise).
302 CMOS Mixed-Signal Circuit Design

V 2 /Hz
NEB = f 3dB ⋅ π
2
4kTR ⋅ 1
1 + (2πf ⋅ RC) 2 Same area

f
f 3dB

Figure 33.83 Showing the same area in the NEB and the actual spectrum.

As an example of where we can use NEB consider the

dominant-pole-compensated op-amp in a unity follower configuration shown in Fig.
33.84a. It's important to note that noise is always measured on the output of a circuit and
then referred back to the input, Fig. 33.84b. Also note that we are assuming the op-amp
can drive the possibly low input resistance of the spectrum analyzer. If not, as we'll see
when characterizing the noise performance of MOSFETs, we'll need to introduce a
low-noise amplifier (LNA) in between the circuit-under-test and the spectrum analyzer for
isolation.
To calculate the RMS input-referred noise voltage, we can remember that the unity
gain frequency of an op-amp, fu, is related to the op-amp's 3-dB frequency and open loop

Spectrum V( f )
analyzer
f

0.75 Assuming a white noise spectrum

(a)

Input-referred noise spectrum Measured output noise spectrum, V( f )

Here V( f ) = V in ( f )
V in ( f )
(b)

Figure 33.84 (a) Measuring op-amp output noise spectral density and, (b) noise
model where output noise is referred back to the input.
Chapter 33 Submicron CMOS Circuit Design 303

gain, AOL, using f 3dB = f u /A OL . Assuming the op-amp is the limiting bandwidth factor in
the circuit, the RMS input-referred noise is given by
fu π
V in,RMS = V( f ) ⋅ ⋅ (33.42)
A OL 2
NEB

This assumes V( f ) is a constant magnitude number (white noise) vs. frequency. (White
noise is analogous to white light where the spectrum of white light is occupying all
frequencies of interest with equal amplitude.)
In a CMOS op-amp we'll be able to use NEB to get an idea for the circuit noise,
especially if the circuit bandwidth is wide. However, because of flicker noise (1/f noise
discussed in Ch. 9) present in MOSFETs we will need to use Eq. (33.34) to get an exact
idea for the output RMS noise. Equation (33.34) is rewritten as
fH

V 2out,RMS ( f ) = ∫ V 2 ( f ) ⋅ df (33.43)
fL

where now the measured noise output spectrum, V( f ) , is not a constant but changes with
frequency. The RMS input-referred noise can be determined for a particular circuit
configuration using
fH
V2 ( f )
V 2in,RMS ( f ) = ∫ H( f ) 2
⋅ df (33.44)
fL

where H( f ) is the transfer function of the circuit.

MOSFET Noise
The noise mechanisms present in MOSFETs (thermal and 1/f ) were discussed back in Ch.
9. Figure 33.85 shows how a low-noise amplifier (LNA) keeps the spectrum analyzer from
loading the MOSFET-under-test and is used to set the drain voltage of the MOSFET. In
order to simplify the calculations in the following discussions, we will write the total noise

i 2therm + i 21/f , A 2 /Hz

MOSFET noise
1/f

LNA Spectrum -10 dB/decade

noi

analyzer
se
dom

1/f noise corner

Sets drain voltage and
ina

provides isolation
tes

Thermal noise dominates

Sets drain current 1k 10k 100k f

Figure 33.85 Determining MOSFET noise.

304 CMOS Mixed-Signal Circuit Design

power of both contributions from thermal noise and 1/f noise (flicker) in a MOSFET's
drain current as i 2noise or
i 2noise = i 2therm + i 21/f (33.45)
Because noise is always measured on the output of a circuit and referred back to
the input for comparison with the input signal we can use either of the circuits shown in
Fig. 33.86 for performing simple noise analyses in our CMOS circuits.

g m v gs = i d
i 2noise /g 2m
i 2noise

Figure 33.86 Modeling MOSFET noise.

Noise Performance of the Source-Follower

Examine the source-follower configuration shown in Fig. 33.87. The input-referred noise
voltage (the noise added to the input signal) is
 
V 2in ( f ) = (i 2noise1 + i 2noise2 ) ⋅  12 + r 2o  (33.46)
 g m1 
By increasing gm1 (making the gain of the source-follower approach one), the
input-referred noise can be minimized (ultimately approaching the measured output noise
[i 2noise1 + i 2noise2 ] ⋅ r 2o ). This statement alone isn't too useful because increasing the biasing
current flowing in M1 (and M2) will increase gm1 but not necessarily decrease the

VDD VDD

In
M1 M1 i 2noise1
Out In
Out
Bias M2
Bias
i 2noise2

Figure 33.87 Noise performance of the source-follower.

Chapter 33 Submicron CMOS Circuit Design 305

input-referred noise. Increasing the biasing current will also cause the noise currents to
increase (as discussed in Ch. 9). To increase gm1 without changing the noise currents we
must increase the width of M1. While increasing the width improves the noise
performance, it slows down the inherent speed of the circuit because of the drop in ∆V
(and thus fT ). However, speed is usually not a concern with a source-follower (under light
to reasonable load conditions) because its bandwidth approaches fT . The point here is that
increasing the width of the MOSFET whose gate is connected to an input node can be
used in any amplifier to reduce the input-referred noise assuming constant drain current.
An important use of the source-follower is in small-input capacitance amplifiers
(such as charge amplifiers used in charge-coupled devices [CCDs]). Because the AC input
voltage is ideally equal to the AC output voltage, the voltage change across the gate-
source capacitance is zero. This means that the input capacitance of the source-follower in
Fig. 33.87 is set by the gate-drain capacitance of M1 (and, compared to a common-
source amplifier, is considerably smaller). However, because the voltage gain of the
source-follower is one the input-referred noise contributions from the amplifier connected
to the output of the source-follower are referred directly back to the source-follower's
input without any amplitude reduction. To understand this statement in more detail, let's
consider the noise performance of a cascade of amplifiers.
Noise Performance of a Cascade of Amplifiers
Consider the cascade of amplifiers shown in Fig. 33.88. Here we are assuming the
amplifiers have infinite input resistance (the amplifier input is the gate of a MOSFET; the
amplifiers amplify an input voltage). If this isn't the case, then we need to model the
input-referred noise with both voltage and current generators to account for the loading
on the amplifier output. As seen in the figure, referring all three stage's noise contributions
back to the overall amplifier input results in
V22 ( f ) V 23 ( f )
V 2in ( f ) = V 21 ( f ) + + 2 2 (33.47)
A 21 A1A2

V 21 ( f ) V 22 ( f ) V 23 ( f )
In A1 A2 A3 Out

First stage Second stage Third stage

In A1 A2 A3 Out

V 21 ( f ) + V 22 ( f )/A 21 + V 23 ( f )/A 21 A 22

Figure 33.88 Noise performance of a cascade of amplifiers.

306 CMOS Mixed-Signal Circuit Design

Stage two's input-referred noise, V 22 ( f ) , is referred back to the overall amplifier's input by
dividing by the first stage's gain, A 21 . If the first stage's gain is one then the second-stage's
input-referred noise appears directly on the overall amplifier's input (which is the case
when using a source-follower as the first amplifier). However, if the first stage has a large
gain, then the contributions from the following stages are negligible. The point here is that
to minimize the input-referred noise the gain of the first stage should be large.
For the basic op-amp shown in Fig. 33.70 the noise performance is dominated by
both the first-stage diff-amp and the second-stage amplifier made up of the cascoded
transistors and floating-current source. The voltage gain of the diff-amp will be close to
one making the second stage's input-referred noise reflect directly back to the input of the
op-amp. Again, for low-noise design, we want large first-stage gain.
To minimize a diff-amp's input-referred noise (see Ch. 24), we can increase the
widths of the diff-pair. As discussed earlier, this also minimizes both the systematic and
random offsets in an op-amp and increases the input common-mode range. The cost of
these benefits, again, is the lowering of the parasitic poles (ultimately affecting op-amp
stability) that the diff-pair introduces into the op-amp's overall transfer function. The fT of
the two MOSFETs used in the diff-pair decreases.
It's interesting to note that an amplifier's offset voltage can be thought of as a
special case of noise at DC. This means that Eq. (33.47) can be applied to determine the
importance of amplifier offset in a cascade of amplifiers. (Replace V[ f ] with VOS in Eq.
[33.47].) Note that because of the small voltage gain of the diff-pair used in our
mixed-signal op-amp of Fig. 33.70, the topology can have a relatively large systematic
offset voltage (e.g. 5 mV). The noise and offset performance of this op-amp, however, is
no worse than that of the folded-cascode amplifiers presented in Ch. 25. Folded cascode-
based op-amps also use a low-voltage gain in the input diff-pair. For circuit techniques to
reduce both noise and offsets (chopper stabilization, offset storage, and correlated double
sampling) the reader is referred to [9].
DAI Noise Performance
Figure 33.89 shows the DAI (see Fig. 31.78) with kT/C noise sources shown. The input-
referred noise is given by

V 2in,RMS = kT (33.48)
CI
in series with both v1 and v2. A total of 2kT/C I is sampled onto CI during each clock cycle.
If the input signal can swing from VDD to ground, then we can estimate the SNR using

VDD/  2 2 
SNR = 20 log (33.49)
2kT/C I
If VDD = 1.5 V, T = 300K, and CI = 100 fF then the maximum SNR is 68 dB (roughly
11-bits of resolution). Equation (33.49) is useful in determining the minimum value of
capacitors used in a DAI for a specific application.
Chapter 33 Submicron CMOS Circuit Design 307

φ1 φ2
CF
V CM CI
V out
v1
v2
kT/C I kT/C I
Sampled onto C I when φ 1 switches close.

Sampled onto C I when φ 2 switches close

Figure 33.89 Noise performance of the DAI.

REFERENCES
[1] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS: Circuit Design, Layout, and
Simulation, Wiley-IEEE, 1998. ISBN 0-7803-3416-7
[2] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge
University Press, 1998. ISBN 0-521-55959-6
[3] C. Enz, F. Krummenacher, and E. Vittoz, "An analytical MOS transistor model
valid in all regions of operation and dedicated to low-voltage and low-current
applications," Journal on Analog Integrated Circuits and Signal Processsing,
Kluwer Academic Publishers, pp. 83-114, July 1995
[4] M. Bucher, C. Lallement, C. Enz, F. Théodolz, and F. Krummenacher, Electronics
Laboratories, Swiss Federal Institute of Technology (EPFL), Lausanne,
Switzerland. Available at http://legwww.epfl.ch/ekv/index.html
[5] D. P. Foty, MOSFET Modeling with SPICE: Principles and Practice,
Prentice-Hall, 1997. ISBN 0-13-227935-5
[6] D. I. Hariton, Floating MOS Capacitor, U.S. Patent 5,926,064, July 20, 1999.
[7] J. Yuan and C. Svenson, "High-Speed CMOS Circuit Technique," IEEE Journal
of Solid State Circuits, Vol. 24, No. 1, pp. 62-70, February 1989.
[8] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching
Properties of MOS Transistors," IEEE Journal of Solid State Circuits, Vol. 24,
No. 5, pp. 1433-1440, October 1989.
[9] C. C. Enz and G. C. Temes, "Circuit Techniques for Reducing the Effects of
Op-Amp Inperfections: Autozeroing, Correlated Double Sampling, and Chopper
Stabilization," Proceedings of the IEEE, Vol. 84, No. 11, pp. 1584-1614,
November 1996. Available at http://cmosedu.com
308 CMOS Mixed-Signal Circuit Design

QUESTIONS
33.1 Regenerate the plots shown in Fig. 33.1 using an L of 5 µm and a W of 15 µm. Do
the curves look similar? Could we use the level 1 model with long L devices?
33.2 Can we use a native MOSFET in an application where we need a small threshold
voltage? What are the limitations?
33.3 Sketch the implementation of a floating capacitor that uses a MOSFET switch to
connect the source/drain/bulk to ground. Show the capacitor used in a DAI, Fig.
31.78. Assume the switch connected to the capacitor is clocked with the φ1 clock
(why?). Explain the operation of the circuit.
33.4 Sketch the practical layout of a 10k n+ poly resistor using a silicide block.
33.5 Verify the error in Fig. 33.18 is due to differing device drain-source voltages.
Show that using an even longer length device can result in less error.
33.6 If the drawn area of a source implant is 100 m2, what is the actual area if a scale
factor of 0.15 µm is used.
33.7 Using Eqs. (33.3) and (33.4), estimate the high-to-low and low-to-high delays in
the circuits shown in Fig. 33.90.

40/20 40/20
In Out In
1 pF

Figure 33.90 Circuits used in problem 33.7.

33.8 Using WinSPICE results, tabulate the output amplitude of the circuit in Fig. 33.32
against capacitive load.
33.9 Show that kickback noise on the inputs of the comparator shown in Fig. 33.34
using simulations. Show adding the circuit of Fig. 33.91 (a source-follower) to
each input of the comparator will drastically reduce kickback noise.
33.10 Modify the design of the digital input buffer shown in Fig. 33.39 using the
topology shown in Fig. 33.78. Show that the circuit still functions as expected
using simulations.
33.11 Show, using simulations, that the circuits in Fig. 33.47 do indeed behave as
counters.
33.12 Verify the operation of the element in Fig. 33.50 as a 1-bit adder.
Chapter 33 Submicron CMOS Circuit Design 309

VDD

10/50
Out

In
20/1

Figure 33.91 A source-follower used to reduce kickback noise.

33.13 Do the capacitors in Fig. 33.51 slow down the operation of the diff-amp? Why?
33.14 Estimate the input common-mode range of the diff-amp shown in Fig. 33.51.
33.15 Regenerate the plots shown in Figs. 33.54 and 33.55 if the drain-source voltages
of the MOSFETs are increased to 1.5 V. Why did the transconductance increase?
33.16 Show, using simulations, that a MOSFET's transition frequency does increase with
increasing gate-source voltage and decreasing length.
33.17 Do any of the MOSFETs in Fig. 33.58 move into the triode region if the resistor's
value is decreased to 1k? Verify your answers with simulations.
33.18 Compare the cascode current mirror performance shown in Fig. 33.61 to a basic
current mirror. Show the increase in output resistance when using a cascode and
compare the minimum voltages across the mirrors.
33.19 What happens in Fig. 33.65 to the current flowing in the push-pull amplifier if we
increase the lengths of MC1 and MC2?
33.20 Estimate the minimum VDD allowed for proper operation of the diff-amps shown
in Fig. 33.69.
33.21 If, in Fig. 33.70, V GS = V SG = 0.5 V and ∆V = V DS,min = 0.1 V what is the minimum
allowable power supply voltage, VDD, for proper op-amp operation.
33.22 Sketch the implementation, based on the topology of Fig. 33.70, of a wide-swing
op-amp with rail-to-rail input common-mode range. Assume the tail currents used
in the diff-amps use 20/2 (NMOS) and 40/2 (PMOS) devices (half the current
flowing each MOSFET of the diff-pair) so that summing the currents in the circuit
of Fig. 33.75 at the top and bottom nodes doesn't cause any MOSFET to enter the
triode region.
33.23 Resketch Fig. 33.79 for the cases when the thermal noise is averaged. Show the
cases with K = 1, 2, 4, 8, and 16.
310 CMOS Mixed-Signal Circuit Design

33.24 Suppose a MOSFET is used as a switch connecting an input signal to a capacitor.

The MOSFET can be modeled, for noise purposes while the switch is on, as a
simple resistor, Fig. 33.82. When the capacitor is charged, zero current flows in
the MOSFET. Is the noise in the circuit due to thermal or 1/f (flicker) noise?
Why? Note that each time the MOSFET turns on we can think that an RMS noise
voltage of kT/C is sampled on the capacitor.
 Chapter

34
Implementing Data Converters

Minimum gate lengths in CMOS technology are falling below 100 nm [1]. This feature
size reduction is driven mainly by the desire to implement digital systems of increased
complexity in a smaller area. This natural trend in feature size reduction, with
accompanying reduction in supply voltage, can present challenges for the mixed-signal
design engineer. The accompanying lower supply voltage results in an inherent reduction
in dynamic range, decrease in SNR, and increasing challenges when implementing analog
circuitry with little, ideally zero, voltage overhead. This chapter focuses on these issues,
and others, related to the implementation of data converters in a digital, submicron CMOS
technology.
Data converters are fundamental building blocks in mixed-signal systems. This
chapter presents and discusses methods and trade-offs for designing CMOS data
converters in submicron CMOS. For DAC design, we focus on converters implemented
with resistors using R-2R networks. The benefit of, and reason we are focusing on, using
R-2R networks over other methods for DAC implementation, such as charge
redistribution [2] or current steering topologies [3], is the absence of good poly-poly
capacitors in a digital CMOS process, the desire for small layout area, and/or the ability to
drive an arbitrary load resistance. R-2R-based DACs can be laid out in a small area while
achieving resolutions in excess of 12-bits. Charge-scaling DACs require linear capacitors.
The layout area needed for these capacitors can often be very large and practically limit
both the resolution and accuracy of the DAC. Similarly, the implementation of
current-steering topologies can result in a very large layout area with limited resolutions,
generally less than 8 bits if integral nonlinearity (INL) is a concern and, more importantly,
if limited output swing and the requirement of known, fixed-load resistances are a
concern.
The first section of this chapter reviews current- and voltage-mode R-2R-based
DACs. The second section of the chapter discusses the use of op-amps in data converters,
while the third section presents an overview of general ADC implementations in
312 CMOS Mixed-Signal Circuit Design

submicron CMOS process. While we briefly discuss the future direction of ADCs, we
concentrate our discussion on the implementation of pipeline data converters.
The goal in this chapter is not to provide an exhaustive overview of data converter
design but rather to provide discussions and practical insight. We assume that the reader is
familiar with data converter fundamentals (discussed in Ch. 28) and data converter
architectures (discussed in Ch. 29). For example, the reader knows the difference between
differential nonlinearity (DNL) and integral nonlinearity (INL) or the difference between a
two-step flash ADC and a pipeline ADC.

34.1 R-2R Topologies for DACs

We begin this section by discussing R-2R DAC topologies. The problems encountered in
the traditional R-2R topologies with low-voltage overhead are illustrated. Also, concerns
related to the performance of the op-amps used in data converters (both ADCs and DACs)
are discussed. Finally, matching and accuracy concerns are presented along with
techniques to remove these imperfections using calibration.
34.1.1 The Current-Mode R-2R DAC
The R-2R DAC can be classified into two categories: voltage-mode and current-mode [4].
A current-mode R-2R DAC is shown in Fig. 34.1. The branch currents flowing through
the 2R resistors are of a binary-weighted relationship caused by the voltage division of the
R-2R ladder network and are diverted either to the inverting input of the op-amp (actually
the feedback resistor) or the noninverting input of the op-amp (actually VREF−). The
voltage on the R-2R resistor string at the X th tap (where X ranges from 0 to N – 1), in Fig.
34.1, can be written as
X
V TAPX = 2 N ⋅ (V REF+ − V REF− ) + V REF− (34.1)
2
where VREF+ and VREF− are the N-bit DAC’s reference voltages. The current that flows
through the 2R resistor at the X th tap is then
V TAPX − V REF− X
I TAPX = = 1 ⋅ 2 N (V REF+ − V REF− ) (34.2)
2R 2R 2
This current is summed at the inverting input of the op-amp and flows through the
feedback resistor to the DAC output, Vout. The output voltage of the DAC can be written
as
N−1
V out = V REF− − R ⋅ Σ (bX ⋅ I TAPX ) for V REF+ > V REF−
X=0
(34.3)

where bX is either a 1 or 0, or
N−1
V out = V REF− + R ⋅ Σ (bX ⋅ I TAPX ) for V REF+ < V REF−
X=0
(34.4)
Chapter 34 Implementing Data Converters 313

VDD
V REF+
V out
R 1 0
2R b N−1
TapN-1

R 1 0 V REF+ − V REF−
b N−2 1 LSB =
2R 2 N+1
TapN-2 (Output swing limited to VDD/2.)

R 1 0
b N−3
2R
1 0

Detail
b N−3 b N−3
R 1 0
b0
2R To resistor
Tap0
MOSFET channel resistance should be << 2R
under most circumstances only either NMOS
2R or PMOS devices need be used

V REF−

Figure 34.1 Traditional current-mode R-2R DAC.

Using these equations, we can see the main problem with the basic current mode topology
of Fig. 34.1 in a submicron CMOS process using low-power supply voltages, namely,
limited output swing. If VREF− is set to 0 V, with VREF+ > 0, then the output of the DAC
must be negative, which, of course, can't happen when the only power supply voltage is
VDD. If VREF− is set to VDD, then we can see from Eq. (34.4) that this would require Vout
> VDD. After reviewing Eqs. (34.1)-(34.4), we see that the range of output voltages
associated with the current mode R-2R DAC is limited to VDD/2, e.g., 0 to VDD/2,
VDD/2 to VDD or 0.25VDD to 0.75VDD, etc. Giving up half of the power-supply range
in a DAC and correspondingly reducing the dynamic range, is usually not desirable.
314 CMOS Mixed-Signal Circuit Design

By removing the requirement that the noninverting input of the op-amp be tied to
VREF− and that the feedback resistor be R (the same value used in the R-2R string), we can
increase the output range of the DAC. The output of the op-amp is level-shifted by the
voltage on the noninverting input of the op-amp and by increasing the closed-loop gain of
the op-amp. Similarly, we could add a gain stage to the output of the DAC (two op-amps
would then be used) to achieve wider DAC output swing. We don't cover these options
any further here because they either put more demand on the op-amp design, such as
increased op-amp open-loop gain and speed, or won't, in a practical implementation, result
in a rail-to-rail output swing.
34.1.2 The Voltage-Mode R-2R DAC
Figure 34.2 shows a schematic of a voltage-mode DAC. The voltage on the non-inverting
input of the op-amp can be written as
b N−1 ⋅ V REF+ + b N−1 ⋅ V REF− b N−2 ⋅ V REF+ + b N−2 ⋅ V REF−
V+ = + + ... + VREF− (34.5)
21 22
or, in general terms,
N
b N−k ⋅ V REF+ + b N−k ⋅ V REF−
V+ = Σ + V REF− (34.6)
k=1 2k

The output of the N-bit voltage-mode DAC can be written as

 N b ⋅V +b ⋅V 
V out =  1 + F  ⋅  Σ N−k REF+ k N−k REF− + V REF− 
R
(34.7)
 R I   k=1 2 
If the input code is all zeroes, with VREF−= 0, VREF+ = VDD, and the op-amp in the follower
configuration, then Vout = VREF−. If the input code is all ones, then the output of the DAC is
VREF+ − 1 LSB.
By using the voltage-mode DAC, we would seem to have solved the problem of
the limited output swing associated with the current-mode DAC of Fig. 34.1. However,
consider how the finite common-mode rejection ratio (CMRR) of the op-amp in Fig. 34.2
can affect the linearity of the overall DAC design. We know the effects of finite CMRR
can be modeled as a variable offset voltage, ∆V OS (see Ch. 25), in series with the
noninverting input of the op-amp that is a function of the change in the op-amp common-
mode voltage, ∆V C , or
∆V C
∆V OS = (34.8)
CMRR
We should see the problem at this point: that is, ∆V OS is in series with the R-2R resistor
string and will ultimately limit the linearity of the DAC. To further illustrate the problem,
let's assume the CMRR of the op-amp in Fig. 34.2 is 20 dB at 1 MHz. Since the
common-mode voltage on the input of the op-amp, again assuming VREF+ = VDD, VREF− =
0, and the op-amp in the unity follower configuration can range from zero to
approximately VDD, the change in the offset voltage used to model finite CMRR when the
Chapter 34 Implementing Data Converters 315

RF

VDD
RI

V out

V REF+

1 2R
0
b N−1
R
2R
b N−2
V REF+
R
2R detail
b N−3 to resistor
b N−2

2R
V REF−
b1
R MOSFET channel resistance
should be << 2R
2R

b0
V REF+ − V REF−
2R 1 LSB =
2N
(Assuming op-amp is in the
follower configuration)
V REF−

Figure 34.2 Traditional voltage-mode R-2R DAC.

DAC's inputs are changing at 1 MHz is 10% of VDD. At first glance we might simply
consider the resulting offset as a nonlinear gain error affecting only the large-signal
linearity (INL). However, it is unlikely in any practical op-amp design that the CMRR will
vary linearly with changes in the input common-mode voltage and so the small-signal
linearity (DNL) will be affected as well. Since, for this example, 1 LSB = VDD/2N, the
resolution of the DAC, because of the finite CMRR and assuming 1 LSB > ∆V OS , is
limited to 4 bits! Performing DC or audio-frequency tests on the voltage-mode DAC made
with an op-amp with a CMRR of, for example, 120 dB at DC results in no practical
316 CMOS Mixed-Signal Circuit Design

resolution limit (indicating that if DAC speed isn't a concern, the voltage-mode
configuration may still be used for high resolutions). Note how CMRR isn't a concern with
the current-mode R-2R DAC (assuming no secondary effects, such as common mode
substrate noise, are present on the input of the op-amp). For precision, high-speed data
converter design we must use an inverting op-amp topology where the inputs of the
op-amp remain at a fixed voltage.
34.1.3 A Wide-Swing Current-Mode R-2R DAC
We've shown that it is desirable to have a wide output swing, as is provided by the
voltage-mode R-2R DAC, while at the same time having a fixed input common mode
voltage, as is provided by the current-mode R-2R DAC. Figure 34.3 shows a wide-swing
current-mode R-2R DAC configuration that has a rail-to-rail output swing while keeping
the input common-mode voltage of the op-amp fixed at the common mode voltage, VCM ,
or (V REF+ + V REF− )/2 .
Like traditional current-mode R-2R DACs, the DAC scheme shown in Fig. 34.3
operates on currents. Using superposition and assuming VREF− is the reference for
calculations, we can show that the current flowing in the feedback resistor, RF , is given by
V REF+ − V REF− V REF+ − V REF−
IF = − + ⋅  1 ⋅ b N−1 + 1 ⋅ b N−2 + ... + N−1
1 ⋅b 
0 (34.9)
2R 2R  2 2 

noting the inversion used in the control logic of Fig. 34.3. The output voltage of the DAC
is then given, assuming R = RF , by
V REF+ − V REF−
V out = V REF− + + IF ⋅ R (34.10)
2
or

V out = V REF− + (V REF+ − V REF− ) ⋅  1 −  1 ⋅ b N−1 + 1 ⋅ b N−2 + ... + 1N ⋅ b 0   (34.11)

 2 4 2 
From this equation, we see that as the digital input code is sequenced through 000... to
111... the output of the DAC changes in steps of (V REF+ − V REF− )/2 N (= 1 LSB) from VREF+
(when the input code is 111...) to VREF− + 1 LSB (when the input code is 000...). Setting
VREF− to ground and VREF+ to VDD allows the DAC output to swing from rail to rail.
In practice, since any rail-to-rail output op-amp has high nonlinearity close to its
power-supply rails, a slightly “shrunk” output range from power rails is often desired. For
example, we can set VREF+ = 0.9·VDD and VREF− = 0.1·VDD. The output will change
between 10 and 90% of VDD centered at VDD/2. Another way to shrink the output range
is to make the feedback resistance RF smaller than R (as seen in Eq. [34.10]) by either
trimming or programming the value of the feedback resistor RF.
The matching between the resistors of the R-2R ladder is one of the most
important and limiting factors that determine the linearity (e.g., DNL and INL) of the
entire DAC. It is helpful, when designing any type of resistor string DAC, if we can
estimate the resistor matching requirements based on a desired resolution.
Chapter 34 Implementing Data Converters 317

R = RF
V REF+
2R VDD
0 MSB
1
b N−1 V out
R
2R
V REF+ + V REF−
b N−2 V CM =
2
R
0 2R
1 V REF+
b N−3
detail

0 2R to resistor
1 b N−2
b1
R
0 2R V REF−
LSB
1
b0
2R
V REF+ − V REF−
1 LSB =
2N

V REF−

Figure 34.3 Wide-swing current-mode R-2R DAC.

DNL Analysis
It was shown back in Ch. 29 that for a binary-weighted DAC the worst case DNL
condition tends to occur at midscale when the code transitions from 01…11 to 10…00.
Let's assume in a worst-case scenario the 2R resistance of the MSB input in Fig. 34.3 has
a maximum positive mismatch of ∆R, and all other resistors have a maximum negative
mismatch of –∆R. In this case, the current provided by the MSB has to match the sum of
currents provided by all other lower input bits plus one LSB. Again using the
superposition principle we can verify that the step error of the current flowing through the
feedback resistor RF, caused by the resistor mismatch at the midscale transition, is
approximately equal to
318 CMOS Mixed-Signal Circuit Design

V REF+ − VREF−  1  − V REF+ − V REF−

∆I = ⋅  1 − N−1  (34.12)
2(R − ∆R)  2  2(R + ∆R)
Assuming RF = R, the final output step error (DNL) is approximately

DNL = ∆I ⋅ R ≈ (V REF+ − V REF− ) ⋅  ∆R − 1N  (34.13)

 R 2 
For the DNL to be within 1 LSB (1 LSB equals to [V REF+ − V REF− ]/2 N ) the matching
required of the resistors is

Resistor mismatch = ∆R ≤ N−1

1 (34.14)
R 2
For a 10-bit data converter to have a DNL of less than 1 LSB requires the MSB resistor
to match within 0.2% (= ∆R/R) of the lower resistors (which were assumed to have the
same value, i.e., the maximum mismatch from the MSB resistor) in the R-2R string.
Equation (34.14) results in a pessimistic estimate for the matching required of the resistors
because the variation in resistance along the string does not vary abruptly at the MSB
resistor but rather, in most cases, varies linearly from LSB to MSB. As we'll see in the
experimental results discussed in the next section, the matching requirements results in a
practical limit of 10 bits for an R-2R-based converter with no special layout or circuit
techniques (for example, averaging process gradients by using multiple resistor strings or
using segmentation).
INL Analysis
Since any change of the 2R resistance in the MSB has the largest influence on the ladder
output current among that of all the branch resistors (2R), the worst case INL tends to
occur when the input code is 01…11. (The gain error is nulled from the INL calculation
here, and therefore there is no INL error, but a gain error instead, if all the resistors have a
maximum mismatch.) Assuming that the 2R resistance of the MSB has a maximum
positive mismatch of ∆R/R, the error in the current flowing through RF from its ideal value
caused by the resistance mismatch is
V REF+ − VREF− V REF+ − V REF− V − V REF− ∆R
∆I = − ≈ − REF+ ⋅ (34.15)
2(R + ∆R) 2R 2 (R + ∆R) ⋅ R
The worst-case INL tends to occur, assuming RF = R, when
V REF+ − V REF−
INL = −∆I ⋅ R ≈ ⋅ ∆R (34.16)
2 R + ∆R
For the INL to be within 1 LSB, this also approximately yields

Resistor mismatch = ∆R ≤ 1 (34.17)

R 2 N−1
Again, as was mentioned in the DNL analysis, this is a pessimistic estimate if the sheet
resistance varies linearly with distance. Equations (34.14) and (34.17) indicate that a
resistance matching to within 1/2N is required for less than ½ LSB of DNL and INL for the
DAC scheme in Fig. 34.3. Layout of R-2R resistors was discussed in Ch. 33.
Chapter 34 Implementing Data Converters 319

Switches
The switches (MOSFETs) used in the R-2R DAC should have an effective switching
resistance (see Eqs. [33.3] and [33.4]), much less than the resistors used in the R-2R
ladder. The inherent switching time of the switches is extremely fast (speeds comparable
to logic gate delays). Since the switches are in series with the branch resistances of the
R-2R ladder, the R-2R relationship is broken if the switch resistance is not negligible, and
this affects both the INL and the DNL. Also note that we can try to compensate for the
switch-effective resistance by making the length of the 2R resistor slightly shorter than the
length of the R resistor. However, if not careful, this may lead to problems over the
process corners and temperature.
Experimental Results
The wide-swing, current-mode R-2R DAC, based on the scheme in Fig. 34.3, was
fabricated in a 0.21 µm/1.8 V CMOS process (single poly, up to five layers of metal) for
resolutions of 8, 10, and 12 bits. The cell dimensions of the 12-bit DAC are 150 µm by
300 µm. The goal of the experimental results was to verify that the topology of Fig. 34.3
would indeed perform as predicted by Eqs. (34.14) and (34.17) and to generate a
low-power, small-area DAC cell for general-purpose, mixed-signal circuit designs.
Unsilicided n+ poly was used for the R-2R resistances as discussed earlier (see Table
33.1). The mismatch indicated in Table 33.1 for an unsilicided n+ poly resistor is 0.005
(= ∆R/R). Using Eqs. (34.14) and (34.17), we would estimate that our resolution is
limited to 8.6 bits if we want both INL and DNL less than 1 LSB. The results in Table
34.1, however, show that the resolution is better than estimated. This may be because of
our pessimistic assumption of how the resistor values change with position as discussed in
the derivation of these equations. The nominal resistor value used in these experimental
DACs is 10k. To enhance the resistance matching, dummy resistors are implemented at
both ends of the R-2R ladder (see Fig. 33.13). The output range of the DAC is
programmable by choosing the value of the feedback resistance or by the setting of the
reference voltages VREF+ and VREF−.

8-bit 10-bit 12-bit

DNL (LSB) 0.150 0.450 2.000
INL (LSB) 0.200 1.000 3.000
Settling time 200 ns
Power 3.88 mW (driving a 1k load)
2
Area (mm ) 0.045
fclk,max 4 MHz
Output swing 0 < Vout < VDD (= 1.8 V )

Table 34.1 Summary of experimental results.

320 CMOS Mixed-Signal Circuit Design

The measured INL and DNL profiles of the three DACs with resolutions of 8, 10,
and 12 bits are shown in Fig. 34.4. The outputs of the DACs are configured to swing to
both rails (VREF+ = VDD and VREF− = 0). The first several points, adjacent to the two rails,
are not shown in Fig. 34.4 due to the high nonlinearity of the op-amp in those regions.
Major performance results are maximum DNLs of 0.15 LSB, 0.45 LSB, and 2 LSB for
8-bit, 10-bit, and 12-bit resolutions, respectively, with no special circuit techniques (laid
out as shown in Fig. 33.13) or trimming (adjustments). The corresponding maximum DAC
INLs are 0.2 LSB, 1 LSB, and 3 LSB, respectively. Notice that the LSB of the 8-, 10-,
and 12-bit DACs are 7.03 mV, 1.75 mV, and 439 µV, respectively. The DNL/INL can be
written in terms of a voltage as 1.05 mV/1.4 mV for the 8-bit DAC, 0.788 mV/1.75 mV
for the 10-bit DAC, and 0.878 mV/1.31 mV for the 12-bit DAC. The measurements were
taken while the DAC was driving a 1k load. The power dissipated by the DAC, with 1.8 V
output, while driving a 1k resistor is 3.88 mW. The unloaded power dissipation of the
DAC is approximately 500 µW. The DACs were designed using op-amps with simulated
unity gain frequencies of 10 MHz. The measured DAC settling time was approximately
200 ns.

LSB DNL Profile (8-bit) LSB INL Profile (8-bit)

0.15 0.3
0.1 0.2
0.05 0.1
0 0
-0.05 -0.1
-0.1 -0.2
-0.15 -0.3
0 50 100 150 200 250 0 50 100 150 200 250

LSB DNL Profile (10-bit) INL Profile (10-bit)

LSB
0.5 1.2
0.4
0.3
0.9
0.2 0.6
0.1 0.3
0 0
-0.1 -0.3
-0.2
-0.3 -0.6
-0.4 -0.9
-0.5 -1.2
0 200 400 600 800 1000 0 200 400 600 800 1000

LSB DNL Profile (12-bit) INL Profile (12-bit)

LSB
2 3
1.5
2
1
0.5 1
0 0
-0.5
-1
-1
-1.5 -2
-2 -3
0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000

Figure 34.4 Experimental results for the wide-swing DAC of Fig. 34.3.
Chapter 34 Implementing Data Converters 321

Improving DNL (Segmentation)

After reviewing the DNL plots in Fig. 34.4, we see that the worst-case DNL occurs when
the input code transitions from 01111... to 10000... (midscale) where the current in the top
2R should be 1 LSB (equivalent in current) greater than the sum of all of the currents
contributed by the lower resistors. As an example, consider the 12-bit R-2R ladder in Fig.
34.5 where we have used 1 µA to indicate an LSB of current contribution to the feedback
path. When the input digital code is 0111 1111 1111, the feedback current is 2047 µA.
When the code changes to 1000 0000 0000, the feedback current becomes (ideally) 2048
µA. If a 1/2 LSB error (0.5 µA) is the maximum error allowable, then the accuracy
required of the currents when transitioning is 0.5/2048 or 0.0244%. If we use fewer bits,
say eight, then the accuracy required when transitioning from 255 µA to 256 µA is
0.5/256 or 0.2%.
Let's consider segmenting the upper four bits in Fig. 34.5 so that the four bits
control 16 segments each contributing 256-µA to the feedback current. This segmentation

V REF+
0 2048 µA IF
MSB
b 11 1
2R
R
1024 µA

b 10
2R
R
512 µA

b9 1 LSB = 1 µA
2R

0 2 µA
1
b1 2R
R
Contribution to the
0 1 µA
LSB feedback current
1 when bit is high
b0 2R
2R

V REF−
Figure 34.5 Showing how currents sum into the feedback current.
322 CMOS Mixed-Signal Circuit Design

makes attaining good DNL with less accurate components possible [5]. A segmented
wide-swing DAC is shown in Fig. 34.6. In this figure we've taken the upper four bits and
segmented their current contributions to the feedback resistor. If we use the numbers from
Fig. 34.5, then when the code 0000 1111 1111 (255 µA) transitions to 0001 0000 0000
(256 µA) the 1 output of the decoder goes high and the bottom resistor connected to the
output of the decoder contributes 256 µA to the feedback path. When the code changes
from 0001 1111 1111 (511 µA) to 0010 0000 0000 (512 µA), both lower outputs (1 and
2) of the thermometer decoder are high. Since the 1 decoder output continues to
contribute to the output current, the step height is set by the difference between the 2
decoder output and the contributions from the lower eight bits. This makes the accuracy

0 V REF+ R
3-bit thermometer decoder output
1
15 7 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
b 11 6 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0

Outputs
5 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0
4 0 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0
Thermometer

0 R
b 10 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
decoder

1 2
14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
b9
0 R 011 101 011 101 000
(3) Inputs
b8 1
1 R F = R/16

2R VDD
0
1
b7 V out

0 2R
1 VREF+ + V REF−
b1 V CM =
2
R
0 2R
1
b0
2R

V REF−

Figure 34.6 Segmentation in a wide-swing R-2R DAC.

Chapter 34 Implementing Data Converters 323

requirements for 1/2 LSB DNL in a 12-bit converter set by 8-bit matching. Note that
while segmentation reduces DNL error, it does nothing for INL. Segmentation can also be
used to reduce the glitch area associated with the changing DAC output.
Trimming DAC Offset
Figure 34.7 shows how the op-amp's offset voltage shifts the DAC's output. It may be
desirable in some situations to trim or remove this offset. The offset may be the result of
an inherent systematic offset in the op-amp or the result of random variations in the
characteristics of the MOSFETs used in the op-amp. An offset may also result because of
the voltage dependence of the resistors used to generate the common-mode voltage, VCM.

V out

V out

± V OS
+V OS
V CM −V OS Digital input code
(a) Showing offset voltage in an op-amp.
(b) DAC transfer curves showing offset.

Figure 34.7 Showing how an op-amp offset affects the DACs transfer curves.

Figure 34.8 shows one possible method to generate a common-mode voltage that
is adjustable with a digital code. Here again we are assuming that VCM is ideally 0.75 V.
We should recognize the R-2R ladder from Fig. 34.2. The output voltage of this ladder, as
seen in Eq. (34.6), is an analog voltage related to the digital input word (assuming the
voltage divider made up of Rbig and the two R resistors connected to the output in Fig.
34.8 doesn't load the circuit). Figure 34.9 shows the output of this circuit for all possible
digital input words when R is 10k and Rbig is 100k. The inset in Fig. 34.9 shows that the
adjustability of the output is approximately 1 mV. To decrease this value, we can either
increase Rbig (resulting in a decrease in the output swing) or increase the number of bits in
the R-2R DAC. The value, R, of the resistors on the output can be decreased, but this can
result in an increase in power dissipation.
Note that the accuracy required of the 5-bit DAC can be very loose. n-Well
resistors can be used to implement the offset trimming circuit to reduce area and power.
The main concerns are considering the possibility of substrate noise injection and making
sure that the same resistive material is used for the entire circuit. We wouldn't want the
temperature behavior of an n-well resistor used in a circuit with a poly resistor because the
temperature dependencies are different (the offset trimming would only be effective at the
temperature it was performed). Finally note that in a practical circuit it is a good idea to
324 CMOS Mixed-Signal Circuit Design

VDD = 1.5 V
VDD = V REF+
R
2R R big
b4 To op-amp + input
R
2R R
b3 Adjustable voltage
R
2R
b2
R Selected large so it doesn't load the R-2R
2R
b1 ladder and so we get a large attenuation
to the output.
R
2R
b0
1 LSB ≈ VDD ⋅ R/2
2R 2 N R/2 + R big
centered around V CM

Voltage-mode R-2R DAC

Figure 34.8 Trimming circuit for DAC offset.

Ideal output

Figure 34.9 Output of the circuit in Fig. 34.8 for all possible digital codes.
Chapter 34 Implementing Data Converters 325

add capacitors from the output of the circuit to both VDD and ground to ensure that the +
op-amp input is connected to a good AC ground.
Trimming or calibrating out the offset can be performed at a time prior to
packaging the chip, or it can be performed with some autocalibration sequence after the
chip has been fabricated where the output of the DAC is compared to a known voltage
reference. The concern, as with any calibration, is to adjust only one known error at a time
(known as orthogonal tuning in filter design). For example, the DAC may not have any
offset but may have an INL error for a given input code, Fig. 34.10a. If we were only to
look at this one input code, say 10000... (VCM in binary offset), we wouldn't know if the
error is an INL error or an offset error. After the offset is calibrated out, Fig. 34.10b, we
would then perform an INL calibration to pull the end-points of the transfer curve back to
the ideal straight line transfer curve.

V out V out
INL error

Ideal curve

Digital input code Digital input code

(a) DAC transfer curves before calibration. (b) DAC transfer curves after offset calibration

Figure 34.10 Showing how INL can be seen as an offset error.

Trimming DAC Gain

We assumed in Fig. 34.10 that the gain of the DAC was one, in other words, there wasn't
any gain error in the DAC's transfer function. If there is a gain error, the offset calibration
can lead to poorer INL. Consider Fig. 34.11a showing gain and INL errors without any
offset. Performing an offset calibration, Fig. 34.11b, can result in significant INL error.
We can avoid this situation by calibrating out the gain error by trimming the op-amp's
feedback resistor prior to offset calibration. A reference voltage close to the ends of the
transfer curve is used while adjusting the gain of the op-amp used in the DAC. If VREF+ is
less than VDD (to avoid op-amp saturation as its output approaches the supply rails), then
it can be compared directly to the output of the DAC (keeping in mind the maximum
output of the DAC may be V REF+ − 1 LSB). Having gone through all of this discussion, it
still would be nicer if we could simply perform two calibrations, offset calibration and INL
calibration, effectively using the INL calibration to remove the gain error. The drawback
of this two calibration method is the requirement that an INL calibration circuit be capable
of removing very large INL errors.
326 CMOS Mixed-Signal Circuit Design

V out V out
Ideal gain (slope)

Actual gain
INL

Digital input code Digital input code

(a) DAC transfer curves with gain error. (b) DAC transfer curves after offset
calibration with gain error.

Figure 34.11 Showing gain error and how it can cause problems in an offset calibration.

Improving INL by Calibration

We can calibrate out errors in our wide-swing DAC in two basic ways as seen in Fig.
34.12. The method shown in part (a) adds or subtracts a current from the feedback path to
adjust the DAC output to the correct value. In part (b) the noninverting input of the
op-amp is varied to force the DAC output to the correct value. The offset calibration
described earlier uses the method shown in part (b). Note that the resistance looking from
the inverting op-amp terminal back through the ladder to AC ground is simply R, so using
the method in part (b) results in a noninverting op-amp configuration with a gain of two.
(A variation of 1 mV on the + op-amp terminal causes an output variation of 2 mV.)
Because we already have a circuit, Fig. 34.8, to make adjustments to the DAC output and
the topology of part (b) doesn't provide any DC load to the calibrating voltage source and
provides the least interaction with the main R-2R ladder, we will use this topology to
illustrate how we can calibrate out INL errors.
Consider the calibration circuit shown in Fig. 34.13. In this figure the five most
significant bits of a 12-bit DAC, that is, b11, b10, b9, b8, and b7 are applied to the 12-bit
DAC and to the address input of a 32-to-1 MUX with 5-bit input and output words. The
MUX drives the R-2R circuit of Fig. 34.8. The 5-bit register feeding each MUX input is
used to store the calibration values. Again the calibration can be performed after the DAC
is manufactured or during its use by employing a self-calibration sequence. In this scheme
the DC offset calibration shown in Fig. 34.10 is simply one case of the 32 calibrations
performed. (The top five bits of the input word are 10000 for the DC calibration.) This
technique can be used to precisely set the linearity of the DAC, perhaps up to 16-bits.
Note that segmentation must still be employed to keep the DNL small. Also note that
adding a large capacitance, C, to the noninverting input of the op-amp can result in a long
time constant  ≈ R2 ⋅ C  , slowing the settling of the circuit and affecting the high-
frequency SNDR.
Chapter 34 Implementing Data Converters 327

R-2R
ladder
Fig. 34.3 V CM

Variable current
(a)

R-2R
ladder
Fig. 34.3

Variable voltage

(b)

Figure 34.12 Trimming the output of the DAC using (a) current and (b) voltage.

Digital 12 R-2R
input (12) ladder
Fig. 34.3 V out
5
Upper five bits
Address R-2R
5
5-bit Register 31 circuit
5-bit Register 30 MUX Fig. 34.8

Out
5-bit Register 2
5-bit Register 1 00010
5-bit Register 0
00000 (upper five bits all zeroes)

Figure 34.13 Calibration scheme for 12-bit DAC.

328 CMOS Mixed-Signal Circuit Design

34.1.4 Topologies Without an Op-Amp

We discuss the requirements of op-amps used in data converters in detail in the next
section. In this section we present an overview of topologies using voltage and current
mode DACs based on both R-2R and W-2W topologies (see Fig. 33.17). The benefit of
using a DAC with an op-amp is that an arbitrary load impedance (within reason) can be
connected to the DAC's output. Without the op-amp, the load impedance must either be
known, capacitive, or very large, since it will load the DAC's output and affect INL, DNL,
and, ultimately, the SNR. The benefits of not using an op-amp are faster-speed (with light
loads) and guaranteed stability.
The Voltage-Mode DAC
The simplest voltage-mode DAC is the R-2R string shown in Fig. 34.14. We should
recognize this circuit from both Figs. 34.2 and 34.8. For the moment we assume the load
is purely capacitive so that errors resulting from sourcing a DC current are not present in
the DAC. Here, through several examples, we discuss settling time, resistor voltage
coefficient, matching, and the effects of a DC load.

VDD

2R V out
b4
R CL RL
2R
b3
R
2R
b2

2R
R 1 LSB = VDD
2N
b1
R
2R
b0
2R

Figure 34.14 Voltage-mode (5-bit) DAC without an op-amp.

Example 34.1
Suppose a 10-bit, voltage-mode DAC with the topology given in Fig. 34.14 is
implemented where R = 10k and CL = 10 pF. Estimate the maximum clocking
Chapter 34 Implementing Data Converters 329

frequency we can use to clock the register supplying the input words to the DAC.
Verify your answer using SPICE.
For complete settling we require that the DAC be 10-bit accurate to within 0.5
LSBs over its full-scale range
N+1
Accuracy = 0.5 LSB = VDD/2 = 111 = 0.04883%
Full scale range (VDD) VDD 2
The time constant associated with the DAC and capacitive load is
RC L = 10k ⋅ 10p = 100 ns
We can use this time constant to relate the final ideal output voltage, Voutfinal, to the
actual output voltage, Vout, using
V out = V outfinal (1 − e −t/RC L )
or, relating this to the required accuracy,
1 = 1 − V out = e −t settling /RC L
2 N+1 V outfinal
The required settling time is then
t settling = RC L ⋅ ln 2 N+1 (34.18)
Using the numbers from this example results in tsettling = 762 ns. The SPICE
simulation results are shown in Fig. 34.15. The maximum clock frequency is then
estimated as

f clk,max = 1 = 1 (34.19)
t settling RC L ⋅ ln 2 N+1

For this example, fclk,max= 1.3 MHz. Note that the fundamental way to decrease the
settling time is to decrease the resistance in the R-2R ladder (assuming we have no
control over the load capacitance). The practical problem then becomes
implementing the switches (MOSFETs) with a resistance small compared to R. T

Figure 34.15 Example output for the 10-bit DAC in Ex. 34.1 showing settling time limitations.
330 CMOS Mixed-Signal Circuit Design

Example 34.2
Suppose that the 2R MSB resistor in the DAC described in Ex. 34.1 experiences a
0.5% mismatch. Estimate the resulting DACs INL and DNL. Use SPICE to verify
your answer.
The 0.5% mismatch (∆R/R or 1 σ [standard deviation]) is the mismatch specified
for the unsilicided n+ polysilicon resistors specified in Table 33.1. Again it is
desirable to use poly resistors because they sit above the substrate on the field
oxide and are more immune to substrate noise. Note that the voltage coefficient
can (will) also cause nonlinearities. However, instead of the worst-case situation of
an abrupt mismatch between the lower resistors and the MSB 2R resistor, as used
in this example, a first-order voltage coefficient error will cause a linear variation
of the resistor values from the LSB resistor up to the MSB resistor (and so the
effects of the voltage coefficient, for reasonably small values, are generally not
significant compared to the random mismatch effects).
Rewriting Eqs. (34.14) and (34.15) to estimate the maximum number of bits
possible with 1 LSB INL or DNL results in

N = 1 − 3.3 ⋅ log  ∆R  (34.20)

R
Using this equation with ∆R/R = 0.005 results, again, in N = 8.6 bits. For a 10-bit
DAC, we would estimate both the INL and DNL as 2.4 bits.
To verify these results using SPICE, let's input a code of 01 1111 1111 (ideally
748.5 mV) and then step the input code to 10 0000 0000 (ideally, 750 mV). With
the MSB 2R resistor changed to 20.1k (a 0.5% mismatch from its ideal 20k value)
the simulation results are shown in Fig. 34.16. With this mismatch the output of
the DAC is 750.4 mV when the input is 01 1111 1111. The INL with this input
code is 1.25 LSBs (roughly 1.9 mV). The INL when the input digital code is 10
0000 0000 is −1.25 LSBs. The DNL at this worst-case point is −2.5 LSBs. Note
INL = 1.25 LSBs

INL = 1.25 LSBs

Actual DAC output

Ideal response
1 LSB

DNL = 2.5 LSBs

01 1111 1111 10 0000 0000

Figure 34.16 Output if MSB resistor in Fig. 34.14 experiences a 0.5% mismatch.
Chapter 34 Implementing Data Converters 331

that the DAC is nonmonotonic (DNL < −1 LSB). An increase in the digital input
code results in a decrease in the output voltage. Nonmonotonic DACs can result in
circuits that don't function properly (an example being a successive approximation
ADC). A DNL of −1 LSB would indicate the output voltage of the DAC doesn't
change when the input code changes.
To improve the DNL, the upper bits of the DAC must be segmented as seen in
Fig. 34.6. Improving the INL relies on calibrating out the mismatch errors (see
Figs. 34.12 and 34.13). Also note, again, that mismatch can be improved by layout
techniqes (e.g., common-centroid) and by averaging the outputs of multiple
resistor strings. T
We can characterize the effects of a DC load resistance, RL , as seen in Fig. 34.14,
by noticing that RL forms a divider with the R-2R ladder. The LSB with a load can be
written as
RL
1 LSB = VDD ⋅ (34.21)
2N R + RL
Notice that if R L → ∞ , this equation reduces to the LSB value given in Fig. 34.14. The
time constant associated with driving an output capacitance can now be written as
τ = R R L ⋅ CL (34.22)
Two Important Notes Concerning Glitches
Note that we have assumed that the RC delay through the resistors used in the R-2R
ladder is negligible. This may not be the case in many practical situations (especially if
diffused or implanted resistors are used), resulting in a DAC output glitch. Also, we have
been simulating with perfectly aligned digital signals, that is, signals that change at the
exact same moment. When the digital signals are slightly misaligned, a significant glitch
can occur in the DAC's output. This means that the inputs to the DAC should be provided
by the same digital hold register. Using segmentation with the required thermometer
decoder can result in the digital signals driving the R-2R ladder seeing differing delays.
Care must be exercised when designing the DAC input clocking circuit (e.g., add small
dummy delays).

Example 34.3
Repeat Ex. 34.2 if a 200 ps skew is experienced by the lower nine bits in the digital
inputs with relation to the MSB.
The simulation results are shown in Fig. 34.17. When comparing this result to Fig.
34.16, the magnitude of the glitch in relation to the much smaller final step in the
output voltage should be obvious. The small 200 ps skew in the digital inputs
causes a code of 00 0000 0000 to be applied to the DAC for 200 ps. For this very
short period of time the output begins to discharge from 750 mV down to ground.
Note in this figure and in Fig. 34.16 the load capacitance was reduced to 0.1 pF to
decrease the settling time. T
332 CMOS Mixed-Signal Circuit Design

Glitch area ≈ 125 mV ⋅ 2 ns = 250 V ⋅ ps

Figure 34.17 Showing glitch if the lower 9-bits are skewed by 200 ps in Ex. 34.2.

The Current-Mode (Current Steering) DAC

Figure 34.18 shows the two basic cells used in the implementation of a current-mode
DAC. In this section we focus on the use of the current source-based cell. The advantage
of the current-source cell is the fact that the value of the current can be adjusted, via the
bias voltage, to compensate for process variations, while the value of the resistor, in the
resistor-based cell is fixed. The advantages of the resistor-based cell are wider output
swing (the MOSFET current source must remain in the saturation region), better voltage
coefficient (no channel length modulation or other finite MOSFET output resistance
effects), and better substrate noise immunity (assuming the resistors are integrated on the
top of the field oxide and not down in the substrate with the MOSFETs). Notice, in this
figure, that we've implemented the cells with two complementary outputs. Having
complementary outputs is useful, for example, in a DAC used with a video monitor
(driving two complementary 75 Ω loads). The load resistors are labeled the left load
resistor, RLL , and the right load resistor, RRL.

VDD VDD VDD VDD

Bias This simplified to This simplified to

R dac
I bias R dac

b b
b b
R LL R RL R LL R RL
R LL R RL R LL R RL

Current-source-based cell. Resistor-based cell.

Figure 34.18 Basic cell used in a current-mode DAC.

Chapter 34 Implementing Data Converters 333

Figure 34.19 shows the block diagram implementation of a current-mode DAC.

The output voltages depend on both IREF and the load resistors. The current sources are
implemented using the PMOS cell in Fig. 34.18 and a PMOS W-2W mirror (see Fig. 33.17
in the last chapter) to improve layout area. The combination of binary-weighted current
sources must be used together with the required segmentation of the upper bits to reduce
DNL. Although not drawn so in Fig. 34.18, the current sources can be cascoded to
increase their output resistance (decrease their voltage coefficient). Again the switches
connected to the loads should be controlled by signals from the same register to avoid
significant glitches in the outputs.
While the matching requirements of current-mode (current steering) DACs were
discussed in Ch. 29, we should comment on ways to improve matching before leaving this
section. The layout of the W-2W ladder should follow the basic techniques discussed in
Ch. 20, i.e., devices oriented the same way, use of dummy poly and diffusions, attempt to
keep the source-drain voltages constant, and use of long L devices. The layout of the
W-2W mirror should look similar to the layout of the R-2R string in Fig. 33.13, but it can
also employ two or more W-2W segments to average variations. The upper segmented bits

VDD I REF 7 V out+

V out−
7
Thermometer

b7 6 I REF 6
Segments
Decoder

5
b6 4 R LL R RL
3
b5 2
1 I REF 1

2 −1 I REF
b4
W-2W current mirror (see Fig. 33.17)

2 −2 I REF b
3

2 −4 I REF b 2

2 −8 I REF b 1

2 −16 I REF b 0

Figure 34.19 Implementation of a current-mode DAC.

334 CMOS Mixed-Signal Circuit Design

can be laid out adjacent to the W-2W and can also benefit from averaging the outputs of
several DAC layouts. In some cases the number of bits used in the W-2W ladder equals the
number of bits used for the upper segments. For example, a 10-bit DAC would use a 5-bit
W-2W ladder (whose MSB is IREF /2) and 31 segments with values of IREF (a total of 36
outputs as seen in Fig. 34.20a). To improve INL, the layouts are connected (see the
example common-centroid layout in Fig. 34.20b) together to, hopefully, average the
random mismatch effects and increase the linearity of the DAC. Of course, the current
output in the circuit of 34.20b is four times the current in 34.20a for the same reference
biasing levels.

and W-2W mirror

and W-2W mirror

Segments

Segments
Outputs

31
Segments
and W-2W mirror.

3
2
Segments

1
and W-2W mirror

and W-2W mirror

W-2W

Segments

Segments

(a) Layout block.

(b) Averaging the outputs of

several layout blocks to
improve linearity.

Figure 34.20 Layout of a current-mode DAC.

34.2 Op-Amps in Data Converters

The open-loop magnitude and phase responses of a typical op-amp are shown in Fig.
34.21. In this section we discuss the gain and bandwidth requirements of op-amps used in
either a DAC or an ADC. We assume that the op-amp is designed to have a phase margin
of 90 degrees under full load conditions and over process variations. (We should point out
that this assumption is easily met using an OTA that is compensated by a load capacitance
as discussed in Ch. 25.) It's important to understand why having a 90-degree phase margin
is important, namely, to avoid a second-order step response with the associated ringing. If
the phase margin is 90 degrees, we get an RC-like settling response shape as seen in Fig.
34.15. Figures 33.73 and 33.74 show the AC responses and step response of a basic
Chapter 34 Implementing Data Converters 335

20 log [A OL ( f )]
A OLDC
A OL ( f ) = f
A OLDC 1+j⋅ f
3dB

Assumes a dominant pole

op-amp (phase margin of
90 degrees)
f 3dB
0 dB f

0 f u ≈ f 3dB ⋅ A OLDC Gain margin

−45
−90
Phase margin
= 90 here
−180

Figure 34.21 Magnitude and phase responses of an op-amp.

mixed-signal op-amp. The phase margin of this op-amp was 70 degrees. The step response
shows a moderate amount of ringing. Decreasing the phase margin increases the peak
amplitude of the ringing and can lengthen the settling time (the time it takes the op-amp's
output to settle to within 1/2 LSB of the ideal final value). Note that the settling time, in
Fig. 33.74, was measured using an inverting op-amp topology. While we concluded, in
Sec. 34.1.2, that we must use an inverting op-amp (or a fully-differential topology where
the input common-mode voltage remains constant), it is still useful to look at the basic
speed (bandwidth) differences between noninverting and inverting topologies.
Gain Bandwidth Product of the Noninverting Op-Amp Topology
Figure 34.22 shows the basic topology of a noninverting op-amp amplifier. The voltage on
the inverting op-amp input can be written as
β

R1
v − = V out ⋅ (34.23)
R1 + R2
where β is the feedback factor for this series-shunt feedback amplifier (the ideal closed-
loop gain, ACL , is 1/β or 1 + R2/R1). The output of the amplifier is
V out = (V in − v − ) ⋅ A OL ( f ) (34.24)
Solving these equations for the closed-loop bandwidth of the amplifier, fCL,3dB, gives
f CL,3dB ≈ β ⋅ A OLDC ⋅ f 3dB = β ⋅ f u (34.25)
336 CMOS Mixed-Signal Circuit Design

R2

R1
v−
V out = A OL ( f ) ⋅ (v + − v − )
v+
V in

Figure 34.22 Noninverting op-amp topology.

The gain bandwidth product of the noninverting amplifier is then

Gain ⋅ bandwidth = f u (34.26)
Gain Bandwidth Product of the Inverting Op-Amp Topology
Figure 34.23 shows the schematic diagram of an inverting op-amp topology using an
op-amp. Summing the currents at the inverting input node gives
V in − v − v − − V out
= (34.27)
R1 R2
The output of the amplifier is related to the op-amp's input terminals using
V out = (−v − ) ⋅ A OL ( f ) (34.28)
Solving these two equations for the closed-loop bandwidth once again results in Eq.
(34.25) with β defined as indicated in Eq. (34.23). This can be confusing because the
feedback factor, β, for the inverting amplifier is not the same as for the noninverting
amplifier. The inverting op-amp is an example of a shunt-shunt amplifier (current input and
voltage output). The feedback factor for this amplifier is −1/R2 (= β) where
V out
= −R 2 (34.29)
i in
If we assume the input current source (Norton equivalent) has a source resistance of R1 so
that V in = i in ⋅ R 1 , we can write
V out R
A CL = = 2 (34.30)
Vin R1
Keeping in mind that closed-loop bandwidth of the inverting amplifier is still, from Eq.
(34.25),
R1
f CL,3dB ≈ ⋅ fu (34.31)
R 1 + R2
we can write
R2
Gain ⋅ bandwidth = ⋅ fu (34.32)
R1 + R2
Chapter 34 Implementing Data Converters 337

R2

R1
V in v−
V out = A OL ( f ) ⋅ (v + − v − )
v+

Figure 34.23 Inverting op-amp topology.

Example 34.4
Compare the bandwidth of a +1 gain amplifier implemented using a noninverting
op-amp topology (Fig. 34.22) to the bandwidth of a −1 gain amplifier using the
inverting op-amp topology (Fig. 34.23).
Using Eq. (34.26), the bandwidth of the +1 gain amplifier is fu. This amplifier is
commonly known as a unity voltage follower and has R 1 = ∞ (an open) and R 2 = 0
(a short). The bandwidth of the inverting, −1, gain amplifier can be determined
using Eq. (34.32) with R1 = R2 and is 0.5fu. This result is important because it
shows that for the fastest speed the noninverting op-amp topology offers the best
choice. Practically, however, the nonlinearities related to the finite CMRR (see Eq.
[34.8]) force the use of inverting op-amp topologies. As discussed earlier, the
input common-mode voltage must remain constant in any precision application.
Note that a fully-differential op-amp topology is also a shunt-shunt amplifier with a
gain bandwidth product given by Eq. (34.32). T

Example 34.5
Comment on the derivations of Eqs. (33.23)-(33.25) in the last chapter.
The equations are still valid; however, it would be more correct to use the value of
β given by the resistive divider in Eq. (34.23) instead of β = 1. For the test setup
shown in Fig. 33.74 β = 0.5 and so the settling time would more accurately be
estimated as 31.8 ns. T
34.2.1 Op-Amp Gain
In this section we answer the question of how large the DC open-loop gain of the op-amp,
AOLDC , must be in a data converter with a resolution of N bits. We know that the op-amp
must amplify signals to within 1/2 LSB of the ideal value. Further we know that the
closed-loop gain of an amplifier can be written as
A OL ( f )
A CL = (34.33)
1 + β ⋅ A OL ( f )
The feedback factor can be written, after reviewing Fig. 34.23 or Fig. 34.24, as
338 CMOS Mixed-Signal Circuit Design

R1 CF  1/jωC I 
β= or =  (34.34)
R1 + R2 C F + C I  1/jωC I + 1/jωC F 
where the capacitive dependence, or second term in this equation, is used when estimating
the feedback factor present in a DAI.

CF

CI
V in
V out

Figure 34.24 Inverting op-amp topology.

As we discussed in Ch. 29 the output of the amplifier will be equal to its ideal
value minus some maximum deviation, ∆A. We can write the gain of the DAI over one
clock cycle (treating the integration, z −1 /[1 − z −1 ] , as an initial DC condition on the
feedback capacitor) as
CI
A CL = (34.35)
CF
Then we can write
CI A OLDC
A CL = − ∆A = CF
(34.36)
CF 1 + A OLDC ⋅ C F+C I

If the maximum value of ∆A is at most 1/2 LSB of the ideal gain, or,
CI 1/2 LSB C 1/2 ⋅ (V REF+ − V REF− )/2 N C I
∆A = ⋅ = I ⋅ = ⋅ 1 (34.37)
C F Full scale output C F (V REF+ − V REF− ) C F 2 N+1
then we can estimate the minimum required DC open-loop gain as

A OLDC ≥ 1 ⋅ 2 N+1 (34.38)

β
If β = 1/2 , as in the R-2R DAC of Fig. 34.3 or in a DAI with C I = C F , then this equation
can be reduced to
A OLDC ≥ 2 N+2 (34.39)
A 12-bit ADC or DAC requires the use of an op-amp with a gain greater than 16k while a
16-bit converter must have A OLDC ≥ 256k. Clearly, this estimate can present a real design
concern. Note that Eq. (34.38) is optimistic. For a general design, an error of 1/2 LSB due
just to op-amp gain is not desirable (so a larger value of AOLDC must be used).
Chapter 34 Implementing Data Converters 339

34.2.2 Op-Amp Unity Gain Frequency

The speed of a data converter is mainly limited by the op-amp used. In general, the
minimum op-amp gain-bandwidth product ( fu) required for a specific settling time t
(where t is less than 1/fclk , within a dead band of ±1/2 LSB ) can be estimated, assuming
no slew-rate limitations (see also Eqs. [34.18] and [34.19]), by

V out = V outfinal  1 − N+1

1  =V
outfinal (1 − e
−t/τ
) (34.40)
 2 

where, once again,

τ= 1 (34.41)
2π ⋅ β ⋅ f u
The minimum required op-amp unity gain frequency is then given by
f clk ⋅ ln 2 N+1
fu ≥ (34.42)
2π ⋅ β
or, again assuming β =1/2,
f u ≥ 0.22 ⋅ (N + 1) ⋅ f clk (34.43)
If we design a 12-bit ADC that is clocked at 100 MHz, we need to use op-amps with unity
gain frequencies, fu , of 286 MHz (and a DC gain of at least 16k). Again, this estimate for
the unity gain frequency is optimistic. A good design would use a larger fu than what is
specified by Eq. (34.43).
34.2.3 Op-Amp Offset
A critical characteristic of any op-amp used in a data converter is its offset voltage. We
introduced the concept of reducing the offset voltage of an op-amp back in Ch. 27. Here
we provide additional comments and possibilities for offset reduction.
Adding an Auxiliary Input Port
A simple method of nulling the offset voltage of an op-amp is shown in Fig. 34.25 [6]. In
this figure the added MOSFETs, M1 and M2 (which operate in the triode region) are
essentially used to balance the current flowing in the current mirror load. We can think of
the added MOSFETs as providing an auxiliary input port for offset calibration.

VDD VDD

M1 M2 Adjust the voltage here

to trim offset voltage

To diff-amp
Figure 34.25 Trimming offset using an auxiliary input port.
340 CMOS Mixed-Signal Circuit Design

Figure 34.26 shows how we would use the auxiliary input port to remove (lower)
the offset. When zeroing out the offset, the op-amp is removed from the circuit by opening
S1 (and possibly a switch [not shown] in series with the op-amp's output). This is followed
by closing S2 and S3 so that a control voltage is stored on C. Note that we have assumed
that the op-amp is used in an inverting configuration (that is, the noninverting input of the
op-amp, +, is tied to VCM). The offset removal is dynamic and will have to be performed
periodically. We could also use a simple R-2R DAC with a topology similar to what is
seen in Fig. 34.8 to calibrate out the offset (eliminating the dynamic nature of the method).
The output of the DAC would be connected to the auxiliary input port. Note that an
increase in voltage on the auxiliary input port must result in a decrease in output voltage.
(There must be negative feedback when connecting the output of the op-amp to the input
port.)

S1 S2

V CM V out
S3

C
Auxilary input port

Figure 34.26 Using an auxiliary input port to lower offset.

The practical problem with the topology of Fig. 34.26 is the charge injection and
capacitive feedthrough resulting from shutting off (opening) S3. This "glitch" of charge
causes a change in the auxiliary port's input voltage and can place a significant limitation
on the minimum possible offset voltage attainable after calibration. The amplitude of the
glitch can be reduced by increasing C or by increasing the length of the MOSFET used in
the op-amp (M2 in Fig. 34.25). Increasing the length results in a decrease in the
MOSFET's transconductance (keeping in mind that the MOSFET is operating in the triode
region) making the amplitude of the glitch less harmful. The drawback of increasing the
MOSFET's length is that the range of offset voltages we can remove is reduced.

Example 34.6
Suppose perfect switches are available for the circuit of Fig. 34.26. Estimate the
residual offset voltage in terms of the op-amp's gain, AG, from the auxiliary port to
the op-amp output.
If the offset voltage before reduction is VOS, then the offset voltage after reduction
is VOS/AG. For reasonable values of AG the final inherent offset voltage is negligible.
The point of this example is that the charge injection and capacitive feedthrough
from the switches is the dominant source of offset error using this technique. T
Chapter 34 Implementing Data Converters 341

We've seen the problem of charge injection and capacitive feedthrough before. The
most common technique for reducing its effect is to use a fully-differential topology.
Figure 34.27 shows a modification of Figs. 34.25 and 34.26 to compensate for charge
injection. The idea is that when S4 and S3 turn off (open) the variation in voltages on the
gates of M1 and M2 are equal resulting in a common change in each MOSFET's
resistance. Ideally then the current will remain balanced in the diff-amp. Note that while
we've shown the use of triode-operating MOSFETs M1/M2 in Figs. 34.25 and 34.27 in
series with the load of a diff-amp on the input of an op-amp, we could also use this
concept in later stages of the op-amp.

VDD VDD S2
S1
V CM V out
M1 M2
S3

S4 C C
To diff-amp

Figure 34.27 Using an auxiliary input port to lower offset (two terminals).

Figure 34.28 shows another possible topology for offset removal using an auxiliary
input [7]. An additional diff-amp is added in parallel to the main input diff-amp stage of an
op-amp to balance the currents and zero out the offset voltage. Again, long length
MOSFETs are used in the added input so that the glitches resulting from the imperfections
in the MOSFET switches (S4 and S3 in Fig. 34.27) have the least effect on the operation
of the circuit.

Long L devices

Main input diff-amp

Auxiliary input port

Figure 34.28 Using an auxiliary diff-amp for balancing current in an op-amp's input.
342 CMOS Mixed-Signal Circuit Design

We can estimate the maximum offset voltage we can zero out using the technique
of Fig. 34.28 by writing the imbalance in the main diff-amp's currents because of its offset
voltage as
g m ⋅ V OS,max = i d (34.44)
The auxiliary input must sum the opposite of this current in the main diff-amp's load to
balance the currents in the main diff-amp (and hence eliminate the offset voltage). If we
label the transconductance of the diff-amp used in the auxiliary input gmaux and the
maximum allowable differential voltage on the auxiliary input for linear operation Vaux,max
then we can write
g m ⋅ V OS,max = g maux ⋅ V aux,max (34.45)
Because we are using long length devices in the auxiliary input g maux << g m for the same
biasing current levels. If V aux,max = 200 mV (a differential voltage of ± 200 mV will cause
all of the diff-amp tail current to flow through one side of the diff-amp) and
g m /g maux = 10, then we can zero out at most 20 mV of op-amp offset.
The offset storage technique shown in Fig. 34.27 relies on the removal of the
op-amp from the circuit while autozeroing the offset. The scheme in Fig. 34.29 shows
how the technique can be extended to remove the offset while leaving the main op-amp,
O1 in the circuit at all times. When S2, S3, and S4 are closed, the offset of O2 is zeroed
out. At this time switches S1 and S5 are open. After O2's offset is stored, S2, S3, and S4
are then opened. Next S1 and S5 close. O2 is used to precisely set the inverting input of
O1 to VCM through the feedback around O1 (not shown). When O2 goes back to zeroing
out its own offset (S2-S4 close) the capacitor connected to the auxiliary port of O1 retains
the charge, and thus voltage, needed to keep O1's offset nulled out to zero. Again this
capacitor should be large to avoid problems from the imperfections of S5.

O1
V CM V out

V OS

S2 O2
S1 V CM
S5
S3

S4

Figure 34.29 Continuous-time offset removal.

Chapter 34 Implementing Data Converters 343

34.3 Implementing ADCs

In this section we continue to discuss implementing data converters with design concerns
for S/Hs, cyclic ADCs, and pipeline ADCs.
34.3.1 Implementing the S/H
We assume the reader is familiar with the fundamental implementation of a CMOS S/H
discussed in Ch. 27. Figure 34.30 shows the more general implementation of a S/H. Note
that if CI goes to 0 (an open) this topology reduces to the basic S/H given in Ch. 27
(repeated in Fig. 34.31 for convenience).
We can determine the relationship between the input of the S/H and its output by
writing the charge stored on CI and CF when the φ1 and φ2 switches are closed (the φ3
switches are open) as
φ
Q I,F1 = C I,F ⋅ (V in − V CM ± V OS ) (34.46)
where VOS is the offset voltage of the op-amp and the input (and output) voltages are
referenced to ground (Vin [Vout] varies from 0 to 2VCM [= VDD here]). Note that the reason
why the φ2 switches turn off slightly after the φ1 switches is shown in Figs. 30.31 and
30.32 and in the associated discussion (bottom plate sampling). When φ3 goes high, the
charge on CI is
φ
Q I 3 = C I ⋅ (V CM − V CM ± VOS ) (34.47)

φ2 φ3

CF φ1
φ3 φ3
CL
V in+ CI
V out+
V CM
V in− CI V out−
CL
CF
φ1
to t1 t2 t3
φ3
φ1

φ2

φ3 Indicates plate closest to the substrate

Figure 34.30 Data converter S/H building block.

344 CMOS Mixed-Signal Circuit Design

φ3

φ2 φ1
CF φ3
V in+ V out+
V in− V out−
φ2 CF φ3
to t1 t2 t3 φ1
φ1

φ2
φ3
φ3

Figure 34.31 S/H differential topology from Ch. 27.

φ φ
The difference between Q I 1 and Q I 3 is transferred to CF when φ3 goes high. The output
voltage is then determined knowing charge must be conserved
C F ⋅ (V out − V CM ± V OS )
φ φ φ
Q F1 QI 1 QI 3

= C F ⋅ (V in − V CM ± V OS ) + C I ⋅ (V in − VCM ± V OS ) − C I ⋅ (V CM − V CM ± V OS )
(34.48)
or when φ3 goes high

V out =  1 + I  ⋅ V in − I ⋅ V CM
C C
(34.49)
CF CF
Notice how the op-amp offset is autozeroed out. The ideal residual offset is VOS/AOL.
Practically the residual offset is limited by the imperfections in the switches (which, once
again, forces us to use fully-differential topologies). Also note, in Fig. 34.30, that we have
drawn the input capacitance of the next stage as a load, CL. This was so that the output of
the S/H would appear to change only on the rising edge of φ3 (plus the output settling
time). Finally, if the S/H is clocked at fclk = 1/Tclk, the output of the S/H must settle to less
than 1/2 LSB, worst-case, in a time of Tclk/2. This means that the value of op-amp unity
gain frequency given by Eq. (34.42) should be doubled.
Chapter 34 Implementing Data Converters 345

Equation (34.49) can be used to determine the relationship between Vin and Vout for
fully-differential signals

V out = V out+ − V out− =  1 + I  ⋅ (V in+ − V in− )

C
 (34.50)
CF 
Note how, as we would expect, the common-mode voltage subtracts out of the
relationship when we take the difference between Vout+ and Vout−. A block diagram
representing the S/H of Fig. 34.30 is shown in Fig. 34.32. The use of block diagrams, as
we saw in Ch. 32 when discussing noise-shaping, can be very useful to describe data
converter architectures.

V in S/H V out

CI
1+
CF
Figure 34.32 Block diagram for the S/H of Fig. 34.30.

Example 34.7
Simulate the operation of the data converter S/H building block shown in Fig.
34.30. Assume CI = CF = 1 pF and fs = 100 MHz.
The simulation results are shown in Fig. 34.33. In part (a) the clock signals are
shown. Unlike the clock signals shown in Fig. 34.30 where the falling edge of φ2 is
delayed from φ1, the simulation sets the signals so they go low at the same time.
This was to avoid the outputs of the op-amp changing to very large values for the
small amount of time the op-amp operates open-loop with an input signal applied.
In part (b) we show the op-amp outputs. Note how, when φ1 goes high, both
outputs are set to the common-mode voltage by forcing the op-amp into a follower
configuration (which may lead us to use switches to short the terminals of the
op-amp to VCM when φ1 is high if offset isn't important). When φ3 goes high, the
circuit behaves as an S/H with a gain of two. Part (c) of the figure shows the
outputs connected through φ3 switches, as seen in Fig. 34.30, driving 10 pF load
capacitances. T
A Single-Ended to Differential Output S/H
Note how we have assumed in the S/H of Fig. 34.30 that the input voltage was fully-
differential. In most practical situations at the input of an ADC, this isn't the case. While
we can connect Vin− to VCM in an attempt to change the single-ended input into a
fully-differential sampled output, the practical problem is the variation of the op-amp's
input common-mode voltage. As we've already discussed, precision data converters must
use op-amp configurations where the input common-mode voltage is constant. Also, and
346 CMOS Mixed-Signal Circuit Design

φ1

(a)
φ2
Clock signals

φ3

(b)
Op-amp outputs

Inputs

(c)
Outputs across C L

Figure 34.33 SPICE simulations of the operation of Fig. 34.30.

perhaps more practically, the range of allowable common-mode voltages can be very
restricted when designing low-voltage circuits. As we saw with our basic mixed-signal
op-amp in the previous chapter, Fig. 33.70, the minimum input common-mode voltage can
be very close to VCM when only an NMOS diff-pair is used. A technique to force the
op-amp's input common-mode voltage to VCM when a single-ended input is applied to the
S/H is seen in Fig. 34.34 [8]. The error amplifier senses the op-amp's input common-mode
Chapter 34 Implementing Data Converters 347

φ2 φ3

CF φ1
φ3 φ3
CL
V in + V CM CI v o+
V out+
CI V out−
V CM v o−
CL
CF
φ1

φ3

V CM
Error amplifier

Figure 34.34 Single-ended to differential S/H.

voltage. It adjusts the value of the voltage applied to the bottom plates of the input
capacitors when the φ3 switches are closed until the common-mode voltage is
approximately VCM. We say "approximately" to indicate that we don't want the gain of the
error amplifier to be so large that stability is a concern. The settling time of this circuit is
not too important because any variation in its output simply represents a deviation from
VCM on the op-amp inputs. As long as the deviation is small and falls within the
common-mode range of the op-amp, the single-ended to differential S/H functions
properly. The addition of this error amplifier will increase the CMRR and thus reduce
op-amp distortion (see Eq. [34.8]). Of course, when the φ1 and φ2 switches are closed, the
op-amp's input common-mode voltage is V CM ± V OS . Figure 34.35 shows a possible design
for the error amplifier. The error amplifier is simply an operational transconductance
amplifier.
A common-mode feedback (CMFB) circuit is still required to precisely balance the
outputs of the op-amp. Figure 34.36 shows one possible design. In this figure we assume
the reader is familiar with the designs and notation used in the last chapter for op-amp
design in a submicron process. When the φ1 switches are closed, the outputs are connected
to the CMFB amplifier (see Fig. 34.36a). Also when the φ1 switches are closed, from Figs.
34.30 or 34.34, the op-amp is placed in the unity feedback configuration. Because the gain
of the op-amp is large, the inputs must be at the same voltage. The CMFB circuit is used
to ensure that this voltage is VCM (±V OS ) . A typical mixed-signal op-amp is seen in Fig.
34.36b. This op-amp is derived from the topology given in the last chapter, without the
output buffers. The benefit of removing the output buffers when driving purely capacitive
loads is the ease of attaining a 90-degree phase margin (and so clean settling behavior).
348 CMOS Mixed-Signal Circuit Design

VDD

W/2
Out
W/2 W
Bias

Figure 34.35 Schematic of the error amplifier.

The drawbacks of not using an output buffer are the reduced gain and the need to increase
the biasing currents and device sizes to drive a given load capacitance. Again, the
gain-boosting amplifiers labeled N and P in part (b) can be compensated, if needed, using
capacitors at their outputs to ground (or VDD). If a basic diff-amp, as seen in Fig. 33.69,
is used then in most situations no additional capacitance is needed. The CMFB amplifier is
seen in Fig. 34.36c. It is simply a PMOS diff-amp with diode loads. The gain of this
amplifier should be similar to the gain of the diff-amp used in the main op-amp so that the
same load capacitances can be used for compensating both the op-amp and the CMFB
loop. Note that when the φ1 switches are open in Fig. 34.36a, the capacitors essentially
average the outputs maintaining a balanced condition.

Example 34.8
Simulate the operation of the S/H shown in Fig. 34.31. Assume the S/H is clocked
at 100 MHz, Vin+ is a sinewave that swings from ground to VDD, and Vin− is
connected to VCM (the input signal is single-ended and covers the entire supply
range). Show how the op-amp's input common-mode voltage range changes (that
is, doesn't remain at VCM as it would if the input signals were fully-differential).
Show how a 10% mismatch in the two capacitors affects the output of the S/H.
Figure 34.37 shows the simulation results. In part (a) the input common-mode
voltage of the op-amp is shown. When the φ1 switches are closed, the voltage
returns to VCM (the op-amp is placed in a follower configuration where the input
signal charges the two capacitors). In part (b) the rail-to-rail input signal is
converted into a differential S/H output signal. Note that the gain of the S/H is
one. Note also how, unlike the op-amp outputs in Fig. 34.33, the outputs are
limited to V CM + V p /2 where Vp is the peak amplitude of the input sinewave (= 0.75
V here). When the input sinewave has an amplitude of 1.5 V (0.75 V above the
Chapter 34 Implementing Data Converters 349

φ1
v o+
V CM
v o−

CMFB amp
detail shown
op-amp in (c) on the
detail V CMFB next page

(a)
Common-mode feedback circuit

VDD VDD VDD VDD

V bias2
N V high V high N

v o− v o+
V low V low
P V bias3 P
2W

V bias4
2W

V CMFB

(b)
Figure 34.36 Mixed-signal op-amp for use in a S/H with CMFB.

VCM ), the positive output is 1.125 and the negative op-amp output is 0.375.
Subtracting the op-amp outputs results in 0.75 V (the same voltage as the input
signal referenced to VCM). It's important to understand how going from a
single-ended signal to a fully- differential signal results in a reduction in the op-amp
output swing.
Finally, the simulation results were generated using 0.9 pF and 1.0 pF sampling
capacitors (labeled CF in Fig. 34.31). Because the feedback factor is unity, these
capacitors will not affect the gain of the S/H. The point here is that the matching of
the capacitors isn't important for a precise gain of one when using this (Fig. 34.31)
S/H topology. (The op-amp open-loop gain, however, is still important.) T
350 CMOS Mixed-Signal Circuit Design

VDD

V bias1
2W

V bias2
2W

W/2
W/2
Out
V bias3

(c)
Figure 34.36 (cont'd) CMFB amplifier circuit.

(a) Showing how the

input common-mode
voltage varies in a
S/H with a single-
ended input.

Input

(b) Input and outputs

of a S/H performing
single-ended to
Outputs
differential coversion.

Figure 34.37 Simulation results for Ex. 34.8.

Chapter 34 Implementing Data Converters 351

34.3.2 The Cyclic ADC

Cyclic or algorithmic DACs were first discussed back in Ch. 29. Here we present the
concept of a cyclic ADC. A block diagram of a cyclic ADC is seen in Fig. 34.38 assuming
an 8-bit (N = 8) conversion. The input signal is sampled on the rising edge of every eighth
(N) clock pulse. On the rising edge of every clock pulse the comparator determines if the
S/H input is above or below the common-mode voltage. If it is below VCM , nothing is
subtracted from the S/H output. If it is above VCM , then VCM is subtracted from the S/H
output. In either case the resulting output is multiplied by two and cycled back to the S/H
input. Each time the comparator output goes high the value is stored in a shift register.
When the conversion is complete, the digital word stored in the shift register, which
corresponds to the analog input voltage, is shifted into a hold register. The next
conversion then begins on the following clock pulse starting with sampling the input
voltage, Vin. Note that it takes N clock cycles for one conversion.

Move switch to input when high

(Assuming N = 8.)
S/H
Input V in S/H
V out

Clocked comparator
2
V CM Select MUX
1 0

V CM 0
f clk
In
Clk N-bit shift register
Clock pulses

÷N Clk/N
Hold register

LSB MSB
(Assuming N = 8)

Figure 34.38 Block diagram of a cyclic ADC.

Example 34.9
Determine the output of the ADC in Fig. 34.38 if the input voltage is 1.5 V.
We begin by sampling the input voltage of 1.5 V. The output of the comparator is
a logic 1 (MSB). Next, VCM (= 0.75 V) is subtracted from the S/H output resulting
352 CMOS Mixed-Signal Circuit Design

in an output of 0.75 V. This output is multiplied by 2 resulting in 1.5 V. This 1.5 V

output (the output of the multiplier) is cycled back to the S/H input.
Next, we sample the fed back voltage of 1.5 V, the output of the comparator is,
again, a logic 1 (MSB − 1). VCM (= 0.75 V) is subtracted from the S/H output
resulting in 0.75 V. This output is multiplied by 2 resulting in 1.5 V. This 1.5 V
output (the output of the multiplier) is cycled back to the S/H input.
This continues and the final output of the ADC hold register is 1111 1111 (binary
offset format). T

Example 34.10
Repeat Ex. 34.9 if the Cyclic ADC input is 1.1 V.
1. Sample the 1.1 V input voltage. The comparator output goes high (MSB, b7 , =
1). The output of the multiply by 2, after subtracting VCM (= 0.75) from the S/H
output, is 0.7 V.
2. Sample the 0.7 V fed back voltage. The comparator output goes low (b6 = 0).
The output of the multiplier is 1.4 V.
3. Sample 1.4 V. The comparator output goes high (b5 = 1). The output of the
multiplier is 1.3 V.
4. Sample 1.3 V. The comparator output goes high (b4 = 1). The output of the
multiplier is 1.1 V.
5. Sample 1.1 V (b3 = 1) output of the multiplier is 0.7 V.
6. Sample 0.7 V (b2 = 0) output of the multiplier is 1.4 V.
7. Sample 1.4 V (b1 = 1) output of the multiplier is 1.3 V.
8. Sample 1.3 V (b0 = 1) output of the multiplier is 1.1 V.
9. Sample the new input voltage and begin conversion again. The output word in
the hold register is 1011 1011 (binary offset). T
Comparator Placement
We showed the inverting input of the comparator in Fig. 34.38 connected to the common-
mode voltage. In practice, however, we know that the comparator will have an offset or
that the fed back signal may have a common-mode voltage slightly different than the ideal
value. If the common-mode voltage of the fed back signals was, for example, 10 mV
different than the ideal value, the comparator can make a wrong decision. Further, if the
common-mode voltage is varying because of power supply, noise, or temperature changes,
we can make a wrong decision even if some calibration scheme is employed. To avoid a
wrong decision, the comparator is most often used in a fully-differential configuration, as
seen in Fig. 34.39, with offset storage.
In Fig. 34.39 the clocked comparator shown in Fig. 33.34 is used without the
NAND gates on the output. This comparator can have significant kickback noise. By
Chapter 34 Implementing Data Converters 353

adding the φ2 switches in series with the comparator input, we ensure the kickback noise
doesn't corrupt the S/H input voltage. Note that since φ3 and φ2 are nonoverlapping, we
guarantee that the comparator and S/H are disconnected when the comparator is clocked
(and the kickback noise is generated). When the φ1 switches are closed, the offset voltage
of the comparator or the op-amp is zeroed out. The performance requirements of the
comparator (gain and offset) can be greatly reduced (offset storage is not required) if we
use 1.5 bits per clock cycle instead of the 1 bit per cycle used here [9, 10]. We discuss this
further in the next section.

φ2 φ3

CF φ1
φ3 φ3
CL
V in+ CI v o+
V outa+
V CM CI V outa−
v o−
V in−
CL
CF
φ1

φ3
φ1

V outd+
φ3 Digital
V outd−

φ1
Clocked comparator,
φ3 see Fig. 33.34 where
the NAND gates are
not used

Figure 34.39 Implementation of the comparator with an S/H for use in a cyclic ADC.

Example 34.11
Estimate the gain required of a comparator used in a 10-bit cyclic ADC if VREF+ =
1.5 V and VREF− = 0.
The LSB of this converter is 1.5/2 10 = 1.465 mV . This means that the comparator
gain must be large enough so that the output can fully transition to either VDD or
ground with less than 1.465 mV difference on its inputs (assuming the offset
354 CMOS Mixed-Signal Circuit Design

voltage is zeroed out). In other words, the gain must be well above 1.5/1.465 mV
or 210 or 1,024. Clearly this presents a real design concern. The gain of the positive
feedback comparator of Fig. 33.34 may be very large because of the positive
feedback used. However, the delay time of the comparator (time delay between the
clock going high and the outputs transitioning all the way to VDD and ground)
may be too long with such a little input voltage difference. Increasing the gain of
the comparator, without care, can result in the comparator being unstable when
placed in the unity feedback condition (the φ1 switches closed in Fig. 34.39). To
increase the comparator gain and avoid instability, a diff-amp (or two) can be
added as a pre-amp in front of the basic comparator of Fig. 33.34. The offset of
the diff-amp can then be zeroed out by placing the φ1 switches between the
diff-amp's output and its input. T
Implementing Subtraction in the S/H
Notice in Fig. 34.38 how we can implement the S/H and then multiply by two by simply
setting C F = C I in Fig. 34.30. Reviewing Fig. 34.38 we see that it would also be nice to
implement the subtraction in the S/H. In this figure we see that if the output of the MUX
is 0 V, nothing needs to be changed in Fig. 34.30. However, if the MUX output is VCM ,
then the S/H output must be reduced by VCM. Consider what happens if, when φ3 goes
high, instead of connecting the bottom plate of CI to VCM in Fig. 34.30 we connect it to a
voltage VCI+ (see Fig. 34.40). Doing this, after reviewing Eqs. (34.46) to (34.49), results in
φ
Q I 3 = C I ⋅ (V CI+ − V CM ± V OS ) (34.51)
or

V out+ =  1 + I  ⋅ V in+ − I ⋅ V CI+

C C
(34.52)
CF CF

φ2
CF
φ3
CI V in
V in+ S/H V out
V CI+
V CI− CI CI
V in− 1+ ⋅ (V CI+ − V CI− )
CI CF CF

(Partial view) CF

Figure 34.40 Implementing subtraction in the S/H.

Chapter 34 Implementing Data Converters 355

The differential output voltage is then given by

V out = V out+ − V out− =  1 + I  ⋅ (V in+ − V in− ) − I ⋅ (V CI+ − V CI− )

C C
(34.53)
 CF CF
We can easily rearrange the block diagram of Fig. 34.40 so that it more closely resembles
the block diagram of the cyclic converter (Fig. 34.38), as seen in Fig. 34.41. If C F = C I ,
for our needed gain of two, we end up subtracting VCM when VCI+ is 1.5VCM (= 0.75VDD)
and VCI− is 0.5VCM (= 0.25VDD). For the fully-differential I/O signal case then we are
actually subtracting VCM /2 when V in+ > V in− and adding VCM /2 when V in+ < V in− .

V in S/H V out

V CI+ − V CI− CI
CF
1+
+1 CF
CI

Figure 34.41 Block diagram of Fig. 34.30 with bottom plates of C I tied to V CI.

Example 34.12
Simulate the operation of the S/H shown in Fig. 34.42 if fs = 100 MHz, CF = CI = 1
pF, VCI+ = 1.5VCM , and VCI− is 0.5VCM. Comment on the resulting output.
The simulation results are shown in Fig. 34.43. We only show the situation when
we would want to subtract VCM /2 from the differential input signal of the cyclic
ADC, that is, when V in+ > V in− . When the inputs are approximately the same
voltage, the + input is approximately the same voltage as the − input and Vin is 0.

φ2 φ3

CF φ1
φ3
φ3
CL
V in+ CI
V CI+ V out+
V CI− CI V out−
V in−
CL
CF
φ1

φ3

Figure 34.42 S/H used in Ex. 34.12

356 CMOS Mixed-Signal Circuit Design

+ input signal
+ output signal

input signal output signal

Figure 34.43 Simulation results for Ex. 34.12.

We subtract 0.375 V (VCM /2) from the input and multiply by 2. The result, when
the input is 0, is − 0.75 V (−VCM ). When this happens, Vout+ is 375 mV and Vout− is
1.125 V. Taking the difference in these signals results in − 0.75 V. At 100 ns in
Fig. 34.43, for example, Vin is + VCM. After we subtract VCM /2 and multiply by 2,
we get VCM again (as indicated in the figure). T

Example 34.13
Repeat Ex. 34.12 if we want to add VCM /2 to the input signal.
We only want to add VCM /2 to the input signal when V in+ < V in− . In this situation
we set VCI+ = 0.5VCM and VCI− to 1.5VCM. The simulation results are shown in Fig.
34.44. T

input signal
output signal

+ input signal + output signal

Figure 34.44 Simulation results for Ex. 34.13.

Chapter 34 Implementing Data Converters 357

Let's write the analog output of the single-ended cyclic stage as

V out = 2 ⋅ (V in + b ⋅ 0 − b ⋅ V CM ) (34.54)
where b is the digital (1 or 0) output of the comparator. Figure 34.45 shows the transfer
curve for the cyclic stage. If the comparator output, b, is a 1 (V in > V CM ) , then we subtract
VCM from Vin before multiplying by two. Note that we have assumed
CI
=1 (34.55)
CF

V out

2V CM = V REF+ = VDD b=0 b=1

V in
V REF− = 0 V CM = VDD/2 V REF+ = VDD
= 2V CM

Figure 34.45 Transfer curve for the cyclic ADC (single-ended case).

Understanding Output Swing

After reviewing Fig. 34.45, the reader may wonder how the ADC will perform when the
op-amp output must swing all the way up to VDD and down to ground. Any practical
op-amp output voltage will become nonlinear as it approaches the supply rails. What must
be realized is that the single-ended voltage, which ranges from 0 to VDD, is changed into
a fully-differential voltage using the circuit of Fig. 34.34, which varies from VDD/4 to
3VDD/4 (as seen in Fig. 34.37). If we use our common-mode voltage as a reference (VCM
= VDD/2) for single-ended inputs, then we can show some conversions from single-ended
to differential.
Single-ended input Differential outputs
1. V in = 0.5VDD V out+ = V out− = V CM , V out = V out+ − V out− = 0
2. V in = VDD V out+ = 0.75VDD, V out− = 0.25VDD, or V out = VDD/2
3. V in = 0 V out+ = 0.25VDD, V out− = 0.75VDD, or V out = −VDD/2
4. V in = 0.6VDD V out+ = 0.55VDD, V out− = 0.45VDD, or V out = 0.1VDD
358 CMOS Mixed-Signal Circuit Design

Figure 34.46 shows the transfer curve of Fig. 34.45 redrawn to indicate that the signals,
both input and output, are fully-differential. Note, as seen in Fig. 34.39, that the
comparator output transitions from a 0 to a 1 when V in+ > V in− (Vin > 0).

V out

VDD/2 V CM
b=0 b=1

V in

−VDD/2 −V CM
−VDD/2 0 VDD/2

Figure 34.46 Transfer curve for the cyclic ADC when using fully-differential signals.

We can rewrite Eq. (34.54) for fully-differential signals by looking at Fig. 34.46
and noticing that now because the inputs and outputs are fully-differential and referenced
to VCM instead of 0 so must the voltages we add and subtract from the input. Equation
(34.54) can be written as

V out+ − V out− = 2 ⋅  V in+ − V in− + b ⋅ 0 − b ⋅ V CM  + b ⋅ V CM + b ⋅ V CM (34.56)

or

V out+ − V out− = 2 ⋅  V in+ − V in− + b ⋅ 0 − b ⋅ V CM + b ⋅ CM + b ⋅ CM 

V V
(34.57)
2 2
and finally
Vout
 Vin

= 2 ⋅  V in+ − V in− + b ⋅ CM − b ⋅ CM 
 V V
V out+ − V out− (34.58)
 2 2 
 

Example 34.14
Using the fully-differential S/H stage of Fig. 34.42 simulate the transfer curve
shown in Fig. 34.46.
The results of the simulation are shown in Fig. 34.47. To simulate Vin, the Vin+
input is a ramp that varies from 0.375 V to 1.125 V while, at the same time, the
Vin− is a ramp that varies from 1.125 V to 0.375 V. This results in Vin changing
linearly from −VCM to +VCM (knowing VCM = VDD/2). When the two ramps are
equal, that is, when they are both VCM (Vin = 0), VCI+ changes from 0.5VCM to
Chapter 34 Implementing Data Converters 359

1.5VCM, and VCI− changes from 1.5VCM to 0.5VCM so that we go from adding VCM /2
when Vin < 0 to subtracting VCM /2 when Vin > 0. T

Figure 34.47 Simulating the transfer curves of a cyclic ADC stage.

34.3.3 The Pipeline ADC

One drawback of the cyclic ADC discussed in the previous section is the requirement of N
clock cycles for each N-bit conversion. From Ch. 29 we know that the flash and pipeline
(after an N-bit latency) topologies can perform an analog-to-digital conversion in one
clock cycle. Another possibility for an N-bit conversion in one clock cycle is to use a time-
interleaved topology [11]. The basic idea is seen in Fig. 34.48. The S/Hs are sequentially
clocked so that during each clock cycle the input voltage, Vin, is sampled, held, and applied
to the input of an N-bit ADC. If the outputs of each ADC are then sequentially available
through a MUX, the overall topology behaves as if it were a single ADC with flash-like
performance. The practical problem with this topology is the matching between the ADCs.
Differences in the DC characteristics of each ADC, for example, can result in measuring
digital output values that change with time when a DC input signal is applied (a ripple on
the output similar to what was seen in a noise-shaping data converter output). Mismatches
in the ADCs can also result in a reduced (from ideal) signal-to-noise plus distortion ratio
(SNDR).
The pipelined ADC can be thought of as an amplitude-interleaved topology where
errors from one stage are correlated with errors from previous stages. The basic block
diagram implementation of an N-bit pipelined ADC using the cyclic stage (see Fig. 34.42
for example) is seen in Fig. 34.49. Instead of cycling the analog output of the 1 bit/stage
section back to its input, we feed the output into the next stage. The stages are clocked
with opposite phases of the master clock signal. The comparator outputs are labeled
digital in the figure. The digital comparator outputs are delayed through latches so that
the final digital output word corresponds to the input signal sampled N clock cycles
earlier. The first stage in Fig. 34.49 must be N-bit accurate. It must amplify its analog
output voltage, V N−1 , to within 1 LSB of the ideal value (after the subtraction of 0 or VCM
from the input signal and the multiplication by two). The second stage output, V N−2 , must
 360 CMOS Mixed-Signal Circuit Design

T1 N clock cycles per each N-bit conversion

S/H N-bit ADC
T2
S/H N-bit ADC
T3
S/H N-bit ADC MUX
V in
TN N stages
Output changes with
S/H N-bit ADC
each clock cycle

Figure 34.48 Time-interleaved operation of an ADC [10].

be an analog voltage within 2 LSBs of its ideal value. The third stage output, V N−3 , must
be an analog voltage within 4 LSBs of its ideal value and so forth. The important point
here is that because the required accuracy of each stage decreases as we move down the
line, the settling time, gain accuracy, and offsets all become less important. Smaller (and
thus lower power) stages can be used for the later stages having, possibly, a dramatic
effect on both layout size and power dissipation. While we're showing 1 bit/stage in Fig.
34.49, most commercially available pipeline ADCs use the digital error correction present
in the 1.5 bit/stage topology discussed later.

Total N stages
V in V N−1 V N−2 V0
1-bit/stage 1-bit/stage 1-bit/stage 1-bit/stage
V N−3
digital digital digital digital

latch latch latch latch

(N - 1) latches

b0
N latches

latch latch
latch
latch
latch b N−3

latch b N−2
t
word ou
b N−1 Digital

Figure 34.49 Pipelined ADC based on the cyclic stages discussed in the last section.
Chapter 34 Implementing Data Converters 361

We know from our analysis of pipeline ADC errors in Ch. 29 that they can be the
result of comparator offsets, gain or linearity errors, and amplifier offsets. In the remainder
of this section we discuss how to reduce the effects of these errors. We begin with a
discussion of using the 1.5 bit/stage topology to make the comparator offsets (and the
reference voltages used with the comparators) a "don't care." While we might think that
using six stages with 1.5 bits/stage would result in an ADC with 9-bit resolution, we find
that the extra 0.5 bit/stage is used to correct for errors introduced by the comparators.
Using six stages will still result in a 6-bit ADC. We then cover the use of capacitor error
averaging [12] to set the gains of the amplifiers to precisely two. The cost of this
technique is the increase in the number of clock cycles required for each stage's operation
and a slightly more complex switching scheme. Finally, we cover some other topologies
useful in amplifier offset removal and discuss offsets in general.
Using 1.5 Bits/Stage
As we saw in Ex. 34.11, the gain of the comparator (and the offset) can present a practical
limitation to the operation of the ADC at high resolutions. The transfer curve of Fig. 34.45
relates the analog input of the cyclic ADC to its analog output voltage. The important
point in this figure, besides the gain and linearity, is where the output of the comparator,
b, transitions from a 0 to a 1. One-bit corresponds to two levels, i.e., a 0 or a 1. Two bits
corresponds to four levels, i.e., 00, 01, 10, and 11. If we were to use three levels then we
would get 1.5 bits of resolution. Using a thermometer code or decimal numbers, the three
levels would then be
Thermometer, ab Decimal
11 3
01 1
00 0
Next consider the transfer curves shown in Fig. 34.50 where three levels are used
(1.5 bits). We can rewrite Eq. (34.54) for the 1.5 bit case as
V out = 2 ⋅ (V in − ab ⋅ 0 − ab ⋅ V CM − ab ⋅ 2V CM ) + V CM (34.59)
or
V CM V 3V
V out = 2 ⋅ (V in + ab ⋅ − ab ⋅ CM − ab ⋅ CM ) (34.60)
2 2 2
or if ab = 00 (V in < V CM /2) , then V out = 2 ⋅ (V in + VCM /2) , if ab = 01 (V CM < V in < 3V CM /2)
then V out = 2 ⋅ (V in − 0.5V CM ) , and if ab = 11 then V out = 2 ⋅ (V in − 1.5VCM ) . For the
fully-differential situation Eq. (34.59) can be rewritten as
V out+ − V out− = 2 ⋅ (V in+ − Vin− + ab ⋅ V CM − ab ⋅ 0 − ab ⋅ V CM ) (34.61)
where all we did was reference, to VCM, the voltages added/subtracted to Vin as seen in Eq.
(34.58).
362 CMOS Mixed-Signal Circuit Design

V out −VDD/2 V out VDD/2

ab
00 01 11 00 01 11
2V CM VDD VDD/2

V CM VDD/2 V in

V in −VDD/2
V CM V REF+ = VDD = 2V CM −V CM V CM
0
V REF− = 0 V CM V CM
−
V CM 3V CM 2 2
2 2
Single-ended input and output Double-ended input and output

Figure 34.50 Transfer curves for using 1.5-bits per clock cycle.

Figure 34.51a shows how the comparators would be set up to determine ab and
how we would provide the outputs. The outputs of the comparators are used as address
inputs to a MUX. The MUX is used to set the bottom plate voltage of the CI capacitor in
Fig. 34.42. Figure 34.51b shows how we would implement the comparators if the input
and output signals are double-ended.

V in + V CM
(a) Single-ended input To bottom plate ofC I (V CI )

3V CM 2 addr out
ab
2 MUX
00 01 11

0 2V CM = VDD
V CM
V CM
2
V in− V CI+

ab MUX
3V CM 2 00 01 11
(b) Double-ended input
4 0 V CM 2V CM
ab 11 01 00
MUX
V in+
V CI−
Figure 34.51 Implementing comparators and MUX for 1.5 bits.
Chapter 34 Implementing Data Converters 363

Example 34.15
Repeat Ex. 34.14 if 1.5 bits/stage are used.
The simulation results are shown in Fig. 34.52. The same signals were used for the
inputs (two ramps) here as used in Ex. 34.14. The voltage VCI+ is 0 V when Vin is
less than − 375 mV and is 0.75 when Vin is between − 375 mV and + 375 mV,
while it is 1.5 V (= VDD = 2VCM ) when Vin is greater than + 375 mV. Notice how
we only need three precision voltages, unlike the 1-bit/stage case, that is, VDD,
VCM , and 0. T

VDD = 1.5 V

Figure 34.52 Simulating the transfer curves for 1.5 bits/stage.

Before going any further, let's answer, "How can using 1.5 bits/stage eliminate the
need for precision comparators?" After reviewing Fig. 34.50, we see that an output of 11
cannot be followed by another output of 11 because we subtract VCM from the input prior
to multiplication by two. Even if the comparator has a reasonable offset (say less than 100
mV) or low gain (say less than 50) resulting in a wrong decision, it's impossible for a 11 to
be followed by another 11 or for a 00 to be followed by another 00. It is possible,
however, to get a continuous string of 01 outputs (a simple example is when VCM is
applied to the ADC).
Let's now discuss how the outputs of the 1.5-bit stage are combined into the final
ADC output word. Let's assume, again, that VREF+ = VDD = 1.5 V, VREF− = 0, and VCM =
0.75 V. We know that the final N-bit output word can be converted back into an output
voltage (with the unwanted quantization noise) using a DAC with the following weighting,
Eq. (30.27),
1 LSB

V CM V V CM
V out (if a DAC or V in if an ADC) = b N−1 ⋅ V CM + b N−2 ⋅ + b N−3 ⋅ CM + ... + b 0 ⋅ N−1
2 4 2
(34.62)
364 CMOS Mixed-Signal Circuit Design

Reviewing Eq. (34.54) note how if, on the first cycle, b = 1, we subtract VCM from the
input and then multiply the result by two. After a little thought, we should be able to see
how we derive Eq. (34.62) from Eq. (34.54) after N clock cycles.
If the first thermometer code output of the 1.5-bit stage is labeled a 1.5N−1 b 1.5N−1 and
the second output is a 1.5N−2 b 1.5N−2 , etc., then we can write, with the help of Eq. (34.59),
the relation between the ADC input (analog) and the ADC outputs (digital) as
V CM
V in = a 1.5N−1 b 1.5N−1 ⋅ V CM + a 1.5N−1 b 1.5N−1 ⋅ 2V CM −
2
V 2V V
+ a 1.5N−2 b 1.5N−2 ⋅ CM + a 1.5N−2 b 1.5N−2 ⋅ CM − CM
2 2 4
V 2V V
+ a 1.5N−3 b 1.5N−3 ⋅ CM + a 1.5N−3 b 1.5N−3 ⋅ CM − CM + ... (34.63)
4 4 8
noting that we can group
= 0 here

−
V CM V CM V CM
− − − ... = −V CM ⋅ − 1 = −V + 0.5 LSB + V REF−
2N (34.64)
CM
2 4 8 2N 2N
which is nothing more than a level shift. Clearly we can combine outputs in the following
manner to arrive at an equation similar to Eq. (34.62)
V CM
V in = (a 1.5N−1 b 1.5N−1 + a 1.5N−2 b 1.5N−2 ) ⋅ V CM + (a 1.5N−2 b 1.5N−2 + a 1.5N−3 b 1.5N−3 ) ⋅
2
V CM
+ (a 1.5N−3 b 1.5N−3 + a 1.5N−4 b 1.5N−4 ) ⋅ + ...
4
a 1.5N−1 b 1.5N−1 ⋅ 2V CM − V CM + 0.5 LSB (34.65)
Next notice that, when using a thermometer code, the only time a 1.5N−X b 1.5N−X (the logical
AND of ab) can be high is when both are high. The term a 1.5N−X cannot be high while
b 1.5N−X is low (there is no such output code as 10, see Fig. 34.50). This means that we can
replace a 1.5N−X b 1.5N−X with simply a 1.5N−X . We can rewrite Eq. (34.65) as
V CM
V in = a 1.5N−1 ⋅ 2V CM + (a 1.5N−1 b 1.5N−1 + a 1.5N−2 ) ⋅ V CM + (a 1.5N−2 b 1.5N−2 + a 1.5N−3 ) ⋅
2
V CM V CM
+ (a 1.5N−3 b 1.5N−3 + a 1.5N−4 ) ⋅ + ... + a 1.50 b 1.50 ⋅ N−1 − (V CM − 0.5 LSB) (34.66)
4 2
The + symbol in Eq. (34.66) indicates addition rather than a logical OR. If
a 1.5N−1 b 1.5N−1 = 1 and a 1.5N−2 = 1, then the second term in this equation is 2VCM and the first
term must be 0. When this occurs, the addition of the two terms is 0 and a carry is
generated. We can now use this information to write the relationship between Eq. (34.62)
and Eq. (34.63) knowing ⊕ indicates an exclusive OR
b 0 = a 1.50 b 1.50 with carry = c 0 = a 1.50 (34.67)
b 1 = a 1.51 b 1.51 ⊕ c 0 with c 1 = a 1.51 b 1.51 c 0 (34.68)
Chapter 34 Implementing Data Converters 365

b 2 = a 1.52 b 1.52 ⊕ a 1.51 ⊕ c 1 with c 2 = a 1.52 b 1.52 a 1.51 + c 1 (a 1.52 b 1.52 + a 1.51 ) (34.69)
noting each bit and carry are the outputs of a full adder. To simplify the carry equation,
and the subsequent equations, we can substitute c 1 to get
c 2 = a 1.52 b 1.52 a 1.51 + c 1 a 1.52 b 1.52 (34.70)
We can write the general form of b 2 through b N−1 , using full adders, as
b N−1 = a 1.5N−1 b 1.5N−1 ⊕ a 1.5N−2 ⊕ c N−2 and
c N−1 = a 1.5N−1 b 1.5N−1 a 1.5N−2 + c N−2 (a 1.5N−1 b 1.5N−1 + a 1.5N−2 ) (34.71)
The bit bN has a weighting of 2VCM and thus the final output word size is N + 1
b N = a 1.5N−1 ⊕ c N−1 (34.72)
Before we sketch the implementation of this digital circuit, let's make a few
comments. To begin, notice that the word size is one larger than N (the resolution). In the
1 bit/stage circuit our maximum output is (assuming N = 8)
1111 1111 = VDD − 1 LSB = 2VCM − 1 LSB (1 bit/stage)
Now our maximum output is
1 0000 0000 = VDD = 2VCM (1.5 bit/stage)
The resolution is still essentially eight bits; we just have a slightly larger (1 LSB) output
range. To make the words exactly match, we can throw out the MSB and assume 1 0000
0000 is an out-of-range condition. Note that an input of VDD − 1 LSB using 1.5 bits/stage
gives an output code of 0 1111 1111.
One more comment: if we go through the logic in Eq. (34.66), we don't get the
correct outputs unless we subtract VCM − 0.5 LSB. The binary offset representation can be
written as
V CM − 0.5 LSB = 0011111111... (34.73)
For example, applying VCM (single-ended, see Fig. 34.51) to the ADC input results in a
continuous output (ab) of 01. The output prior to subtraction, from Eqs. (34.67) to
(34.72), is then 01111111... (bN = 0, bN−1 = 1, bN−2 = 1, etc.). After subtracting
0011111111..., we get 01000000 or VCM knowing the weighting of the second bit is VCM.
Figure 34.53 shows one possible implementation of Eqs. (34.67)-(34.72) for a
cyclic ADC. The state shown, i.e., the ab values, is valid at the end of the conversion
(after N clock cycles). When starting the algorithm (on the first rising edge of clock), all
latches are reset to zeroes and the first comparator outputs, ab, are applied. On the second
rising edge of clock the output b2 corresponds to the final bN . After N clock cycles, the
hold register is clocked (and the latches are reset). The final ADC output is the contents of
the hold register after subtracting 00111111.... Changing the numbers to two's
complement may be useful when implementing this stage (assuming the MSB has a
weighting of VCM , i.e., throw out bN ). Note the subtraction can precede the hold register.
366 CMOS Mixed-Signal Circuit Design

a b a 1.51 b 1.51 a 1.52 b 1.52

D Q D Q
inputs
clk clk

a 1.50 a 1.51
D Q
clk

c1 Full c 2
c0 Adder
a 1.50 b 1.50

b 0 LSB b1 b2 b3 b4 bN
f clk /N
clk Hold register

LSB MSB
001111...
Subtraction

ADC out

Figure 34.53 Combining the outputs of the cyclic ADC when 1.5 bits/stage is used.

Example 34.16
Repeat Ex. 34.10 if 1.5 bits/stage are used. Assume the converter is ideal and the
comparators switch precisely at VCM /2 (= 0.375 V here) and 3VCM /2 (= 1.125 V
here). Assume all latches initially contain zeroes.
Vin Comparator outputs, ab Vout Digital out
1.1 (N − 1 = 7) 01 1.45 b7 = 0 c7 = 1 b8 = 1
1.45 (N − 2 = 6) 11 0.65 b6 = 0 c6 = 0
0.65 (N − 3 = 5) 01 0.55 b5 = 1 c5 = 0
0.55 (N − 4 = 4) 01 0.35 b4 = 1 c4 = 0
0.35 (N − 5 = 3) 00 1.45 b3 = 1 c3 = 0
1.45 (2) 11 0.65 b2 = 0 c2 = 0
0.65 (1) 01 0.55 b1 = 1 c1 = 0
0.55 (0) 01 0.35 b0 = 1 c0 = 0
Chapter 34 Implementing Data Converters 367

We can reorder the bits so the MSB is on the left, the LSB is on the right, and
subtract 0 0111 1111 yielding
1 0011 1011 (315 decimal)
- 0 0111 1111 (127)
0 1011 1100 (188)

This is the result given in Ex. 34.10 (0 1011 1011) plus 1 LSB. The 1 LSB
discrepancy can be traced to Eq. (34.66) where we used 0.5 LSBs. Because our
resolution is at best 1 LSB, sometimes the result will experience a round-off error.
To understand this in the subtraction above, the more correct decimal
representation of VCM − 0.5 LSBs is 127.5 and the more correct decimal output is
187.5 (the answer given in Ex. 34.10 was decimal 187). When we discussed the
output of the ADC with an input voltage of VCM, on the bottom of page 365, our
output prior to subtraction was 011111... For eight bits this is decimal 255 (nine
bits out). When we subtract 127, we get the correct output of 128 for the final
output. In this situation the round-off worked in our favor (we round 127.5 up to
128). Because of this 0.5-bit offset, one might simply subtract VCM (= 0 1000
000...) to simplify the subtraction circuitry. While this appears complicated, the
significant benefit is relaxed comparator and reference voltage (used with the
comparators) requirements. T

Example 34.17
Repeat Ex. 34.16 if the comparators switch at 0.4 V (a 25 mV offset) and 1.05 V
(a 75 mV offset).
Vin Comparator outputs, ab Vout Digital out
1.1 (N − 1 = 7) 11 − 0.05 b7 = 0 c7 = 0 b8 = 1
− 0.05 (N − 2 = 6) 00 0.65 b6 = 0 c6 = 0
0.65 (N − 3 = 5) 01 0.55 b5 = 1 c5 = 0
0.55 (N − 4 = 4) 01 0.35 b4 = 1 c4 = 0
0.35 (N − 5 = 3) 00 1.45 b3 = 1 c3 = 0
1.45 (2) 11 0.65 b2 = 0 c2 = 0
0.65 (1) 01 0.55 b1 = 1 c1 = 0
0.55 (0) 01 0.35 b0 = 1 c0 = 0
Which is the exact same result! While the comparator performance can be
extremely poor, the circuit of Fig. 34.42 must subtract and amplify to an accuracy
set by the least significant bit of the converter. When we calculated values in Ex.
34.16 and here we assumed subtractions of exactly 0, VCM , and 2VCM followed by a
multiplication of exactly two. Finally, notice that the negative output of −0.05 V
(single-ended) is easily accommodated when using fully-differential op-amps. T
368 CMOS Mixed-Signal Circuit Design

Capacitor Error Averaging

While using 1.5 bits/stage has made the comparator offset unimportant, we still have to
amplify the signal by a precise factor of 2. Toward the goal of precision gain consider the
redrawn version of our basic S/H, Fig. 34.42, shown in Fig. 34.54. In this figure we've
shown the clock phases (but not the slightly delayed clock signals also used) and the
capacitors with mismatch. Ideally, ∆C +,− = 0 and the gain of the S/H is precisely 2
(assuming sufficiently high op-amp open-loop gain, see Eq. [34.38]). From Eq. (34.52) we
can write
∆C +  ∆C + 
V out+ =  2 + ⋅ V in+ −  1 + V CI+ (34.74)
C+  C+ 
where ∆C/C is the capacitor mismatch (say, ± 1% or ± 0.01, noting ∆C may be positive or
negative). For the negative output
∆C −  ∆C − 
V out− =  2 + ⋅ V in− −  1 + V CI− (34.75)
C−  C− 
where V out = V out+ − V out− . Note that when using this topology in a pipeline converter one
stage can be in the hold state while the next stage can be in the sampling state effectively
sharing the time. The result of this sharing is the need for only one clock cycle for each
stage in the conversion.

φs φh

C+

φh φs
C + + ∆C +
V in+
V CI+ V out+
V CI− V out−
V in−
C − + ∆C −
φs
C−

one cycle φh

φs Sample Sample

φh Hold Hold

V out valid

Figure 34.54 S/H of Fig. 34.42 with mismatched capacitors.

Chapter 34 Implementing Data Converters 369

Next consider what happens if, instead of sampling the input voltage again, we
simply switch the positions of the C and C + ∆C capacitors, that is, we connect C to VCI
and C + ∆C to Vout. Figure 34.55 shows this switch and the modified S/H using an extra
half-clock cycle. The sample and amplify phases of the clock are exactly the same as
before, and so Eqs. (34.74) and (34.75) are still valid. We denote the outputs at the end
(falling edge) of the amplify phase as V outa+ and V outa−
∆C + (V
V outa+ = 2 ⋅ V in+ − V CI+ + ⋅ in+ − V CI+ ) (34.76)
C+
and
∆C − (V
V outa− = 2 ⋅ V in− − V CI− + ⋅ in− − V CI− ) (34.77)
C−
where the ideal situation is ∆C = 0 .

φh
φa φh φs φa
C+
φs

C + + ∆C +
V in+
V CI+ V out+
V CI− V out−
V in−
C − + ∆C −

φs
C−
φa
φh
V outa valid

φs Sample Sample

φa Amplify

φh Hold (average)

V outh and V avg valid

Figure 34.55 S/H using capacitor error averaging.

370 CMOS Mixed-Signal Circuit Design

At the end of the amplify phase the charge on the capacitors is (assuming the
op-amp input voltages are 0 and only looking at the + path to simplify the equations)
Q a+ = (C + + ∆C + ) ⋅ (V CI+ ) + C + ⋅ (V outa+ ) (34.78)
and at the end of the hold phase
Q h+ = (C + + ∆C + ) ⋅ (V outh+ ) + C + ⋅ (V CI+ ) (34.79)
Because charge must be conserved, Q a+ = Q h+ , and therefore
C+ C+
V outh+ = V CI+ + ⋅ V outa+ − ⋅ V CI+ (34.80)
C + + ∆C + C + + ∆C +
It will be useful to use
C+ 1 ∆C +
= ≈1− (34.81)
C + + ∆C + 1 + ∆C + /C + C+
Rewriting Eq. (34.80) gives
∆C +  ∆C +
V outh+ =  1 − ⋅ V outa+ + ⋅ V CI+ (34.82)
C+  C+
Substituting Eq. (34.76) for V outa+ results in
∆C + (V
V outh+ = 2V in+ − V CI+ − ⋅ in+ − V CI+ ) (34.83)
C+
where the terms containing (∆C + /C + ) 2 are assumed negligible. If the matching is 1%, then
(∆C + /C + ) 2 = 10 −4 .
Clearly averaging Vouta+ (Eq. [34.76]) and Vouth+ (Eq. [34.83]) results in the precise
desired gain. The question now becomes: "How do we perform the averaging without
introducing more error?" Ideally we want
V outa+ + V outh+
V avg+ =
2
∆C + (V ∆C + (V
= 1 ⋅  2V in+ − V CI+ + ⋅ in+ − V CI+ ) + 2V in+ − V CI+ − ⋅ in+ − V CI+ ) 
2 C+ C+
= 2V in+ − V CI+ (34.84)
or more generally
V avg = V avg+ − V avg− = 2(V in+ − V in− ) − (V CI+ − V CI− ) (34.85)
This equation should be compared to Eq. (34.61).
Consider the averaging amplifier shown in Fig. 34.56. We can write the charge on
the four capacitors when the φ a switches are closed (actually at the falling edge of the φ a
clock, assuming complete settling) as
φa
Q + = (V outa+ − V CM ± V OS ) ⋅ C F + (Vouta− − V CM ± V OS ) ⋅ C I (34.86)
and
Chapter 34 Implementing Data Converters 371

φh

φa CF

φa
CI
V outa+ ⋅ φ a + V outh+ ⋅ φ h
V avg+
V outa− ⋅ φ a + V outh− ⋅ φ h V avg−
CI
φa
φa CF
φh

Figure 34.56 Averaging amplifier for use on the output of Fig. 34.55.

φa
Q − = (V outa− − V CM ± V OS ) ⋅ C F + (Vouta+ − V CM ± V OS ) ⋅ C I (34.87)
Note that the common-mode voltage and op-amp offset subtract out when we take the
difference between the balanced signals and so we do not include VCM or VOS in the
remaining analysis. (The offset from the common-mode feedback circuit results in an
unharmful variation in VCM and is discussed later in this section.) On the falling edge of φ h ,
and following the same procedure as used in Eq. (34.48), we can write
C F ⋅ V avg+ = C F ⋅ V outa+ + C I ⋅ V outa− − C I ⋅ V outh− (34.88)
and
C F ⋅ V avg− = C F ⋅ V outa− + C I ⋅ V outa+ − C I ⋅ V outh+ (34.89)
We can then write
CI
V avg+ = V outa+ + (Vouta− − V outh− ) ⋅ (34.90)
CF
CI
V avg− = V outa− + (Vouta+ − V outh+ ) ⋅ (34.91)
CF
noting that if V outa− = V outh− and V outa+ = V outh+ , the matching of the capacitors in Fig.
34.55 is perfect and V avg+ − V avg− = V outa+ − Vouta− (the output perfectly follows Eq.
[34.61]). Taking the difference of these two equations
Error adjustment term

(V outa+ − V outh+ ) − (V outa− − V outh− )

V avg+ − V avg− = V outa+ − V outa− − (34.92)
2
If we substitute Eqs. (34.76), (34.77), and (34.83) into this equation, we get
372 CMOS Mixed-Signal Circuit Design

∆C + ∆C −
V avg+ − V avg− = 2(V in+ − Vin− ) − (V CI+ − V CI− ) + (V in+ − V CI+ ) ⋅ − (V in− − V CI− ) ⋅ −
C+ C−
2(V in+ − V CI+ ) ∆C + 2(V in− − V CI− ) ∆C −
⋅ + ⋅ (34.93)
C F /C I C+ C F /C I C−
which reduces to Eq. (34.85) or (34.61) assuming CI /CF is 1/2 (CF is twice as large as CI ).
Note how the selection of (and matching) of the capacitor ratios, C F /C I , is not that
important. The capacitors do not have to match to the final ADC resolution. A matching
of 1% will result in an error term that is one-hundreth of the error that would be present if
the error averaging were not used. Also note, as indicated at the beginning of the section,
that only the first stages (say the first five in a 14-bit ADC) need use capacitor error
averaging because of the reduced accuracy requirements placed on the later stages as we
move through the converter.
The penalty for this precision technique is the increase in conversion time used in
each stage (and increased noise because two op-amps are used in each 1.5-bit section). As
seen in Fig. 34.55, an extra half-clock cycle is required. For 20 Msamples/s a 30 MHz
clock would be required. Again while one stage is in the hold (average) state, the next
stage in the pipeline can be in the sample state so that the conversion time is shared (but
still requiring 1.5 clock cycles). Using the capacitor error averaging technique for
precision gain (and subtraction) and using 1.5-bit/stage sections a 14-bit ADC, using
fully-differential input signals, has been attained at 20 Msamples/s without trimming or
calibration [13].

Example 34.18
Simulate the operation of the circuit shown in Fig. 34.57. Comment on the ideal
outputs and the simulation results.

φs φh

1.00p
φh φs
1.02p
V in+ 1.00 V
V out+
0.75 V
V out−
V in− 0.50 V
1.04p
φs

1.06p

φh

Figure 34.57 Matching errors in capacitors (see Ex. 34.18).

Chapter 34 Implementing Data Converters 373

The capacitor values were chosen arbitrarily. The input voltage, Vin, is 1 − 0.5 or
0.5 V. The ideal output voltage, Vout, is then 1 V. Vout+ should ideally be 1.25 V,
and Vout− should ideally be 0.25 V. The simulation results are shown in Fig. 34.58.
The error plotted in this figure is the result of taking the difference between the
ideal output and the actual output. The error for the capacitor values shown in Fig.
34.57 is approximately 5 mV. Clearly, at the risk of stating the obvious, capacitor
mismatch is a fundamental limitation to ADC accuracy. T
Error, millivolts

Figure 34.58 Simulation results from Ex. 34.18 showing amplification error.

Example 34.19
Simulate the operation of the circuit shown in Fig. 34.59 (a cascade of Figs. 34.55
and 34.56). Comment on the ideal outputs and the simulation results.
This circuit shows the same mismatched capacitors in the multiply-by-two stage as
we saw in Ex. 34.18. The averaging stage also shows mismatched capacitors with

1.00p 2.05p
1.02p 0.91p
1.00 V V out+
0.75
0.50 V 1.04p
V out−
1.10p

1.06p 1.94p

Figure 34.59 Implementation of error averaging (see Ex. 34.19).

374 CMOS Mixed-Signal Circuit Design

arbitrary values. Again, as in Ex. 34.18, the ideal output voltage is 1.0 V (Vout+ =
1.25 V and Vout− = 0.25 V). The simulation results are shown in Fig. 34.60. The
error has dropped from 5 mV to −70 µV. It may be instructive to resimulate the
capacitor error averaging topology of Fig. 34.59 using different values of
capacitors in order to get a feeling for just how forgiving the topology is to
mismatches.
Note that in the simulation netlist, where we are using near ideal op-amps with
open loop gains of 100 million, we added switches in series with the CI capacitors
in the averaging circuit to avoid the situation of the op-amp operating open-loop
with its outputs going to millions of volts when both φa and φh are low. (The
op-amp operates open loop when φs is high, which is usually not a problem in a
practical circuit). T
Error, microvolts

Figure 34.60 Simulation results from Ex. 34.19 showing amplification error.

Example 34.20
Repeat Ex. 34.19 if the op-amps used have open-loop gains of 1,000.
The simulation results are shown in Fig. 34.61. The error has increased by a factor
greater than 10. As indicated earlier in Eq. (34.39), the minimum op-amp open-
loop gain is set by the resolution of the data converter. If we were designing a
14-bit ADC, the op-amp used would require open-loop gains greater than 216 or
64k (96 dB). T
Comparator Placement
The implementation of a pipeline ADC showing how the clock signals are used in each
error averaging stage is shown in Fig. 34.62. The important thing to note is the use of only
three phases of an input clock signal. The connection of the clock phases to the switches
changes in each stage allowing a stage to sample an input signal while the previous stage is
in the hold mode. We'll discuss the generation of these clock signals in the next section;
here we discuss comparator placement and performance.
Chapter 34 Implementing Data Converters 375

Error, microvolts

Figure 34.61 Regeneration of Fig. 34.60 using op-amps with open-loop gains of 1,000.

Clock (3 phases)
One Two Three One
V in+ Error avg. Error avg. Error avg. Error avg.
V in− Fig. 34.59 Fig. 34.59 Fig. 34.59 Fig. 34.59

Sample, one Sample, one

Amplify, one

Hold, one

Sample, two

Amplify, two Amplify, two

Hold, two Hold, two

Sample, three Sample

Amplify, three

Hold, three Hold, three

Sample, one Sample, one

Figure 34.62 Implementation of a pipeline ADC using error averaging (Fig. 34.59).
376 CMOS Mixed-Signal Circuit Design

As seen in Fig. 34.55 the voltages VCI+ and VCI− must be valid and stable when the
amplify-and-hold clock phases are high. Reviewing Fig. 34.51 we can implement the two
comparators using a clock signal followed by a latch, Fig. 34.63. The comparators can be
clocked on the rising edge of the amplifying clock (which is a different clock phase in each
of the three possible clocking schemes). It's important to place a separate clocked latch on
the outputs of each comparator (clocked with a slightly delayed clock signal which isn't
shown in the figure) to ensure that comparator metastability isn't a factor when generating
the MUX addressing (select inputs). We can get away with this type of clocking scheme
because we are using three levels/stage (1.5 bits/stage). The comparators don't have to be
N-bit accurate, as discussed earlier, but can withstand offsets/errors approaching VCM /4.
The signals VCI+ and VCI− do have to be N-bit accurate, though, and must settle and stay
settled to this accuracy by the end of the amplify phase.

Clock (3 phases)
One Two Three
Error avg. Error avg. Error avg.
Fig. 34.59 Fig. 34.59 Fig. 34.59
Amplify, one

Amplify, two

Amplify, three

Ref Ref Ref

D Q

D Q

D Q

D Q

D Q

D Q
clk

clk

clk

clk

clk

clk

Select V CI− Select Select

MUX V CI+ MUX MUX

VDD VDD 0 VDD VDD 0 VDD VDD 0

2 2 2

Figure 34.63 Placement of comparators in a pipeline ADC.

The two bits coming out of the comparators (actually the latches connected to the
comparator outputs) can be thought of as the first delay element shown in Fig. 34.49
(except now it is a 2-bit delay element). Because each of these first delays are clocked on
the rising edge of one phase of the clock signal, we have a problem with synchronizing the
bits together prior to application to the digital correction logic (similar to Fig. 34.53).
Reviewing the clock signals in Fig. 34.62, we see that if we clock all other delay elements
in the pipeline of Fig. 34.49 on the rising edge of "amplify, one" we can synchronize all of
the digital data together.
Chapter 34 Implementing Data Converters 377

Clock Generation
Generating the nonoverlapping clock signals used in, for example, Fig. 34.55 can be
accomplished by using the basic circuit shown in Fig. 34.64. It might be helpful to review
Fig. 33.32 before we discuss the operation of this circuit. To understand the operation of
this circuit (Fig. 34.64), note that when one of the input signals goes low the
corresponding output phase goes high. The feedback ensures that the output doesn't go
high until the previous phase goes back low (both inputs of the NOR gate must be low
before its output goes high). The amount of nonoverlap time, again, is set by the delay in
series with the output of the NOR gates.

In1
Phase1

Nonoverlapping clock signals

Phase2
In2

Phase3
In3

Overlapping clock signals Delay (inverter buffers, or charge pumps)

Figure 34.64 Circuit used for generating three phases of a nonoverlapping clock.

The input signals (overlapping clock signals) are generated with the circuit shown
in Fig. 34.65. The outputs of this circuit change states on both the rising and the falling
edges of the input clock signal. The latches are clocked on both the rising and falling
edges of the input clock. They can be implemented with a parallel connection of the
dynamic latches given in the last chapter (one latch clocked on the rising edge and one
clocked on the falling edge with both latches sharing the common output MOSFETs). If
the input clock signal is 25 MHz with a period of 40 ns, then the width of each of the
output nonoverlapping clock phases in Fig. 34.64 is less than (but approximately) 20 ns.
Note that there are other ways to generate the input clock signals for the circuit of Fig.
34.64. (A shift register with one bit set low is one example.) The method shown starts
with both latches' outputs set low, 00 (= Q 1 Q 2 ). On the rising edge of the clock signal the
output changes to 01. On the following falling edge the output changes to 11. On the next
rising edge the output changes to 01 and the sequence repeats itself.
378 CMOS Mixed-Signal Circuit Design

Q1
D Q
In1
Clkin
clk Q

Q2 In2
D Q

clk Q
In3

Figure 34.65 Generating the overlapping input clock signals for Fig. 34.64.

Offsets and Alternative Design Topologies

When discussing offsets, we've concentrated on the op-amp's offset. The offset associated
with the common-mode voltage hasn't been discussed in detail. What happens if the output
signals are moving around a voltage of VCM + VOS? Taking the difference in the output
signals will eliminate both the common-mode voltage and the offset. A problem could
occur if the CMFB circuit doesn't affect each output the same. (The result is a difference-
mode signal.)

Example 34.21
Simulate the operation of the circuit shown in Fig. 34.66. Show the input and
output signals as the difference between the two differential input signals. Assume
the common-mode voltage coming out of the op-amp is precisely 0.75 V.

V in+ = 0.75 + 0.5 sin 2π ⋅ 1 MHz

V CI+
0.75 V V out+

V out−
V CI−

All caps are 1 pF

V in− = 0.75 − 0.5 sin 2π ⋅ 1 MHz

Figure 34.66 ADC building block discussed in Ex. 34.21.

Chapter 34 Implementing Data Converters 379

The simulation results are shown in Fig. 34.67. Note how, as we would expect, the
gain of the circuit is two. The signals shown are ideal. T

V out+ − V out−

V in+ − V in−

Figure 34.67 Input and output for the circuit of Fig. 34.66.

Example 34.22
Repeat Ex. 34.21 if the common-mode voltage coming out of the op-amp sees an
offset of 100 mV, i.e., it is 850 mV.
The differential input and output signals with this output common-mode offset
look exactly like what is seen in Fig. 34.67. The single-ended output signals, Fig.
34.68, show the offset (the signals swing around 850 mV in Fig. 34.68). Clearly a
common-mode offset in the op-amp output signals isn't a concern (unless it's so
large that it limits the op-amp output swing range). Likewise an offset in the
common-mode voltage of the input signals isn't a concern (this comment is easy to
verify with simulations). What is a concern, though, is the value of the voltages
used for VCI+ and VCI−. T

V out+
V out−

Figure 34.68 Output signals for the circuit of Fig. 34.66 if common-mode voltage is 0.85 V.
380 CMOS Mixed-Signal Circuit Design

In Fig. 34.66 VCI+ and VCI− are shorted together and connected, through a switch,
to 0.75 V (VCM). It can be shown that when this occurs, the absolute value of the voltage is
irrelevant because it is common to both input signal paths, see Eq. (34.53). This means
that if we used ground instead of VCM in Fig. 34.66, we would get the same outputs. A
problem does occur if the difference in the voltages (when adding or subtracting a voltage
from the input signal) isn't exactly what is desired, see Eq. (34.61).
While an offset in the common-mode voltage isn't important, the op-amp's offset is
a concern. The op-amp offset voltage is zeroed out when using the topology shown in Fig.
34.66. Equation (34.50) was derived assuming the op-amp had a nonzero offset voltage
and shows the offset will not (ideally) affect the building block's output signals. To show
the removal of the offset using simulations, consider the following example.

Example 34.23
Simulate the operation of the circuit shown in Fig. 34.69. This figure is Fig. 34.66
redrawn with a 100 mV op-amp offset.
The simulation results are shown in Fig. 34.70. Figure 34.70 should be compared
to Fig. 34.67. Note how the unrealistically large offset has no effect on the building
block's output signals. T

V in+ = 0.75 + 0.5 sin 2π ⋅ 1 MHz

0.75 V V out+
100 mV
V out−

All caps are 1 pF

V in− = 0.75 − 0.5 sin 2π ⋅ 1 MHz
Offset

Figure 34.69 ADC building block discussed in Ex. 34.23.

If the op-amp offset is zeroed out and doesn't affect the circuit's outputs when
using the basic topology shown in Fig. 34.30, why would we want to consider some other
topology? The answer to this question comes from the realization that the op-amp's
outputs must settle to the final accuracy of the ADC, referring to Fig. 34.55, by the falling
edge of all three phases of the clock. It would be nice to make the settling during one of
these three (or two) phases irrelevant. Also, and perhaps more importantly, it would be
nice to use other types of CMFB (discussed in the next section).
Chapter 34 Implementing Data Converters 381

V out+ − V out−

V in+ − V in−

Figure 34.70 Input and output for the circuit of Fig. 34.69 with op-amp offset of 100 mV.

Consider the building-block topology shown in Fig. 34.71. During the sampling
phase, the inputs of the op-amp are shorted to the common-mode voltage. During this
time the op-amp operates open loop, and settling time is meaningless. The status of the
op-amp outputs during this time is discussed in the next section. The charge stored on the
capacitors during the storage phase is
φs
Q I,F = C I,F ⋅ (V in − V CM ) (34.94)
while during the hold phase
φ φ
Q I h = C I ⋅ (V CI − V CM ± V OS ) and Q Fh = C F ⋅ (V out − V CM ± V OS ) (34.95)

V CM
φs
φs
φh
CF
φh
φh CI
V in+
V CI+ V out+
φs
V CI− V out−
V in− CI

CF φh

φs
V CM

Figure 34.71 Alternative ADC building block.

382 CMOS Mixed-Signal Circuit Design

Once again knowing charge must be conserved, the output voltage can be written as
unwanted term

V out = V out+ − V out− =  1 + I  ⋅ (V in+ − V in− ) − I ⋅ (V CI+ − V CI− ) ±  1 + I  ⋅ V OS

C C C
 CF CF CF
(34.96)
This equation should be compared to Eq. (34.53) where the offset was zeroed out during
the sample phase of the clock (the phases φ1 and φ2 ). The topology would be useful in an
ADC where we can guarantee that the offset contribution is well below the data
converter's LSB or in a later stage in the ADC where the accuracy requirements are
relaxed.

Example 34.24
Repeat Ex. 34.23 using the topology shown in Fig. 34.71.
The simulation results are shown in Fig. 34.72. The ratio of CI to CF is one and so,
ideally, the output is just twice as large as the input. The output should swing from
2 V down to −2 V. However, because of the 100 mV offset, which is also
multiplied by a factor of 2, the output is shifted downwards so that it swings from
1.8 V to −2.2 V. T

V out+ − V out−

V in+ − V in−

Figure 34.72 Input and output for the circuit of Fig. 34.71 with op-amp offset of 100 mV.

Dynamic CMFB
The CMFB circuits discussed earlier employ an amplifier to sense the average of the
outputs and feedback a correction to center the signals around VCM. In Ch. 27 we
discussed a CMFB technique used in an op-amp that was dynamic and doesn't employ an
amplifier. A simplification of this dynamic CMFB can be realized by noting that during the
sampling phase in Fig. 34.71 the op-amp inputs are forced to VCM. The scheme we are
about to present won't force the inputs to V CM ± V OS during the sample phase as in the
other topologies based on Fig. 34.30.
Chapter 34 Implementing Data Converters 383

The basic dynamic CMFB circuit is shown in Fig. 34.73. During the sample phase
of the clock the inputs and outputs of the op-amp are shorted to the common-mode
voltage. Also during this time the common-mode feedback voltage, VCMFB, is set to a bias
voltage (Vbias4 if the op-amp of Fig. 34.36 is used [see Fig. 33.60]). During the hold phase,
the CMFB capacitors on the output of the circuit are disconnected from both VCM and
Vbias4 and are used to sense the average value of the outputs. If the outputs move in a
balanced fashion, then VCMFB remains equal to Vbias4. If the average of the outputs moves
upwards above VCM, then VCMFB increases, pulling the output common-mode voltage
downwards. Again, because the CMFB loop utilizes negative feedback, an increase in
VCMFB must result in a decrease in (v o+ + v o− )/2 .

V CM

φs φh

v o+
v o−
V CMFB
φs V CM

V CM
V bias4
CMFB capacitors φs

Figure 34.73 Dynamic CMFB.

Looking at Fig. 34.73 we see that because of the op-amp's offset voltage the
outputs of the op-amp will source/sink a current into VCM during the sample phase of the
circuit's operation. By adding an extra pair of switches to disconnect the CMFB capacitors
from the op-amp outputs we can avoid this situation. Adding the switches causes the
op-amp outputs to approach the power supply rails during the sample phase (because of
the offset voltage). This output railing isn't a problem if an OTA (single-stage) topology
like the one in Fig. 34.36 is used. The outputs have no capacity to hold charge and so
when the CMFB capacitors are reconnected to the op-amp outputs, the outputs
immediately go to VCM (neglecting the connection of the feedback capacitors which are not
shown in Fig. 34.73). If a two-stage op-amp is used then care must be taken to ensure that
the compensation capacitor (which, of course, does have the capacity to hold charge)
doesn't charge to the rail resulting in a large recovery time when the op-amp circuit is put
in the hold mode.
384 CMOS Mixed-Signal Circuit Design

One solution to the problem of offset (when using the topology of Fig. 34.71) is to
AC couple the output of the first op-amp stage to the input of the second op-amp stage, as
in Fig. 34.74 (add a capacitor between the two stages to remove the DC component). The
first stage's offset is stored on the capacitors during the sample phase, while the second
stage's inputs are shorted to Vbias1. When the op-amp is used in the hold phase of
operation, the second stage's offset is referred back to the input of the op-amp after
dividing by the first stage's gain. For example, if the first stage of the op-amp has a gain of
50 and the second stage's offset is 10 mV, then the input-referred offset of the op-amp in
the hold mode is only 0.2 mV. Note that the gain of the first stage can't be too large. If,
for example, the first stage's gain were 1,000 and its offset were 10 mV, the outputs
would saturate and the offset would not be stored on the capacitors. If the gain of the first
stage were 50 with a 10 mV offset, then the (differential) outputs of the first stage would
change by 500 mV. As long as the MOSFETs remain in the saturation region, the offset
storage works as desired.

V bias1 VDD VDD V bias1

VDD VDD
φs V bias1 φs

N V CM V CM N
φs φs
v o− v o+

P 2W P

2W

V CMFB

φs
V bias4

φs φs
V CM

Figure 34.74 Implementation of dynamic CMFB.

Chapter 34 Implementing Data Converters 385

Depending on the design parameters the op-amp shown in Fig. 34.74 would be
compensated using either a load capacitance (as if the op-amp were a single stage) or
using Miller compensation by adding a capacitor from the output of the op-amp to the
output of the diff-amp (first stage) with a series resistance to cancel the right-hand plane
zero (as discussed in Ch. 25).
Layout of Pipelined ADCs
Before leaving this chapter, let's comment on the layout of pipeline ADCs. Using a fixed-
height layout structure, with the automatically routed power and ground busses (when the
cells are laid end-to-end), is a good place to start when laying out the op-amp. As seen in
Fig. 34.75, a height (with example values shown) is selected with the width variable. It's
important, as discussed in Ch. 28, to keep the analog signals separate, both physically and
by distance, from the digital signals.

Analog VDD 10 um

Place PMOS here 30 um

n-well

Place NMOS here 30 um

Analog ground 10 um

Figure 34.75 Fixed-height layout structure.

A possible block diagram of the placement of the fixed-height cells together with
the capacitors and switches used to implement a stage of the ADC is seen in Fig. 34.76.
Looking at the input signal, we notice that they are laid out next to each other and routed
as close as possible to the input of the first stage of the ADC. All of the differential analog
signals in the ADC should follow this practice to help make any coupled noise truly
common-mode. Notice how we have placed ground pads adjacent to the input signals.
These pads are not used for ground connections on-chip. The pads are used to help reduce
noise coupling into the input signals. Ideally, these ground pins provide a termination for
the noise keeping the input signals "clean." This is especially important when bonding
wires connect the integrated circuit to a padframe in the final packaged part. The bonding
wires used for digital signals tend to radiate more than enough signal to corrupt the input
signal and ruin the ADC's SNR when placed close to an analog low-level signal.
Next notice that we must have a clock signal in our analog domain. This signal, as
we have seen, is used for clocking the switches in the S/H stage. Although in the figure we
show the placement of the clock adjacent to the input signals, it may be better to move the
pad and, if possible, the routing of the clock signals away from the inputs. The main goal
386 CMOS Mixed-Signal Circuit Design

Pads Gutter for routing low-noise signals.

VDD Reference
VDD ground VDD ground VDD ground
GND Reference
Op-amp Op-amp Op-amp
VDD Power with bias with bias with bias
GND Power capacitors capacitors capacitors
clock clock
drivers switches switches switches
GND
V in+
V in−
signals

signals
signals
clk

clk

clk
GND
Analog domain
Digital domain
Digital power

GND Comparators Comparators Comparators

and latches and latches and latches
VDD
GND Digital correction logic
Out
Out
Out

Figure 34.76 Block diagram layout of a pipeline stage.

when routing the clock signals is to keep the layout regular. Routing clock signals all over
the layout is asking for problems.
Two sets of power and ground pads are used (more if possible) in the analog
domain for the implementation of the ADC. One set of pads is used for supplying power
to the op-amps while the other set is used for supplying the reference voltages to each
stage. The power and ground supplies are common to both digital and analog sections
off-chip. Off-chip the supplies are connected together and decoupled (bypassed) using
large capacitors (actually a wide range of capacitor values are connected in parallel
between the VDD and ground to avoid the increase in a single large capacitor's effective
series resistance with frequency). On-chip decoupling capacitors can be used as well. The
analog and digital power and ground connections are not shared, and so care must be
taken not to decouple the analog VDD to digital ground or digital VDD to analog ground.
Figure 34.77 shows one example of how the decoupling capacitors can be connected.
Chapter 34 Implementing Data Converters 387

Bonding inductance Interconnect resistance

On-chip decoupling capacitor.

Pin Pad Pad Pin

Analog circuitry

VDD
Off-chip decoupling capacitor.

Digital circuitry
Pin Pad Pad Pin

On-chip decoupling capacitor for the digital circuitry.

Figure 34.77 Showing how decoupling capacitors are used in a mixed-signal chip.

In general we don't want any DC current flowing on our reference voltages (those
voltages used for VCI in our op-amp) because of the possible voltage drop along the
supplying line. There may also be a voltage drop along the metal lines supplying power to
the op-amps. However, small (DC) changes in these voltages are usually not a significant
factor in the precision of the ADC. These changes could be a factor if the output signal
approaches the power-supply voltages where the op-amp runs out of head room. AC
changes in the power-supply voltages can be a significant factor limiting the ADC's
performance.
Ground planes and wide conductors should be used where possible. Using power
and ground planes not only provides good distribution of power and ground but also
increases the capacitance between the supplies. Areas, labeled "gutter" in Fig. 34.76
should be provided for low-level analog signals. These areas are free to allow the quiet
routing of the switch inputs and outputs to the op-amp outputs.
It's also a good idea to use guard rings around the sensitive analog circuits (e.g.,
the switched capacitors) to avoid coupled substrate noise. Figure 34.78 shows the basic
idea. In this figure the capacitors are laid out over an n-well. The n-well is tied to analog
VDD through an n+ implant in the n-well and metal. Surrounding the n-well is a ring of
p+. This ring is tied to analog ground. The idea is that the p+ will provide a sink for any
current injection from the surrounding circuitry. Because ground is the lowest potential in
the circuit, the noise will terminate on this p+ and not penetrate the area under the
capacitors (and then hopefully not couple into the capacitors). While this works well by
itself, it may not be enough. Noise currents may still move deep in the substrate and work
their way up under the capacitors. Because the n-well under the capacitor is held at the
most postive potential in the circuit, any noise that does get into the n-well will hopefully
be swept out through VDD and not couple into the capacitors.
388 CMOS Mixed-Signal Circuit Design

p+ tied to ground

n-Well

n+ tied to VDD
Capacitor layout area

Figure 34.78 Using guard rings for protection in sensitive analog blocks.

Finally, if a sensitive analog signal does need to cross a digital signal (an example
being the potential need to feed the switch inputs and outputs across the three phases of
the switch clock signals in Fig. 34.76) a shield should be used, Fig. 34.79. In this figure
the sensitive analog signal is assumed to exist on Metal1, while Metal2 is used for an
analog ground shield from the digital signal on Metal3. This shield is used for isolation
providing a terminating plane for the electric fields resulting from the voltages on both the
digital and analog signals.

Metal2 shield
(tied to analog ground)
Layout view Digital signal, Metal3

Analog signal

Metal3 Digital signal

Cross section
Metal2 Analog ground (shield)

Metal1 Sensitive analog signal

Figure 34.79 Shielding a sensitive analog signal from a digital signal.

Chapter 34 Implementing Data Converters 389

REFERENCES
[1] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge
University Press, 1998.
[2] R. E. Suarez, P. R. Gray, and D. A. Hodges, “All-MOS Charge Redistribution
Analog-to-Digital Conversion Techniques - Part II,” IEEE Journal of Solid-State
Circuits, Vol. 10, No. 6, pp. 379-385, December 1975.
[3] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout, and
Simulation, Wiley-IEEE, 1998.
[4] S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits,
Second Edition, McGraw-Hill, 1998.
[5] J. A. Schoeff, An Inherently Monotonic 12-bit DAC, IEEE Journal of Solid-State
Circuits, Vol. SC-14, No. 6 December 1979, pp. 904-911.
[6] C. G. Yu and R. L. Geiger, "An Automatic Offset Compensation Scheme with
Ping-Pong Control for CMOS Operational Amplifiers," IEEE Journal of
Solid-State Circuits, Vol. 29, No. 5 May 1994, pp. 601-610.
[7] C. C. Enz and G. C. Temes, "Circuit Techniques for Reducing the Effects of
Op-Amp Inperfections: Autozeroing, Correlated Double Sampling, and Chopper
Stabilization," Proceedings of the IEEE, Vol. 84, No. 11, pp. 1584-1614,
November 1996.
[8] I. E. Opris, L. D. Lewicki, and B. C. Wong, "A Single-Ended 12-bit 20 Msample/s
Self-Calibrating Pipeline A/D Converter," IEEE Journal of Solid-State Circuits,
Vol. 33, No. 12, December 1998.
[9] E. Fong, private communication, May 2001.
[10] B. Ginetti, P. G. A. Jespers, and A. Vandemeulebroecke, "A CMOS 13-b Cyclic
RSD A/D Converter," IEEE Journal of Solid-State Circuits, Vol. 27, No. 7, July
1992.
[11] W. C. Black and D. A. Hodges, "Time Interleaved Converter Arrays," IEEE
Journal of Solid-State Circuits, Vol. SC-15, No. 6, December 1980.
[12] B. S. Song, M. F. Tompsett, and K. R. Lakshmikumar, "A 12-bit, 1-MSample/s
Capacitor Error-Averaging Pipelined A/D Converter," IEEE Journal of Solid State
Circuits, Vol. 23, No. 6, pp. 1324-1333, December 1988.
[13] H. S. Chen, B. S. Song, and K. Bacrania, "A 14-b 20-Msample/s CMOS Pipelined
ADC," IEEE Journal of Solid State Circuits, Vol. 36, No. 6, pp. 997-1001, June
2001.
QUESTIONS
34.1 Assuming the DAC shown in Fig. 34.1 is 8 bits and VREF+ = 1.5 V and VREF− = 0,
what are the voltages on each of the R-2R taps?
390 CMOS Mixed-Signal Circuit Design

34.2 Give an example of how the traditional current-mode DAC will have limited
output swing.
34.3 Repeat question 34.1 for the DAC shown in Fig. 34.2.
34.4 For the wide-swing current mode DAC shown in Fig. 34.3, what are the voltages
at the taps along the R-2R string assuming 8 bits, VREF+ = 1.5 V, VREF− = 0, and a
digital input code of 0000 0000?
34.5 Can the op-amp shown in Fig. 34.36 be used in fully-differential implementations
of the DACs shown in Figs. 34.1 - 34.3? Why or why not?
34.6 Show the detailed derivation of Eqs. (34.12)-(34.14).
34.7 Why would we want to use both current segments and binary-weighted currents to
implement a current-mode DAC? (Why use segmentation?)
34.8 Why do we subtract ∆A in Eq. (34.36)? Why not add the gain variation?
34.9 Does the matching of the capacitors matter in the S/H of Fig. 34.31? Why or why
not?
34.10 Neglecting offsets and assuming the φ1 switches are closed in Fig. 34.34, can the
two inverting terminals of the error amplifier (the input terminals of the fully-
differential op-amp) be at different potentials?
34.11 When the φ3 switches are closed in Fig. 34.34, is it possible for the inverting inputs
of the error amplifier to be at different potentials? Again, neglect offsets.
34.12 Repeat Ex. 34.10 if the cyclic ADC's input is 0.41 V.
34.13 Is kick-back noise from the comparator a concern for the circuit of Fig. 34.39?
34.14 Derive the transfer function for the circuit shown in Fig. 34.80.

φs φh

CF φs
V CF+ φh
φh
CL
CI
V in+ V out+
V CI+
V CI− CI V out−
V in−
CL
V CF− CF
φs

φh

Figure 34.80 Circuit used in question 34.14.

Chapter 34 Implementing Data Converters 391

34.15 Repeat Ex. 34.16 if the input voltage is 0.41 V.

34.16 Repeat Ex. 34.17 if the input voltage is 0.41 V.
34.17 Resketch the clock waveforms for Fig. 34.54 if bottom plate sampling is used.
34.18 Show the derivation leading up to Eq. (34.83). Show, using practical values for
mismatch, how the squared mismatch terms are negligible.
34.19 What happens to the error adjustment term in Eq. (34.92) if the capacitors in the
S/H are perfectly matched?
34.20 Repeat Ex. 34.18 if all capacitors are 1 pF (the ideal situation) and verify that the
error out of the stage is zero.
34.21 Sketch a circuit to provide the inputs for the four-phase, nonoverlapping clock
generator shown in Fig. 34.81.

In1
Phase1

Nonoverlapping clock signals

Phase2
In2

Phase3
In3

Phase4
In4

Figure 34.81 Four-phase, nonoverlapping clock generator.

34.22 What is the main advantage of using dynamic CMFB over other CMFB circuits?
What is the main disadvantage?
392 CMOS Mixed-Signal Circuit Design

34.23 Can MOSFETs be used to implement the on-chip decoupling capacitors in Fig.
34.77?
34.24 Sketch the cross-sectional view of the layout in Fig. 34.78.
34.25 Figure 34.82 shows the implementation of a pipeline DAC. How would we
implement this DAC using a topology similar to Fig. 34.42? Sketch the DAC's
implementation and the timing signals (clock phases) used.

S/H ×1 + S/H ×1 + S/H ×1 V out

2 2 2

Stage 1 Stage 2 Stage N

b0 b0 b1 b1 b N−1 b N−1
V REF+ V REF− V REF+ V REF− V REF+ V REF−

Figure 34.82 A pipeline digital-to-analog converter.

 Chapter

35
Integrator-Based CMOS Filters

We've covered the detailed design of analog interfaces used for analog-to-digital and
digital-to-analog conversion in the past five chapters. While we can perform signal
processing and filtering in the digital domain, as seen in Fig. 30.2, analog antialiasing and
reconstruction filters are still required in our system. Analog continuous-time filters (a
simple example being the RC circuit shown in Fig. 30.9) can be faster (have wider
bandwidths) and take up less area than their discrete-time counterparts. However, unlike
discrete-time filters, continuous-time filters cannot be fabricated with precise transfer
functions and must be tuned. This is especially true if passive resistors and capacitors are
used where each can have a variation of ± 20% . By using active CMOS integrators in the
filter implementations instead of passive elements, we can electrically tune the filters. Also,
we can more easily implement higher order filters while minimizing the effects of loading.
In this chapter we discuss analog filters (both continuous- and discrete-time filters
where the input and output are analog) made using continuous-time analog integrators
(CAIs or active-RC integrators), MOSFET-C integrators, transconductor-capacitor
(gm-C) integrators, and discrete-time analog integrators (DAIs). We also discuss digital
filter design (which, of course, is also a discrete-time filter) based on the topologies
developed using the digital integrator (e.g., see Fig. 31.34) where the input and output are
digital.

35.1 Integrator Building Blocks

35.1.1 Lowpass Filters
To methodically develop our understanding of CMOS filters, consider the lowpass filter
shown in Fig. 35.1. The transfer function of this filter (see also Ex. 30.3) is
V out ( f ) 1
= (35.1)
V in ( f ) 1 + jωRC
394 CMOS Mixed-Signal Circuit Design

f 3dB = 1
2πRC
v in (t) R v out (t) 0 dB f (Hz)
V out ( f ) 20 dB/decade
C
Vin ( f )

V out ( f )
∠
s=− 1 Im Vin ( f ) 0
RC
45

Re 90

s plane 0.1f 3dB 10f 3dB

Pole s = σ + jω

Figure 35.1 First-order lowpass filter.

where ω = 2π ⋅ f and f is the frequency of the input (and thus the output). Next consider
the block diagram in Fig. 35.2. This figure shows an integrator and a summing block
(which by now we know can be implemented with a single op-amp). The output of the
block diagram can be determined by solving

V out ( f ) = G
s ⋅ (Vin ( f ) − V out ( f )) (35.2)

or
V out ( f )
= 1 (35.3)
V in ( f ) 1 + s/G
where for a sinewave input s = jω . Comparing this equation to Eq. (35.1), we see that if
we set the integrator's gain, G, using

G = 1 where f 3dB = G (35.4)

RC 2π
we can use an integrator to implement a lowpass first-order filter (the filter has a single
pole).

In G Out
V in ( f ) s V out ( f )
Integrator

Figure 35.2 Block diagram of an integrator-based lowpass filter.

Chapter 35 Integrator-Based CMOS Filters 395

35.1.2 Active-RC Integrators

We showed a continuous-time analog integrator (CAI) in Fig. 32.24. The fully-differential
version of this integrator is shown in Fig. 35.3. The CAI goes by other names, including
the Miller integrator, the active-RC integrator, and when the resistors are replaced with
MOSFETs operating in the triode region, the MOSFET-C integrators. The gain of the
CAI can be written as
G

V out V out+ − V out− 1

= =s⋅ 1 (35.5)
V in V in+ − V in− RC

R
V in+ V out−

V in− V out+
R
Switched so gain is
positive
C

Figure 35.3 A continuous-time analog integrator (CAI).

Reviewing Fig. 35.2, we see that the CAI of Fig. 35.3 alone will implement the
needed integration but not the summing (difference) block. By adding an additional
feedback path, as we did in Fig. 32.24, the entire block diagram of Fig. 35.2 can be
implemented. Figure 35.4 shows the integrator-based implementation of the circuits in

R C
V out−

R
V in+ V out−
R
V in− V out+
R

V out+ Active-RC filter.

C

Figure 35.4 Implementation of a first-order lowpass filter using a CAI.

396 CMOS Mixed-Signal Circuit Design

Figs. 35.1 and 35.2 (noting the op-amp must be able to drive a resistive load). This filter is
called an active RC filter because the RC is used with an active element (the op-amp). At
this point there are several practical and useful modifications that we can make to this
filter. However, let's work an example before moving on.

Example 35.1
Simulate the operation of the filter in Fig. 35.4 from DC to 100 MHz if R = 10k
and C = 10 pF. Show both the magnitude and phase responses of the filter.
Assume the op-amp is ideal.
From Fig. 35.1 we know the 3 dB frequency of the filter is 1.59 MHz. The
simulation results are shown in Fig. 35.5. The magnitude and phase response
follow, as expected, the responses for the simple RC filter shown in Fig. 35.1. T

V out ( f )
V in ( f )

V out ( f )
∠
V in ( f )

Figure 35.5 Magnitude and phase responses for the first-order filter in Fig. 35.4
if R = 10k and C = 10 pF.

What would happen if we switched what we define as V out+ and V out− in the filter
described in Ex. 35.1 without changing any other connections? Perhaps it is trivial, but the
answer is that the output will be inverted. We can modify the block diagram of Fig. 35.2
by simply multiplying the output by −1, as seen in Fig. 35.6. The phase shift in Fig. 35.5
would shift up or down by 180 degrees. It would vary from 180 to 90 degrees, or from
Chapter 35 Integrator-Based CMOS Filters 397

V in ( f )
In G1 Out
s 1 V out ( f )

Integrator

G2
Switch for inversion
see Fig. 35.4

RF C

G1 = 1
RI RIC
V in+ V out+ R
G2 = I
RI RF
V in− V out−
G1G2
RF f 3dB =
2π
C

Figure 35.6 Integrator-based first-order filter.

−180 to −270 (because +180 degrees is the same as −180 degrees) instead of from 0 to
−90 degrees.
If we allow the resistors used in the filter to have different values, as seen in Fig.
35.6, we can add a feedback gain to our block diagram. Assuming the outputs are labeled
so that we don't have an inversion in the output of the filter (i.e., they are labeled as seen
in Fig. 35.4), we can write
V in V out V out
− = (35.6)
RI R F 1/sC
It's important to note (for use later) that in order to subtract the output from the input, the
voltages are first changed to currents. This equation can be rewritten as
RF
V out RI
= (35.7)
V in 1 + sR F C
Using the block diagram in Fig. 35.6, we can write
1
V out G2 G G
= and f 3dB = 1 2 (35.8)
V in 1 + G sG 2π
1 2
398 CMOS Mixed-Signal Circuit Design

Equating coefficients in these equations results in

RI
G2 = and G 1 = 1 (35.9)
RF RIC
Note that at DC where s → 0 , the block diagram in Fig. 35.6 becomes the classic feedback
diagram with the forward gain approaching infinity and a feedback factor of G2. Then from
classic feedback theory, the closed-loop gain becomes 1/G2 or, for the filter in Fig. 35.6,
RF/RI. Of course, analyzing this circuit (using loop equations) at DC when the capacitor is
an open results in the same gain.

Example 35.2
Modify the filter in Ex. 35.1 so that the low-frequency gain is 20 dB.
Using Eq. (35.7) or Eq. (35.8), we leave C = 10 pF and RF = 10k. To get the gain
of 10, we make RI = 1k. The simulation results are shown in Fig. 35.7. T

V out ( f )
V in ( f )

Figure 35.7 A first-order filter with gain, see Ex. 35.2.

Effects of Finite Op-Amp Gain Bandwidth Product, fu

In the previous two examples we assumed a near-ideal op-amp. We know from Fig. 34.21
that the open-loop gain of the op-amp can be written, assuming a dominant-pole
compensated op-amp, by
V A OLDC
A OL ( f ) = v −outv = f
(35.10)
+ −
1 + j ⋅ f 3dB

where v+ and v− are the voltages on the noninverting and inverting op-amp input terminals,
respectively. (Note how we are using f3dB in both Figs. 35.6 and 34.21 to indicate the 3 dB
frequency of a frequency response.) When a practical op-amp is operating at frequencies
above a few kHz, we can approximate the open-loop response (knowing the imaginary
part of the denominator is much larger than the real part) as
A OLDC ⋅ f 3dB f u 2πf u ω u
A OL ( f ) ≈ = = s = s (35.11)
j⋅f j⋅f
Chapter 35 Integrator-Based CMOS Filters 399

where, again from Fig. 34.21, fu is the frequency where the op-amp's open loop gain is
unity (0 dB). Rewriting Eq. (35.6) to include the op-amp's finite gain bandwidth product
(that is, fu ) and assuming, without the loss of generality that the op-amp is operating with
a single-ended output (v+ tied to VCM [AC ground]), results in
V in − v − V out − v −
− = sC ⋅ (V out − v − ) (35.12)
RI RF
After some algebraic manipulation with v − = −V out /A OL ( f ) , we get
RF
V out RI
= (35.13)
1 + sCR F + A OL ( Ff ) + A OL1( f )  1 − RFI 
V in sCR R

Desired response

or, with A OL ( f ) = ω u /s
RF
V out RI
= (35.14)
+ s ⋅  CR F + ω1u  1 − RFI   + 1
V in CR F R
s2 ωu
 
This equation is very revealing and shows just how significant a limitation the op-amp can
be in a filter. For the moment, to simplify things, let's assume ω 2 << ω u /CR F so that the s2
term in Eq. (35.14) is negligible. We can then write the magnitude and phase responses as
RF

= −tan−1  ωCR F + ωω  1 − F  
V out RI V out R
= and ∠
V in 2 Vin  u RI 
1 +  ωCR F + ωωu  1 − RFI  
R
 
(35.15)

Example 35.3
Suppose a first-order filter is designed based on the topology seen in Fig. 35.6,
where ω u = 10/R F C and R F /R I = 10. Assuming ω 2 << ω u /CR F , comment on how
the magnitude and phase responses of the filter will be affected by the finite
op-amp, fu.
The op-amp's unity gain frequency is only 10 times larger than the bandwidth of
the filter. This means the op-amp's closed-loop bandwidth (with a gain of 10) is
equal to the desired bandwidth of the filter. The bandwidth of a gain of 10 op-amp
circuit is f u /10, which here is equal to the ideal filter 3 dB frequency of 1/2πR F C .
The magnitude of the filter's response can be written as
RF

= −tan−1  ω ⋅
V out RI V out CR F 
= and ∠
V in CR F 2 Vin  10 
1 +  ω ⋅ 
10 

which shows the filter's 3 dB frequency is off by a factor of 10. T

400 CMOS Mixed-Signal Circuit Design

The point of the preceding example is, in general lowpass filter design, to minimize
the effects of the op-amp's finite fu a low value of closed-loop DC gain should be used. In
the remaining discussion let's assume R F /R I = 1 , so Eq. (34.14) simplifies to
V out 1
= CR F
(35.16)
V in ⋅ s + s ⋅ CR F + 1
2
ωu

The poles of this transfer function are located at

CR
−CR F ± (CR F ) 2 − 4 ω uF
s p1, p2 = CR F
(35.17)
2⋅ ωu

noting that if ω u → ∞ , then s p1 = ∞ , and s p2 = −1/CR F (the ideal position of the pole, see
Fig. 35.1).
To get some idea of the required op-amp fu (ω u = 2πf u ) , let's assume that we want
the pole to vary no more than 1% from the ideal location due to finite op-amp bandwidth
CR
−1 = 99 ⋅ −CR F − (CR F ) − 4 ω u
2 F

CR
(35.18)
CR F 100 2 ⋅ ω uF
This can be rewritten as
ω u ⋅ CR F 1
1.01 = − (ω u ⋅ CR F ) 2 − 4(ω u ⋅ CR F ) (35.19)
2 2
If we let x = ω u ⋅ CR F , then we need to solve
x − x 2 − 4x = 2.02 (35.20)
knowing x is positive and much larger than one (ω u >> 1/CR F ). Solving Eq. (35.20) for x,
results in x = 100. This means the op-amp's unity gain frequency must be 100 times larger
than the filter's f3dB in order for the variation of this frequency (the pole) to deviate less
than 1% from the ideal. If we can withstand a 10% decrease in the filter's cutoff frequency,
then fu need only be 10 times larger than the filter's f3dB. Clearly, from Eq. (35.14), the
first-order filter's frequency response is actually second-order when the op-amp's gain
bandwidth product fu is a factor. Therefore, the shapes of the magnitude and phase
responses will deviate from the ideal first-order shapes seen in Fig. 35.1 so we can draw
two very practical conclusions. First, even if it were possible to fabricate precise resistor
and capacitor values, the limitations of the op-amp's finite bandwidth may still require the
use of tuning when filtering with active-RC integrator-based filters. Tuning would consist
of adding or removing resistors and capacitors to adjust the precise filter cutoff frequency
(adding/removing the elements using either fuses or, if possible, MOSFET switches).
Second, the op-amp's fu should be at least 10 times larger than the cutoff frequency ( f3dB )
of the filter (again assuming a closed-loop DC gain of unity, i.e., RF /RI = 1). This is a
general "rule-of-thumb." Precision filters (well-defined magnitude and phase responses)
would require wider bandwidth op-amps. Consider the following example.
Chapter 35 Integrator-Based CMOS Filters 401

Example 35.4
Repeat Ex. 35.1 if an op-amp is used with a DC gain of 10,000 and an fu of 10
MHz.
Because the op-amp's AOLDC is 10,000 and fu = 10 MHz, the op-amp's open loop
f3dB is 1 kHz (see Fig. 34.21). We can use the circuit shown in Fig. 35.8 (see also
Fig. 32.45) in our SPICE simulation to model an op-amp with finite fu. The RC in
Fig. 35.8 is selected to give an op-amp open loop f3dB of 1 kHz.

v o+
1k
10k 1
v−
E1
V CM 159n
op-amp outputs

v+ 159n
E2
1k
v o−
10k
1

Figure 35.8 SPICE modeling a differential input/output op-amp with finite bandwidth.

The 3-dB frequency of the filter described in Ex. 35.1 is, under ideal
conditions, 1.59 MHz. Because our op-amp's unity gain frequency is only 10 MHz,
we would expect, from Eq. (35.16), the op-amp to affect the frequency response
of the filter. Figure 35.9 shows the simulation results using the op-amp model of
Fig. 35.8. Comparing Fig. 35.9 to Fig. 35.5, we see differences in both the
magnitude and phase responses of the filters. The magnitude response of Fig. 35.9
initially rolls off at 20 dB/decade below the ideal 1.59 MHz. Around 10 MHz the
response transitions to 40 dB/decade. Clearly this faster roll off is the result of the
op-amp's closed-loop pole coming into play. The limiting behavior of the op-amp,
when looking only at the magnitude response, may be welcome (the filter's
response rolls off faster) in a lowpass filter. However, it is not welcome in other
filters (a highpass filter, for example). Figure 35.10 shows what happens if we
decrease the filter's 3 dB frequency to 159 kHz by increasing the resistors used to
100k. What we are doing here is showing how making the op-amp's bandwidth
much larger than the filter's affects the frequency response of the circuit. The
magnitude response starts to fall off at −40 dB/decade at the op-amp's unity gain
frequency, fu, of 10 MHz. Also seen in Fig. 35.10 is the phase response of the
filter. The op-amp's (closed-loop) phase response, which starts rolling off one
decade below fu, results in the final phase shift of the filter approaching −180
degrees. T
402 CMOS Mixed-Signal Circuit Design

V out ( f )
V in ( f )

V out ( f )
∠
V in ( f )

Figure 35.9 Magnitude and phase responses for the first-order filter in Fig. 35.4
if R = 10k and C = 10 pF using an op-amp with a 10 MHz unity-gain
frequency.

−20 dB/decade
−40 dB/decade

Figure 35.10 Increasing the resistance to 100k and replotting Fig. 35.9.
Chapter 35 Integrator-Based CMOS Filters 403

To model the effects of op-amp finite bandwidth on an active-RC filter's frequency

response we can add a pole to the ideal transfer function. Assuming unity gain in the
passband (see Eq. [35.3]) results in
Undesired

V out ( f )
= 1 ⋅ 1 (35.21)
V in ( f ) 1 + s/G 1 + j f
fu

This result could have been used in the previous example to predict how the op-amp
affects the filter's behavior. If the filter has gain (> 1) in the passband, see Eq. (35.8), we
can modify this equation to read
Undesired
1
V out ( f ) G2 1
= ⋅ (35.22)
V in ( f ) 1 + G 1sG 2 1 + j f
G 2 ⋅f u

For a higher order filter we would multiply the desired frequency response by the
undesired term's (the op-amp's) response for each op-amp used in the circuit. Clearly, this
limits the order of the filter (limits the number of op-amps used in a circuit; a first-order
filter uses one op-amp, a second-order filter uses two op-amps, etc.). This is especially
true if the filter has a passband approaching the fu of the op-amps used.
Active-RC SNR
Consider the single-ended active-RC filter shown in Fig. 35.11. Let's assume an ideal
op-amp with a maximum RMS output voltage of VDD/(2 2 ) . The RMS input-referred
noise of the filter, assuming thermal noise dominates over the bandwidth of interest, is
simply kT/C . The filter's SNR can then be written as

VDD/  2 2  2
SNR = 20 ⋅ log = 10 ⋅ log VDD /8 (35.23)
kT/C kT/C

This result shouldn't be too interesting at this point. As we've already seen, the size of the
integrating capacitor fundamentally sets the SNR in integrator-based data converters or

C V out
VDD
VDD
V in R
VDD /2 V CM
V out
V CM 0
time

Figure 35.11 Estimating maximum possible SNR of an active-RC filter.

404 CMOS Mixed-Signal Circuit Design

modulators. But consider the following: the maximum electrical energy stored in the
capacitor used in an integrator is
2
Maximum electrical energy = 1 C ⋅  VDD  (35.24)
2 2
Equation (35.23) can then be rewritten as
2
1  VDD 
2
C
2  2  Electrical energy
SNR = 10 ⋅ log VDD /8 = 10 ⋅ log = 10 ⋅ log (35.25)
kT/C kT Thermal energy
This equation can also be used to estimate the fundamental dynamic range, DR, of a filter.
That is, we can estimate DR by assuming DR = SNR. Of course, as discussed in Ch. 31, a
more accurate estimate of DR is the measured signal-to-noise plus distortion ratio, SNDR.
Practically, DRs approaching 90 dB (15 bits) can be attained using active-RC filters with
good polysilicon resistors (to avoid the large nonlinear voltage coefficient associated with
diffused or implanted resistors) and linear capacitors. Bandwidths approaching 50 MHz,
assuming 500 MHz fu op-amps are used, can be attained (at, of course, lower DRs).
35.1.3 MOSFET-C Integrators
Let's now look at a variation of the active-RC filter where the resistors are replaced with
MOSFETs. Figure 35.12 shows a MOSFET-C filter. In order for the MOSFETs to behave
as resistors they must remain in the triode region. Using long length devices helps ensure
triode operation. Because the MOSFETs are operating as resistors, their speed is not
governed by their gate-source voltage or channel length, as indicated in Eq. (33.20).
However, the linearity of the MOSFET resistors is still very important as is the possiblity
that the MOSFETs will introduce a parasitic pole into the filter's frequency response
because of the distributed resistance/capacitance of the channel (Fig. 35.12). Figures 33.23
and 33.29 show how the channel resistance of an NMOS device changes with VDS. For
large input signals, the active MOSFET resistors become nonlinear, resulting in filters with
SNDRs of around only 40 dB. The bandwidth of the MOSFET-C filters parallels that of
the active-RC filters.
We might be questioning the usefulness of the MOSFET-C filter with an SNDR of
only 40 dB. Clearly this filter will only find use in data conversion systems using six bits of
resolution or less (36 dB DR) or in systems that process continuous-time signals. The big
benefit of this filter over the active-RC filter is its ability to be tuned. Tuning the active-RC
filter required adding or removing, via switches or fuses, resistors or capacitors in parallel
or series with the existing resistors and capacitors. Tuning the MOSFET-C filter shown in
Fig. 35.12 can be accomplished by adjusting Vtune upwards or downwards. If we assume
long-channel behavior, we can write the resistance (see Ch. 9) of the MOSFETs in terms
of Vtune (assuming the input common-mode voltage of the op-amp is 0) as

Rn = 1 (35.26)
 
KP ⋅ WL ⋅  V tune − V THN − V DS 
 
 =Vin 
Chapter 35 Integrator-Based CMOS Filters 405

V tune
MOSFET-C filter
C

M1
V in+ V out−

V in− V out+

G
Drain current

S D
One over the slope of n+ n+
this line is the MOSFETs
resistance

Drain-source voltage Inverted channel Parasitic

resistance channel
capacitance

Figure 35.12 A first-order MOSFET-C filter.

The current through M1 in Fig. 35.12 is

V in+
= V in+ ⋅ KP ⋅ W (V tune − V THN − V in+ ) (35.27)
R n1 L
Some improvement in the linearity of the MOSFET resistors, say 10 dB (resulting in an
SNDR of 50 dB), can be achieved by utilizing the fully-balanced signals available in the
circuit. Consider replacing M1 in Fig. 35.12 with the pair of MOSFETs, M1A and M1B,
shown in Fig. 35.13. The resulting current is now
V in+ V in−
+ = KP ⋅ W [V in+ ⋅ (V tune+ − V THN − V in+ ) + V in− ⋅ (V tune− − V THN − V in− )]
R n1A R n1B L
(35.28)
Knowing V in+ = −V in− and letting V tune = V tune+ − V tune− , we can write the equivalent
current through M1 as
V in+
= V in+ ⋅ KP ⋅ W ⋅ V tune (35.29)
R n1 L
406 CMOS Mixed-Signal Circuit Design

V tune+ V tune−

V in+
M1A

V in−
M1B

Figure 35.13 Linearizing MOSFET resistors.

The result is that the nonlinear behavior of the MOSFET's channel resistance due to the
changing drain-source voltage cancels to a first order. Figure 35.14 shows the
implementation of a first-order MOSFET-C filter using linearized MOSFETs.

V tune+ V tune−

M1A M1B
V in+
V out−
V in− V out+

Figure 35.14 First-order MOSFET-C filter using linearized MOSFET resistors.

Why Use an Active Circuit (an Op-Amp)?

Before going any further, let's realize that we can get the exact same frequency
performance using a simple resistor/capacitor or MOSFET/capacitor as we get when we
use these elements with an op-amp. So, "Why use the op-amp?" The answer to this
question comes when we realize that when a capacitive or resistive load is connected to
the output of the filter (without an active element), the frequency behavior changes. Using
the op-amp allows us to drive an arbitrary (within reason) capacitive or resistive load.
Using an active element will also allow us to cascade first-order sections to implement
higher order filters.
Chapter 35 Integrator-Based CMOS Filters 407

35.1.4 gm-C (Transconductor-C) Integrators

We first described operational-transconductance amplifiers, OTAs, back in Ch. 25. Figure
35.15 shows a schematic symbol, transfer curves, and a possible implementation for an
OTA (based on a fully-differential diff-amp). Transconductor-C, or gm-C, filters use a
circuit, a transconductor, that provides a linear voltage-current transfer curve. Our OTA in
Fig. 35.15 does behave like a transconductor over a portion of the input voltage range but
becomes nonlinear for large input voltage differences, v in+ − v in− . By increasing the lengths
of the NMOS diff-pairs used in the OTA, we can increase the linear common-mode range
of the OTA, making it appear as though it were a transconductor. The fundamental
problems with increasing the lengths of the diff-pair MOSFETs are the increase in the
OTA's input capacitance (affecting the location of the filter's poles and zeroes) and,
perhaps more fundamentally, the inherent reduction in the MOSFET's fT (see Eq. [33.20]).
The MOSFET parasitic capacitances introduce parasitic poles into the filter's transfer
function.

i out+ − i out−
i out+
v in+ v out+
Slope = g m
C
v in−
v out− v in+ − v in−
i out−
(a) Schematic symbol of an OTA
or transconductor. (b) Transfer curves for an OTA.

VDD

i out− i out+
Tuning current

v out− v out+
V CM
v in+ v in−

V bias3

(c) One possible implementation

of an OTA.

Figure 35.15 Showing an implementation of an OTA and transfer curves.

408 CMOS Mixed-Signal Circuit Design

Before discussing these issues in more detail let's look at an important limitation of
gm-C filters; namely, the fact that the transconductor's input voltage must vary. As we
discussed in Sec. 34.1.2, in any precision application the input voltage must remain
constant because of the roll-off associated with the amplifier's CMRR (unless, of course,
the common-mode voltage can be held at a precise value). This limits the SNDR of gm-C
filters to around 50 dB. Again, not too useful if used as an antialiasing or reconstruction
filter unless the system's resolution is less than eight bits (48 dB SNR). The gm-C filter
finds extensive use in continuous-time signal processing.
We can relate the input voltage difference to the output voltage difference for the
circuit in Fig. 35.15a using
I out+ I g m (Vin+ − Vin− )
V out+ − V out− = = − out− = (35.30)
jωC jωC jωC
where, for example, V out+ = V out+ ( f ) , is the frequency domain representation of the output
voltage v out+ (t) . Comparing this result to Eq. (35.5), we can use the same design
techniques if we require
gm
G= 1 = or f 3dB = G (35.31)
RC C 2π
The big benefit of the gm-C filter over the active-RC filter is the ability to tune the filter by
adjusting the transconductor's gm.
The circuit of Fig. 35.15a implements an integrator, as does the active-RC circuit
of Fig. 35.3. However, as seen in Fig. 35.2, we also need to implement a summing block
in a first-order filter. Toward the goal of implementing the summing block, consider the
transconductor circuit shown in Fig. 35.16a. The output current of a single transconductor

g m (v in+ − v in− )
v in+

v in−

(a)
Switched for subtraction

v in+ v out−
C
v in− v out+

(b)

Figure 35.16 Implementing a first-order filter using transconductors.

Chapter 35 Integrator-Based CMOS Filters 409

is, as shown in the figure, g m (V in+ − V in− ) . We can sum this current with the output current
from the second transconductor to implement the summing block in Fig. 35.2. As seen in
Fig. 35.16b, the outputs of the two OTAs are combined, so the currents output from each
transconductor subtract. Assuming each transconductor has the same transconductance,
we can write
g m (V in+ − V in− ) − g m (V out+ − V out− ) − jωC(V out+ − V out− ) = 0 (35.32)
or
V out+ − V out− 1
= (35.33)
V in+ − V in− 1 + jωC ⋅ g1m
If the transconductors have different gms, we can design a filter with a DC gain (see
Problem 35.10), which can be characterized using Eq. (35.8).

Example 35.5
Repeat Ex. 35.1 using a gm-C filter with a gm of 100 µA/V.
To simulate a transconductor using SPICE, a voltage-controlled current source
can be used as seen in Fig. 35.17. In order to set the output common-mode voltage
to VCM in the simulation, we add the large resistors (whose values can be changed
to simulate the finite, nonideal, output resistance of the OTA) connected to VCM.
Not using these resistors after reviewing Fig. 35.16 would result in an unknown
common-mode voltage on the second transconductor input.
In order to have the same time constant, and thus pole location, as in Ex. 35.1,
let's set the capacitor value, in the schematic of Fig. 35.16 to 10 pF. The value of
the transconuctance, 1/gm, is 10k. The simulation results are shown in Fig. 35.18.
As we would expect, the shape follows, exactly, that of the active-RC filter in Fig.
35.5. Also, although not shown, the phase response matches as well. T

i out+ V CM
v in+ v out+
big
v in− i out+
v out− v out+
i out− voutp
v in+ vinp
v in− 100u
vinm voutm
v out−
SPICE i out−
big
G1 voutm voutp vinp vinm 100u
V CM
Notice how SPICE defines positive current flow as current
flowing from the + terminal to the terminal

Figure 35.17 Modeling an ideal transconductor in SPICE using a voltage-controlled

current source.
410 CMOS Mixed-Signal Circuit Design

Figure 35.18 Simulation results for Ex. 35.5.

Common-Mode Feedback Considerations

In most of our high-gain OTAs, such as the one shown in Fig. 34.36, we used the load
capacitances to compensate the amplifier. These capacitances compensated both the
normal, forward, differential signal path as well as the CMFB path. Reviewing Fig. 35.15,
we see that the capacitance in part (a) indeed does provide a load for differential signals.
However, any signal that is common to both outputs (a common-mode signal) doesn't
cause a displacement current to flow through the capacitor. Because both sides of the
capacitor change at the same rate for common-mode signals, the change in voltage across
the capacitor is zero. This can result in unstable CMFB loops. Figure 35.19 shows how we
would break the capacitor in Fig. 35.15 up into two components to provide the same
loading for differential and common-mode signals. We can write
V out+ −Vout−
= I out+ = I out− = (35.34)
1/jω2C 1/jω2C
I out+ = g m (V in+ − V in− ) = I out− (35.35)
V out+ − V out− gm
= (35.36)
V in+ − V in− jωC
which is the same result as Eq. (35.30).

i out+ 2C
i out+
v in+ v out+ v in+ v out+
C
v in− v in− v out−
v out−
i out− i out− 2C

Figure 35.19 Showing how we break the capacitor up to provide a load for
the CMFB circuit.
Chapter 35 Integrator-Based CMOS Filters 411

A High-Frequency Transconductor
A transconductor, Fig. 35.20, can be implemented using the common-mode noise
elimination discussed in Ch. 33 [6]. To increase the input common-mode range, the
lengths of INV1 and INV2 can be increased as in the diff-amp of Fig. 35.15. This, again,
lowers the location of the parasitic poles introduced into the transconductor's response.
Note, in this circuit, that other than the power supplies and the tuning voltage, there are
only two sets of nodes: the input and the output nodes. This allows the transconductor's
capacitances to sum with the load capacitances and be tuned out.

V tune
Inverter power supply

INV1
v in+ v out+

INV2
v in− v out−

Figure 35.20 High-frequency transconductor (see also Figs. 33.36 - 33.39).

35.1.5 Discrete-Time Integrators

Let's consider using the DAIs in Fig. 31.80 to implement a first-order filter. The gain of a
DAI is
V out (z) C −1
= I ⋅ z −1 (35.37)
V in (z) − V out (z) C F 1 − z
Knowing
f
j2π f
z=e s and e jθ = cos θ + j sin θ (35.38)
we can write
V out (z) C 1
= I ⋅ (35.39)
V in (z) − V out (z) C F  f  f
 cos 2π f s − 1  + j sin 2π f s
The sampling frequency (the frequency the discrete-time filter is clocked at) is fs , while
the filter's input frequency is labeled f. If we require f << f s (say at least sixteen times less)
f f f
where cos 2π fs ≈ 1 and sin 2π fs ≈ 2π f s , then we can rewrite Eq. (35.39) as
412 CMOS Mixed-Signal Circuit Design

V out (z) C −1 C fs 1
= I ⋅ z −1 ≈ I ⋅ =G⋅ s (35.40)
V in (z) − V out (z) C F 1 − z C F j2πf
where
CI 1 and
G= ⋅ fs = f 3dB = G (35.41)
CF C F R sc 2π
placing the gain of the integrator in the same form as Eqs. (35.4). From Ch. 27 we should
recognize Rsc as a switched capacitor resistor
1 T
R sc = = s (35.42)
CI ⋅ f s CI
noting that in Ch. 27 we used fclk to indicate the frequency of the clock waveform used
with the filter (not fs as we are here). The equivalent block diagrams for first-order filters
using CAIs and using the DAIs (again assuming f << fs) are compared in Fig. 35.21.

V in ( f ) In G Out
V out ( f )
s
Integrator
(a) CI
G= ⋅ fs
CF

CI −1
V in ( f ) In ⋅ z
Out
V out ( f )
C F 1 − z −1
Integrator
(b)

Figure 35.21 Block diagram of an integrator-based lowpass filter.

(a) Continuous-time and (b) the discrete-time equivalent.

Example 35.6
Sketch the implementation of a DAI-based (switched-capacitor), first-order filter
with characteristics like the one in Ex. 35.1. Using SPICE simulate the design.
The schematic of the filter is shown in Fig. 35.22. Here we are assuming the
clocking frequency of the filter is 100 MHz. If the feedback capacitance, CF, is 10
pF, the size of the input capacitor, CI, is then, from Eq. (35.42) and knowing Rsc is
10k, 1 pF. The 3 dB frequency of the filter is, once again,1/2πR sc C F = 1.59 MHz .
Because of the time-domain (clock) component of the filter, we can't use an AC
analysis for the SPICE simulation. Let's apply a 1 V peak-to-peak sinewave to the
filter at 1.59 MHz and verify the output of the filter is 3 dB down (0.707 V
peak-to-peak). The results are seen in Fig. 35.23.
Chapter 35 Integrator-Based CMOS Filters 413

Indicates plate
10 p closest to the
φ1 φ2 substrate

1p V CM v out
v in

f s = 100 MHz

Figure 35.22 A switched capacitor, first-order filter similar to the one described in Ex. 35.1.
See Fig. 31.80a for additional information concerning the DAI topology used in
this filter.

Let's comment on the exact transfer function of the DAI in Fig. 35.22. It might
be helpful, at this point, to review Fig. 31.80a. We see in Fig. 35.22 that the output
is indeed fed back to the input through a φ1 controlled switch. The result is that the
output, through the feedback loop, sees one clock cycle delay, z−1. The output is
assumed settled on the falling edge of φ2 during each clock cycle. Because of this,
the input, which is settled on the falling edge of φ1, sees only a half clock cycle
delay, z−1/2. This means that the DAI in Fig. 35.22 really has a transfer function of
CI −1
V out (z) = ⋅ z ⋅ [V in (z) ⋅ z 1/2 − V out (z)] (35.43)
C F 1 − z −1
If we think of the input signal arriving a half-clock cycle earlier, then the only
difference in the transfer function here, when compared to the continuous-time
equivalent and assuming f << fs , is a small phase difference. We can delay the input
signal a full clock cycle by adding a φ1 controlled switch on the output of the filter.
However, because this switch may be part of the next filter section, we don't
discuss this option further. T

Filter input
Filter output

Figure 35.23 Output of the switched-capacitor circuit in Fig. 35.22.

414 CMOS Mixed-Signal Circuit Design

Example 35.7
Sketch the switched-capacitor implementation of the discrete-time lowpass (first-
order) filter shown in Fig. 35.24.

In G1 Out
V in ( f ) s V out ( f )

1
V out ( f ) G2
=
G2 V in ( f ) 1 + G 1sG2

Figure 35.24 General implementation of a lowpass first-order filter.

The implementation is seen in Fig. 35.25. The coefficients, see question 35.12, are
C I1 C C
G1 = ⋅ f s and G 2 = I2 ⋅ f s ⋅ 1 = I2 (35.44)
CF CF G 1 C I1
The DC gain, as seen in Eq. (35.8) is set by the ratio of C I2 to C I1 (1/G2 ), and the
filter's 3 dB frequency is
G1G2
f 3dB = (35.45)
2π
Note that the DAI used in this filter has a transfer function of

V out (z) = z −1 ⋅ [ C I1 ⋅ V (z) ⋅ z 1/2 − C I2 ⋅ V (z)] (35.46)

in out
1 − z −1 C F CF
T
CF
φ1 φ2

V CM
C I1 V CM v out
v in

C I2

Figure 35.25 Implementation of the block diagram shown in Fig. 35.24.

Chapter 35 Integrator-Based CMOS Filters 415

The big benefit of switched-capacitor-based filters is the fact that the filters' poles
and zeroes are determined by a ratio of capacitors and an external clock frequency (which
is often a precise frequency set by a crystal oscillator). No tuning is needed. Varying the
clocking frequency can precisely set the filter's characteristics for adaptive filtering
(changing the filter's characteristics on the fly). Switched-capacitor filters with SNDRs in
the 90 dB range have been attained at audio frequencies. SNDRs in the 60-70 dB range
have been achieved when the filter is operating in the MHz range.
In the previous two examples we used ideal op-amps and didn't concern ourselves
with the potential aliasing resulting from the analog sample and hold operation on the
input of the filter. Back in Secs. 34.2.1 and 34.2.2 we derived the requirements placed on
the op-amp's open-loop gain and unity-gain frequency for a given data converter
resolution (which can easily be converted to SNR for the ideal situation using Eq. [31.4]).
An analog antialiasing filter, AAF, (that is, not discrete-time filter) must be used to remove
the potential aliased signal prior to sampling. As with the noise-shaping modulator-based
data converters the fact that the sampling frequency, fs, is much larger than the input
frequencies of interest allows a relaxed AAF design. Indeed, the resistance of the
MOSFET switches used combined with the switched input capacitance (CI ) form a
lowpass filter. This filtering may serve as the switched-capacitor filter's AAF.
An Important Note
If we pause for a moment and think about the filters we have covered in this chapter (and
the data converter topologies in Ch. 34), we come to the realization that all require precise
analog components. High-speed, wide-bandwidth op-amps and/or components with
precise matching or absolute values are needed. We might argue that this would be a
reason to focus our discussion on digital filtering (filters using only multipliers, delays, and
adders) instead of filters using analog components. However, digital filters can't alone
filter an analog waveform without first running the signal through an ADC. Further,
traditional digital filters that use general-purpose multipliers at reasonable speeds can be
very large (take up a significant layout area). So large in fact as to not be practical in a
general purpose filtering application. Special-purpose chips have been fabricated
specifically for digital filtering (called digital signal processors, DSPs).
At this point we should remember that the reason we spent a whole chapter, Ch.
32, on noise-shaping topologies (see Sec. 31.3.2) was that they reduce the requirements
placed on the analog components in the circuit. Isn't it logical then to attempt to combine
noise-shaping with purely digital filtering for the design of future analog interfaces? The
answer is obviously, "yes"; however, as mentioned above, we have some caveats. While
the resulting interface will place lower demands on the precision of the analog circuitry,
we'll need to (1) develop digital filters that don't rely on complex multipliers. The
multiplications we do use should be simple, perhaps requiring an additional adder, or
trivial (shift) multiplication. Also we'll need to use the digital filters to not only filter the
input signal but to (2) filter out the modulation noise present in the output of the NS
modulator. We used a single-bit quantizer in the majority of our examples in Ch. 32. For a
general analog interface (where we are using the term "analog interface" to indicate both
analog-to-digital conversion and filtering), with up to 60 dB DR a better choice is to use a
416 CMOS Mixed-Signal Circuit Design

multibit quantizer. We say "better" to indicate that we can achieve a higher DR at a lower
oversampling ratio when using a multibit modulator. We'll briefly cover this type of
interface at the end of this chapter. For now let's show how the filter of Fig. 35.21b can be
implemented as a purely digital filter. This will also allow us to derive the exact transfer
function of the filter of Fig. 35.22 when the input frequency gets large (where the DAI
doesn't behave like a CAI, as indicated by Eq. [35.40]).
Exact Frequency Response of a First-Order Discrete-Time Digital (or Ideal SC) Filter
Figure 35.26 shows the digital only equivalent of Figs. 35.21a and 35.21b. We have
replaced the ratio of capacitors, C I /C F , with the variable A in the figure. To determine the
transfer function we can write

V out ( f ) = A ⋅ [V in ( f ) − V out ( f )] ⋅ z −1 (35.47)

1 − z −1
or
V out ( f ) −1
= −1 Az = A (35.48)
V in ( f ) Az + 1 − z −1 z − (1 − A)

z −1
1 − z −1 Integrator
V in ( f ) V out ( f )
A z −1
In Out

Figure 35.26 Digital block diagram of an integrator-based lowpass filter

(digital version of the block diagrams of Fig. 35.21).

Figure 35.27 shows the z-plane plot and magnitude response for this first-order
filter. Note the similarity to Fig. 31.62. Remembering all digital filters have a periodic
frequency response (a period of fs or one complete revolution around the unit circle), we
can compare this filter's response to the filters in the previous examples. To do so let's
assume f s = 100 MHz and write, from Eq. (35.41),

= 1.59 MHz = 0.1 ⋅ 100 MHz that is, A = 0.1

Af s
f 3dB = (35.49)
2π 2π
We can write the magnitude response of Eq. (35.48) as
V out A
= (35.50)
V in 2
(cos 2πf/f s − 1 + A) + sin2 2πf/f s
Chapter 35 Integrator-Based CMOS Filters 417

H(z) = A
z − (1 − A) z-plane

H( f )
1
A

A
2−A
f s /2 fs 3f s /2 f

Figure 35.27 The z-plane representation and magnitude response of a first-order digital filter.

Figure 35.28 shows the responses of the first-order discrete-time filter (or the SC filter
using an ideal, that is, no dominate pole, op-amp). The maximum attenuation of the filter
occurs at fs/2 or 50 MHz here and is, from Fig. 35.27 with A = 0.1, 0.0526 or − 25.6 dB.

(a) linear vs. linear (b) dB vs. linear

f s /2 fs 3f s /2 Continuous-time f s /2 fs 3f s /2
filter response
(c) dB vs. log of frequency
fs
Discrete-
Continuous-time time filter
filter response response

f s /2 3f s /2

1 GHz
100 MHz
Figure 35.28 The magnitude response of the discrete-time first-order filter
of Fig. 35.26 with an A of 0.1.
418 CMOS Mixed-Signal Circuit Design

35.2 Filtering Topologies

In this section we present some basic filter building blocks using integrators. While we
show the continuous analog implementations of these filters, our focus, in preparation for
the next section covering the combination of NS modulators and digital filters, will be on
using the results to design digital filters.
35.2.1 The Bilinear Transfer Function
Consider the block diagram of the general first-order filter shown in Fig. 35.29. We can
relate the filter's output to its input using
G
[V in ( f ) ⋅ [1 + sG 3 ] − G 2 ⋅ V out ( f )] ⋅ s1 = V out ( f ) (35.51)

or
V out ( f ) 1 1 + 1/Gs 3
= ⋅ (35.52)
V in ( f ) G 2 1 + G 1sG 2

In G1 Out
V in ( f ) s V out ( f )

sG 3

G2

Figure 35.29 Implementation of a bilinear transfer function using an integrator.

This filter's transfer function is termed "bilinear" because it is the ratio of two linear
functions. Using this topology we can implement lowpass, allpass (used for phase
shifting), and highpass filters (keeping in mind that the highpass filter will ultimately
change into a bandpass filter response because of the op-amp's or transconductor's high
frequency rolloff). The location of the filter's pole is given by
G1G2
f 3dB, pole = (35.53)
2π
while the filter's zero is located at

f 3dB, zero = 1 (35.54)

2πG 3
The filter's gain at DC, in all cases, is

A DC = 1 (35.55)
G2
Chapter 35 Integrator-Based CMOS Filters 419

Active-RC Implementation
The active-RC implementation of the bilinear transfer function is seen in Fig. 35.30. Again,
as mentioned earlier, the resulting active-RC transfer function suffers from poor
repeatability from one process run to the next. The RC time constants must be tuned,
on-chip, with fuses (or switches) and adding/removing resistors or capacitors. Note how
the summation is implemented by changing the input/output voltages to currents. The
currents are summed at the inputs of the op-amp (which remain, ideally, at the
common-mode voltage, VCM). This is important to note in both the active-RC and
switched-capacitor implementations.
We won't discuss the implementation of the MOSFET-C-based bilinear transfer
function. It should be obvious that replacing the resistors in Fig. 35.30 with MOSFETs or
linearized MOSFETs (see Figs. 35.12-35.14) provides a MOSFET-C implementation.

RF

CI CF

RI
V in+
V out−

V in− V out+
RI 1
G1 =
R ICF
R
CI CF G2 = I
RF
RF G3 = R ICI

Figure 35.30 Implementation of an active-RC bilinear transfer function filter.

Transconductor-C Implementation
Figure 35.31 shows the implementation of the bilinear transfer function using
transconductor stages. Again, as with the active-RC filter, signals are summed using
currents. Summing the currents at the output nodes results in
V in+ − V out+ V
g m1 (V in+ − V in− ) − g m2 (V out+ − V out− ) + − out+ = 0 (35.56)
1/s2C 1 1/s2C 2
where we know V out+ = −V out− and V in+ = −V in− . It will be helpful to write
420 CMOS Mixed-Signal Circuit Design

V in+ 2V in+ V in+ − V in−

= = (35.57)
1/s2C 1 1/sC 1 1/sC 1
Using this expression, we can write Eq. (35.56) as
(V out+ − V out− ) ⋅ (s(C 1 + C 2 ) + g m2 ) = (V in+ − V in− ) ⋅ (g m1 + sC 1 ) (35.58)
or finally

V out+ − V out− g m1 1 + g m1 /C 1 s

=g ⋅ (35.59)
V in+ − V in− m2 1 + s
g /(C +C m2 1 2)

It's important to note that when looking at this equation the location of the pole and zero
can be adjusted by changing each transconductor's gm independently. The ability to adjust
one variable in a filter's transfer function and only change the position of a single pole or
zero is called orthogonal tuning.

2C 1
G 1 = g m1 /(C 1 + C 2 )
2C 2 g m2
G2 = g
m1
v in+ v out−
C1
g m1 g m2 G3 = g
v in− v out+ m1

2C 2

2C 1

Figure 35.31 Implemention of a bilinear filter using transconductors.

Switched-Capacitor Implementation
The switched-capacitor, SC, implementation of the bilinear filter is seen in Fig. 35.32. This
filter is directly derived from the active-RC filter of Fig. 35.30. From Eq. (35.42) we can
write

RI = 1 and R = 1 (35.60)
F
C I1 ⋅ f s C I2 ⋅ f s
and so
C I1 C C I3
G1 = ⋅ f s , G 2 = I2 , and G 3 = (35.61)
CF C I1 C I1 ⋅ f s
Note how, in this discrete-time filter, the passband gain is C I3 /C F when the filter is
designed for a highpass response (and the filter no longer behaves like a discrete-time
filter). The gain at DC in all situations is C I1 /C I2 .
Chapter 35 Integrator-Based CMOS Filters 421

φ1 φ2
C I11
G1 = ⋅ fs
CF
C I21
v in+ CF C I21
G2 =
C I11 C I11

C I1 C I1
v out− G3 =
C I11 ⋅ f s
V CM V CM
v out+
C I1
C I11 1 + 1/Gs 3
V out ( f ) 1
v in− CF = ⋅
C I21 V in ( f ) G 2 1 + G 1sG 2

Figure 35.32 Implemention of a bilinear filter using switched capacitors.

Digital Filter Implementation

To implement the differentiation in Fig. 35.29, the circuit shown in Fig. 35.33 can be used
(see also Figs. 31.50 and 31.51). The transfer function of the filter is
f
−j2π f f f
1 − z −1 = 1 − e s = 1 − cos 2π ⋅ + j sin 2π ⋅ (35.62)
fs fs
Knowing from Fig. 35.28 that the digital filter functions as desired (with characteristics
similar to an analog filter) when f << f s , we can write (see Fig. 35.33)
G3

G 3D
G 3D (1 − z −1 ) ≈ ⋅s (35.63)
fs

1 − z −1
In Out In Out
G 3D G3s

z −1 Continuous-time symbol; see Fig. 35.29

Digital implementation

Figure 35.33 Implementating a digital differentiator.

 422 CMOS Mixed-Signal Circuit Design

Figure 35.34 shows the digital implementation of the bilinear filter of Fig. 35.29.
It's important, at this point, to see how the continuous-time implementation in Fig. 35.29
is directly implemented in Fig. 35.34. In particular we note that
G 3D
G 1 = G 1D ⋅ f s and G 3 = (35.64)
fs
and so
f
V out ( f ) 1 + 1/Gs 3 1 + j ⋅ f s /(2πG )
= 1 ⋅ = 1 ⋅ 3D
(35.65)
V out ( f ) G 2 1 + G 1G 2 G 2 1 + j ⋅
s f
f s G 1D G 2 /2π

The location of the pole is given by

f s G 1D G 2
f 3dB, pole = (35.66)
2π
while the location of the zero is at
fs
f 3dB, zero = (35.67)
2πG 3D
Note in order for our filter to be useful where the frequencies of interest are much less
than the filter's clocking frequency, fs, the pole and zero location must be much less than fs.
This means, assuming G2 = 1, that G 1D << 1 and G 3D >> 1 .

In z −1
V in ( f ) 1 − z −1 Integrator
1 − z −1
Out
G 3D G 1D z −1
V out ( f )
z −1
Differentiator
G2

Figure 35.34 Digital implementation of the bilinear transfer function.

Let's attempt to simplify this filter. If we look at the transfer function, Eq. (35.65),
we see that the feedback gain, G2, simply scales the amplitude of the transfer function and
can be used to further adjust the pole of the filter. Because we can scale the amplitude of
the signal either before or after the filter, and independent of the filter's operation, and we
can precisely set the pole of the filter using G1D, we can, without loss of functionality, set
G2 to 1. We can then rearrange the summing, delaying, and multiplying blocks, as seen in
Fig. 35.35.
Chapter 35 Integrator-Based CMOS Filters 423

In

Out
G 3D G 1D z −1

z −1

In

Out
G 3D G 1D z −1

z −1
1 − G 1D
In Out
1 + G 3D G 1D z −1

G 3D z −1
1 − G 1D

In 1 + G 3D Out
G 3D
G 1D G 3D z −1

1 − G 1D
z −1

In 1 + G 3D Out
z −1 G 1D G 3D
G 3D

1 − G 1D
z −1

In 1 + G 3D Out
z −1 G 1D G 3D
G 3D

1 − G 1D z −1

G 1D z − G 3D /(1 + G 3D )
z − (1 − G 1D ) (1 + G 3D ) ⋅ z

Figure 35.35 Simplifying the digital implementation of the bilinear filter.

424 CMOS Mixed-Signal Circuit Design

Using the results of Fig. 35.35 we can write the z-domain respresentation of the
transfer function, Eq. (35.65), as
V out (z) G 1D (1 + G 3D ) z − G 3D /(1 + G 3D )
= ⋅ (35.68)
V in (z) z − (1 − G 1D ) z
Note how, for a lowpass filter with G3D set to 0, this equation reduces to Eq. (35.48) with
A = G1D. Before attempting to simplify the filter implementation seen in Fig. 35.35 further,
let's show that, indeed, Eq. (35.68) is equivalent to Eq. (35.65) when f << fs. It will be
helpful to remember that
2
z ≈ 1 + s and z −1 ≈ 1 − s if f << f s or z ≈ 1 + s ≈ 1 s ≈ 1−1 if s 2 ≈ 0 (35.69)
fs fs f s 1 − fs z fs
where s = jω = j2πf . Rewriting Eq. (35.68) in the frequency-domain gives
V out ( f ) G 1D (1 + G 3D )    
= ⋅  1 − 1 − s G 3D /(1 + G 3D )  (35.70)
V in ( f ) 1 + fss − 1 + G 1D   fs  
f
1 + f s /Gs 1 + j ⋅ f s /(2πG
3D )
= 3D
= (35.71)
1 + G s ⋅f s 1+j⋅ G
f
1D ⋅f s /2π
1D

which is clearly the same as Eq. (35.65) when G2 = 1.

Example 35.8
Sketch the digital filter equivalent of the following RC circuit. Assume the digital
filter is clocked at 100 MHz.

10k

10p
V out ( f ) 1 1 + jω ⋅ 100 ns
v in v out = ⋅
V in ( f ) 2 1 + jω ⋅ 50 ns
10k

Figure 35.36 A simple first-order RC circuit.

Comparing the transfer function in Fig. 35.36 to Eq. (35.71), we see that if
G 3D 1
= 100 ns → G 3D = 10 and = 50 ns → G 1D = 0.2
fs G 1D ⋅ f s
then we can use any of the filters in Fig. 35.35. The sketch of the digital filter is
seen in Fig. 35.37. The multiplication of the transfer function by 1/2 is nulled by
the multiplication by G 1D G 3D (= 2) . To verify that the filter in Fig. 35.37 functions
as desired at DC, we see that the output of the first stage is 0.5 when the input is
0.1, and the output of the second stage is 0.05 (with a 0.5 on its input). T
Chapter 35 Integrator-Based CMOS Filters 425

In 1 + G 3D Out
z −1 G 3D
G 1D G 3D

1 − G 1D
z −1

In
z −1 1.1 Out

0.8
z −1

H(z) = 1.1 ⋅ z −
10/11 1.1
= ⋅ z −1 ⋅ (1 − z −1 ⋅ 10/11)
z(z − 0.8) 1 − 0.8z −1

Figure 35.37 Digital filter from Ex. 35.8.

The Canonic Form (or Standard Form) of a Digital Filter

Studying Fig. 35.37, we might wonder if we can further reduce the size of the digital filter.
We see in this figure that it may be possible to eliminate the second delay element (which,
of course, is a register) and use only a single delay. The result of this modification is seen
in Fig. 35.38. Intuitively we would think that the phase response of the filter will change
because, now, there is less delay in series with input of the second adder. We can write the
output as
V out (z)  1 + G 3D 1 z −1 
= G 1D G 3D  ⋅ −  (35.72)
V in (z)  G 3D 1−z −1 (1 )
− G 1D 1 − z −1 (1 )
− G 1D 
or

1 + G 3D Out
G 1D G 3D
G 3D V out (z)

In
z −1
V in (z)

1 − G 1D

Figure 35.38 Canonic form of a first-order digital filter.

426 CMOS Mixed-Signal Circuit Design

V out (z) z − G 3D /(1 + G 3D )

= G 1D (1 + G 3D ) ⋅ (35.73)
V in (z) z − (1 − G 1D )
which is clearly the same response as derived in Fig. 35.35 or Eq. (35.68) except that the
output is one clock cycle, z, earlier (remembering to delay a signal by one clock cycle we
simply multiply it by z −1 [latch it into a register for one clock cycle]). This reduced delay,
of course, has no effect on the magnitude response of the filter and little effect, assuming
f << f s , on the phase response of the filter.
The general form of this first-order canonic (or standard form) filter is seen in Fig.
35.39. The filter is termed canonic because the minimum number of delays are used. One
delay is used for each pole (remembering from Ch. 31 that in order for a digital filter to be
realizable in hardware there must be fewer or an equal number of zeroes than poles in a
filter's transfer function [see page 101]).

Change to addition and negate B 1

Out
B0
A 1 = 1 − G 1D
In B 0 = G 1D (1 + G 3D )
z −1 B1
B 1 = −G 1D G 3D B
B 0 + B 1 z −1 z + B 10
H(z) = = B0 ⋅
A1 1 − A 1 z −1 z − A1

Figure 35.39 General canonic form of a first-order digital filter.

We can, again, derive the transfer function for the first-order bilinear digital filter.
This time, however, let's use the variables in Fig. 35.39. Again, assuming f << f s , and
using Eq. (35.69) results in
1+ s
f s  1+ B1 
B
B0 + B1
H( f ) = ⋅ 0
(35.74)
1 − A 1 1 + f (1−A
s
)
s 1

where
f s (1 − A 1 )
f 3dB, pole = (35.75)
2π
and
fs 
1+ 1
B
f 3dB, zero = (35.76)
2π  B0 
and the gain at DC is
B 0 + B1
A DC = (35.77)
1 − A1
Chapter 35 Integrator-Based CMOS Filters 427

Example 35.9
Using the canonic form of the first-order digital filter, repeat Ex. 35.8.
Comparing Eq. (35.74) with the transfer function in Fig. 35.36, we can write

2πf 3dB, pole = 1 = f ⋅ (1 − A ) = 100 MHz(1 − A ) → A = 0.8

s 1 1 1
50 ns
B + B1 B0 + B1
A DC = 1 = 0 = → B 0 + B 1 = 0.1
2 1 − A1 1 − 0.8

2πf 3dB, zero = 1 = f ⋅  1 + B 1  = 100 MHz  0.1  → B = 1

100 ns
s
 B0   B0  0

and thus B 1 = −0.9 . The filter's sketch is seen in Fig. 35.40. We will discuss how to
implement the multipliers in the final section of the chapter.
Let's do a quick check to see if the filter functions as desired at DC. If we
apply 0.1 to the input of the filter then, according to the transfer function in Fig.
35.36, the output of the filter should be 0.05 or one-half the input. Because the
input to the filter is a DC signal, both sides of the delay will have the same value.
According to Fig. 31.62, this value will be 0.5 (the output of the weighted
integrator is 1/[1 − 0.8] times the input signal, here 0.1, at DC). The output will
then be 0.5 − 0.45 or 0.05 (as we would expect). T

Out

In
z −1 0.9

0.8

Figure 35.40 Canonic form of the first-order digital filter in Ex. 35.8.

Example 35.10
Sketch the digital filter implementation of the lowpass filter in Ex. 35.1 that has a
DC gain of one and a 3 dB frequency of 1.59 MHz. Assume the filter is clocked at
100 MHz.
The filter's continuous-time frequency response is given by

H( f ) = 1
f
1 + j ⋅ 1.59 MHz
428 CMOS Mixed-Signal Circuit Design

Using Eqs. (35.74) to (35.77), we begin by calculating A1

f s (1 − A 1 ) 100 MHz
f 3dB, pole = 1.59 MHz = = (1 − A 1 ) → A 1 = 0.9
2π 2π
and then
B 0 + B1 B + B1
A DC = =1= 0 → B 0 + B 1 = 0.1
−
1 A1 1 − 0.9
Let's put the zero at infinity so it doesn't affect the transfer function
fs 
1 + 1  → B 0 = 0 and B 1 = 0.1
B
f 3dB, zero = ∞ =
2π  B0
A sketch of the filter is seen in Fig. 35.41. Note that this is the exact same filter as
the one seen in Fig. 35.26 except that we have combined multipliers so B 1 = A
where the A is seen in Fig. 35.26. T

In Out
z −1 0.1

0.9

Figure 35.41 First-order digital filter in Ex. 35.10.

Before leaving this section, let's show in Fig. 35.42 the general form of an nth-order
canonic digital filter (where n indicates the number of poles in the transfer function). The
z-domain transfer function of the filter is given by
m m
Σ
i=0
B i z −i Σ
i=0
B i z n−i
H(z) = n = n (35.78)
1 − Σ A i z −i z n − Σ A i z n−i
i=1 i=1

If we want to write the frequency domain transfer function, we write, again assuming
f << f s and using Eq. (35.69),
n−1 i n−1 n−i
Σ B i  1 − j f  Σ B i  1 + j f 
2πf 2πf
s s
H( f ) ≈ i=0
n i
≈ i=0
n n n−i
(35.79)
1 − Σ A i  1 − j f s   1 + j 2πf  − A i  1 + j 2πf 
Σ
2πf

i=1
 fs 
i=1
 fs 

While we can design higher order digital filters using the topology of Fig. 35.42, we will
restrict our analysis in the remainder of the book to first- and second-order filters where
hand calculations are relatively easy to do. We can increase the attenuation of a filter using
several of these sections, either cascading the stages in series or taking the outputs of
several first- or second-order sections and adding them together.
Chapter 35 Integrator-Based CMOS Filters 429

B0
B1

Out

Bm

In
z −1 z −1 z −1 z −1

A1
A2
A n−1
An
Number of poles n ≥ number of zeroes.

Figure 35.42 General canonic form of a digital filter.

35.2.2 The Biquadratic Transfer Function

As we briefly indicated in the last section, higher order filters can be implemented by
cascading first-order sections. However, because the pole and zero locations in these
first-order filters are restricted to real values, the performance of these cascades is poorer
than filters with complex pole and zero locations. For example, cascading two identical
lowpass filters having f3dB frequencies of 1.59 MHz would result in a filter that has an
attenuation of 6 dB at 1.59 MHz and a − 40 dB/decade roll off at higher frequencies.
Using a second-order filter, we can design a filter to have a sharper transition at 1.59 MHz
so that the attenuation is less than 6 dB at 1.59 MHz (however, the roll off remains −40
dB/decade). Further, we can use these sections to implement higher order filters using
Butterworth, Chebyshev, Elliptic (Cauer), or Bessel responses [9].
The biquadratic, or "biquad" for short, filter transfer function (a ratio of two
quadratic equations) is given by
V out a2 s2 + a1 s + a0
= (35.80)
s 2 +  Q 0  s + (2πf 0 )
V in 2πf 2

where 2πf 0 = ω 0 . The complex-conjugate poles are located at

430 CMOS Mixed-Signal Circuit Design

2
πf 0 1  2πf 0  2
p1, p2 = ± − 4(2πf 0 ) (35.81)
Q 2  Q 
or
2
πf 0  
p1, p2 = ± j ⋅ 2πf 0 1 − 1 (35.82)
Q  2Q 

V out1
In G1 G4 V out ( f )
V in ( f ) s s

sG 3 G2 sG 6

G5

Figure 35.43 Implementation of a biquadratic transfer function using two integrators.

Toward the goal of implementing a biquad, consider the block diagram in Fig.
35.43. This block diagram is essentially the cascade of two first-order blocks (as seen in
Fig. 35.29) except that instead of feeding the output of the second stage back to its input,
we feed it back to the input of the first stage. We can determine the transfer function of
this filter by writing
G
V out1 = (V in + sG 3 V in − G 5 Vout − G 2 V out1 ) ⋅ s1 (35.83)
or
s + G1G2  (1 + sG 3 )G 1
V out1 
G G
s  = V in s − V out 1s 5 (35.84)

Further, we can relate Vout1 to the output using

G
V out = V out1 (1 + sG 6 ) ⋅ s4 (35.85)

Using Eq. (35.84) with Eq. (35.85) gives

(1 + sG 3 )G 1
V out =  V in ⋅
G1 G 5  G
− V out ⋅ (1 + sG 6 ) s4 (35.86)
s + G1G2 s + G1G2 
or
 G G G (1 + sG 6 )   (1 + sG 3 )G 1 (1 + sG 6 )G 4 
V out 1 + 1 24 5 = V in (35.87)
 s + sG 1 G 2   s 2 + sG 1 G 2 
Finally, the transfer function of the biquad is given by
V out s 2 G 1 G 3 G 4 G 6 + s(G 1 G 3 G 4 + G 1 G 4 G 6 ) + G 1 G 4
= (35.88)
V in s 2 + s(G 1 G 2 + G 1 G 4 G 5 G 6 ) + G 1 G 4 G 5
Chapter 35 Integrator-Based CMOS Filters 431

Equating terms in Eqs. (35.80) and (35.88) gives

a2 = G1G3G4G6 (35.89)
a1 = G1G3G4 + G1G4G6 (35.90)
a0 = G1G4 (35.91)
2πf 0
= G1G2 + G1G4G5G6 (35.92)
Q
2
(2πf 0 ) = G 1 G 4 G 5 (35.93)
Active-RC Implementation
Figure 35.44 shows the active-RC implementation of the biquad filter along with the
associated design equations. It should be noted that this is the general design schematic. If,
for example, a lowpass filter needs to be implemented, the filter can be greatly simplified.

R F1 C F1
R F2
C I1

C I2
C F2
V in+ R I1 V out1− R I2
V out+

V in− V out−
R I1 V out1+
R I2
C I2 C F2

C I1
R F2
R F1 C F1

1 R
G1 = G 2 = I1 G 3 = R I1 C I1 G 4 = 1 R
G 5 = I1 G 6 = R I2 C I2
R I1 C F1 R F1 R I2 C F2 R F2
C I1 C I2 C I1 C I2 a0 = 1
a2 = a1 = + R I1 C F1 R I2 C F2
C F1 C F2 R I2 C F1 C F2 R I1 C F1 C F2

ω 0 2πf 0 1 C I2
= = + f0 = 1 ⋅ 1
Q Q R F1 C F1 C F1 R F2 C F2 2π C F1 R I2 C F2 R F2

Figure 35.44 Implementation of the active-RC biquadratic transfer function filter.

432 CMOS Mixed-Signal Circuit Design

Figure 35.45 shows the frequency response, pole-zero locations in the s-plane, and
transfer function for a second-order lowpass circuit made using an inductor (L), capacitor
(C), and resistor (R). This LRC circuit has the same frequency response shape as a
lowpass biquad filter. However, the DC gain of the LRC circuit must be unity while the
2
DC gain of the biquad filter can be set to a 0 /(2πf 0 ) . Note that if the pole quality factor,
Q, is greater than 1/ 2 the response will show peaking. Setting Q to 0.707 results in the
Butterworth or maximally flat response.

L 1
f0 = 1
v in (t) R v out (t) V out
= LC
V in s 2 + s R + 1 2π LC
L LC
C Q= 1 L
R C
Q
V out ( f ) max =
V in ( f ) 1 + 4Q1 2
Im, jω
0 dB f (Hz)
ω0 zeroes at infinity
- 40 dB/decade
Re, σ
f0
ω0
s plane
2Q
s = σ + jω
f max = f 0 ⋅ 1 − 1 2
2Q

Figure 35.45 Second-order lowpass filter.

Example 35.11
Design an LRC circuit with a Q of 0.707 and a cutoff frequency ( f0) of 1.59 MHz.
From Fig. 35.45 we have two equations we need to solve

f0 = 1 = 1.59 MHz → LC = 10 × 10 −15 and Q = 1 = 1 L

2π LC 2 R C
We can set C = 100 pF, then L = 100 µH, and R = 1.414k (definitely not practical
values if the circuit is going to be purely integrated). The response of the resulting
LRC circuit is shown in Fig. 35.46. Note how the cutoff frequency is set by the
inductor and capacitor, while the Q of the circuit is set by all three elements
(variations in the resistance having the largest effect on the circuit's Q). Higher Q
indicates the poles are moving toward the imaginary axis (keeping in mind that a
system with right-hand plane poles is unstable [oscillates]) and more peaking, Fig.
35.47. T
Chapter 35 Integrator-Based CMOS Filters 433

3 dB down at f 0

- 40 dB/decade

Figure 35.46 Second-order magnitude response for the circuit described in Ex. 35.11.

Q=5
Q=1

Q = 0.2

Q = 0.5 Q = 0.707

Figure 35.47 The effect of Q on the frequency response of a second-order lowpass filter.

Example 35.12
Simulate the design of an active-RC filter that has frequency characteristics similar
to Fig. 35.46.
Using the basic topology of Fig. 35.44, we see that for a lowpass filter,
C I1 = C I2 = 0 and therefore G3 = G6 = 0. Further

f 0 = 1.59 MHz = 1 1
2π C F1 R I2 C F2 R F2
which we shall use to set R I2 = R F2 = 10k and C F1 = C F2 = 10 pF . The Q of the
filter is given by

Q = 1 = 2πf 0 ⋅ R F1 C F1 → R F1 = 7.07 kΩ
2
2
Knowing a2 = a1 = 0, the gain at DC is a 0 /(2πf 0 ) or R F2 /R I1 (1/G5), which is 1
here. The simulation results are shown in Fig. 35.48. T
434 CMOS Mixed-Signal Circuit Design

magnitude phase

Figure 35.48 Magnitude and phase responses for the active-RC filter of Ex. 35.12.

Notice that at DC, when used in the lowpass configuration, the outputs of the first
integrator in Fig. 35.44, Vout1+ and Vout1− , must be equal. If not, the difference is integrated
by the second section. As the frequency increases, so does the difference in these voltage
levels.
Figure 35.49 shows the second-order bandpass response. Again, as with the
second-order lowpass response, the center frequency (resonant frequency) is set by the
values of the inductor and capacitor. The Q of the filter indicates how narrow the
bandpass response is; higher Q indicates a narrower response. Note how the response
eventually rolls off at −20 dB/decade. At low frequencies the capacitor can be thought of
as an open (resulting in a first-order RL circuit response), while at high frequencies the
inductor can be thought of as an open (resulting in a first-order RC circuit response).

1
V out s RC 1
v in (t) R v out (t) = f0 =
V in s 2 + s 1 + 1 2π LC
RC LC

L C
V out ( f ) Q=R C
L
V in ( f ) f 0 /Q
0 dB f (Hz)

Im, jω - 3 dB

ω0 One zero at infinity

and one at the origin
Re, σ
ω0
s plane
2Q
s = σ + jω 20 dB/decade
f0

Figure 35.49 Second-order bandpass filter.

Chapter 35 Integrator-Based CMOS Filters 435

Example 35.13
Repeat Ex. 35.11 for the bandpass LRC circuit.
Again, we can set C = 100 pF and L = 100 µF. Solving for Q using the equation in
Fig. 35.49 results in
100p
Q = R C = 0.707 = R → R = 707
L 100µ
The simulation results are seen in Fig. 35.50. T

Figure 35.50 Bandpass response of a second-order circuit with a Q of 0.707.

Example 35.14
Repeat Ex. 35.13 if the Q is increased to 20.
Figure 35.51 shows the simulation results. To attain a Q of 20, we use a resistor of
20k with the inductor and capacitor values remaining unchanged. T

Figure 35.51 Bandpass response of a second-order circuit with a Q of 20.

436 CMOS Mixed-Signal Circuit Design

Example 35.15
Use an active-RC filter to implement a filter with the response shown in Fig. 35.51.
Let's begin by writing the filter's transfer function
V out a1s a1s
= =
V in  2πf 0 
s +  Q  s + (2πf 0 )
2 2  10×10 6 
s +  20  s + (10 × 10 6 )
2 2

Looking at this equation, Eq. (35.80), and Fig. 35.44 we see that a2 = a0 = 0 and
so CI2 = 0 and RI1 = ∞ . Further then
C I1
a1 = f0 = 1 1 = 1.59 MHz
R I2 C F1 C F2 2π C F1 R I2 C F2 R F2
2πf 0 2π ⋅ 1.59 MHz 1
= =
Q 20 R F1 C F1
The passband gain (the maximum gain) occurs at f0 and is calculated by replacing s
in the transfer function above with j2πf 0 . It is given by
a1 Q
A passband =
2πf 0
If, again, we set CF1 = CF2 = 10 pF and RI2 = RF2 = 10k, we get an f0 of 1.59 MHz.
Further then, with a Q of 20, we can set RF1 to 200k. Finally, setting the passband
gain to unity results in
2πf 0 C I1
a1 = = → C I1 = 0.5 pF
Q R I2 C F1 C F2
While these values do result in a biquad with the shape seen in Fig. 35.51, the
values are not practical. Redoing the calculations while trying to minimize the
component spread gives another possible solution: RI2 = 100k, CF1 = 20p, RF1 =
100k, CF2 = 5p, CI1 = 5p, and RF2 = 1k. The simulation results are seen in Fig.
35.52. T

magnitude phase

Figure 35.52 Outputs of the biquad of Ex. 35.15 using active-RC elements.
Chapter 35 Integrator-Based CMOS Filters 437

Switched-Capacitor Implementation
The switched-capacitor implementation of the biquad circuit is shown in Fig. 35.53. Note
how this circuit is a simple translation of the active-RC circuit of Fig. 35.44. Again, if the
filter designed using this section has a lowpass or bandpass response, it can be simplified.
For example, from Figs. 35.45 and 35.49 (the implementation of lowpass and bandpass
filters), we see that a2 is zero. This indicates that G6 can be set to zero (removing CI2 in
Figs. 35.44 or 35.53). The resulting second-order filter response can be written as
V out a1s + a0 sG 1 G 3 G 4 + G 1 G 4
= = (35.94)
V in  2πf 0  s + (2πf ) s + sG 1 G 2 + G 1 G 4 G 5
2
s2 +  Q  0

Technically, the filter is no longer biquadratic, so we will refer to it as a second-order

filter.
The biquad in Fig. 35.53 can look confusing until we start to dissect it. If we
understand the topology of Fig. 35.32 we see that the switched-capacitor biquad is
nothing more than two bilinear filters connected in cascade. The only difference is that the
switched capacitance, CI22, is fed back to the input of the first op-amp to simulate the
feedback resistance, RF2, in Fig. 35.44. This circuit, for the general lowpass or bandpass
filter implementation, gets much simpler when the unused components are removed.

φ1 φ2 φ1 φ2

C I21 C I22
v in+ C F2
C I11
C I2 C I12
C F1
C I1 v out1− v out+
V CM V CM

C I1 v out1+ v out−
C I11 C F1
C I2 C I12
C F2
v in−
C I21 C I22

C I11 C I21 G = C I1 G = C I12 ⋅ f G = C I22 C I2

G1 = ⋅ fs G2 = 5 G6 =
C F1 C I11
3
C I11 ⋅ f s
4
C F2
s
C I11 C I12 ⋅ f s

Figure 35.53 Implementing a biquad filter using switched capacitors.

438 CMOS Mixed-Signal Circuit Design

High Q
We have a major concern alluded to in Ex. 35.15 when using either of the topologies of
Fig. 35.44 or 35.53 with a large Q. As we saw in this example the capacitor values were
within a factor of 4 of each other (20p and 5p) but the resistors used were two orders of
magnitude different (100k and 1k). This large difference can be traced to, again assuming
G6 = 0,
2πf 0 G4G5 C F1
= G 1 G 2 and 2πf 0 = G 1 G 4 G 5 or Q = = ⋅ R F1 (35.95)
Q G1 G2 R I2 C F2 R F2

This equation shows that RF1 has the largest direct dependence on Q. Using a large value
of RF1 results in a smaller feedback signal (a smaller amount of current is fed back to the
input of the first op-amp). In other words G2 in Fig. 35.43 is small.
In order to minimize the amount of signal, Vout1, fed back and summed with the
input signal, while at the same time forcing the components to have similar values,
consider the modified, from Fig. 35.43, biquad block diagram shown in Fig. 35.54. All we
have done here is added a separate signal path in parallel with the G2 path. Instead of
subtracting, though, we are now adding the signal to the input summing block. Equation
(35.88) can be rewritten, assuming G6 is zero (a bandpass or lowpass response), as
V out s(G 1 G 3 G 4 ) + G 1 G 4
= (35.96)
V in s 2 + sG 1 (G 2 − G 2Q ) + G 1 G 4 G 5
or, equating the coefficient of s in the denominator of this equation with the coefficient of
s in the denominator of Eq. (35.80), results in
2πf 0
= G 1 (G 2 − G 2Q ) (35.97)
Q
The implementation of the "high-Q" biquad is seen in Fig. 35.55 (with G6 included). The
additional gain from the figure is
R I1 Q−1
G 2Q = Q
= G2 ⋅ (35.98)
R F1 Q−1 Q

V out1
In G1 G4 V out ( f )
V in ( f ) s s

sG 3 G2 sG 6

G 2Q

G5

Figure 35.54 Implementation of a "high-Q" biquadratic transfer function.

Chapter 35 Integrator-Based CMOS Filters 439

R F1 C F1
R F2
C I1 Q
R F1 Q−1 = R F1Q
C I2
C F2
V in+ R I1 V out1− R I2
V out+

V in− V out−
R I1 V out1+
R I2
C F2
Q
C I2
R F1 Q−1 = R F1Q
C I1
R F2
R F1 C F1
R I1 Q−1
G 2Q = Q
= G2 ⋅
R F1 Q−1 Q

Figure 35.55 Implementation of the "high-Q" active-RC biquadratic transfer function filter.
The bold lines indicate the added components.

Rewriting Eq. (35.97) results in

2πf 0  Q − 1  G1G2
= G1G2 1 − = (35.99)
Q  Q  Q
Let's use this result in the following example.

Example 35.16
Repeat Ex. 35.15 using the high-Q circuit of Fig. 35.55.
The passband gain is one so we know that
a1
2πf 0 G G
a1 = = G 1 G 3 G 4 = G 1 (G 2 − G 2Q ) = 1 2
Q Q
or 2πf 0 = 10 × 10 6 = G 1 G 2 = 1/R F1 C F1 . We also know that
C I1 1 1
G1G3G4 = = G 1 (G 2 − G 2Q ) = ⋅
C F1 R I2 C F2 C F1 R F1 Q
and

2πf 0 = 10 × 10 6 = 1
C F1 R I2 C F2 R F2
440 CMOS Mixed-Signal Circuit Design

In an attempt to minimize component spread let's set RF1 to 5k, RI2 to 20k, CI1 to
4p, CF2 to 20p, CF1 = 20p, RF2 = 1.25k, and finally RF1Q = 5.25k (roughly). The
simulation results and schematic are shown in Fig. 35.56. T

5k

20p
1.25k

5.25k
20p
4p
V in+ 20k
V out+
V in− V out−
4p 20k
20p
5.25k

1.25k
20p
5k

magnitude phase

Figure 35.56 Bandpass filter discussed in Ex. 35.116.

Example 35.17
Repeat Ex. 35.16 using a switched-capacitor implementation. Assume that the
filter is clocked at 100 MHz.
To implement the filter, we need to replace the resistors in Fig. 35.56 with
switched capacitors. However, we notice in the gain equations that the resistors
are all ratios of capacitors. This means we can reduce the size of the filter by
scaling the values in Fig. 35.56. To do this let's divide all capacitors by 10 and
multiply all resistors by 10. Therefore, we can write CI1 = 0.4p, CF1 = 2p, and CF2 =
2p. The resistors can be calculated using
Chapter 35 Integrator-Based CMOS Filters 441

R F1 = 1 = 50k → C I21 = 0.2p

C I21 ⋅ f s

R F1Q = 1 = 52.5k → C I21Q = 0.190p

C I21Q ⋅ f s

R I2 = 1 = 200k → C I12 = 0.05p (!)

C I12 ⋅ f s

R F2 = 1 = 12.5k → C I22 = 0.8p

C I22 ⋅ f s
Looking at the value of CI12, we see it may be too small. Let's change its scale
factor from 10 to 4. This means

R I2 = 1 = 80k → C I12 = 0.125p

C I12 ⋅ f s
We have to scale CF2 as well (so that G4 remains constant). Now CF2 = 5 pF.
Figure 35.57 shows the implementation of the filter. Note how easy it was to
implement the high-Q circuitry. All we did was add two capacitors to the circuit.
Also note how the circuit is simplified after removing the unused components (RI1
and CI2 ).
Again, as in Ex. 35.6, because this circuit can only be simulated using a
transient analysis, we will input a sinewave at a known frequency and verify we get

φ1 φ2 φ1 φ2
(0.16p)
0.2p 0.19p
0.8p
(0.8p) 2p 5p
0.4p
V in+ 0.125p
V out+
V CM
V CM
V out−
V in− 0.125p
0.4p
(0.8p) 2p 5p
0.8p
0.2p 0.19p
(0.16p)

Figure 35.57 Switched-capacitor implementation of a high-Q filter; see Ex. 35.17.

442 CMOS Mixed-Signal Circuit Design

the correct output. Looking at Fig. 35.56, we see that if we apply a 1 V signal to
the filter at 1.59 MHz we should get a 1 V signal out at 1.59 MHz. However, as
seen in Fig. 35.58, the filter is unstable and oscillates. Indeed, using simulations it's
easy to show that even if we ground the inputs of the filter, the outputs will
oscillate at f0 (1.59 MHz). To understand why, remember in Fig. 35.49 that as the
Q of the bandpass filter is increased, the poles move closer to the right-hand plane.
If, for some reason, the poles move into the right-hand plane, the filter will become
an oscillator (unstable). It's important to remember that when we designed the
2πf
filter we approximated our discrete-time variable z as 1 + fss = 1 + j f s (when f << fs
2πf 2πf 2πf
cos fs
≈ 1 and sin fs
≈ fs
). We could be more exact and write
2πf
jf 2πf 2πf
z=e s = cos + j sin (35.100)
fs fs
2πf
which clearly will not follow 1 + f s for frequencies f approaching the sampling
frequency fs. As we discussed in Ch. 30, sampled signals will have spectral content
in excess of the sampling frequency. Practically, the spectral content is limited by
the combination of the switches "on" resistance and the capacitors in the circuit. In
Eqs. (35.68) - (35.71) we wrote, for a pole,
2πf f
z − (1 − G 1D ) ≈ 1 + j ⋅ − 1 + G 1D = G 1D + j ⋅ (35.101)
fs f s /2π
The pole is ideally located at (G 1D f s )/2π (the frequency where the imaginary part
is equal to the real part). Using Eq. 35.100, we can write, more exactly,
Real Imaginary

2πf 2πf
z − (1 − G 1D ) = cos − 1 + G 1D + j sin (35.102)
fs fs
It should be clear from this equation that as f gets larger, the cosine term will
decrease from one, causing the real portion to get smaller. A decrease in the real
component, as seen in the complex plane in Fig. 35.49, causes the pole to move
closer to the right-hand plane (causing the Q to increase).

Output
Input

Figure 35.58 Output of the filter in Fig. 35.57 showing instability.

Chapter 35 Integrator-Based CMOS Filters 443

Practically, the maximum Q we can design for (not attain) is in the

neighborhood of 5. If we redesign the biquad of Fig. 35.57 to have a Q of 5, we
see that all we need to change is CI1 (from 0.4p to 0.8p) and CI21Q (from 0.19p to
0.16p). The simulation results are seen in Fig. 35.59. In this figure, we adjusted the
input frequency until we reached a 3 dB point (the filter's center frequency was
1.59 MHz, as expected). This occurred at 1.52 MHz and 1.66 MHz. The Q of the
circuit is not 5 as we designed for but is, from Fig. 35.49, 1.59/(1.66 − 1.52) or
11.36. (See problem 35.25 for reducing the spread between CF2 and CI2.) T

Input

Output

Figure 35.59 Output of the filter in Fig. 35.57 after lowering the Q to maintain stability.

Q Peaking and Instability

While it would appear the active-RC circuit is the best choice for high-Q filter
implementations, we must remember that the discussion neglected the effects of the finite
gain-bandwidth product ( fu) of the op-amps. We can model these effects by replacing the
ideal integrator gain of 1/s with
1→ 1 (35.103)
s
s  1 + 2πfs u 


Using this result, we can rewrite the pole locations of Eq. (35.80) (see Eqs. [35.81] and
[35.82]) as
1 ⋅ 1 (35.104)
 s  1 + s  + p   s 1 + s  + p 
  2πf u  1   2πf u  2

or, looking at a single term,

Unwanted
2
  (2πf )
s 1+ s + p1 = s + p1 − (35.105)
 2πf u  2πf u
444 CMOS Mixed-Signal Circuit Design

This subtraction results in a shift in the pole toward the right-hand plane, increasing the Q
of the circuit; Fig. 35.60. Reviewing Eq. (35.82), we can subtract the unwanted term in
Eq. (35.105) to estimate the shift in the Q or
2
πf 0 (2πf )  2f 0 
− or at f = f0 we can write πf 0 1 − (35.106)
Q 2πf u  Q fu 
The shifted Q is then
1 2f 0 Q
= 1− → Q shift = Q2f
(35.107)
Q shift Q fu 1 − fu 0

So, for the filter Q to remain finite, we require

Q2f 0
<< 1 (35.108)
fu
Let's use this result in the following example.

Im,
Poles move towards right-hand plane
due to finite op-amp gain-bandwidth.
The result is an increase in the filter's Q.

Re
s plane

ω0
Ideal distance is
2Q

Figure 35.60 Showing Q peaking resulting from the op-amp finite gain bandwidth product.

Example 35.18
Resimulate the filter in Ex. 35.16 using op-amps that have an fu of 100 MHz.
The center frequency, f0, of this filter is 1.59 MHz and the Q is 20. Using Eqs.
(35.107) and (35.108), we can estimate the increase in Q due to op-amp finite
gain-bandwidth product as
Q2f 0 20 ⋅ 2 ⋅ 1.59
= = 0.636 → Q shift = 55
fu 100
Practically, this is too high of a Q (the poles are too close to the right-hand plane),
and the filter will be unstable (noise in the circuit, or simulation noise in the
simulation, will push the poles into the right-hand plane). Figure 35.61 shows the
simulation results (see also Ex. 35.4). The inputs to the filter are grounded. The
unstable oscillation frequency is close to the ideal, f0, but is shifted by a small
amount. T
Chapter 35 Integrator-Based CMOS Filters 445

Figure 35.61 Showing how the filter of Ex. 35.16 becomes unstable due to
finite op-amp bandwidth.

Transconductor-C Implementation
Let's redraw the bilinear filter in Fig. 35.31 as seen in Fig. 35.62. We redraw it like this to
show how the feedback gain, G2, is implemented. In the block diagram of the biquad filter
shown in Fig. 35.43, we used a similar scheme to implement the feedback gain, G5. Figure
35.63 shows the implementation of a biquad filter using transconductors where we have
drawn it so that the transconductors appear to be connected in series. This topology can
be redrawn so that it looks similar to Fig. 35.62 (showing a direct correspondence
between it and Fig. 35.43). Note how we could have drawn the schematic without the
crossing wires if we switched the output polarity of two of the transconductors (that is,
put the minus output on the top of the output instead of the plus output).

2C 1

2C 2
v in+ v out+
g m1
v in− v out−
2C 2

2C 1

G 1 = g m1 /(C 1 + C 2 ) g m2
g m2
G2 = g
m1
C1
G3 = g
m1

Figure 35.62 Redrawing the bilinear filter shown in Fig. 35.31.

446 CMOS Mixed-Signal Circuit Design

2C 1 2C 3 2C 4
v out−
2C 2
v in+
v out1− g m4
g m1 g m2 g m3
v in− v out1+

2C 2
v out+
2C 1 2C 3 2C 4

g m2 C g C
G 1 = g m1 /(C 1 + C 2 ) G 2 = g G 3 = g 1 G 4 = g m3 /(C 3 + C 4 ) G 5 = g m4 G6 = g 3
m1 m1 m1 m3

Figure 35.63 Implementing a biquadratic filter using transconductors.

The Digital Biquad

The digital biquad filter based on the canonic form of Fig. 35.42 is shown in Fig. 35.64.
The transfer function of this filter is
Y(z) B 0 + B 1 z −1 + B 2 z −2 B 0 z 2 + B 1 z + B 2
H(z) = = = 2 (35.109)
X(z) 1 − A 1 z −1 − A 2 z −2 z − A1z − A2

Out
B0

B1 B2

In
z −1 z −1

A1
A2

Figure 35.64 The digital biquad filter (see Fig. 35.42).

Chapter 35 Integrator-Based CMOS Filters 447

To translate this transfer function into the frequency domain, we use Eq. (35.69) and
assume our frequencies of interest are much less than the sampling frequency
2
B 0  1 + fss  + B 1  1 + fss  + B 2
H( f ) = 2
(35.110)
1 + s  − A 1 + s  − A
 fs  1 fs  2

After some algebraic manipulation we can put this equation in the form seen in Eq. (35.80)
B 0 ⋅ s 2 + f s (2B 0 + B 1 ) ⋅ s + f s2 (B 0 + B 1 + B 2 )
H( f ) = (35.111)
s 2 + f s (2 − A 1 ) ⋅ s + f s2 (1 − A 1 − A 2 )
where
a2 = B0 (35.112)
a 1 = f s (2B 0 + B 1 ) (35.113)
a 0 = f s2 (B 0 + B 1 + B 2 ) (35.114)
2πf 0
= f s (2 − A 1 ) (35.115)
Q
fs
f0 = ⋅ (1 − A 1 − A 2 ) (35.116)
2π

Example 35.19
Repeat Ex. 35.11 using the digital biquad clocked at 100 MHz.
In this example a lowpass filter is designed with f0 = 1.59 MHz and Q = 0.707.
Reviewing Fig. 35.45, we see that for a lowpass filter a2 and a1 are zero. This
means, in Eq. (35.111), B0 and B1 are zero. Further,
2π ⋅ 1.59 × 10 6
Q= = 0.707 → A 1 = 1.859
100 × 10 6 (2 − A 1 )
and
2
 2πf 0 
1 − A 1 − A2 = → A 2 = −0.869
 fs 
and finally, because the gain at DC is 1,
B 2 = 1 − A 1 − A 2 = 0.01
Note that if a scaling in the amplitude is allowable, we can remove this
multiplication or approximate it with shifts in the digital word.
The simulation results are shown in Fig. 35.65. To implement this simulation in
WinSPICE, we used transmission lines for the delay elements and voltage-
controlled voltage sources for both the multiplications and the adders. Note how
the frequency response is periodic with the filter's clocking frequency. T
448 CMOS Mixed-Signal Circuit Design

magnitude

Figure 35.65 Simulating the digital filter of Ex. 35.19

35.3 Filters Using Noise Shaping

The basic idea of implementing a filter using noise-shaping is seen in Fig. 35.66. The
modulator converts the analog input signal into a digital signal containing both the original
input spectrum and the unwanted modulation noise. The output of the circuit is digital. If
we want an analog output signal, then we would add a noise-shaping demodulator to the
output of the circuit.

Analog Noise-shaping
modulator Digital filter Digital output
input

Figure 35.66 Combining a noise-shaping modulator with digital filter.

Removing Modulation Noise

Back in Ch. 32 we said that we can use a sinc averaging filter with an order L (see Eq.
[32.20]) that is one greater than the order of the modulator, M. For a second-order
modulator implemented using an oversampling ratio K, the filter would have a transfer
function given by
−K 3
H(z) =  1 ⋅ 1 − z −1  (35.117)
K 1 − z 

Assuming we don't design the filter to decimate (reduce the digital word output rate) the
modulator's output, this filter will require more than 3K registers. As K gets large, this can
result in a large layout area. To reduce this layout area, as discussed in Sec. 31.2.2, we can
decimate the modulator's output. However, the big concern when using decimation to
reduce the filter's size and complexity is aliasing. It would be nice to have a small-area
filter to remove modulation noise.
Chapter 35 Integrator-Based CMOS Filters 449

Consider the frequency response of the Sinc decimating filter shown in Fig. 35.67.
This filter uses a clocking frequency of 100 MHz and assumes K is 16. Note how, at the
bandwidth of the desired signal, B, there is significant droop in the filter's response. It will
be highly desirable to design a filter that doesn't have this droop or, even more desirable,
contains a small amount of peaking at B to compensate for the eventual needed decimation
filter response (a Sinc shape with 3.9 dB droop at B). Using Eqs. (35.114) - (35.116) (and
some simulations), we can set, for a digital biquad, B2 = 0.03125, A1 = 1.75, A2 =
−0.78125 (there are several other solutions, depending on the desired complexity or
performance of the filter). Knowing that the sinc filter was almost ideal for removing
modulation noise and that a second-order (biquad) filter rolls-off at −40 dB/decade, we
can estimate, with the help of Fig. 35.67, the number of biquads required to remove the
modulation noise. One decade above 3.125 MHz (i.e., at 31.25 MHz) the attenuation of
the sinc filter is approximately −70 dB. This might make us think that two biquads in
cascade would be enough to remove the modulation noise since one decade above f0 we
would have −80 dB attenuation (and two may suffice in many applications). However, as
seen in Fig. 35.67, the sinc filter response is not monotonic. We will use three biquads to
remove the modulation noise (or again the number of filters cascaded is one more than the
order of the modulator). The simulation results comparing the Sinc and biquad filters are
seen in Fig. 35.68. The transfer function of the biquad filter is

H(z) = 0.03125 (35.118)

z 2 − 1.75z + 0.78125
The block diagram of the filter is seen in Fig. 35.69.

B = 3.125 MHz f s = 100 MHz

−16 3
H(z) = 1 ⋅ 1 − z −1
f s /2 = 50 MHz 16 1 − z

Figure 35.67 Frequency response of a third-order comb filter.

450 CMOS Mixed-Signal Circuit Design

Figure 35.68 Comparing a third-order Sinc filter to a third-order biquad for

removing modulation noise in a second-order noise-shaping
modulator.

In z −1 z −1 0.03125 Out

1.75 Adjust as needed

for the increase in
0.78125 word size (when
used on the output
of a modulator).
Figure 35.69 The digital biquad filter described by Eq. (35.118).

Example 35.20
Redesign the filter in Fig. 35.69 so that the response has a small amount of peaking
at 3.125 MHz. Compare, with simulations, the new response to the sinc filter seen
in Fig. 35.67.
Reviewing Eq. (35.115), we see that to increase the Q we need to increase A1.
Keeping in mind that we want to have simple multiplications relying heavily on
shifts, let's try increasing A1 to 1.78125 and A2 to 0.8125. The simulation results
are seen in Fig. 35.70. In this figure we compare the modified filter response to the
response of the Sinc filter. Note how we have a couple of dB peaking in the
cascaded biquad filter's output. T
Chapter 35 Integrator-Based CMOS Filters 451

Figure 35.70 Simulation results for Ex. 35.20.

Implementing the Multipliers

An important component of any digital filter is the multiplier. While implementing general
digital multipliers is outside the scope of this book, we can discuss practical multiplier
implementation for custom digital filters. To begin let's remember from Ch. 31 (see Figs.
31.36 and 31.37) that in the binary offset representation of a number the most positive
voltage in a digital system (VREF+ − 1 LSB) is represented by 11111... The most negative
voltage (VREF−) is represented by 00000... in binary offset while the center voltage, or
common-mode voltage VCM , is represented by 10000... To change between binary offset
and two's complement, we simply invert the MSB (the sign-bit). We'll assume that two's
complement numbers are used throughout the filter.
Let's say that a noise-shaping modulator uses a single-bit quantizer that has an
output of 1 or 0. To filter this data stream, we begin by changing the output into a two's
complement number
1 → 01 (+1 in two's complement) (35.119)
and
0 → 11 (−1 in two's complement) (35.120)
To multiply the output by two, we simply add a zero to the end of the word
+1 × 2 → 010 (+2 in two's complement) (35.121)
or
452 CMOS Mixed-Signal Circuit Design

−1 × 2 = 110 (−2 in two's complement) (35.122)

To multiply by one-half, we simply insert a zero in between the sign bit and the remaining
part of the word if the word is positive
+1 × 0.5 = 001 (+1 in two's complement) (35.123)
or a one if the word is negative
−1 × 0.5 = 111 (−1 in two's complement) (35.124)
In either case, what we are doing is simply extending the sign bit one place to the left.
Equations (35.123) and (35.124) may not make sense unless we rewrite Eqs. (35.119) and
(35.120) if the single-bit modulator outputs were instead changed to 3-bit numbers
modulator output of 1 → +1 → 010 (+2 in two's complement) (35.125)
and
modulator output of 0 → −1 → 110 (−2 in two's complement) (35.126)
It's important to note that the word size increases after the multiplication to avoid
rounding errors (unless, of course as seen in Eqs. [35.125] and [35.126], the LSB is
always 0). Figure 35.71 shows the implementation of multiply by 2 and 0.5.

N-bits N+1 bits MSB

N-bits N+1 bits
Two's complement input
New LSB Two's complement input
(a) Multiply by two. (b) Divide by two. Top two bits
are the input's
MSB
Figure 35.71 Multiply by (a) two and (b) one-half.

Example 35.21
Suppose a noise-shaping modulator uses a 4-bit quantizer where 1111 is the most
positive output code and 0000 is the most negative output code. How would these
codes be converted into two's complement format?
Inherent in the binary offset format shown back in Fig. 31.36 is an LSB offset. This
resulted in our LSB being defined by, see Eq. (30.23),
V REF+ − V REF−
1 LSB= (35.127)
2N
In a noise-shaping modulator (see question 30.14) we may use a quantizer that
doesn't have this offset. When using a 1-bit quantizer, an output of 1 corresponds
to VREF+ and an output of 0 corresponds to VREF−. We can write 1 LSB for this
situation as
Chapter 35 Integrator-Based CMOS Filters 453

V REF+ − V REF−
1 LSB = (35.128)
2 N−1
To convert the 4-bit modulator outputs ranging from 0 to 15 into two's
complement, we simply complement the MSB. This would mean the most positive
output in two's complement is 0111, while the most negative output is 1000. In
order to eliminate the offset (asymmetry in the digital output code) we may use an
additional output bit in our quantizer so that the maximum modulator output is 1
0000 corresponding to VREF+. If this is the case, then the modulator outputs can be
converted to two's complement as seen below.
Maximum modulator output 1 0000 → 0 1000 (+8 in two's complement)
Middle modulator output 0 1000 → 0 0000 (0 in two's complement)
Minimum modulator output 0 0000 → 1 1000 (−8 in two's complement)
T
We can extend our discussion of multiplying by 0.5 to multiplying by 0.25, 0.125,
0.0625, 0.03125, etc., by simply extending the sign-bit of the input word. To multiply a
word by 0.03125, we simply shift the word to the right five times. For example,
multiplying a two's complement code of 01 by 0.03125 would give
+1 or +0.5 +1 or 0.015625

+1 × 0.03125 = 01 × 0.03125 = 000 0001 (35.129)

Multiplying a two's complement code of 11 by 0.0625 results in
-1 or -0.5 -1 or -0.03125

−1 × 0.0625 = 11 × 0.0625 = 11 1111 (35.130)

While, in some filtering applications, simple shifts can prove very useful, we can
implement more useful multipliers using adders. Figure 35.72 shows one possible
implementation using a single adder along with the associated multiplication factors. We
could implement the coefficients in Ex. 35.20 using a similar scheme. For example, A1 =
1.78125 = 2 − 0.25 + 0.03125 and A2 = 0.8125 = 1 − 0.25 + 0.0625 (both requiring two
adders). Other creative ways can be used to implement multiplers. For example, a
multiplication of 0.5625 by cascading two simple multipliers with multiplication factors
0.875.

B= Multiply by
1 0
In Out 0.5 0.5
0.25 0.75
0.125 0.875
B 0.0625 0.9375
0.03125 0.96875

Figure 35.72 A simple multiplier using a single adder.

454 CMOS Mixed-Signal Circuit Design

REFERENCES
[1] R. E. Bogner and A. G. Constantinides (eds.), Introduction to Digital Filtering,
John Wiley and Sons, 1975. ISBN 0-471-08590-1
[2] P. R. Gray, D. A. Hodges, and R. W. Brodersen (eds.), Analog MOS Integrated
Circuits, Wiley-IEEE, 1980. ISBN 0-471-08964-8
[3] P. R. Gray, B. A. Wooley, and R. W. Brodersen (eds.), Analog MOS Integrated
Circuits II, Wiley-IEEE, 1989. ISBN 0-87942-246-7
[4] P. A. Lynn, An Introduction to the Analysis and Processing of Signals,
Hemisphere Publishing Corporation, 1989. ISBN 0-89116-981-4
[5] Y. P. Tsividis and J. O. Voorman (eds.), Integrated Continuous-Time Filters:
Principles, Design, and Applications, Wiley-IEEE, 1993. ISBN 0-7803-0425-X
[6] B. Nauta, Analog CMOS Filters for Very High Frequencies, Kluwer Academic
Publishers, 1993. ISBN 0-7923-9272-8
[7] A. S. Sedra and K. C. Smith, Microelectronic Circuits, Oxford University Press,
1998. ISBN 0-1951-1663-1
[8] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley and
Sons, 1997. ISBN 0-471-14448-7
[9] E. P. Cunningham, Digital Filtering: An Introduction, John Wiley and Sons, 1995.
ISBN 0-471-12475-3
[10] R. Schaumann and M. E. Van Valkenburg, Design of Analog Filters, Oxford
University Press, 2001. ISBN 0-19-511877-4
QUESTIONS
35.1 Resketch Fig. 35.2 for the following circuit.

L
v in (t) v out (t)

Figure 35.73 First-order lowpass filter using an inductor and a resistor.

35.2 Show that Eq. (35.6) is still valid if the circuit's inputs and outputs are referenced
to the common-mode voltage, VCM. (The op-amp inputs should also be at VCM.)
Chapter 35 Integrator-Based CMOS Filters 455

35.3 Sketch the implementation of a first-order lowpass filter using a CAI with a 3 dB
frequency of 10 MHz and a DC gain of 6 dB. Simulate your design to verify if it
works as expected.
35.4 Plot, in the complex plane, the ideal pole location and the actual pole locations due
to finite op-amp unity gain frequency for the filter described in Ex. 35.4.
35.5 Regenerate Fig. 34.21 of the last chapter using SPICE and the op-amp model
shown in Fig. 35.8.
35.6 Suppose an antialiasing filter was required for a 12-bit data converter. Further
assume the filter is to be implemented using an active-RC topology. If VDD = 1.5
V, estimate the minimum value of the integration capacitor used, assuming the
filter's noise performance is dominated by thermal noise. Is it wise, for 12-bit
system performance, to design the filter so that its SNR is equal to the SNR of the
data converter?
35.7 Repeat question 35.6 if the op-amp used in the filter has a linear output swing of
80% of the power supply voltage.
35.8 Show, using the topology shown in Fig. 33.22 (and the same SPICE models), how
using the two MOSFETs linearizes the change in resistance with VDS.
35.9 Repeat Ex. 35.4 using a MOSFET-C filter. Use the MOSFET SPICE model given
in Ch. 33. After performing the AC simulations, try a transient simulation with an
input sinusoid at 1 MHz. Show how the output of the filter becomes distorted as
the amplitude of the input signal increases. Determine the filter's SNDR when the
input signal has a frequency of 1 MHz and an amplitude of VDD peak-to-peak.
35.10 Derive the transfer function for the filter shown in Fig. 35.16 if the transconductors
have different gms. Sketch the block diagram, similiar to the one seen in Fig. 35.6,
for the filter.
35.11 Derive the transfer function for the following first-order transconductor filter.

v in1+

v in1−
v out+
C
v in2+ v out−

v in2−

Figure 35.74 A first-order filter with two inputs.

35.12 Show the derivation details that result in Eqs. (35.44) and (35.46).
456 CMOS Mixed-Signal Circuit Design

35.13 From the derivation of Eq. (35.48), what would happen if we repeated Ex. 35.6
with an input frequency of 101.59 MHz?
35.14 Show that if the values of A and B are restricted to 1, 0.5, 0.25, 0.125, etc. that the
circuit of Fig. 35.75 can be used to implement multiplication by coefficents that
aren't directly powers of two. How would a multiply by 0.75 be implemented? a
multiply-by-0.9375? a multiply-by-0.5625?

In A Out

Figure 35.75 A simple multiplier where A and B simply shift the data.

35.15 From the results of the preceding question, sketch the implementation of one
possible design of a multiplier topology that multiplies an input word by 0.8789
and 0.3164.
35.16 Show the details of how the gains, G, are derived in Fig. 35.30.
35.17 In Fig. 35.35 a filter section has a transfer function that can be written
z − A/(1 + A)
H(z) = (1 + A) ⋅ z
For this transfer function generate a z-plane plot and a magnitude plot similar to
what is seen in Fig. 35.27.
35.18 Plot the time-domain output of the filter in Fig. 35.37 when the input is a zero to
one step function.
35.19 Design a first-order canonic digital filter that is clocked at 100 MHz and has a
transfer function, in the frequency domain, given by

H( f ) = 1
f
1 + j 4 MHz
35.20 Redraw Fig. 35.42 using only two input adders.
35.21 Is it possible to tune the gain, Q, and cutoff frequency of the lowpass biquad
independently? If so, how? Give examples using the simulation netlist used to
generate Fig. 35.48.
35.22 What happens to the poles in the biquadratic equation, Eq. (35.80), if the Q is less
than 0.5? (Hint: The filter behaves like the cascade of two first-order filters.) Is the
fmax equation in Fig. 34.45 valid?
Chapter 35 Integrator-Based CMOS Filters 457

35.23 Compare the size of the elements used in Exs. 35.11 and 35.12. Is there a benefit
to using an active element for monlithic implementation?
35.24 Show, using the simulations from Ex. 35.17, that increasing the switch resistance,
and thus the spectral content present in a switched capacitor circuit, can help to
stabilize high-Q switched-capacitor bandpass filters.
35.25 Redesign and simulate the operation of the filter discussed in Ex. 35.17, with a Q
of 5, while trying to minimize the difference between CI1 and CF2. Suggest a
possible modification to the filter topology (similar to how we add G2Q in Fig.
35.54) to reduce this component spread.
35.26 Derive the transfer function of the transconductor-C biquad shown in Fig. 35.63.
Can this filter be orthogonally tuned? If so how?
35.26 Repeat Ex. 35.12 using the transconductor-based biquad.
35.27 How would a "high-Q" biquad be implemented using transconductors? Repeat Ex.
35.15 using the transconductor-based biquad.
35.28 Repeat Ex. 35.13 using a digital filter.
35.29 Repeat Ex. 35.14 using a digital filter.
35.30 Show, using biquad sections, how the following lowpass ladder filter would be
implemented.

v in v out

Figure 35.76 Implementing a ladder filter using biquads, see problem 35.30.

35.31 Show how to implement the multipliers used in Ex. 35.20.

35.32 Show that the filter shown in Fig. 35.77 can be implemented using a single
multiplier.
35.33 Show how the output of a single-bit noise-shaping modulator would be multiplied
by 1.9375. Make sure that the detail on converting the modulator's output to two's
complement is shown.
458 CMOS Mixed-Signal Circuit Design

In Out
z −1 A

1−A A<1

Figure 35.77 Filter used for Problem 35.32.

 Chapter

36
At the Bench

In this chapter we present some practical prototyping techniques to illustrate a few of the
concepts discussed in this book. The goal of the chapter is to simply provoke thought and
show alternative possibilities (other than hand calculations and simulations) for looking at
the performance of a mixed-signal circuit or system.

36.1 A Push-Pull Amplifier

The basic CMOS push-pull amplifier (see Ch. 22) is shown in Fig. 36.1a. Figure 36.1b
shows the schematic of the implementation used in this section where we have AC
coupled the input and output of the amplifier to allow the 9.1 MEG resistor to self-bias the
circuit. The bold numbers shown adjacent to the MOSFET terminals correspond to the pin
numbers of the 4007, Fig. 36.2, used to prototype the amplifier. Note that by AC coupling
our input and output, we can use ground as our input/output reference.

VDD BNC connector +9V

14

6
0.01u 0.01u
13
In Out In Out
8
6

(a) 9.1 MEG (b)

7

VSS -9V

Figure 36.1 (a) Push-pull amplifier and (b) prototyping the amplifier.
460 CMOS Mixed-Signal Circuit Design

14 2 11

6 13 3 1 10
12
8 5

7 4 9

Figure 36.2 Pin diagram for the 4007. Note how the bodies of all PMOS
devices are tied to pin 14, while the bodies of the NMOS devices
are tied to pin 7. This means that pin 14 must be tied to the highest
potential in the circuit (if the PMOS devices are used), and pin 7
must be tied to the lowest potential.

While the detailed datasheet for the 4007 can be found at the book's website
(http://cmosedu.com), we will comment that the threshold voltage for these transistors is
approximately 2 V and that they can drive around 1 mA or so into a load (this is a serious
limitation and will limit the size of the load we can drive). The large threshold voltage and
limited drive capability are the reasons we used ± 9 V power supplies.
Deadbug Prototyping
Figure 36.3 shows a chip flipped upside down and placed on a copper conductor (a glass
epoxy, FR-4 material coated with copper used in printed circuit board manufacuturing).
The reason this technique is called "deadbug prototyping" should be obvious (unless the
reader is so lucky they've never seen a dead cockroach). We use this approach instead of
the common white protoboards found in most undergraduate electronics laboratories for
prototyping because of the ability to use a good ground plane (the copper conductor). The
big drawback is the need to solder all of the components together. A good (meaning
equipotential) ground plane is essential to any low-noise, wide-dynamic range,
measurement. We'll also use BNC connectors to pipe our signals on-to and off-of the
board to avoid long wires, which tend to pick up coupled noise.
Figure 36.4 shows the prototype of the amplifier in Fig. 36.1b implemented using
the deadbug technique. The black and red wires coming into the circuit provide power and
ground. At the connections of power and ground on the board we add a decoupling
capacitor (a capacitor soldered from the power-supply connection to the ground plane).
This capacitor provides charge for any fast transients that may occur in the circuit. The
capacitor leads can be twisted into small loops and soldered to the ground plane or to a
pin on a chip and used as a contact point for the power supply clips. Before looking at
some measurement results, we need to discuss probe loading and measurement techniques.
Chapter 36 At the Bench 461

Figure 36.3 Deadbug prototyping using a copper ground plane.

Figure 36.4 Deadbug prototype of the amplifier in Fig. 36.1b.

462 CMOS Mixed-Signal Circuit Design

Probing
If we're not careful, we can load the circuit we are testing with our measuring system.
Consider the connection of a piece of coaxial cable to the oscilloscope shown in Fig. 36.5.
The scope has an input resistance of 1 MΩ and an input capacitance of 15 pF. When a
coax cable is driven by a large impedance and is terminated with a large impedance, we
think of it as a capacitor. If a 5-foot piece of coax is used to connect the push-pull
amplifier to the oscilloscope, we would get the circuit shown in Fig. 36.6. Clearly, the
measuring system will load the amplifier and keep us from accurately measuring the
response of the circuit.

BNC Around 20 to 30 pF/ft BNC

15 pF
1 MEG
Shield of coax connected to ground

Board under test Oscilloscope

Figure 36.5 The loading when probing with a piece of coaxial cable.

To reduce the loading by the required coaxial interconnect cable (150 pF in Fig.
36.6), a scope probe trades off sensitivity for lighter loading. Figure 36.7 shows a 10:1
compensated scope probe. The term 10:1 represents the attenuation factor from the probe
tip to the input of the scope. One-tenth of the voltage on the tip of the probe actually
makes it to the input of the scope. The term "compensated" indicates that the probe is
designed to compensate for the large loading of the coaxial cable. If the probe is
compensated correctly, the impedance in the probe's tip (9Z) is exactly, independent of

+9V

0.01u 0.01u Measurement loading.

Out
In
150 pF 1 MEG 15 pF

9V

Figure 36.6 How we can mess up a measurement if we're not careful.

Chapter 36 At the Bench 463

16.5 pF
5 feet Scope input

9MEG 30 pF/ft 15 pF
Probe tip 1 MEG
Probe cable

16.5 pF
Scope

9MEG 150 pF
15 pF
1 MEG
Probe tip
9Z Z

Approximation to calculate
10 MEG 15 pF effects of loading
Probe tip

Figure 36.7 How a compensated probe loads a circuit.

frequency, nine times larger than the impedance of the combination of the coaxial cable
and the scope (Z) . Note how the loading of the probe at DC is 10 MEG while at high
frequencies the loading is roughly 15 pF.
Testing the Circuit
To test this circuit, we'll use a vector signal analyzer, VSA, (an instrument similar to a
spectrum analyzer with the capability to perform an inverse Fourier transform for viewing
a signal in the time domain). A test setup is seen in Fig. 36.8. We'll use an input resistance
of 50 Ω to avoid the need for a compensated probe. Because of the limited drive capability
of the amplifier, we'll add a 5k resistor in series with the output. This results in a 100:1
attenuation (− 40 dB) from the amplifier's output to the input of the VSA. The schematic
of the amplifier is seen in Fig. 36.9. Note that we also added a resistor to ground on the
input of the amplifier to avoid a floating node.
Figure 36.10 shows the input signal to the amplifier in the time domain. It is a 100
mV sinewave with a frequency of 100 kHz. The spectrum of this signal is seen in Fig.
36.11. Note the units on the y-axis are dBm or decibels with respect to 1 mW of power.
464 CMOS Mixed-Signal Circuit Design

Figure 36.8 A test setup showing a VSA, spectrum analyzer (not in use), and power
supply.

+ 9 V 0.01u

0.01u 0.01u
5k
In to 50 ohm input VSA

0.01u

9V

Figure 36.9 Final schematic of the push-pull amplifier shown in Fig. 36.3.
Chapter 36 At the Bench 465

Figure 36.10 Input sinewave to the circuit of Fig. 36.9.

Because this is a 50 Ω system, we can verify the power in the input sinewave is, as seen in
Fig. 36.11, − 10 dBm by writing
2
 RMS voltage of the input sinewave 
 
 (Peak voltage amplitude)/ 2  /50 Ω
 
 
dBm = 10 ⋅ log = 10 ⋅ log 0.1 mW = −10 dBm
1 mW 1 mW
(36.1)

−10 dBm

Figure 36.11 Spectrum of the input sinewave.

466 CMOS Mixed-Signal Circuit Design

The spectrum of the amplifier's output is seen in Fig. 36.12. Keeping in mind that we have
an attenuation of −40 dB between the amplifier's output and the VSA's input, we can
estimate the amplitude of the output as the − 37 dBm + 40 dB or 3 dBm. The gain is then
13 dB. This can be converted into a voltage amplitude (of the output sinewave) using
V 2outpeak /(2 ⋅ 50)
3 dBm = 10 ⋅ log → V outpeak = 447 mV (36.2)
1 mW

Figure 36.12 Spectrum of the amplifier's output with the input seen in Fig. 36.11.

Figure 36.13 shows the output spectrum if the amplitude of the input sinewave is
increased to 1 V. Note the additional tones at multiples of the input frequency. The ideal
resulting sinewave peak output amplitude is 4.47 V. Clearly this amplitude is well within
the bounds of the power supply voltages. However, knowing the MOSFETs in the 4007
can supply only 1 to 2 mA and that our load is nominally 5k (because of the added
attenuating resistor seen in Fig. 36.9), we may run into some loading problems (resulting
in the output becoming distorted). Further, we might expect some distortion simply
because the amplifier is operating open-loop and, as indicated back in Ch. 22, the large
signal gain varies with the input amplitude. Toward characterizing this distortion, we can
specify the total harmonic distortion (THD), as

a 22 + a 23 + a 24 + ... + a 2n
THD = (36.3)
a 21
where a1 is the amplitude of the fundamental, a2 is the amplitude of the second harmonic
(or the tone at twice the desired frequency), a3 is the amplitude of the third unwanted
tone, etc. The THD is usually specified as a percentage, e.g., 0.01%. We can determine
the amplitude of the tones from the plot, neglecting the division by 1 mW (making the
Chapter 36 At the Bench 467

Figure 36.13 Output spectrum showing distortion when the input amplitude is
increased to 1 V.

actual units dBm) because of the ratio in Eq. (36.3), as −18 dB = 10 ⋅ log a 21 or
a 21 = 0.0159 , assuming the second harmonic's amplitude is −40 dB a 22 = 0.0001 , assuming
the third harmonic's amplitude is −45 dB, then a 23 = 0.0000316 , and finally the fourth
harmonic's amplitude is approximately 2 × 10 −6 . The THD can then be calculated as

THD = 0.1 + 0.0316 + 0.002 → THD = 9.1%

15.9
a large value (indicating that this isn't a good, low distortion, amplifier topology by itself).

36.2 A First-Order Noise-Shaping Modulator

Let's show how we can implement a simple noise-shaping modulator using a comparator,
a capacitor, and a couple of resistors, Fig. 36.14. This type of modulator can be built using
discrete components because we can precisely set the values of the resistors and capacitor.
This topology may also find use in clever integrated versions of lower SNR NS data
converters. When the circuit is operating correctly, the comparator holds its inverting
input (the voltage across the integrating capacitor) at ground. Remembering from Ch. 32
that the forward gain of the modulator must be unity, we see that, because the gain of the
integrator is much less than one over a significant portion of its operating frequency range,
the performance of the comparator becomes very important. In order for the comparator
to hold the voltage across the capacitor to a constant value, its gain must be very large. In
the following analysis we assume infinite comparator gain, so the voltage across the
capacitor is forced to zero by the feedback loop.
The input current (the input signal) can be written as
I in = V in /R in (36.4)
468 CMOS Mixed-Signal Circuit Design

Held at V CM by the comparator.

V in /R in clk
V in
R in C V out
V CM
−V out /R f Rf

Figure 36.14 A passive-integrator NS modulator.

while the feedback current can be written as

I f = V out /R f (36.5)
Note that we have not included the common-mode voltage, VCM, in Eqs. (36.4) and (36.5).
If the output of the comparator is 5 V (a logic 1) or 0 V (a logic 0), then the common-
mode voltage is 2.5 V. Also note, as we'll show in a moment, the input signal amplitude
can be scaled by adjusting the ratio of Rin/Rf .
Consider the block diagram of the modulator of Fig. 36.14 shown in Fig. 36.15.
The comparator has been represented, as in Chs. 31 and 32, as a noisy circuit block. For
example, assuming the inverting input of the compartor is precisely at 2.5 V and the
noninverting input is at 2.6 V, the output of the comparator is 5 V and the quantization
noise added to the signal, E(s) (for this particular input sample), is 2.4 V. We can write
 V in Vout  1
− ⋅ + E(s) = V out (36.6)
 R in R f  sC
After some manipulation, we can write
R f /R in sR f C
V out = V in ⋅ + E(s) ⋅ (36.7)
1 + sR f C 1 + sR f C

E(s)
V in /R in
V in V out
R in C

−V out /R f Rf

Figure 36.15 Block diagram of a passive-integrator NS modulator.

Chapter 36 At the Bench 469

The desired signal is lowpass filtered, while the quantization noise is, again, highpass
filtered (resulting in the modulation noise). Again, assuming the comparator gain is
infinite, passing the output of the moduator through a digital filter with a bandwidth less
than 1/2πR f C results in a digital replica of the analog input signal. The practical problems
with this topology are the importance of the comparator's gain and the kickback noise
injected into the input signal when the comparator switches states.
Prototyping the Modulator
Figure 36.16 shows the schematic of the prototype modulator. The D flip-flop was added
to make the LM339 comparator appear as though it were a clocked comparator. Also, the
74HC74 is implemented using CMOS and so its outputs swing all the way down to
ground and up to +5 V. This is important when we use its output as the fed-back signal in
our modulator. The resistors and capacitor on the input of the modulator form a lowpass
filter (as seen in Eq. [36.7]) with a time constant of 100 µs. The 3 dB frequency
associated with this circuit is then 1.59 kHz. Input signal frequencies above this value will
experience an attenuation. Figure 36.17 shows the deadbug prototype of the modulator.

Analog out
5V 100k
In 5V 5V 1,000p
100k 1.2k 1,4 14
5 3
2
1,000p LM339 D Q
4 2 5
12 74HC74
100k 3 clk Q Digital out
5V 1k 1k clk 6
(1 MHz)
7

Figure 36.16 Schematic of the passive-integrator NS modulator.

The input to the modulator used to generate some test results, see Fig. 36.18, is a
4 V peak-to-peak sinewave at a frequency of 500 Hz centered around 2.5 V. The digital
modulator output is shown in this figure as well. Looking at this digital data alone is
somewhat meaningless using the oscilloscope (and so we'll look at the spectrum of this
data). Figure 36.19 shows the spectrum of the digital data. A 3-foot coaxial cable is
connected between the digital output in Fig. 36.16 and the VSA (with a 1 MEG input
resistance so the loading will affect signal frequencies greater than roughly 100 kHz).
Figure 36.20 shows the spectrum of the modulator's output up to 200 kHz. Note how, as
seen back in Fig. 32.15, the modulation noise increases with increasing frequency. The
resolution of the measurement, in Fig. 36.20, is 25 kHz. This causes the desired signal at
500 Hz to appear as though it were occurring at DC. Finally, the bottom trace in Fig.
36.18 shows what happens if we pass the digital data output from the modulator through
an RC lowpass filter with a 3-dB frequency of 1.59 kHz. As expected, the resulting analog
output is a very close replica of the input signal.
470 CMOS Mixed-Signal Circuit Design

Figure 36.17 The prototype of the passive noise-shaping modulator

of Fig. 36.16.

Input to the modulator

Digital modulator output

RC filtered output

Figure 36.18 The outputs of the circuit in Fig. 36.16.

Chapter 36 At the Bench 471

Input sinewave with a peak amplitude of 2 V and a frequency of 500 Hz

DC 5 kHz 10 kHz

Figure 36.19 The base spectrum of the modulator's output data.

DC 100 kHz 200 kHz

Figure 36.20 The spectrum of the modulator's output data up to 200 kHz.
Resolution bandwidth is 2.5 kHz (and so our input signal is smearing
with DC).
472 CMOS Mixed-Signal Circuit Design

36.3 Measuring 1/f Noise

Circuit noise was reviewed back in Sec. 33.3.3. In that section we showed that averaging
thermal noise can be used to increase the SNR. Averaging, as seen in Chs. 30 and 31, can
be thought of as lowpass filtering (and thus reducing the bandwidth of the signal and
noise). We might wonder if averaging Flicker (1/f ) noise results in a reduction of the
circuit's input-referred RMS noise voltage. We'll show in this section that averaging a
wideband signal has little effect on the input-referred contributions from 1/f noise.
Figure 33.85 showed the basic setup to measure 1/f noise. Figure 36.21 shows a
lab setup used to measure the 1/f noise present in a submicron MOSFET. Because these
devices aren't packaged, we need to use a probe station to pipe the bias signal on to the
wafer and the noise signal off of the wafer.
The low-noise amplifier (LNA) shown in Fig. 36.21 is housed in a shielded box to
avoid pickup of stray electromagnetic interference. Remembering that the LNA must both
amplify the MOSFET's noise and bias the MOSFET to a specific operating point, we can
sketch a possible LNA implementation, Fig. 36.22. The circuit is powered with 9 V
batteries to avoid the possibility of regular bench power supplies injecting noise into the
circuit and thus corrupting the measurement. The low-noise op-amp used, the OP-37, is
configured in a gain of 100 configuration. A potentiometer is used to trim out the offset
voltage of the op-amp. To see the basic op-amp's noise characteristics (without the

Shows location of probes

Low noise amplifier Dynamic signal analyzer

Wafer

Figure 36.21 A lab setup used to measure Flicker noise.

Chapter 36 At the Bench 473

Triaxial connection to drain. 100k 9V batteries

+9V
5.1k 0.01
100u, C2
DUT
OP-37 Out
100k
Tri-axial connection to gate.
0.01
+9V
+9V
100k 10k
100k
100k
100u C1 1k
-9V
Input switch
Used to trim the op-amp's offset

Figure 36.22 Schematic of an LNA.

MOSFETs connected), we simply remove C2 and connect the output to the spectrum
analyzer (dynamic signal analyzer). The resulting spectrum is seen in Fig. 36.23. Note that
the output spectral noise density of the LNA is roughly −80 dBV/ Hz (100 µV/ Hz ) at
1 Hz (dividing this by the op-amp's gain of 100 results in 1 µV/ Hz at the MOSFET's
drain). In the following, we ignore the LNA's contribution (to simplify the discussion).

-80 dB

10

1Hz 100 1k 100k

Figure 36.23 Measured noise characteristics of an LNA using the OP-37.

474 CMOS Mixed-Signal Circuit Design

MOSFET Noise
Figure 36.24 shows the noise spectrum when we put C2 back in the circuit, bias the
MOSFET at a specific operating point, and connect C1 to ground. The spectral density at
1 kHz is roughly −70 dBV/ Hz or
−70 dBV/ Hz = 316 µV/ Hz at 1 kHz (36.8)
or, calculating the 1/f spectral density (see Ch. 9)
FNN
2
 316 µV  100 × 10 −9 V 2 = Flicker noise numerator (FNN) = 100 pV
2
v 21/f,out =   =
 Hz  Hz 1 kHz f

(36.9)
As a quick check, the spectral density of the noise at 10 kHz can be calculated as
100 pV 2 10 nV 2 100 µV
v 21/f,out = = → v 21/f,out = = −80 dBV/ Hz (36.10)
10 kHz Hz Hz
which is what we see at 10 kHz in Fig. 36.24. (To determine the MOSFET's output noise
spectral density alone we divide the spectral density in Fig. 36.24 by the LNA's gain of
100.) To determine the RMS output noise, we can integrate the 1/f noise spectral density
1/2
1/2
 fH 
v 2on =  ∫ v 21/f,out ⋅ df 
fH
=  FNN ⋅ ln  (36.11)
 fL   fL 

-70 dB -10 dB/decade

-80 dB

1 kHz 10 kHz

Figure 36.24 Measured Flicker noise from the MOSFET/LNA in Fig. 36.22.
Chapter 36 At the Bench 475

This equation is fundamentally important to understand our statement at the beginning of

the section, that is, averaging a wideband signal will have little effect on the contributions
from 1/f noise to the input-referred or output RMS noise voltages. If we select the largest
frequency, fH, as 10 GHz (1010 Hz) and the lowest frequency as 1 Hz (once per second),
then the natural log term in Eq. (36.11) is 23. However, if we change the lowest frequency
of interest to 10-10 Hz (roughly once every 320 years), the natural log term increases to
only 46! So to get a quick-and-dirty estimate of the contribution of 1/f noise to an output
RMS noise voltage, we simply use
contributions from 1/f noise to RMS output voltage = 7 ⋅ FNN (36.12)
(knowing, of course, we can only add mean squared noise voltages). So, for the noise
spectrum in Fig. 36.24, we can estimate the RMS output noise contributions as

v 2on = 7 ⋅ 100 × 10 −12 V 2 = 70 µV (36.13)

Again, this approximation is useful for wideband estimates of the RMS noise due to
Flicker noise. It's not useful if a narrow bandpass filter is used on the output of a circuit
where fH and fL are well defined.
Input-Referred Noise Voltage
While knowing the output noise is useful, it is generally more useful to refer this noise
back to the input of the circuit so that it can be compared with an input signal. Towards
this consider, in Fig. 36.22, connecting C1 to the BNC connector instead of ground. We
can inject a signal, say a 1 mV sinewave, into the gate of the MOSFET and then look at
the output of the circuit. If the overall gain of the circuit is 1,000 (= A), then we would see
an output sinewave with an amplitude of 1 V. Knowing the gain of the circuit (MOSFET
and op-amp), we can determine the input-referred noise by dividing the noise power
spectral density with units of V 2 /Hz , by A2 or the noise voltage spectral density (or RMS
output voltage) by A. Rewriting Eq. (36.12) for the input-referred RMS voltage
Contributions from 1/f noise to RMS input-referred voltage = 7 ⋅ FNN /A (36.14)
An important consideration when measuring the gain of the circuit is the frequency
response of the gain. At the high end, the op-amp, in a gain of 100 configuration will have
a bandwidth of approximately 10 kHz (assuming a gain bandwidth product of 1 MHz).
Also, the MOSFETs have to drive the capacitance of the triax cables, which will result in
an upper frequency roll-off in the amplifier's response. At the low end, C1 and C2 must be
very large to keep the low-frequency roll-off point from becoming too large. The overall
MOSFET/LNA's response has a bandpass shape. The point is that the input sinewave's
frequency should be varied in order to find the passband gain of the circuit. Once C1 is
grounded, its effect on the low-frequency roll-off is eliminated.
Clearly, 1/f noise can be a significant limiting factor when making sensitive
measurements or when trying to attain large SNRs. Because averaging won't provide any
help in reducing 1/f noise, let's show one very practical method that will help. While
correlated double sampling (CDS) can be used here we discuss chopper stabilization
(CHS). See reference [9] in Ch. 33 for additional information.
476 CMOS Mixed-Signal Circuit Design

Chopper Stabilization
Consider the OTA shown in Fig. 36.25a and the associated noise spectral density shown in
Fig. 36.25b. This circuit is essentially an integrator. In an ideal integrator, connecting the
inputs together and to the common mode voltage would result in the outputs remaining
unchanged. However, in a real integrator, the OTA's offset and the 1/f noise results in the
outputs of the integrator eventually reaching the supply rails. It would be nice if we didn't
have to worry about either the offset or the 1/f noise. What we are going to do in the CHS
scheme is modulate the offset and noise to a place in the frequency spectrum where it
won't interfere with our desired signal.

Output noise, V/ Hz
10 dB/decade

In Out 20 dB/decade

1/f noise
(a) dominates

Thermal noise frequency

dominates Noise rolls off
(b) with amplifier bandwidth

Figure 36.25 Integrator noise using an OTA.

Toward understanding this last statement consider the first-order noise-shaping

modulator shown in Fig. 36.26. This topology is useful when measuring very small signals.
It is very power-supply insensitive because of the current sources used. The noise and
Connected as shown when cout is high.

cout
In
cout

clk

Figure 36.26 A first-order noise-shaping modulator using an OTA integrator.

Chapter 36 At the Bench 477

offsets contributed by the OTA will directly affect the input sensitivity. Consider what
would happen if we chopped (or switched back-and-forth) the input/output terminals of
the OTA as seen in Fig. 36.27. When clk is high, the OTA is connected through switches
so that it behaves as seen in Fig. 36.26. The OTA's offset, for example, causes a current to
charge/discharge the capacitors. When clk is low, both the input and output terminals are
switched so that the gain of the amplifier remains the same polarity. The offset now causes
a current to flow in the capacitors in the opposite direction from the flow when clk was
high. This effectively, if the rate at which we switch back-and-forth is fast, results in net
zero current flow into the capacitors. A similar argument can be made for the low-
frequency 1/f noise. The chopping, or switching, reduces both the offset and the Flicker
noise on the output of the integrator (and so the input-referred noise is decreased as well).

clk clk clk

clk

Figure 36.27 Switching (chopping) the inputs and outputs of the OTA integrator.

Figure 36.28 shows a possible implementation of the chopping switches. This

should look familiar from Ch. 26. It was used to implement a multiplier. Here we are also
using it for a multiplication. We are multiplying our OTA's input signal by +1 or −1 while
doing the same to the OTA's output signal in order to maintain the same gain polarity. If
the frequency we chop at is labeled fchop, then we are multiplying the input by a square
wave with this frequency. Looking at only the first harmonic of the waveform, we see this
is simply amplitude modulation.

clk clk

Figure 36.28 Showing a possible implementation of the chopping switches.

478 CMOS Mixed-Signal Circuit Design

Consider the block diagram of the chopper and OTA of Fig. 36.27 shown in Fig.
36.29. Here we set the chopping frequency to one-half of the clock frequency (the clock
used to strobe the comparator in the noise-shaping modulator of Fig. 36.26). We do this
so that no aliasing occurs in our signal of interest from sampling the D signal at fclk (the
OTA noise doesn't fold into the signal of interest after sampling). If the settling time, when

A B C D
OTA
Note integration
is not occurring in
cos 2πf chop cos 2πf chop the traces below

Input (desired) signal at A

frequency

Signal at B after amplitude modulation

Desired signal

f chop f clk frequency

Signal at C after OTA noise is added to signal

OTA noise
not to scale
frequency
f chop f clk

Desired signal
Signal at D after demodulation

OTA noise

f chop f clk frequency

Figure 36.29 How chopping affects the noise and signal in an OTA.
Chapter 36 At the Bench 479

chopping at fchop, of the amplifier is longer than 2/fchop, then a lower chopping frequency
can be used (ultimately set by the integrator's bandwidth). For example, if we are clocking
the NS modulator of Fig. 36.26 at 100 MHz, then we might chop the OTA's input/output
at a rate of 12.5 MHz (divide the NS modulator's clock by eight using a cascade of three
of the circuits in Fig. 33.46).
In a second-order noise-shaping modulator the input-referred noise is mainly due
to the first integrator as discussed in Ch. 32. The input-referred 1/f noise is passed directly
to the output of the modulator. Modulators that use an autozeroed integrator don't have
this problem because the autozeroing operation removes both the offset at DC and
attenuates the 1/f noise spectral density. Looking at the power spectral density of 1/f noise
on the output of an integrator, when not used in a modulator with feedback, results in a
1/f 3 spectral shape. Averaging this noise results in linear growth with averaging time.

36.4 A Discrete Analog Integrator

Let's build a DAI-based first-order lowpass filter. Figure 36.30 shows the circuit (see Fig.
35.22). The charge stored on CI when the φ1 switches are closed is given by
Q 1 = C I (v in [(n − 1/2)T s ] − v out [(n − 1)T s ]) (36.15)
When the φ2 switches close, this charge is transferred to the feedback capacitor, CF,
Q 1 = C F (v out [(n)T s ] − v out [(n − 1)T s ]) (36.16)

CF
φ1 φ2

CI V CM v out
v in

Ts
φ1

φ2

n−1 n t
n − 1/2

Figure 36.30 A first-order filter made using a DAI.

480 CMOS Mixed-Signal Circuit Design

Taking the z-transform of this equation results in

C I (V in (z) ⋅ z −1/2 − V out (z) ⋅ z −1 ) = C F (V out (z) − Vout (z) ⋅ z −1 ) (36.17)
C I ⋅ V in (z) ⋅ z −1/2 = V out (z) ⋅ (C F − C F ⋅ z −1 + CI ⋅ z −1 ) (36.18)
or
V out (z) z 1/2
= (36.19)
V in (z) CF C
⋅ z − CFI + 1
CI

noting the z1/2 term in the numerator is simply a phase shift (a time delay), which will be
neglected as long as our input frequencies, f, are much less than the filter's clocking
frequency, fs. Remembering from Eq. (35.69) that
z ≈ 1 + s when f << fs (36.20)
fs
we can rewrite Eq. (36.19) as
V out (s) 1
= (36.21)
V in (s) 1 + sR sc C F
where
1
R sc = (36.22)
f sCI
The filter's 3-dB frequency is located at

f 3dB = 1 (36.23)
2πR sc C F
Clock Generation
The first thing we need to build is the clock generation circuit. Figure 36.31 shows the
basic schematic of a nonoverlapping clock generator circuit. We use ± 9 V supplies. The
two phases of the clock should transition between these voltages. We, again, use the 4007

Clk
φ1

φ2

Figure 36.31 Nonoverlapping clock generation circuit.

Chapter 36 At the Bench 481

CMOS transistors shown in Fig. 36.2 to implement the generator. Further, since this is a
purely digital circuit, we breadboard the design (see Fig. 36.32). Figure 36.33 shows the
outputs of this generator.

Figure 36.32 Breadboard of a clock generator.

Figure 36.33 Nonoverlapping clocks.

482 CMOS Mixed-Signal Circuit Design

Prototyping the Filter

The schematic of our filter is seen in Fig. 36.34. The MOSFET switches are implemented
using the 4007. The op-amp is an LT1365. Figure 36.35 shows the deadbug
implementation of the filter.

φ1 φ2
1000p

5 10
4 3 9 12 2 +9V
8
5 10
LT1365 Output
4 9 12 3 1
Input 4
3
130p
-9V

Figure 36.34 Schematic of the DAI-based filter.

Figure 36.35 Deadbug prototype of the DAI filter in Fig. 36.34.

Using Eq. (36.23), we calculate the filter's 3-dB frequency as 2 kHz when the filter
is clocked at 100 kHz. Figure 36.36 shows the filter's input and output at this frequency. If
Chapter 36 At the Bench 483

one looks closely at the output signal, the discrete nature is obvious (see the steps in the
output waveform shown in the simulation in Fig. 35.23). Figure 36.37 shows how the 130
pF capacitor (the node at the bottom of the schematic) charges to the input signal and then
discharges back to ground (making the parasitic capacitance on this node unimportant).

Input Output

Figure 36.36 First-order filter's input and output at the 3-dB frequency of 2 kHz.

Figure 36.37 How the 130 pF capacitor charges and discharges.

484 CMOS Mixed-Signal Circuit Design

Before leaving this section, let's show example input/output spectrums for this
first-order switched-capacitor filter; Fig. 36.38. The desired signal is at 2 kHz and its peak
amplitude has been decreased to 500 mV (to avoid overloading the VSA). The input
signal amplitude is then 10 ⋅ log([(0.5/ 2 ) 2 /1 MΩ]/1 mW) or −39 dBm. Because we are
applying the 3 dB frequency, we expect our output amplitude to be −42 dBm (and it is).
Finally, to show that the filter is indeed a sampled circuit, we increase the input frequency
to 10 kHz and show the output images around the 100 kHz sampling frequency, Fig.
36.39.

Filter output
spectrum

Input spectrum

Figure 36.38 Input and output spectrums for the filter of Fig. 36.34.

Filter output
spectrum

Input spectrum

Figure 36.39 The spectrum up to the clocking frequency (100 kHz).

Chapter 36 At the Bench 485

36.5 Quantization Noise

For the last section in this chapter, let's discuss, and show how to calculate, the
quantization noise added to a spectrum from a data converter. We showed how to
calculate the noise from a simulation spectrum back in Ch. 30; see Eq. (30.33). When
presented with a data converter's output spectrum, Fig. 36.40, we can remove the desired
signal (and perhaps the distortion if we calculate only the noise in the signal) and calculate
the RMS quantization noise (or simply the noise in the spectrum) using
f max

V Qe,RMS = ∫ V out ( f ) ⋅ df
2
(36.24)
0 (DC)

The signal V out ( f ) represents the data converter's output spectrum (after removing the
desired signal and any distortion spikes) and has units of V/ Hz . The maximum
frequency we integrate to, fmax, is generally the Nyquist frequency, f s /2 . We assume that,
when actually using the data converter, a reconstruction filter removes spectral content in
the output signal above the Nyquist frequency. In a noise-shaping modulator, a digital
filter sets fmax. Note that we can't accurately calculate the quantization noise added to an
input signal unless the input to the data converter is busy. A sinewave of sufficiently large
amplitude can be used to exercise the data converter and "whiten" the quantization noise.

Input signal
Quantization noise

Distortion tones

V out ( f )
After removing the desired signal and distortion tones.

Figure 36.40 The output spectrum of a data converter.

486 CMOS Mixed-Signal Circuit Design

Before going any further, let's show some example spectrums and the
corresponding y-axis units. The top waveform in Fig. 36.41 shows the resulting spectrum
when the input to the VSA is a 0.5 V (peak) waveform at 2 kHz. The RMS value of this
waveform is 354 mV. In dBm (using a 1 MΩ VSA input resistance) this is
10 ⋅ log   (0.354) 2 /1 MΩ /1 mW or −39 dBm; see the top trace in Fig. 36.42. The units
for the top trace in Fig. 36.41 are volts, root-mean-square. Many of the spectrums we
used in earlier chapters used peak voltages for the y-axis units.

Figure 36.41 The relationship between units in spectral plots.

The bottom trace in Fig. 36.41 shows the voltage spectral density of our 0.5 V
peak sinewave at 2 kHz. The units of a voltage spectral density are V/ Hz (or more
precisely volts RMS per root Hz). Because the same exact waveform is input to the VSA
for each spectrum, we can relate the top and bottom waveforms in Fig. 36.41 simply by
knowing the resolution bandwidth of the measurement
V RMS V RMS
= (36.25)
Hz Resolution bandwidth
The resolution bandwidth used by the VSA, for the waveforms of Fig. 36.41, was 100 Hz.
This means the amplitude of the sinewave is now 354 mV/ 100 Hz or 35.4 mV/ Hz . In
dB this would be 20 ⋅ log 0.0354 or −29 dB. For a power spectral density, see the bottom
trace in Fig. 36.42, we can use
V 2 (or Watts) V 2 (or Watts)
= (36.26)
Hz Resolution bandwidth
Because our resolution bandwidth is 100 Hz, we expect the power spectral density to be
20 dB less than the power spectrum (top trace in Fig. 36.42) or −59 dBm/Hz. It should be
obvious how to change from dBm/Hz to V2/Hz.
Chapter 36 At the Bench 487

Figure 36.42 Power spectral density of the spectrums in Fig. 36.41.

Given a spectrum with noise (quantization, thermal, Flicker, or whatever), we can

now generate the desired spectrum ( V out [ f ] in Fig. 36.40) for calculating RMS noise. To
illustrate how let's use the modulator output spectrum seen in Fig. 36.19. We begin by
removing the desired tone in the spectrum (the sinewave at 500 Hz). Next we assume the
noise is white (a flat spectrum) and has a value of −60 dBm. Because the VSA's input
resistance is 50 ohms and the resolution bandwidth is 100 Hz, we can estimate the power
spectral density of the noise using
V2RMS /50
10 −60/10 = → V 2RMS = 50 × 10 −9 V 2
1 mW
and
−9 2
PSD = V 2out ( f ) = 50 × 10 V = 500 × 10 −12 V 2 /Hz
100 Hz
Using Eq. (36.24), we now need to estimate the maximum frequency used in the upper
limit of the integration. Looking at the spectrum in Fig. 36.19, we see that the spectrum
appears relatively constant over a wide frequency range. However, in any ADC we must
use a reconstruction filter (or, for this case where a modulator is used, a digital averaging
filter) to bandlimit the noise in the spectrum. For the modulator discussed in Sec. 36.2 a
reasonable value of maximum frequency is 2 kHz (again set by a filter). Going above this
frequency results, as seen in Eq. (36.7), in an undesired signal reduction (the signal sees
the lowpass response of the integrator). The RMS noise in the modulator's output
spectrum is then
1/2
 2k 500 × 10 −12 V 2 
V noise,RMS =  ∫ ⋅ df  = 1 mV
0 Hz 
 
488 CMOS Mixed-Signal Circuit Design

The RMS value of the desired signal in Fig. 36.19 is 1.41 V. The SNR, for this
modulator's output spectrum, is

SNR = 20 ⋅ log 1.41 V = 63 dB

1 mV
Using Eq. (31.5), the effective number of bits is roughly 10.
While these calculations are useful to illustrate how we manipulate data to
calculate a SNR, it will be more useful to prototype an actual ADC and compare the
quantization noise it adds to a signal to the values calculated theoretically.
Prototyping the ADC Circuit
In order to make our measurements practical and simple consider the circuit diagram
shown in Fig. 36.43. An ADC and a purely resistive DAC are used to illustrate the noise
(from the quantization process) added to an analog signal by the analog-to-digital
conversion process. Using such a simple output DAC is useful as long as the ADC outputs
swing from rail-to-rail and we use a relatively large resistance (say 10k) so the CMOS
outputs can supply a current to the load resistors without a significant output voltage sag.

0.01 +5 V

11,13,14,15,17,18
20k Reconstructed
b 10
5
Output
10k
20k
Analog input 19 In 9
b3
20k 10k
8 20k
ADC b2
10k
20k
Clock 12 Clk b 11 7
10k
20k 20k
6
b0
1,2,20,21,23,24 20k

Figure 36.43 Schematic of an ADC and resistive DAC.

The ADC we selected is the TLC5540. It is an 8-bit ADC. However, we will only
use the upper five bits of the ADC to illustrate the quantization process. The maximum
reference voltage, V REF+ , is 5 V, while the minimum reference voltage, V REF− , is ground.
The clock pulse we'll use for our measurements will oscillate between ground and 5 V at 1
Chapter 36 At the Bench 489

MHz. Because we are using five bits we can estimate the weighting of the LSB using Eq.
(30.23) as 156 mV. Further, from Eq. (30.30), we can estimate the RMS value of the
quantization noise as 45 mV. A picture of the prototyped ADC/DAC is seen in Fig. 36.44.
The TLC5540 comes in a plastic small outline package (SOP). This SOP package is
difficult to solder by hand in our deadbug prototyping scheme so we soldered it into a
dual-in-line package (DIP) carrier. This makes prototyping the circuit much easier.

Figure 36.44 Photograph of the ADC/DAC prototype circuit.

Figure 36.45 shows the output spectrum for the ADC and resistive DAC seen in
Fig. 36.43. Again, the clock frequency is 1 MHz. The input signal is a sinewave at 50 kHz
with 0.5 V peak and centered around 2 V. The reason we don't see a DC signal in the
spectrum is that the VSA's input was AC coupled. Again, the VSA's input resistance is 1
MΩ. Note how the spectrum rolls off with increasing frequency. We connected the output
in Fig. 36.43 to the VSA's input through a piece of coax cable. The coax was 3 feet long
and resulted in a capacitance of approximately 100 pF shunting the VSA's input, Fig.
36.46. If we model the ADC/DAC as a voltage source with 10k output resistance, then
the frequency response of the measuring circuit is lowpass with a corner frequency of

f 3dB = 1 = 138 kHz

2π10k ⋅ 115 pF
Frequencies, in the output spectrum above this frequency will start rolling off at a rate of
20 dB/decade. The point is that instead of seeing a flat quantization spectrum (as in Fig.
30.57, for example), we will see a spectrum that rolls off with increasing frequency.
490 CMOS Mixed-Signal Circuit Design

Figure 36.45 Output spectrum showing quantization noise for the 5-bit ADC in Fig. 36.43.

10k

100p 15p
1MEG

ADC source cable capacitance VSA input impedance

Figure 36.46 How loading affects the ADC's output spectrum.

Looking at Fig. 36.45 and knowing that the spectrum rolls off because of the
measuring system, we can get an estimate for the quantization noise power at low
frequencies as −65 dBm. Knowing the resolution bandwidth of the measurement was
10-kHz, we can estimate the power spectral density using
V 2RMS /1 MΩ
−65 dBm = 10 ⋅ log → V 2RMS = 316 × 10 −6 V 2
1 mW
or
−6 2
PSD = V 2out ( f ) = 316 × 10 V = 31.6 × 10 −9 V 2 /Hz
10 kHz
The Nyquist frequency is 500 kHz. If we again assume a filter is used to bandlimit the
ADC output to the Nyquist frequency, we can calculate the RMS quantization noise as
Chapter 36 At the Bench 491

1/2
 500k 
V Qe,RMS =  ∫ 31.6 × 10 −9 ⋅ df  = 125 mV
 0 
 
This RMS noise is three times larger than what we calculated earlier (45 mV). We might
speculate that the difference is due to not adequately randomizing the noise by using too
high of an input frequency, relative to the sampling frequency, or too small an input
amplitude (all of which are easy to verify at the bench).
Finally, let's show some time-domain waveforms showing quantization effects.
Figure 36.47 shows the input and output waveforms when the input frequency is 5 kHz.
Note how, as we calculated earlier, 1 LSB is 156 mV. Figure 36.48 shows the output
when the input frequency is increased to 50 kHz, while Fig. 36.49 shows the circuit's
inputs and outputs when the Nyquist frequency is applied to the circuit. Note how, as we
would expect, the DAC output is simply a square wave at a frequency of 500 kHz. After
this output is passed through a reconstruction filter with a frequency of just over 500 kHz
we get our exact replica of the input signal simply shifted in time. While the signal in Fig.
36.45 was measured by providing a connection between the circuit and the VSA using a
piece of co-ax cable, Fig. 36.46, the signals in Figs. 36.47 - 36.49 were measured using a
compensated scope probe, Fig. 36.7. The significantly reduced loading resulting from
using the compensated scope probe eliminates the spectrum roll off that was present in
Fig. 36.45.

156 mV

Figure 36.47 ADC input frequency of 5 kHz and the DAC output.
492 CMOS Mixed-Signal Circuit Design

Figure 36.48 ADC input frequency of 50 kHz and the DAC output.

Figure 36.49 ADC input frequency of 500 kHz (the Nyquist frequency) and the DAC output.

While the circuits built in this chapter represent a small number of examples,
relative to the material covered in the book, it is hoped that they are representative enough
to make the engineer/student want to spend some time at the bench.
 bandpass filter, 132
circuits, 54, 89-91
clock jitter, 93-94

Index decimation, 106-126

digital filter, 106-114
filter, 167-171
highpass filter, 132
how it reduces noise, 55-57
improving signal-to-noise ratio (SNR), 87-105
interpolating filter, 126-131
limiting bandwidth, 92
A linearity requirements, 56, 95-96
noise, 299, 472-474
AAF. See Antialiasing filter. op-amp, 370-372
ABSTOL, 20, 24-25 quantization noise, 54-57, 89-92
Accumulate-and-dump circuit, 107-111 without decimation, 111-112
cascading, 110-111, 167, 176-177
See Digital averaging filter.
Accumulator, 116, 157-158 B
Accuracy, 96, 321, 329, see also Matching.
Active-RC Integrator, 395 B, bandwidth of the input signal, 73, 92
filter, 395, 419, 431 B device. See Nonlinear-dependent source.
Adaptive filtering, 415 Bandpass filter, 116, 132, 434
ADC. See Analog-to-digital converter. Bandpass modulators, 228-231
Adder, 274-275 Bennett’s criteria, 38, 52-53, 88, 127, 159
Algorithmic ADC, see Cyclic ADC Beta-multiplier, 281
Aliasing, 3-4, 120, 122, 478 Biasing, 280-283
quantization noise, 43 Bilinear transfer function, 418
Analog RC filter, 178 Bin, 44
Analog Sinc averaging filters, 169-171 Binary offset, 105, 451
Analog-to-digital converter (ADC), 26, 136 Biquad filters, 429-448
1.5 bits/stage, 360-367 Biquadratic transfer function, 429
averaging, 57 Boltzmann's constant, 299
calibrating, 372 Bottom plate sampling, 26, 343
capacitor error averaging, 361, 368-376 Buffer,
comparator placement, 352-354, 362, 374-376 digital, 268
cyclic, 351-359 push-pull, 284-286
decimating filters, 93, 106, 136 Buried channel, 238
digital error correction, 360
ideal, 18, 19, 32-36
implementing, 343 C
modulator or coder, 136, 140-141
pipeline, 24, 359 CAI, See continuous-time analog integrator.
Antialiasing filter (AAF), 2-7, 94, 113, 120-121, Calibration, 326-327, 362
125, 156, 393, 408, 415 Canonic digital filter, See Digital filter.
Aperture jitter, 70 Capacitance,
Autocorrelation function (ACF), 79 input, 305
discrete version, 81 metal, 241-244
Autozeroing, 342, 344 MOSFET, 239-241
Auxiliary input port, 339-342 Capacitive feedthrough, 340-341
Average power, 62, 80-81 Capacitor error averaging, 361, 368-376
Average value, 82 Cascaded modulators, 221-227
Averaging, 54-57, 87-135, 299 Causal, 11
494 Index

Charge injection, 340-341 See, also, accumulate and dump.

Charge pump, 260-262 Coupling noise, 385-388
Chopper stabilization, 306, 476-478 Current-mode DAC, 312-314, 316-327, 332-334
Clock driver, 260-262 Current steering DAC, 332-334
Clock generation, 377-378, 480-481 Cyclic ADC, 351-359
Clock jitter, 70-79, 82-86, 93
averaging, 93-94 D
defined, 70
modeling with SPICE, 74 DAC. See Digital-to-analog converter.
oversampling, 73 DAI. See Discrete analog integrator.
power, 83 Data converters,
reducing stability requirements, 72 implementing, see Ch. 34
related to resolution, 71 modeling, see Ch. 30
spectrum, 76-77, 84 SNR, see Ch. 31
stability, defined, 70 dBc (decibels with respect to the carrier), 68, 86
CMOS, 235-238, 311 DC measurements, 176
analog circuit design, 276-298 Deadbug, 460-461
circuit design in a submicron process, see Ch. Decimation, 106-126, 166
33 bandwidth limitations, 92, 120-126
digital circuit design, 255-276 decimating filter, 93, 106, 136
process flow, 236-239 Delay elements, 271-273
Coherent sampling, 45, 65 Delta modulation, 140
Correlated double sampling, 306 Delta-sigma modulation, 154 See noise-shaping.
Comb filter. Demodulator, 136
analog, 7-9 Diff-amp, 276, 290-291
digital. See Digital comb filter. Differential nonlinearity, 311-334
simulating, 169-171 improving using segmenation, 321-322
Common-mode feedback (CMFB), 295-297, Differentiator, 115
347-350 Digital averaging filter, 57, 106-126
dynamic, 382-385 Digital comb filter, 116-119, 128, 132, 135
Common-mode noise elimination (CMNE), Digital differentiator, 115
264-270, 296-297 Digital error correction, 360, see also Analog-
Common-mode rejection ratio (CMRR), 192, 290 to-digital converter (ADC), 1.5 bits/stage
Common-mode voltage, 32, 136, 349 Digital filter
Comparator, biquad, 446-448
clocked, 155, 261-264, 469 canonic, 425-429
gain, 186, 351 characteristics, 101, 421-429
hysteresis, 186 finite impulse response (FIR), 116
in an ADC, 352-354 infinite impulse response (IIR), 116
kickback noise, 263, 308, 353 removing modulation noise, 164-166,
placement, 352-354, 362, 374-376 212-213, 448-451
SPICE modeling, 153 stability, 122-124
Constant delay, 5 Digital integrator, 102-104, 114, 416
Continuous-time analog integrator, 172, 395 Digital resonator, 132-135
Continuous-time comb filter, 7-8, 169-171 Digital signal processing (DSP), 1, 415
Continuous-time Fourier transform, 51 Digital-to-analog converter (DAC), 41, 125-131,
Convergence, 25 136, 140, 485-492
Convolution, 22 calibration, 326-327
Correlated double sampling (CDS), 306, 475 current steering, 332-334
Cosine window. See Hanning window. demodulator or decoder, 136
Counter, 134, 176-177, 216-217, 255 feedback, 174-179
ripple, 272-273 ideal, 26-32
up/down counter, 274 interpolating filter, 93, 127, 136
Index 495

pipeline, 392 gm-C filters. See transconductor-C filter.

R-2R, 245-248, 312-331 highpass, 132, 116, 132, 214-215, 218, 401,
segmentation, 321-322 418, 420, 469
selecting capacitors, 306 in a higher-order modulator, 215
wide-swing, 316-327 infinite impulse response (IIR), 116
without an op-amp, 328-334 integrating filters, 102-103, 124
Dirac delta impulse, 9-10 interpolating filters, 126-129
Discrete analog integrator (DAI), 136-139, 151, ladder filter, 457
154-155, 157, 173, 185, 198, 226, 393, lowpass, 9, 52, 59, 106, 114, 116, 133-134,
411-415, 418, 479 156, 159, 164, 179, 190, 201, 205, 208,
feedback gains, 202-205 214-215, 228, 301, 415, 469, 472,
fully-differential, 191 479-484
noise performance, 306-307 MOSFET-C, 404-406
Discrete Fourier transform, 13-14, 51 Q peaking and instability, 443-445
loading data using WinSPICE, 67 Sinc, 109
Distortion, 66-69, 189, 197, 284, 347, 466-467, SNR, 403-404
484-485 stability in digital filters, 122-124
Dither, 38, 97-99, 180-181 switched-capacitor, 411-415, 420-421, 437,
DNL. See Differential nonlinearity. 440-441, 479-484
Droop, 110, 112 transconductor-C filter, 407-411, 445-446
defined, 213 tuning, 393, 404, 407, 411, 420, 456
DSP. See Digital signal processing. Finite impulse response (FIR) filter, 116
Dump and interpolate, 127-131 First-order noise shaping, 154-193
Dynamic CMFB, 382-385 FIR. See Finite impulse response.
Dynamic range, 68-69 Flicker noise. See Noise.
FM. See Frequency modulation.
Forward modulator gain, 182-186
E Fourier transform, 11, 17, 21, 51, 80-81
Frequency modulation (FM), 74
E device. See Voltage-controlled voltage sources. fT (transition frequency), 279-280
Effective number of bits (ENOB), 64, 67 Fully-differential, 191, 295-297
EKV model, 236, 248-253
Error feedback, 217-220
Excess gate voltage, 276-277 G
Expected value, 82
Gain-enhancement, 288, 290
Gain margin, 335
F Gaussian probability distribution, 82, 84-85
Glitch area, 331-332
Filters, GMIN, 20
active-RC, 395-402, 431-434, 439-440
accumulate and dump, 106-111
antialiasing, 2-7, 94, 113, 120-121, 125, 156 H
bandpass, 116, 132-135, 228, 418, 434-435,
437-442, 457, 475 Half-band digital filter, 125, 131
bilinear, 418-428 Hanning window, 14, 47-48
biquad, 429-448 Harmonics, 191
comb filter, 7-9, 116-117 square wave, 77
decimating filters, 106-126 Highpass filter, 132
digital. See Digital filter. Higher order modulators, 210-215
exact frequency response of discrete-time filter, HSPICE, 290
416-417 Hysteresis, 186
finite impulse response (FIR), 116
496 Index

Linearity requirements for averaging, 56, 95-96,

I LOCOS, 236
Lowpass filter (LPF), 3, 393-394, 479-484
I, in phase or real component, 230 active-RC, 395-404
IIR. See Infinite impulse response filter. bilinear, 418-429
Implementing data converters, see Ch. 34 biquadratic, 429-448
Implementing, MOSFET-C, 404-406
ADCs, 343-387 gm-C, 407-411
Impulse sampling, 2-18, 22 switched-capacitor, 413-417
Infinite impulse response (IIR) filter, 116 LPF. See Low pass filter.
INL. See Integral nonlinearity. LSB. See Least significant bit.
Integral nonlinearity, 311-334
Integrator
analog. See Continuouse-time analog M
integrator.
digital, 102-104, 114 MASH modulator. See Noise-shaping
discrete analog integrator (DAI), 136-139, Matching,
151, 173, 411-415, 479-484 capacitors, 368-374
gain, 182-186, 198-201 R-2R DAC, 317-318
initial conditions, 104 resistors, 245-248, 330-331
leakage, 186 Matlab, 67
Interpolation, 12, 126-131 Mean, 82
interpolating filter, 93, 127, 136 Miller integrator, 395
Interpolative modulators, 217-218 Mixed-signal system
Inverse Fourier transform, 11 block diagram, 2
Modulation noise (removing), 164-166, 212-213,
448-451
J Modulator, 136, 140-141
bandpass, 228-231
Jitter. See Clock jitter. cascaded, 221-227
first-order, RMS quantization noise, 162-164
fully-differential, 193
K gain, 207
higher order, 210-215
K, oversampling ratio or averaging factor, 56, 87,
input and output, 156
92, 97, 106-129
interpolative, 217
clock jitter, 72-74, 94
multibit, 215-221
Kickback noise, 263, 308, 353
noise-shaping, 140-141, 185
predictive, 140
second-order, 221-223
L sigma delta, 154
Ladder filter, 457 third-order, 223-225
Latch, 271-275 topology, second-order, 195
Layout, Monotonic, 57, 330-331
pipeline ADC, 385-387 MOSFET, 25
resistors, 247-248 biasing, 280-283
Leakage, binary weighted current mirrors, 249
cascaded modulators, 222 buried channel, 238
integrator, 186-188 capacitance, 239-241
Least significant bit (LSB), 27, 63, 174 EKV model, 236, 248-254
See Question 30.14 fabrication, 236-238
Limit cycle oscillations, 179-180 floating capacitor, 241
Linear phase, 5, 91 gm (transconductance), 279
Index 497

fT (transition frequency), 279-280 constructing a high-resolution ADC, 136,

long-L, 255 155-156
noise, 303-305 continuous-time, 172-173, 467-471, 476-479
ro (small-signal output resistance), 277-278 implementing DACs, 217-221
scale, 254 DAC linearity, 215
surface device, 238 data converter, see Ch. 32
switch, 256-261 decimation filters, 106-126, 156, 166
W-2W current mirror, 250 demodulator, digital first-order, 157-158
Multibit modulators, 215-221 differences between Nyquist converters, 177,
Multiplexer (MUX), 118, 128, 158, 165, 221, 360, 180
362, 376 dither, 180
Multipliers, 451-453 distortion, 189
Multiply by 2, 343-345, 452 error feedback, 217-220
Multiply by 0.5, 452 feedback DAC, 174, 215
Multistage noise shaping modulator (MASH), first introduced, 217
221-227 first-order, 154-193, 467-471
MUX. See Multiplexer. fully-differential, 192-193
fundamentals, 149-210
higher order modulators, 210-215
N input-referred noise, 190
integrator gain, 182-183
Native MOSFET capacitor, 239 integrator leakage, 186-188
Natural MOSFET capacitor, See native MOSFET interpolating filters, 126-131, 157
capacitor. interpolative modulators, 217-218
Noise leakage, 186, 222
averaging, 299, 472-475 limit cycle oscillations, 179
cascaded amplifiers, 305-306 linearizing, 201
chopper stabilization, 306, 476-478 MASH, 221-227
circuit, 298-307 modulation noise, 159-162
clock jitter, 85, 299 modulators, 140-141, 154
correlated double sampling (CDS), 306, 475 multibit modulators, 215-221
coupling, 385-388 offset, 189, 476-477
flicker (1/f ), 230, 238, 304, 472-478 op-amp gain, 186-188
MOSFET, 303-304 OTA, 476
noise equivalent bandwidth, 301-302 passive, 467-469
of a random voltage, 145 pattern noise, 179
quantization noise, See Quantization noise. ripple, 177-179
RMS calculations, 42, 44, 53, 55-56, 67, 80 second-order, 194-209
485, 491 settling time, 188-189
thermal, 238, 298, 472 slewing, 189
white, 97 SNR, 163, 166, 194, 208-211
Noise equivalent bandwidth, 301-302 stability, 183, 199-200, 213, 221
Noise floor, 24 topologies, 210-213
Noise transfer function, 141, 154, 158-159, 187, transconductor, 476
194-195, 214-215 Nonlinear dependent source, 28
Noise-shaping (NS), 140-141 Nonmonotonic, 57, 330-331
analog implementation, 172-173, 467-471 Nonoverlapping clock generation, 261-262,
averaging filters, 167-171 377-378
bandpass modulators, 228-231 Nutmeg, 13
cascaded modulators, 221-228 Nyquist
comparator gain, 182-186 differences between noise-shaping converters,
comparator offset, 186 177, 180
frequency, 3, 5, 7, 16, 51, 58, 68, 142
498 Index

rate, 59, 142 Overdrive voltage, 276

rate data converter, 177 Overflow, 119
Oversampling, 140
O Oversampling ratio. See K, oversampling ratio
or averaging factor.
Offset, 99, 149, 175, 186, 189, 198, 263, 290, 306,
314-315, 323, 378-382, 477
autozero, 342, 344 P
calibrating DAC offset, 323-325
chopper stabilization, 476-479 Pattern noise, 179-181
common-mode, 378-380 PDF, probability density function,
comparator, 352-353 average value (mean or expected value), 82
input-referred offset, 384, 479 Gaussian, 84, 98, 298
op-amp, 339-342 standard deviation, 83
random, 290 thermal noise, 298
removing using an auxiliary input port, uniform, 82
339-342 variance, 83
storage, 384 Phase-delay relationship, 6
systematic, 290 Phase-locked loop (PLL), 71
Offset binary format, 35, 104-105, 118, 147, Phase,
220-221 discrete analog integrator (DAI), 138, 151-152
One-zero transitions, 181 digital filter, 100-103
Op-amp, 284-297, 349-350 distortion, 5, 115
auxiliary input port, 339-342 excursion (peak), 75
averaging, 370-372 linear, 5, 60, 115
biasing, 280-283 margin, 293, 334-335, 347
common-mode voltage variation, 350 noise, 78, 85-86
compensation, 290-294 response, 6-9, 22, 90-91, 114, 115, 334, 396,
data converters, 334-337 399-402, 409, 418, 425-426, 434
differential outputs, 295-296, 345-350 shift, 55, 80-81, 156, 480
floating current source, 286-287 Picket-fence effect, 44-45, 47
frequency response, 335 Pipeline,
gain, 186, 290-295, 337-338 ADC, 24, 32-35, 67, 312, 343, 359-361, 368,
gain-enhancement, 288, 290 374-376
gain margin, 335 adder, 274-275
input-referred noise, 190-191, 473-478 DAC, 392
minimum open-loop gain, 337-338 Layout, 385-386
modeling, 151-152, 192 PLL. See Phase-locked loop.
noise, 306-307 Power
offset, 189, 290, 307, 476 average, 80-81, 300
output swing, 284, 357-359 Power spectral density (PSD), 62, 80, 85, 161-162,
phase margin, 335 486, 490
push-pull out, 284 jitter, 85
S/H, 343-350 See also Spectral density.
settling time, 188-189, 287-295 quantization noise, 91-92
slew-rate, 188-189, 287-290 WinSPICE, 160-162
simulating, 292-293 Power supply sensitivity, 476
stability, 286, 290-295 Predictive coder. See Predictive modulator.
unity gain frequency, 339 Predictive modulator, 140
Operational transconductance amplifier (OTA), Probability density function, See PDF.
25, 476-478 PSD. See Power spectral density.
OTA. See Operational transconductance amplifier. Push-pull amp, 284-286, 459-467
Output swing, 357-359
Index 499

matching of the capacitors used, 349, 368-374

Q single-ended to differential, 345-350
SPICE model, 19
Q (pole quality factor), 429-434 subtraction, 354-359
high Q, 438-443 Sample frequency reduction. See Decimation.
peaking and instability, 443-445 Sampler, 2
Quadrature or imaginary component, 230 Sampling and Aliasing, 2-26
Quantization noise, 32, 35-57, 485-492 coherent. See coherent sampling.
as a random variable, 42 Sampling gate, 2
calculating from a spectrum, 50 Scale option, 254
defined, 35 Second-order noise-shaping, 194
estimating, 220 Segmentation, 321-322
power, 62 Settling time, 188, 291-295, 319, 329, 334-335,
reducing quantization noise, 54 339
spectral density, 52-57 SFDR. See Spurious-free-dynamic range.
viewing the spectrum, 37-52 SFFM. See Single frequency frequency modulation.
Quantize, 18 S/H. See Sample and hold.
Quantizer, 158, See also Analog-to-Digital Shallow trench isolation (STI), 236-238
converter. Side lobes, 109-110
Sigma delta modulation, 140, 154. See also
Noise-shaping
R Signal-to-noise and distortion ratio(SINAD). See
Signal-to-noise plus distortion ratio (SNDR).
R-2R, 245-248, 312-331
Signal-to-noise plus distortion ratio (SNDR), 64,
topologies for DACs, 312-332
66-67, 69
Random offset, 290
Signal-to-noise ratio (SNR), 63, 69
Random signals
data converter, see Ch. 31
quantization noise, 42
first-order modulator, 163
spectral density, 82-86
higher-order modulators, 211
standard deviation, 83
ideal, 63-64, 208-209
variance, 83
improving using averaging, 87-136
RCF. See Reconstruction filter.
improving using feedback, 136-141
Reconstruction filter (RCF), 3-4, 9-12, 24,
measured, 64
125-126, 130-131, 135, 157, 220
second-order modulator, 194
RELTOL, 20, 24-25
selecting input sinewave, 65
Resolution, 87
specifying, 69
loss because of jitter, 71-74
spectral leakage, 65-66
Resistor,
Signal transfer function (STF), 141, 154, 195
layout, 247-248
Silicide, 236-238, 245-246
properties, 245
Simulation program with integrated circuit
Resolution bandwidth, 486, 490
emphasis. See SPICE.
Return-to-zero (RZ), 20-22
Sinc filter, 108-110, 112 See digital averaging
ro (small-signal output resistance), 277-278
filter.
Ripple, 177-180
SPICE implementation, 169-171
RMS quantization noise voltage, 42, 50, 53, 55-56,
Sinc function defined, 11
87-88, 92
magnitude response, 22
calculating from a spectrum, 43, 88, 91-92
Sinc waveform, 46-48
Root mean square (RMS) voltage, 80
Single-ended to differenial S/H, 345-350
RZ. See Return-to-zero.
Single-frequency frequency modulation (SFFM), 74
Single-ended to differential conversion, 345-350
Slew-rate, 189, 287-290
S SOP, small outline package, 489
Sample and hold (S/H), 19-26, 39, 343-350 Smoothing filter, 3 See reconstruction filter.
500 Index

SNR. See Signal-to-noise ratio. noise-shaping modulator, 183, 199-200, 213,

SNDR. See Signal-to-noise plus distortion ratio. 221
Spectral analysis using SPICE (the spec op-amp, 286, 290-295
command), 13-16 Standard deviation, 83-84, 298
Spectral density, 79-86 STI, See shallow trench isolation.
power spectral density (PSD), 80, 85 Submicron CMOS circuit design, see Ch. 33
quantization noise, 52-57, 88 Subtraction, 119, 354
random signals, 82-86 Switched-capacitor filters, 411-415, 420-421, 437,
voltage spectral density, 80 440-441
Spectral leakage, 45-46, 65-66 Switches, 150
SPICE, 1, 13-15 capacitive feedthrough, 340-341
ABSTOL, 20, 24-25 charge injection, 340-341
AC analysis, 8-10 MOSFET, 256-260, 319
ADCs and DACs, 26-35 Systematic offset, 290
B device, 28
behavioral models, 149-153
comparator modeling, 153 T
DAI modeling, 151-153, 192-193
digital filter, 447-451 THD, See total harmonic distortion.
E device, 13 Thermal noise. See noise.
EKV model, 236, 248-253 Thermometer code, 361
HSPICE, 290 Thermometer decoder, 322
impulse sampler, 13-14 Time domain description of reconstruction, 9-13
jitter model, 74-79 Time-interleaved operation of an ADC, 359-360
level 1 model, 235-236 Total harmonic distortion, 466
linearize before a spectral analysis, 14 TPSC, See true single-phase clocking.
modeling approach, 28 Transconductor-C filters, 407-411
models for ADCs and DACs, 26-35 bilinear, 419-420
nonoverlapping clocks, 150 biquad, 445-446
nutmeg, 13 Triangular response, 168
op-amp (ideal), 13, 151, 192 True single-phase clocking, 272-273
op-amp (MOSFET), 290-293 Tuning, 325, 393, 400, 404-411, 415, 419-420
pulse statement, 13, 19, 29 orthogonal tuning, 325, 420, 457
RELTOL, 20, 24-25 Two’s complement, 105, 117-119, 220, 231,
sample-and-hold (S/H) model, 19 451-453
scale, 254 subtraction, 119
S/H spectral response, 20
Sinc filter, 169-171
sinewave, 152-153 U
spectral analysis (spec command), 13-16
Understanding output swing, 357
step sizes, 15, 78
Unit step function. See u(t).
subcircuit netlist, 30, 34
u(t), 17-18, 21
switch, 13, 150
.tran statement, 15
VNTOL, 20, 24-25
Spike, 69, 77-78
V
Spur, 69 Variance, 83, 299
Spurious free dynamic range (SFDR), 64, 68, 180 VCM , 32, 136 (VDD/2 or 0.75 V in this book)
Square wave, 77 VDD, 59 (1.5 V in this book)
Stability, VSA (Vector Signal Analyzer), 463-464
digital filter, 123 VNTOL, 20, 24-25
filter, 442-445 Voltage coefficient, 245-246, 333
Voltage-controlled voltage source, 13, 204, 401
Index 501

Voltage spectral density, 62, 80, 475, 485-486

Von Hann window. See Hanning window.
VSP , Inverter switching point, 266, 296-297
VSS, 60 (ground or 0 V in this book)

W
W-2W current steering DAC (mirror), 250-251,
333-334
White noise, 97, 303, 485
Windowing, 13-14, 46-48
WinSPICE, See also SPICE.
loading external data to perform a DFT, 67
Wireless, 230
I/Q extraction, 230-231

Z
z
defined, 17
domain, 16-17, 141
to s-transform (practical), 424, 480
z-plane, 99-102
Zeroes padding, 131
 About the Author

Russel Jacob (Jake) Baker (S'83 - M'88 - SM'97) was born in

Ogden, Utah, on October 5, 1964. He received the B.S. and
M.S. degrees in electrical engineering from the University of
Nevada, Las Vegas, and the Ph.D. degree in electrical
engineering from the University of Nevada, Reno.

From 1981 to 1987, he was in the United States Marine Corps

Reserves. From 1985 to 1993, he worked for E. G. & G. Energy
Measurements and the Lawrence Livermore National
Laboratory designing nuclear diagnostic instrumentation for
underground nuclear weapons tests at the Nevada test site.
During this time he designed over 30 electronic and
electro-optic instruments including high-speed (750 Mb/s) fiber-optic receiver/
transmitters, PLLs, frame- and bit-syncs, data converters, streak-camera sweep circuits,
micro-channel plate gating circuits, and analog oscilloscope electronics. From 1993 to
2000, he was a faculty member in the Department of Electrical Engineering at the
University of Idaho. In 2000, he joined a new electrical engineering program at the
Boise State University. Also, since 1993, he has consulted for various companies and
laboratories including the Lawrence Berkeley Laboratory, Micron Display, Amkor
Wafer Fabrication Services, Tower Semiconductor, Rendition, and the Tower ASIC
Design Center. Since 1994, he has also held a position at Micron Technology, Inc., as
a senior design engineer.

Dr. Baker holds over 20 granted or pending patents in integrated circuit design and is a
member of the electrical engineering honor society Eta Kappa Nu. He is a co-author of
CMOS: Circuit Design, Layout, and Simulation, Wiley-IEEE, 1998, and DRAM
Circuit Design: A Tutorial, Wiley-IEEE, 2001. His research interests are in the areas of
CMOS mixed-signal integrated circuit design and the design of memory in new and
emerging fabrication technologies. Dr. Baker was a corecipient of the 2000 Prize Paper
Award of the IEEE Power Electronics Society.

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