Modern System-on-Chip

Design on Arm

TEXTBOOK
David J. Greaves

SoC Design
Modern System-on-Chip
Design on Arm

DAVID J. GREAVES
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Contents

Preface xvii
A
cknowledgments xix
A
uthorBiograph
y xxi
ListofFigures xxiii
ListofT
ables xxxvii

1. IntroductiontoSystem-on-Chip
1.1 WhatisaSystem-on-Chip? 2
1.1.1 HistoricalRe
view 2
1.1.2 SimpleMicroprocessorNet-le
velConnections 4
1.1.3 F
ullNetlistandMemoryMapforaMicrocomputer 5
1.1.4 SeparateReadandW
riteDataBusses 7
1.2 Microcontrollers 8
1.3 LaterChapters 10
1.4 SoCDesignFlows 11
1.4.1 F
unctionalModel 11
1.4.2 ArchitecturalP
artition 14
1.4.3 ArchitecturalP
artitionandCo-design 15
1.4.4 IPBlocks 16
1.4.5 Synthesis 17
1.4.6 Simulation 17
1.4.7 Back-endFlow 18
1.4.8 Example:ACellPhone 20
1.4.9 SoCExample:Helium210 21
1.5 SoCT
echnology 24
1.6 Summary 26
1.6.1 Ex
ercises 26
C
ontents

2. Processors,MemoryandIPBlocks
2.1 ProcessorCores 28
2.1.1 ISAs 30
2.1.2 V
ectorInstructions 31
2.1.3 CustomInstructions 32
2.1.4 TheClassicFiv
e -stagePipeline 32
2.2 Super-scalarProcessors 33
2.2.1 VirtualMemoryManagementUnits:MMUandIOMMU 36
2.3 Multi-coreP
rocessing 37
2.3.1 SimultaneousM
ultithreading 39
2.4 CacheDesign 39
2.4.1 SnoopingandOtherCohe
rencyProtocols 43
2.5 InterruptsandtheInterruptController 46
2.5.1 InterruptStructureW
ithinaD
evice 47
2.6 MemoryT
echnology 48
2.6.1 L
o gicalandPh
ysicalLa
youts 49
2.6.2 Mask-programmedR
O M 51
2.6.3 StaticRandomAccessMe
m ory 52
2.6.4 SynchronousStaticRAM 53
2.6.5 Dual-portedStaticRAM 54
2.6.6 DynamicRAM 54
2.6.7 ElectricallyAlterableR
O Ms 59
2.6.8 Floating-gateEA-R
O MsandFlash 61
2.6.9 EmergingMemoryT
echnologies 62
2.6.10 ProcessorSpeedv
e rsusMemorySpeed 63
2.7 SoCI/OBlocks 64
2.7.1 Univ
e rsalAsynchronousReceiv
e r-T
ransm
itter(U
ART) 65
2.7.2 P
arallelP
ortsUsingGeneral-purposeI/O 68
2.7.3 General-purposeInput/OutputPins 69
2.7.4 Counter/TimerBlocks 70

vi
 Contents

2
.7.5 DMAControllers 72
2
.7.6 NetworkandStreamingM
ediaD
evices 73
2
.7.7 VideoControllersandF
rameStores 75
2
.7.8 DoorbellandM
ailbo
xBlocks 76
2
.7.9 P
erformanceM
anagementUnits 76
2.8 Summary 77
2.8.1 Ex
ercises 77

3. SoCInterconnect
3.1 InterconnectRequirements 82
3.1.1 ProtocolAdaptors 85
3.1.2 On-chipProtocolClasses 89
3.1.3 SimpleBusStructures 89
3.1.4 OrderedandU
nord
eredInterconnects 95
3.1.5 AMBAAXIInterconnect 97
3.1.6 Directory-basedCoherence 99
3.1.7 F
urtherBusOperations 101
3.2 BasicInterconnectT
opologies 105
3.2.1 SimpleBuswithOneInitia
tor 106
3.2.2 SharedBuswithMultipleInitiators 106
3.2.3 BridgedBusStructures 107
3.3 SimpleP
ack
et-SwitchedInterconnect 110
3.3.1 Multi-accessSoCandInter-chipInterconnect 111
3.3.2 Multi-accessF
oldedBus 112
3.4 Network-on-Chip 113
3.4.1 NoCRoutingandSwitchin
g 115
3.4.2 VirtualChannels 118
3.4.3 NoCDeadlocks 118
3.4.4 Credit-basedFlowControl 122
3.4.5 AMBA5CHI 124

vii
C
ontents

3.5 AdvancedInterconnectT
opologies 126
3.5.1 T
raffi
cFlowMatrix 127
3.6 InterconnectBuild
ingBlocks 133
3.7 L
o ng-distanceInterconnects 136
3.7.1 DomainCrossing 136
3.7.2 MetastabilityTheory 137
3.7.3 CD-crossingBridge 138
3.7.4 HarmonicClocks 139
3.7.5 PDCrossing 141
3.8 SerialiserandDeserialiser:SERDES 142
3.8.1 PCIeandSAT
A 144
3.8.2 CCIX,CXLandNVLink 144
3.9 AutomaticT
opologySynthesis 145
3.9.1 DomainAssignment 145
3.9.2 FIFOBufferSizing 146
3.9.3 LinkSizing 147
3.10 Summary 147
3.10.1 Ex
ercises 148

4. SystemDesignConsiderations
4.1 DesignObjectiv
esandMetrics 154
4.2 P
arallelSpeedupT
heory 156
4.2.1 ContentionandArbitration 157
4.3 FIFOQueuingTheoryandQoS 159
4.3.1 ClassicalSingle-serv
e randOpenQueueModels 160
4.3.2 ExpeditedServiceQueuing 163
4.3.3 StatisticalMultiple
xingGain 164
4.3.4 QoSP
olicing 166
4.4 DesignT
rade-offs 168
4.4.1 ThermalDesign 169
4.4.2 F
olding,Re-timingandRe
coding 171

viii
 Contents

4.5 DesignT
rade-offsinMemorySystems 175
4.6 SoCEnergyMinimisation 182
4.6.1 P
ower,ResistanceandCa
p acitance 182
4.6.2 DynamicEnergyandD
ynamicP
ower 183
4.6.3 StaticP
owerUse 185
4.6.4 W
iringandCapacitanceModelling 186
4.6.5 LandauerLimitandRe
versib
leComputation 188
4.6.6 GateDela
yasaF
unctionofSupplyV
oltage 190
4.6.7 SPICESimulationofanIn
vertor 191
4.6.8 DynamicV
oltageandF
requencyScaling 191
4.6.9 DynamicClockGating 194
4.6.10 DynamicSupplyGating 196
4.6.11 F
utureT
rendsforEnergyUse 199
4.7 DesigningforT
estabilityandDebugIntegration 200
4.7.1 ApplicationDebugging 200
4.7.2 Multi-coreDebugIntegration 202
4.7.3 DebugNa
vigationandJT
A G 204
4.7.4 AdditionalD
APFacilities 205
4.7.5 BoundaryandG
eneralP
athScans 206
4.7.6 BISTforSRAMMemories(MBIST) 207
4.8 ReliabilityandSecurity 208
4.8.1 Ph
y sicalFaults,P
e rform anceD e gradatio n,E rrorDetectionand
Correction,andP re-a ndPo st-siliconM itigationTechniques 208
4.9 Hard
w are-b
asedSecurity 209
4.9.1 T
rustedPlatformandComputerModules 210
4.9.2 T
rustedEx
ecutionMode 211
4.9.3 Capability-basedProtection 211
4.9.4 ClockSources 211
4.9.5 PLLandClockT
rees 212
4.9.6 ClockSk
ewingandMulti-cy
cleP
aths 213
4.10 Summary 216
4.10.1 Ex
ercises 216

ix
C
ontents

5. ElectronicSystem-L
evelModelling
5.1 ModellingAbstractions 220
5.1.1 ESLFlowDiagram 223
5.2 InterconnectModelling 225
5.2.1 StochasticInterconnectModelling 226
5.2.2 Cy
cle-accurateInterconnectModelling 226
5.3 SystemCModellingLib
rary 227
5.3.1 SystemCStructuralNetlist 229
5.3.2 SystemCThreadsandMe
thods 230
5.3.3 SystemCPlottinganditsGUI 232
5.3.4 T
owardsG
reaterModellingEffi
ciency 233
5.4 T
ransaction-le
velModelling 234
5.4.1 OSCITLM1.0Standard 235
5.4.2 OSCITLM2.0Standard 237
5.4.3 TLMModelswithTim
ing(TL
M +T) 241
5.4.4 TLMwithL
o oselyTimedModelling 241
5.4.5 ModellingContentionUn
d erL
o oselyTimedTLM 244
5.4.6 Non-blockingT
LMcoding 245
5.4.7 T
ypicalISSSetupwithL
o o
seTim
ingandT
emporalDecoupling 246
5.4.8 TLMT
ransactorsforBridgingModellingStyles 246
5.4.9 ESLModeloftheL
o calL
inkProtocol 248
5.5 ProcessorModellingwithDifferentL
evelsofAbstraction 248
5.5.1 F
ormsofISSandTheirV
ariants 249
5.5.2 UsingtheCPreprocessortoAd
aptFirm
ware 251
5.5.3 ESLCacheModellingandDMI 253
5.6 ESLModellingofP
ower,P
erformanceandArea 254
5.6.1 EstimatingtheOperatingF
requencyandP
owerwithR
TL 254
5.6.2 T
ypicalMacroscopicP
erform
anceEq
uations:SRAMExample 257
5.6.3 T
ypicalMacroscopicP
erform
anceEq
uations:D
RAMExample 259
5.6.4 MacroscopicPhaseandM
odeP
owerEstim
ationF
orm
ula 262

x
 Contents

5
.6.5 Spreadsheet-basedEne
rgyAccounting 263
5
.6.6 Rent’sRuleforE
stimatingW
ireL
ength 263
5
.6.7 DynamicEnergyModellinginTLM 266
5.6.8 ESLModellingofD
VFSandP
owerGating 267
5.7 CaseStudy:ModellingtheZ
ynqPlatform(Prazor) 268
5.8 Summary 268
5.8.1 Ex
ercises 268

6. ArchitecturalDesignExploration
6.1 Hard
w areandSoftwareDesignP
artition 273
6.1.1 DesignP
artitioningExample:ABluetoothModule 274
6.2 DesignSpaceExploration 276
6.2.1 DSEW
orkfl
ows 280
6.2.2 CF
unctionalModels 282
6.2.3 F
unctionalModelRefactoringtoESL 284
6.2.4 MicroarchitectureofaSubsystem 285
6.2.5 InterconnectOptimisation 287
6.3 Hazards 289
6.3.1 HazardsF
romArra
yMemories 291
6.3.2 Ov
e rcomingStructuralH
azardsusingHoldingRegisters 291
6.3.3 NameAliasHazards 293
6.3.4 FIFOBuffersandDual-portIPBlocks 293
6.4 CustomAccelerators 297
6.4.1 AcceleratorComm
unication 298
6.4.2 MultipleSub-tasks 301
6.4.3 CustomAcceleratorExampleI 301
6.4.4 FPGAAccelerationintheC
loud 303
6.5 SuperFPGAs 305
6.6 AsymptoticAnalysis 307
6.6.1 Illustration1
:HierarchicalCache 308
6.6.2 Illustration2
:big.LITTL
E 309

xi
C
ontents

6
.6.3 Illustration3
:NoCT
opologyT
rade-off 311
6.6.4 Illustration4
:StaticandDynamicP
owerT
rade-off 314
6.7 VirtualPlatformExamples 315
6.7.1 ThePrazor/Z
ynqVirtualP
latform 315
6.7.2 Co-designW
ork
edExample:MPEGVideoCompression 317
6.8 Design-entryLanguages 320
6.8.1 F
unctionalUnits 323
6.8.2 AccelleraIP-XACT 326
6.8.3 HardwareConstructionL
anguages 331
6.8.4 Handel-C 334
6.8.5 BluespecSystemV
erilog 335
6.9 High-le
velSynthesis 339
6.9.1 Disco
veringP
arallelismandSharedV
ariablesinIterations 347
6.10 Summary 356
6.10.1 Ex
ercises 357

7. F
ormalMethodsandA
ssertion-basedDesign
7.1 F
ormalLanguagesandT
ools 365
7.1.1 V
erifi
cationCo
verage 367
7.1.2 PropertyCompleteness 369
7.1.3 W
henIsaF
ormalSpecifi
cationComplete? 369
7.2 Assertions 370
7.2.1 PredicateandPropertyF
orm
s 373
7.2.2 Assertion-basedDesign 374
7.2.3 RegressionT
esting 375
7.3 SimulationwithAssertions 375
7.3.1 SimulationsandD
ynamicV
alid
ation 376
7.3.2 AutomatedS timu lusGeneration:DirectedandConstrained
Random Verifi
cation 376
7.3.3 Simulationv
e rsusF
orm
alChecking 378

xii
 Contents

7.4 PropertySpecifi
cationLanguage 380
7.4.1 PSLF
our-le
velSyntaxStructure 382
7.4.2 ExtendedRegularExpressionsandSERES 383
7.4.3 SystemV
erilogAssertion
s 384
7.5 F
ormalInterfaceProtocolCheck
ers 385
7.6 EquivalenceChecking 389
7.6.1 BooleanEquivalenceChe
cking 389
7.6.2 SequentialEquivalenceC
hecking 390
7.6.3 X
-propagationChecking 392
7.6.4 ModelCheckingtheItemsinaDataP
ath 396
7.7 ConnectivityChecking 398
7.8 CheckingtheSecurityP
olicy 399
7.9 Summary 399
7.9.1 Ex
ercises 401

8. FabricationandProduction
8.1 Ev
o lutionofDesignClosure 405
8.1.1 Ph
ysicallyAwareDesignFlows 407
8.2 VLSIGeometry 410
8.2.1 VLSIEv
o lution 412
8.2.2 T
ypicalandF
utureV
alues 415
8.3 RegisterT
ransferLanguages 418
8.3.1 R
TLStructuralElaboration 420
8.3.2 UnsynthesisableR
TL 427
8.3.3 R
TLSimulationAlgorithms 429
8.3.4 Ev
e nt-driv
enSimulation 431
8.3.5 InertialandT
ransportDela
ys 431
8.3.6 Compute/CommitModellingandtheDeltaCy
cle 432
8.3.7 Mix
edAnalogueandD
igitalSimulation 433

xiii
C
ontents

8
.3.8 L
o gicSynthesis 439
8
.3.9 Arra
ysandRAMInferenceinR
TL 442
8.3.10 MemoryMacrocellCompiler 443
8.3.11 Con
ventionalR
TLComparedwithSoftware 444
8.3.12 SynthesisIntentandGoals 445
8.4 ChipT
ypesandClassifi
cations 448
8.4.1 Semi-custom(Cell-based)Design 452
8.4.2 StandardCellData 454
8.4.3 SPICECharacterisation 455
8.4.4 PVTV
ariations 456
8.4.5 Electromigration 456
8.4.6 W
av
eform-basedCellCharacterisation 458
8.4.7 NoiseCharacterisation 460
8.5 GateArra
ys 461
8.5.1 P
ass-transistorMultiple
xers 462
8.5.2 Field-programmableGa
teArra
ys 464
8.5.3 StructuredASIC 467
8.5.4 FPGASoCEmulators 467
8.6 FloorandP
owerP
lanning 468
8.6.1 P
owerPlanning 468
8.7 FlowSteps 470
8.7.1 Placement 470
8.7.2 ClockT
reeInsertion 473
8.7.3 Routing 473
8.7.4 TimingandP
owerV
erifi
cation 474
8.7.5 P
ost-routeOptimisation 475
8.7.6 La
youtv
e rsusSchematicCheck 475
8.7.7 Sign-offandT
apeout 475

xiv
 Contents

8.8 ProductionT
esting 476
8.8.1 Univ
e rsalVerifi
cationM
ethodologyandOpenV
erifi
cation
Metho dology 477
8.8.2 T
estProgramGeneration 478
8.8.3 W
aferProbeT
esting 480
8.8.4 P
ackagedDe
viceT
esting 482
8.9 De
viceP
ackagingandMCMs 483
8.9.1 MCMsandDie-stacking 484
8.10 EngineeringChangeOrd
ers 485
8.11 ASICCosts:RecurringandN
on-recurringExpenses 487
8.11.1 ChipCostv
e rsusArea 487
8.12 StaticTimingAnalysisandTimingSign-off 488
8.12.1 ST
ATypes:MaximumandMinimum 489
8.12.2 MaximumTimingAnalysis 489
8.12.3 MinimumTimingAnalysis 491
8.12.4 ProcessCorners 492
8.12.5 EarlyandLateArrivals 494
8.12.6 TimingModels:Lib
erty 496
8.12.7 Multi-modeM
ulti-cornerAnalysis 499
8.12.8 SignalIntegrity 500
8.12.9 CouplingCapacitance 500
8.12.10NoiseAnalysis 501
8.12.11T
ransitionTimeL
imits 501
8.12.12On-chipV
ariation 502
8.12.13NetDela
yVariation 504
8.12.14V
oltageV
ariation 505
8.12.15AdvancedT
opicsinST
A 505
8.12.16TimingClosure 506
8.13 Summary 507
8.13.1 Ex
ercises 508

xv
C
ontents

9. PuttingEv
erythingT
ogether
9.1 Firm
ware 512
9.1.1 SecureBootstrapping 513
9.2 P
oweringup 514
9.2.1 EngineeringSampleT
esting 514
9.3 SuccessorFailure? 517

GlossaryofAbbre
viation
s 521

Inde
x 551

xvi
Preface

Silico nte ch no lo gyh asse enre lentle ssa dv an ce sinth ep ast5 0y ears,d riv enb yco n sta ntin nov ation
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po w e ra n de n erg yb ud g e ts.T h eaim o fthiste xtb oo kistoe x po sea sp irin ga n dp ractisin gS oC
de sig n erstoth efu n da m e ntalsa ndla testd eve lo p m en tsinS oCd e sig na n dte ch no lo g ies.T he
pro ce sso rsw ith inaS o Cru nah ugeb o d yo fso ftw a re.M ucho fth isco d eisp o rta bleo ve rm a ny
pla tfo rm s,b utlo w -leve lco m po n en ts,su cha sd e viced rivers,a reh a rd w are -d ep en d e n ta ndm ayb e
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lformaltricksare
covered .

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ow sformakin gtheph
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tem pe ratu
rea ndun wantedradioe mission s).

xviii
Acknowledgements

Ia m ve ryg ratefu ltoP ro fe sso rS irA n dyH o ppe r,w h ow asm yP hD su pe rv iso r,w h oh asb ee na
co n sta n tso urceo finsp ira tiona n dd ire ction,a ndw h oh aso fte nb ee nm yb o ssb othinin du strya ndat
th eC o m p uterL a bo rato ry .H ein trod u cedm etoth efi e ldo fch ipd esign .Ia m a lsov eryg rate fultoth e
lateM .G .Scro gg ie,th ep rin cip ala uth o ro f‘Fou n dation so fW ireless’,w h ichw a sab ookIre ada nd
re -re ada llthro u ghm ych ildh o od .Ica no nlyh op eso m ep eo p lefin dth iscu rre n tb ooka sva lu ab leasI
fou n dh is.C erta inlyIh av etrie dtom ixb re adtha ndd ep thinth esa m ea cce ssib lew a
yth ath e
m a n ag ed .Iw o uldlik etoth ankth osew o rkinginth eC o mp u te rL abo rato ryw hoh elpedw ithth isbo ok,
inclu din gD a
v idC hisn all,R o be rtM ullins,O me rS ellaa n dM ilo sP uzo vic.Iw ou lda lsolik
etoth a nkm y
w ife ,A ld yth,forp uttin gu pw ithm efo rth islasty ea r.I’veo fte nre a dsu chco m m en tsinthe
ack now le dge m e ntse ctio n so fo th erb oo ks,bu tn ow Iu n dersta ndw h atca u se sit.

Mostim portantly
,I’dlik
etothan kthem anyA rmsta ffwh oha v
eh elpedwiththisb ook,eitherb
y
contrib
utingtexttola rgechunksofit,orwithadditionalinformationandsugge stions:

KhaledBenkrid,whomadethisbookpossib
le.

L
izW
arman,whok
eptmeontrackandassistedm
ewiththeprocess.

ShuojinHangandF
ranciscaT
anwhohelpedcreatethescopeandre
viewedearlydrafts.

Thisbookwouldn othavebeenpossiblewithoutthecollaborationofthefollowingArmengineers
wh oha
veco-w ritten,re
vie
w edandco m me ntedontheb ook:

Chapter2 :Processors,MemoryandIPBlocks
R
ahu lM athur,StaffEngin
eer

Chapter3:S oCIn te rconn e

cts
AnupG angw ar,DistinguishedE ngineer
AntonyHa rris,Sen iorPrincipalAM BAA rchitect

Chapter6:Arch itecturalD esignExploration

Ed
w inD ank
e rt,D irector,T
ech nologyM an agement

Chapter7:Fo rmalM eth odsandA ssertion-BasedDesign

DarylStewart,DistinguishedEngineer

C hap ter8 :F ab ricationa ndP roduction

Jim D od rill,F ello w
C hristo p h eL op ez,Se niorPrincipalEngineer
A ure lienM e ro ur,PrincipalE ngineer
Jea n-L ucP elloie ,Fellow
AuthorBiograph
y

D r.D av idJ.G re ave s,Ph D CEn g.isS eniorL ecture rinC o m pu tin gS cie ncea t
th eU n ive rsityo fC am b ridge,U Ka ndaF ello w ofC o rpu sC h ristiC o lleg e.
Bo rninL o n d on,h eg rew upinah ousefu llo fen gine erin gtex tb o oks,circu it
dia gra m sa n dp ieceso fte leco m m unication se quip m en t.H isg ra n dfa th erh a d
bu ilth iso w nte levisionse tasso o naste lev isionb ro ad castssta rted .H is
fath e rw o rke da tE M Ian dIB M ,deve lopingm ode m sa n dco m p u ter
inte rfa ce s.W ithth esh ifto fhe ado fficeo fIB M U KtoP ortsm ou th,th efa m ily
m o ve dtoR om se yinH a m p shire.

P lesseyR okeM ano rw asa lsositu atedinR o mse y,a longw ithIBM ’sU Kre se archla b
o rato riesa t
H ursleyP ark .Thesew ere,a n dre m ain ,wo rld
-lea din gre se archcen tre sinth efi eldo fradio
co m mun icationsan dco m p u ting.T hey oungD a
v idJ.G re av eswasare gularv isitora ndin te rna tbo th
site s,andb yth ea geo f1 7h a dde signe da ndb uilth isfirstco mputer.T hech ipsh adb eenm o stly
re m o v
e dfro m oldcircuitb o a rdsu singab lo wlam p .T heso ftware,in cludingth ed isko pera tin gsystem
an daP asca lcom piler,hada llbee nw rittenfrom scra tch .

Duringh isA
-le
velstu dies,Greave sdesignedalocalareanetworkforC om mo d oreP ETcomputers.
Thede signwaspublish edinW irelessW orldmagazinea ndcomm erciallyreplicated.

A sa nu nd ergradu atea tS tJo hn’sC o lleg eC ambridge,h eo ffere dco n su lta ncyse rv icestov arioussm all
ele ctro nicsco m pa n iesinth efie ldofp ro fessionala udio,d ev elopingM ID Iinterface sa ndlo w-noise
pre -a m plifi
ers.H isfi n al-ye ard egreep ro jectw asafu llyd igita lk
e ybo a rdin strum en ttha tw as
seria lisedinW ire lessW orlda ndco p iedb ym anye nth usiastsw orldw ide .Am ainin terestb ecam ethe
de sig na n dim plem e nta tiono fco m pile rs,ase nco uragedb yD r.M artinR ich ardso fS tJoh ns,whoh ad
de v elo pedth eB C PLla n guag e,th edire ctp recursoro fC .

G rea v esd esig nedhisfi rstsiliconch ip sd u ringh isP hD stud ies,w hichw e reinth efieldofm e tropolitan
are an etw ork s.Hed e sign edfi breo p tictra nsce iv erstha tse ntth efirstm ono -m o d esignalso v erthe
ne w lyin stalledfibresth atcriss-cro sse dC a mb rid ge.Inco llab orationw ithA co rnC om pute r,in1 99 5
G rea v esw a sth echiefn etw o rka rchite ctfo rth eC am bridg eIT Vtria l,w hichp u tA T M switch e sinth e
k
e rb sideca b inetsbelo n gingtoC am b ridgeC ab leL tda ndd eliveredv id
e oo nd em andto5 0o rso
ho m e s.Itw a s2 0ye arsla terth atthela stm oviere n talsh opinC am b ridg eclo sed .

Alsoin1 9 95 ,heim pleme ntedC SY N,oneo fth efi

rstV erilogcom pilersfo rsynthesisinghardw are
specifi
ca llyfo rfi
eldp rogramm ablegatea rray s.Thiscom pilerwasd istributedw idelyam onglocal
com pan ie so ntheC a mbridgeS cienceP arka n dalsou sedfo runderg rad uateteaching.Itwaslicensed
toam ultin ationaltob undlew ithitsownfa m ilyofFP GA s.

Grea
ve sh adv isitedArmwh enitfi
rstspunoutofA cornandconsistedofsixe ngineersinabarn .At
theuniversity
,G reav
esusedad onationofArmcircuitboard
sforan ewp racticalcourseinwh ichthe
AuthorBiography

stud entswroteassemblyla
n g uageandV erilogtolea rnaboutlo
w -lev
elh ardwareandsoftware
interfacin
g.Thesecoursesstillruntoda
ya n dth electurenoteshav eevolv
e din
tothiste
xtbook.

Grea ve shasb ee no ntheb o ardo rtech nicala dvisoryb oardofa tle astte nstart-upco m p anies. Heh as
superv isedore xa m inedm o retha n6 0P hD stude nts. Heholdsa tlea stfiveinternation alp ate ntsinthe
fi
eldo fco m mu nicationsa ndele ctron ics.H isco m pan yTenisonE DAw as,beforeacq uisition ,directly
provid in gtoolstoa llm ajorch ipm ake rs. Hiscu rren tresearchin tere stsrem aininth efie ldo f
com pila tiontoolsfo rdesigna utom atio na n dscie n
tificacceleration.

xxii
Modern System-on-Chip
Design on Arm
SoC design has seen significant advances in the decade and Arm-based silicon has often been at
the heart of this revolution. Today, entire systems including processors, memories, sensors and
analogue circuitry are all integrated into one single chip (hence “System-on-Chip” or SoC). The aim
of this textbook is to expose aspiring and practising SoC designers to the fundamentals and latest
developments in SoC design and technologies using examples of Arm® Cortex®-A technology and
related IP blocks and interfaces. The entire SoC design process is discussed in detail, from memory
and interconnects through to validation, fabrication and production. A particular highlight of this
textbook is the focus on energy efficient SoC design, and the extensive supplementary materials
which include a SystemC model of a Zynq chip.
This textbook is aimed at final year undergraduate students, master students or engineers in the field
looking to update their knowledge. It is assumed that readers will have a pre-existing understanding
of RTL, Assembly Language and Operating Systems. For those readers looking for a entry-level
introduction to SoC design, we recommend our Fundamentals of System-on-Chip Design on Arm
Cortex-M Microcontrollers textbook.

Table of contents Dr. David J. Greaves, PhD CEng. is a

Senior Lecturer in Computing Science at
1 Introduction to System-on-Chip the University of Cambridge, UK and a
2 Processors, Memory and IP Blocks Fellow of Corpus Christi College.

3 SoC Interconnect In 1995, Dr Greaves implemented

CSYN, one of the first Verilog compilers
4 System Design Considerations for synthesising hardware specifically
5 Electronic System-level Modelling for field programmable gate arrays. This
compiler was distributed widely among local companies
6 Architectural Design Exploration on the Cambridge Science Park and also used for
7 Formal Methods and Assertion- undergraduate teaching. It was licensed to a multinational
based Design to bundle with its own family of FPGAs.
8 Fabrication and Production Dr Greaves holds at least five international patents in
the field of communications and electronics. His current
9 Putting Everything Together research interests remain in the field of compilation tools
for design automation and scientific acceleration.

Arm Education Media is a publishing operation within Arm Ltd, providing a range of educational materials
for aspiring and practicing engineers. For more information, visit: arm.com/resources/education