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Synchronous Counter

The document describes an experiment to design and verify the operation of 4-bit up and down synchronous counters using JK flip-flops. It provides background on synchronous counters and describes the procedure used to set up the counter circuits and verify their operation.

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58 PRANAV S KUMAR
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32 views5 pages

Synchronous Counter

The document describes an experiment to design and verify the operation of 4-bit up and down synchronous counters using JK flip-flops. It provides background on synchronous counters and describes the procedure used to set up the counter circuits and verify their operation.

Uploaded by

58 PRANAV S KUMAR
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EXPERIMENT NO: 10

SYNCHRONOUS COUNTERS

AIM :

To design , set up and verify the working of the following circuits using JK FFs.

1. 4- bit up counter.
2. 4- bit down counter.

COMPONENTS REQUIRED :

ICs 7473, 7400, 7408, 7432 and IC Trainer kit.

THEORY :

Synchronous and asynchronous counters provide same outputs. The difference is that
in the synchronous counters all flip flops work in synchronism with the input clock pulse, that
means the outputs of all the flip flops in the counter change the states at the same instant.
Therefore, the propagation delay occurring in asynchronous counter is eliminated in synchronous
counters. Synchronous counters for any given count sequence or modulus can be designed and
set up by the following procedure.

1. Find the number of flip flops using the relation 𝑁 = log 2 𝑀 where M is the
modulus of the counter and Nis the number of flip flops.
2. Write down the count sequence (FF outputs) in a tabular form. Determine the flip
flop inputs which must be present for the desired next state using excitation table of
the flip flop.
3. Prepare Karnaugh maps for each FF input in terms of FF outputs as the input
variables and obtain the minimized expressions.
4. Set up the circuit using FFs and other gates.

Up / down counter:

An up / down counter is capable of progressing the counting in either direction through


a certain sequence. A mode control pin decides whether the counter should count ‘up’ or ‘down’.

PROCEDURE :

1. Test all the components and IC packages using the IC tester.


2. Set up the circuit one by one and verify the counter state.

RESULT:

Designed, set up and verified the following synchronous counters,

1. 4 – Bit up counter.
2. 4 – down counter.
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