Electrical Engineering Department

Benha Faculty of Engineering

Benha University

Microprocessors and
Microcontrollers E1328
#Lecture_5
Dr. Mahmoud Adel Hassan,
Ph.D. Degree in Engineering Sciences in
Electrical Engineering,
Email: [email protected]
# Second Semester 2022/2023
Outline
➢Memory Organization
▪ General Purpose RAM
▪ Bit-Addressable RAM
▪ Register Banks
➢Special Function Registers
▪ Program Status Word
▪ B Register
▪ Stack Pointer
▪ Data Pointer
▪ Port Registers
Memory Organization
• Figure gives the details of the on-chip
data memory. As shown, the internal
data memory space is divided between
internal RAM (00H-7FH) and special
function registers (80H-0FFH).

• A confusion sometimes arises between

the concept of internal (on-chip) data
memory and internal RAM. The 8051's
internal data memory space has the
range from 00H-0FFH, which is 256
bytes.
• However, only the lower half (00H-
7FH) of the internal memory space is
for general data while the upper half
(80H-0FFH) is mostly for specific
purposes and not for general data;
hence, only the lower half is
considered to be internal RAM.

• The internal data RAM is further sub-

divided into register banks (00H-1FH),
bit addressable RAM (20H-2FH), and
general-purpose RAM (30H-7FH)..
General Purpose RAM
• Although Figure shows 80 bytes of general-purpose RAM from
addresses 30H to 7FH, the bottom 48 bytes from 00H to 2FH can
be used similarly.

• Any location in the general-purpose RAM can be accessed freely

using the direct or indirect addressing modes. For example, to read
the contents of internal RAM address 5FH into the accumulator, the
following instruction could be used:

MOV A,5FH
General Purpose RAM
• This instruction moves a byte of data using direct addressing to specify the "source location“
(i.e., address 5FH). The destination for the data is implicitly specified in the instruction opcode
as the A accumulator. Internal RAM can also be accessed using indirect addressing through R0
or R1. For example, the following two instructions perform the same operation as the single
instruction above:

MOV R0,#5FH

MOV A,@R0

• The first instruction uses immediate addressing to move the value 5FH into register R0, and
the second instruction uses indirect addressing to move the data "pointed at by R0“ into the
accumulator.
Bit-Addressable RAM
• The 8051 contains 210 bit-addressable locations, of which 128 are at byte addresses 20H
through 2FH.

• The idea of individually accessing bits through software is a powerful feature of most
microcontrollers. Bits can be set, cleared, ANDed, ORed, etc., with a single instruction.

• There are 128 general-purpose bit-addressable locations at byte

addresses 20H through 2FH (8 bits/byte x 16 bytes = 128 bits).
These addresses are accessed as bytes or as bits, depending on the
instruction. For example, to set bit 67H, the following instruction
could be used:

SETB 67H
Referring to internal RAM Figure, note that "bit address 67H" is the most-significant bit at "byte
address 2CH." The instruction above has no effect on the other bits at this address. Most
microprocessors would perform the same operation as follows:

MOV A, 2CH ;READ ENTIRE BYTE

ORL A,#10000000B ;SET MOST-SIGNIFICANT BIT

MOV 2CH,A ;WRITE BACK ENTIRE BYTE

Register Banks
The bottom 32 locations of internal memory contain the register banks. The 8051 instruction set
supports eight registers, R0 through R7, and by default (after a system reset) these registers are
at addresses 00H-07H. The following instruction, then, reads the contents of address 05H into
the accumulator:

MOV A,R5

This instruction is a 1-byte instruction using register addressing. Of course, the same operation
could be performed in a 2-byte instruction, using the direct address as byte 2:

MOV A,05H

Instructions using registers R0 to R7 are shorter than the equivalent instructions using direct
addressing. Data values used frequently should use one of these registers. The active register
bank may be altered by changing the register bank select bits in the program status word .
Register Banks
Assuming, then, that register bank 3 is active, the following instruction writes the contents of the
accumulator into location 18H:

MOV R0,A

The idea of "register banks" permits fast and effective "context switching," whereby separate
sections of software use a private set of registers independent of other sections of software.

Bank 0 Bank 1 Bank 2 Bank 3

07 0F 17 1F
06 0E 16 1E
05 0D 15 1D
04 0C 14 1C
03 0B 13 1B
02 0A 12 1A
01 09 11 19
00 08 10 18
Special Function Registers
In 8051, there are 21 special function registers (SFRs) at the top of
internal RAM, from addresses 80H to 0FFH.
Program Status Word
The program status word (PSW) at address 0D0H contains status bits as summarized in Table
2-3. Each of the PSW bits is examined below.

Carry Flag The carry flag (C or CY) is

dual-purpose. It is used in the traditional
way for arithmetic operations: set if there is
a carry out of bit 7 during an add, or set if
there is a borrow into bit 7 during a
subtract. For example, if the accumulator
contains 0FFH, then the instruction

ADD A,#1

leaves the accumulator equal to 00H and

sets the carry flag in the PSW.
Auxiliary Carry Flag When adding binary-coded-decimal (BCD) values, the auxiliary carry flag
(AC) is set if a carry was generated out of bit 3 into bit 4 or if the result in the lower nibble is in
the range 0AH-0FH. If the values added are BCD, then the add instruction must be followed by
DA A (decimal adjust accumulator) to bring results greater than 9 back into range.
Register Bank Select Bits The register bank select Overflow Flag The overflow flag (OV) is set after
bits (RS0 and RS1) determine the active register bank. an addition or subtraction operation if there was an
They are cleared after a system reset and are changed by arithmetic overflow. When signed numbers are added
software as needed. For example, the following three or subtracted, software can examine this bit to
instructions enable register bank 3 and then move the determine if the result is in the proper range.
content of R7 (byte address 1FH) to the accumulator:
When unsigned numbers are added, the OV bit can be
SETB RS1 ignored. Results greater than +127 or less than -128
will set the OV bit. For example, the following
SETB RS0
addition causes an overflow and sets the OV bit in the
MOV A,R7 PSW:

When the above program is assembled, the correct bit

addresses are substituted for the symbols "RS1" and
"RS0." Thus, the instruction SETB RS1 is the same as As a signed number, 8EH represents -116, which is
SETB 0D4H. clearly not the correct result of 142; therefore, the OV
bit is set.
Parity Bit The parity bit (P) is automatically set or cleared each machine cycle to establish even
parity with the accumulator. The number of 1-bits in the accumulator plus the P bit is always
even. If, for example, the accumulator contains 10101101, P will contain 1 (establishing a total
of six 1-bits; i.e., an even number of 1s). The parity bit is most commonly used in conjunction
with serial port routines to include a parity bit before transmission or to check for parity after
reception.
B Register
• The B register, or accumulator B, at address 0F0H is used along with the accumulator for
multiply and divide operations. The MUL AB instruction multiplies the 8-bit unsigned
values in A and B and leaves the 16-bit result in A (low-byte) and B (high-byte).

• The DIV AB instruction divides A by B, leaving the integer result in A and the remainder in
B. The B register can also be treated as a general-purpose scratch-pad register. It is bit-
addressable through bit addresses 0F0H to 0F7H.
Stack Pointer
The stack pointer (SP) is an 8-bit register at address 81H. It contains the address of the data item
currently on the top of the stack. Stack operations include "pushing" data on the stack and "popping"
data off the stack. Pushing on the stack increments the SP before writing data, and popping from the
stack reads data and then decrements the SP. The 8051 stack is kept in internal RAM and is limited to
addresses accessible by indirect addressing. These are the first 128 bytes on the 8031/8051 or the full
256 bytes of on-chip RAM on the 8032/8052.

To reinitialize the SP with the stack beginning at 60H, the following instruction is used:

MOV SP,#5FH

On the 8031/8051 this would limit the stack to 32 bytes, since the uppermost address of on-chip RAM is
7FH. The value 5FH is used, since the SP increments to 60H before the first push operation.
Data Pointer
The data pointer (DPTR), used to access external code or data memory, is a 16-bit register at addresses
82H (DPL, low-byte) and 83H (DPH, high-byte). The following three instructions write 55H into
external RAM location 1000H:

MOV A,#55H
MOV DPTR,#1000H
MOVX @DPTR,A

The first instruction uses immediate addressing to load the data constant 55H into the accumulator.

The second instruction also uses immediate addressing, this time to load the 16-bit address constant
1000H into the data pointer. The third instruction uses indirect addressing to move the value in A (55H)
to the external RAM location whose address is in the DPTR (1000H). The "X" in the mnemonic
"MOVX" indicates that the move instruction accesses external data memory.
Port Registers
The 8051 I/O ports consist of Port 0 at address 80H, Port 1 at address 90H, Port 2 at address
0A0H, and Port 3 at address 0B0H. Ports 0, 2, and 3 may not be available for I/O if external
memory is used or if some of the 8051 special features are used (interrupts, serial port, etc.).
Nevertheless, P1.2 to P1.7 are always available as general purpose I/O lines.
All ports are bit-addressable. This capability provides powerful interfacing possibilities. If a
motor is connected through a solenoid and transistor driver to Port 1 bit 7, for example, it could
be turned on and off using a single 8051 instruction:
SETB P1.7
might turn the motor on, and
CLR P1.7
might turn it off.
Port Registers
The instructions above use the dot operator to address a bit within a bit-addressable byte
location. The assembler performs the necessary conversion; thus, the following two
instructions are the same:
CLR P1.7
CLR 97H
In another example, consider the interface to a device with a status bit called BUSY, which is
set when the device is busy and clear when it is ready. If BUSY connects to, say, Port 1 bit 5,
the following loop could be used to wait for the device to become ready:
WAIT: JB P1.5,WAIT
This instruction means "if the bit P1.5 is set, jump to the label WAIT." In other words "jump
back and check it again."