Electrical Engineering Department

Benha Faculty of Engineering

Microprocessors and
Microcontrollers E1328
#Lecture_6
Dr. Mahmoud Adel Hassan,
Ph.D. Degree in Engineering Sciences in
Electrical Engineering,
Email: [email protected]
# Second Semester 2022/2023
Outline
Special Function Registers
 Program Status Word Continue…..
 B Register
 Stack Pointer
 Data Pointer
 Port Registers
Instruction Set
Addressing Mode
 Register Addressing
 Direct Addressing
 Indirect Addressing
 Immediate Addressing
Program Status Word
The program status word (PSW) at address 0D0H contains status bits as summarized in Table
2-3. Each of the PSW bits is examined below.
Parity Bit The parity bit (P) is automatically set or cleared each machine cycle to establish even
parity with the accumulator. The number of 1-bits in the accumulator plus the P bit is always
even. If, for example, the accumulator contains 10101101, P will contain 1 (establishing a total
of six 1-bits; i.e., an even number of 1s). The parity bit is most commonly used in conjunction
with serial port routines to include a parity bit before transmission or to check for parity after
reception.
B Register
• The B register, or accumulator B, at address 0F0H is used along with the accumulator for
multiply and divide operations. The MUL AB instruction multiplies the 8-bit unsigned
values in A and B and leaves the 16-bit result in A (low-byte) and B (high-byte).

• The DIV AB instruction divides A by B, leaving the integer result in A and the remainder in
B. The B register can also be treated as a general-purpose scratch-pad register. It is bit-
addressable through bit addresses 0F0H to 0F7H.
Stack Pointer
The stack pointer (SP) is an 8-bit register at address 81H. It contains the address of the data item
currently on the top of the stack. Stack operations include "pushing" data on the stack and "popping"
data off the stack. Pushing on the stack increments the SP before writing data, and popping from the
stack reads data and then decrements the SP. The 8051 stack is kept in internal RAM and is limited to
addresses accessible by indirect addressing. These are the first 128 bytes on the 8031/8051 or the full
256 bytes of on-chip RAM on the 8032/8052.

To reinitialize the SP with the stack beginning at 60H, the following instruction is used:

MOV SP,#5FH

On the 8031/8051 this would limit the stack to 32 bytes, since the uppermost address of on-chip RAM is
7FH. The value 5FH is used, since the SP increments to 60H before the first push operation.
Data Pointer
The data pointer (DPTR), used to access external code or data memory, is a 16-bit register at addresses
82H (DPL, low-byte) and 83H (DPH, high-byte). The following three instructions write 55H into
external RAM location 1000H:

MOV A,#55H
MOV DPTR,#1000H
MOVX @DPTR,A

The first instruction uses immediate addressing to load the data constant 55H into the accumulator.

The second instruction also uses immediate addressing, this time to load the 16-bit address constant
1000H into the data pointer. The third instruction uses indirect addressing to move the value in A (55H)
to the external RAM location whose address is in the DPTR (1000H). The "X" in the mnemonic
"MOVX" indicates that the move instruction accesses external data memory.
Port Registers
The 8051 I/O ports consist of Port 0 at address 80H, Port 1 at address 90H, Port 2 at address
0A0H, and Port 3 at address 0B0H. Ports 0, 2, and 3 may not be available for I/O if external
memory is used or if some of the 8051 special features are used (interrupts, serial port, etc.).
Nevertheless, P1.2 to P1.7 are always available as general purpose I/O lines.
All ports are bit-addressable. This capability provides powerful interfacing possibilities. If a
motor is connected through a solenoid and transistor driver to Port 1 bit 7, for example, it could
be turned on and off using a single 8051 instruction:
SETB P1.7
might turn the motor on, and
CLR P1.7
might turn it off.
Port Registers
The instructions above use the dot operator to address a bit within a bit-addressable byte
location. The assembler performs the necessary conversion; thus, the following two
instructions are the same:
CLR P1.7
CLR 97H
In another example, consider the interface to a device with a status bit called BUSY, which is
set when the device is busy and clear when it is ready. If BUSY connects to, say, Port 1 bit 5,
the following loop could be used to wait for the device to become ready:
WAIT: JB P1.5,WAIT
This instruction means "if the bit P1.5 is set, jump to the label WAIT." In other words "jump
back and check it again."
Instruction Set
• Just as sentences are made of words, programs are made of instructions. When programs are
constructed from logical, well-thought-out sequences of instructions, fast, efficient, and even
elegant programs result. Unique to each family of computers is its instruction set, a repertoire
of primitive operations such as "add," "move," or "jump.“

• The MCS-51TM instruction set is optimized for 8-bit control applications. It provides a variety
of fast, compact addressing modes for accessing the internal RAM to facilitate operations on
small data structures. The instruction set offers extensive support for 1-bit variables, allowing
direct bit manipulation in control and logic systems that require Boolean processing.
Addressing Mode
When instructions operate on data, the question arises: "Where are the data?" The answer to this
question lies in the 8051's "addressing modes." There are several possible addressing modes and
there are several possible answers to the question, such as "in byte 2 of the instruction," "in register
R4," "in direct address 35H," or perhaps "in external data memory at the address contained in the
data pointer." Addressing modes are an integral part of each computer's instruction set. They allow
specifying the source or destination of data in different ways, depending on the programming
situation.

• Register Addressing
• Direct Addressing

Direct addressing can access any on-chip variable or hardware register.

• Indirect Addressing

The 8051 solution is indirect addressing. R0 and R1 may operate as "pointer" registers—their
contents indicating an address in internal RAM where data are written or read. The least-significant
bit of the instruction opcode determines which register (R0 or R1) is used as the pointer.

• Immediate Addressing

When a source operand is a constant rather than a variable (i.e., the instruction uses a value known
at assemble-time), then the constant can be incorporated into the instruction as a byte of
"immediate" data.