Why there was a need for FPGA

1) FPGAs Work in Parallel

2) FPGAS Perform Time-Critical Processing
3) FPGAs Have Optimal Performance per Watt
4) faster than microcontroller

Advantage fo interrupt ?
it can serves multiple devices, it is more flexible and efficient
make the best use of microcontroller
 Question 2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ee is
Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
Y : out STD_LOGIC_VECTOR(3 downto 0));
end ee;
architecture Behavioral of ee is
begin
Y <= NOT A + ‘1’;
end Behavioral;
Question 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity aa is
Port ( A,b,c,d : in STD_LOGIC;
x,Y : out STD_LOGIC);
end ee;
architecture Behavioral of aa is
begin
x <= (A and b) or (not a and c ) or (a and d);
Y <= (a or b or not d) and (a or b or not c);
end Behavioral;
Question 4
1. Behavior of the signals
2. <=
3. field programmable gate array
4. architecture
5. concurrent
6. bit
7. cpld
8. true
9. C
10. sequential
 Question 1 ⇒ 1
it can serves multiple devices, it is more flexible and efficient
make the best use of microcontroller
Question 2
EICRA
0 0 0 0 1 0 0 0
EIMSK
0 0 0 0 0 0 1 0
DDRD
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
PIND
7 6 5 4 3 2 1 0
0 0 0 0 1 0 0 0
DDRC
7 6 5 4 3 2 1 0
0 0 0 1 1 1 1 1
PORTC
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
TCCR0A
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
TCCR0B
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 0
TIMSK0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1
16M clk → prescalar /8 → 2 M
2 M / 2^8 = 2 M / 256 = 7812.5 → 7813
#define F_CPU 16000000UL
#include <avr/interrupt.h>
#include <avr/io.h>
int state = -1;
int count1 = 0;
int delaystate = 0;
void main(void){
int Display[5] = {0x01,0x02,0x04,0x08,0x10};
EIMSK = 0x02;
EICRA = 0x08;
DDRD |= 0x00;
DDRC |= 0x1F;
TCCR0A = 0x00;
TCCR0B = 0x02;
TIMSK0 = 0x01;
sei();
while(1){
if(state == 0){
for(int i=0;i<5;i++){
PORTC=Display[i];
while(delaystate == 0){}
delaystate = 0;
}
state = -1;
}else{
PORTC= 0x00;
}}}
ISR(INT1_vect){
state = 0;
}
ISR(TIMER0_OVF_vect){
if (count1 < (7813 * 2.5))
{ count1 = count1 + 1; }
else {
count1 = 0;
 delaystate =1;
}}
Question 3
1. 32 Kbytes
2. 3
3. 6,6
4. 0
5. 2
6. all
7. a
8. B
9. 0x0012
10. C

_________________________________________________________
‫رابط االمتحان‬
CE2_FinalExamFinal_2021_2ndterm.pdf
‫الحل‬
Question 2 ⇒ 1
EICRA
0 0 0 0 0 0 1 0
EIMSK
0 0 0 0 0 0 0 1
DDRD
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
PIND
7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0
DDRC
7 6 5 4 3 2 1 0
0 1 1 1 1 1 1 1
PORTC
 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
TCCR0A
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
TCCR0B
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 0
TIMSK0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1

16M clk → prescalar /8 → 2 M

2 M / 2^8 = 2 M / 256 = 7812.5 → 7813
#define F_CPU 16000000UL
#include <avr/interrupt.h>
#include <avr/io.h>
int i = 0;
int count1 = 0;
int delaystate = 0;
void main(void){
int Display[5] = {0x3F,0x5B,0x66,0x7D,0x7F};
EIMSK = 0x01;
EICRA = 0x02;
DDRD |= 0x00;
DDRC |= 0x7F;
TCCR0A = 0x00;
TCCR0B = 0x02;
TIMSK0 = 0x01;
sei();
while(1){
for(i=0;i<5;i++){
PORTD=Display[i];
while(delaystate == 0){}
delaystate = 0; }
}}
ISR(INT0_vect){
i = 0;
}
ISR(TIMER0_OVF_vect){
if (count1 < (7813 * 2))
{ count1 = count1 + 1; }
else {
count1 = 0;
delaystate =1;
}}
Question 2 ⇒ 2
Write a VHDL code for 8 to 3 encoder
 Question 2 ⇒ 3
truth table ‫اوال هنحل ال‬
full adder ‫هنالقى ان ده‬
then ⇒ x = a xor b xor c

code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder is
Port ( a,b,c : in STD_LOGIC;
x : out STD_LOGIC);
end fulladder;
architecture Behavioral of fulladder is
begin
x <= a xor b xor c;
end Behavioral;
Question 3
1. VHDL
2. Architecture
3. <=
4. Global interconnection matrix
5. Bit_vector type
6. Sequential
7. True
8. Architecture
9. WAIT WHILE
10. .bit
11. Std_logic
12. 0
13. ALL
14. 0x02
15. True
16. .hex
17. B
18. Internal and External clock
 19. 10
20. 0x0012
ES_FinalExam2021.pdf
Question 2
EICRA
0 0 0 0 1 0 0 0
EIMSK
0 0 0 0 0 0 1 0
DDRD
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
PIND
7 6 5 4 3 2 1 0
0 0 0 0 1 0 0 0
DDRC
7 6 5 4 3 2 1 0
0 0 0 1 1 1 1 1
PORTC
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
TCCR0A
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
TCCR0B
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 0
TIMSK0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1
16M clk → prescalar /8 → 2 M
2 M / 2^8 = 2 M / 256 = 7812.5 → 7813
#define F_CPU 16000000UL
#include <avr/interrupt.h>
#include <avr/io.h>
int state = -1;
int count1 = 0;
int delaystate = 0;
void main(void){
int Display[5] = {0x01,0x02,0x04,0x08,0x10};
EIMSK = 0x02;
EICRA = 0x08;
DDRD |= 0x00;
DDRC |= 0x1F;
TCCR0A = 0x00;
TCCR0B = 0x02;
TIMSK0 = 0x01;
sei();
while(1){
if(state == 0){
for(int i=4;i>=0;i--){
PORTD=Display[i];
while(delaystate == 0){}
delaystate = 0;
}
state = -1;
}else{
PORTD= 0x00;
}}}
ISR(INT1_vect){
state = 0;
}
ISR(TIMER0_OVF_vect){
if (count1 < (7813 * 2.5))
{ count1 = count1 + 1; }
else {
count1 = 0;
 delaystate =1; }}
Question 3
12M clk → prescalar /8 → 1500000
1500000 / 2^8 = 187500 / 256 = 5895.3 → 5896

#define F_CPU 16000000UL

#include <avr/interrupt.h>
#include <avr/io.h>
int state = -1;
int count1 = 0;
int delaystate = 0;
void main(void){
EIMSK = 0x02;
EICRA = 0x08;
DDRD |= 0x00;
DDRC |= 0x0F;
TCCR0A = 0x00;
TCCR0B = 0x02;
TIMSK0 = 0x01;
sei();
while(1){
if(state == -1){
PORTC = 0x09;
while(delaystate == 0){}
delaystate = 0;
PORTC = 0;
while(delaystate == 0){}
delaystate = 0;
PORTC = 0x06;
while(delaystate == 0){}
delaystate = 0;
PORTC = 0;
while(delaystate == 0){}
delaystate = 0;
}}
ISR(INT1_vect){
state = 0;
PORTC = 0;
delaystate = 1;
}
ISR(TIMER0_OVF_vect){
if (count1 < (5896 * 1.5))
{ count1 = count1 + 1; }
else {
count1 = 0;
delaystate =1; }}
Question 4
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity aa is
Port ( A,b,c,d : in STD_LOGIC;
x,Y : out STD_LOGIC);
end ee;
architecture Behavioral of aa is
begin
x <= (A and b) or (not a and c ) or (a and d);
Y <= (a or b or not d) and (a or b or not c);
end Behavioral;
Question 5
1. C Languages
2. True
3. C
4. D
5. SEI
6. 0
7. B
8. .hex
9. B
10. C
11. C
12. D
13. D
14. architecture
15. 0
16. C
17. A
18. B
19. True
 20. B

FinalExam_2020_ComputerEngineering(2).pdf
Question2 ⇒ 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity fourleds is
Port ( clk : in STD_LOGIC;
leds : out STD_LOGIC_VECTOR (3 downto 0));
end fourleds;

architecture Behavioral of fourleds is

signal cnt : std_logic_vector( 31 downto 0 ) :=

"00000000000000000000000000000000";
signal onesecparser : std_logic := ‘0’;
signal sleds : std_logic_vector( 3 downto 0 ) := "0000";

begin

p1 : process(clk)
begin
if(rising_edge(clk)) then
if(cnt < conv_std_logic_vector(50000000,32)) then
cnt <= cnt + '1';
else
onesecparser <= '1';
cnt <= "00000000000000000000000000000000";
end if;
if(onesecparser = '1') then
onesecparser <= '0';
sleds <= sleds + '1';
end if;
end if;
end process;

leds <= sleds;

end Behavioral;
Question2 ⇒ 2
Write a VHDL code for 8 to 3 encoder

Question2 ⇒ 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ee is
Port ( A,b,c : in STD_LOGIC;
x : out STD_LOGIC);
end ee;
architecture Behavioral of ee is
begin
x <= A xor b xor c;
end Behavioral;
Question2 ⇒ 4
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity aa is
Port ( A,b,c : in STD_LOGIC;
f,g : out STD_LOGIC);
end ee;
architecture Behavioral of aa is
begin
f <= (a or not b) and (not(c or (not a and b)));
g <= (A and not b) or ( c and (not a or b ) );
end Behavioral;
Question 3
1. B
2. A
3. B
4. A
5. C
6. C
7. C
8. B
9. C
10. A
11. B
12. D
13. C
14. D
15. A
16. A
17. B
18. D
19. A
20. B
21. D
22. A
23. B
24. B
25. C
 FinalExam_2020_Instrumentation_and_Measurements.pdf
‫السؤال االول والثانى مش علينا‬
Question 1 ⇒ 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity fulladderonebit is
Port ( a,b: in STD_LOGIC;
x : out STD_LOGIC);
end fulladderonebit;
architecture Behavioral of fulladderonebit is
begin
x <= a + b;
end Behavioral;

Question 1 ⇒ 4
Write a VHDL program for 4X1 MUX(Multiplexer)
 Question 1 ⇒ 5
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity aa is
Port ( A,b,c,d : in STD_LOGIC;
x,Y : out STD_LOGIC);
end ee;
architecture Behavioral of aa is
begin
x <= (A and b) or (not a and c ) or (a and d);
Y <= (a or b or not d) and (a or b or not c);
end Behavioral;
Question 2
‫االختيارات التى لم يتم حلها ليست معنا‬
1. C
2. A
3. B
 4. C
5. B
7. C
8. A
10. A
11. C
12. B
13. C
14, B
15. C
16. B
17. A
18. D
21. A
ES_MidTermExam_2019_B.pdf
Question 2
1. B
2. A
‫ مش معانا‬.3
‫ مش معانا‬.4
‫ مش معانا‬.5
6. C
7. B
‫ مش معانا‬.8
9. A
‫ مش معانا‬.10
Question 3
EICRB
0 0 0 0 1 0 1 0
EIMSK
0 0 1 1 0 0 0 0
DDRE
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
PIND
7 6 5 4 3 2 1 0
0 0 1 1 0 0 0 0
DDRK
7 6 5 4 3 2 1 0
0 0 0 1 1 1 1 1
PORTK
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
TCCR0A
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
TCCR0B
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 0
TIMSK0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1
16M clk → prescalar /8 → 2 M
2 M / 2^8 = 2 M / 256 = 7812.5 → 7813
#define F_CPU 16000000UL
#include <avr/interrupt.h>
#include <avr/io.h>
int state = -1;
int count1 = 0;
int count2 = 0;
int delay1 = 0;
int delay2 = 0;
void main(void){
int Display[5] = {0x01,0x02,0x04,0x08,0x10};
EIMSK = 0x30;
EICRB = 0X0A;
DDRK = 0x1F;
DDRE = 0x00;
TCCR0A = 0x00;
 TCCR0B = 0x02;
TIMSK0 = 0x01;
sei();
while(1){
if(state == 0){
for(int i=0;i<5;i++){
PORTK=Display[i];
while(delay1==0){}
delay1=0; }
state = -1;
}else if(state == 1){
PORTK= 0x15;
while(delay2 == 0){}
delay2 = 0;
PORTK= 0x0A;
while(delay2 == 0){}
delay2 = 0;
state=-1;
}else{
PORTK= 0x1F;
}}}
ISR(INT4_vect){
state = 0; }
ISR(INT5_vect){
state = 1; }
ISR(TIMER0_OVF_vect){
if (count1 < 7813)
{ count1 = count1 + 1; }
else {
count1 = 0;
delay1 = 1; }
if (count2 < 15626)
{ count2 = count2 + 1; }
else {
count2 = 0;
delay2 = 1;
}}
 ES_MidTermExam_2019.pdf

mcq

1. A. knowing the status of the timer count

2. DDR register of that port is set to 0.
3. from datasheet
4. from datasheet
5. A. Pin Change.
6. False.
7. from datasheet
8. B. TCON.
9. f/8.
10. C. PORTD.
 Question 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Decoder is
port(din : in std_logic_vector(2 downto 0);
dout : out std_logic_vector(7 downto 0));
end Decoder;
architecture descript of Decoder is
begin
dout <="00000001" when din="000" else
"00000010" when din="001" else
"00000100" when din="010" else
"00001000" when din="011" else
"00010000" when din="100" else
"00100000" when din="101" else
"01000000" when din="110" else
"10000000" when din="111";
end descript;
Question 4
a)
O8
I8 I4 \ I2 I1 00 01 11 10
00
01 1
11 x x x x
10 1 x x
O8 = I4 I2 I1 + I8 I1’

O4
I8 I4 \ I2 I1 00 01 11 10
00 1
01 1 1 1
11 x x x x
10 x x
O4 = I4 I2’ + I4 I1’ + I4’ I2 I1
O2
I8 I4 \ I2 I1 00 01 11 10
00 1 1
01 1 1
11 x x x x
10 x x
O2 = I8’ I2’ I1 + I2 I1’

O1
I8 I4 \ I2 I1 00 01 11 10
00 1 1
01 1 1
11 x x x x
10 1 x x
O1 = I1’

B)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity kmap is
port(I1,I2,I4,I8 : in std_logic;
O1,O2,O4,O8 : out std_logic);
end kmap;
architecture AA of kmapis
begin
O8 <= (I4 and I2 and I1)+ (I8 and not I1);
O4 <= (I4 and not I2) or (I4 and not I1) or (not I4 and I2 and I1);
O2 <= (not I8 and not I2 and I1)+(I2 and not I1);
O1 <= not I1;
end AA;
 Question 5
1) B
2) C
3) B
4) D
5) A
6) D
7) B
8) D
9) A
10) B
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity square is
port(a : in std_logic_vector(3 downto 0);
y: out std_logic_vector(7 downto 0));
end square;
architecture descript of square is
begin
y<="00000000" when a="0000" else
"00000001" when a="0001" else
"00000100" when a="0010" else
"00001001" when a="0011" else
"00001111" when a="0100" else
"00011001" when a="0101" else
"00100100" when a="0110" else
"00110001" when a="0111" else
"01000000" when a="1000" else
"01010001" when a="1001" else
"01100100" when a="1010" else
"01111001" when a="1011" else
"10010000" when a="1100" else
"10101001" when a="1101" else
"11000100" when a="1110" else
"11100001" when a="1111";
end descript;
EICRA
0 0 0 0 1 1 0 0
EIMSK
0 0 0 0 0 0 1 0
DDRD
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
PIND
7 6 5 4 3 2 1 0
0 0 0 0 1 0 0 0
DDRC
7 6 5 4 3 2 1 0
0 0 0 1 1 1 1 1
PORTC
7 6 5 4 3 2 1 0
 0 0 0 0 0 0 0 0

#define F_CPU 16000000UL

#include <avr/interrupt.h>
#include <avr/io.h>
#include <util/delay.h>
int i = 0;
void main(void){
EIMSK = 0x02;
EICRA = 0x0C;
DDRD |= 0x00;
DDRC |= 0x1F;
sei();
while(1){
PORTD = i;
_delay_ms(1500);
i++;
}}
ISR(INT1_vect){
i = 0;
}