CO/DL

1. Consider the following processor design characteristics:

i. Register-to-register arithmetic operations only
ii. Fixed-length instruction format
iii. Hardwired control unit
Which of the characteristics above are used in the design of a RISC processor?
A. I and II only
B. II and III only
C. I and III only
D. I, II and III

2. Consider the following data path diagram.

Consider an instruction: 𝑅0←𝑅1+𝑅2. The following steps are used to execute it over the given data path. Assume
that PC is incremented appropriately. The subscripts 𝑟 and 𝑤 indicate read and write operations, respectively.
1.𝑅2𝑟, TEMP1𝑟,𝐴𝐿𝑈add, TEMP2𝑤
2.𝑅1𝑟, TEMP1𝑤
3.𝑃𝐶𝑟, MAR𝑤, MEM𝑟
4.TEMP2𝑟, R0𝑤
5. MDR𝑟, IR𝑤
Which one of the following is the correct order of execution of the above steps?
A. 2,1,4,5,3
B. 1,2,4,3,5
C. 3,5,2,1,4
D. 3,5,1,2,4
3-store content of pc into memory address register and issue memory read
5-store the data from memory data register into instruction register.
2-store the content of R1 into temporary register TEMP1
1-add contents of R2 and TEMP1 and store result in TEMP2.
4- store contents of TEMP2 into R0

3. A processor has 40 distinct instruction and 24 general purpose registers. A 32-bit instruction word has an
opcode, two registers operands and an immediate operand. The number of bits available for the immediate
operand field is___16____.

Log240 = 6 Log224 = 5 6+ 2 registers * 5  16 bits available  32- 16  16

4. A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits
long. It needs to support 45 instructions, which have an immediate operand in addition to two register
operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate
operand is ____________
Answer : 16383
no. of bits for 45 instructions / opcode = ⌈log245⌉ = 6
no. of bits for each register operand = ⌈log264⌉ =6

6 (opcode) 6 (r1) 6 (r2) p (immediate)

no. of immediate operand bits = no. of bits for machine  (6 + 6 + 6)

no. of immediate operand bits = 32 - 18 = 14 bits
for max value of immediate operand you have to put all 1's in all 14 immediate bits
so, max value of immediate operand = 214-1 = 16383

5. A processor that has the carry, overflow and sign flag bits as part of its program status word (PSW) performs
addition of the following two 2′𝑠 complement numbers 01001101 and 11101001. After the execution of this
addition operation, the status of the carry, overflow and sign flags, respectively will be:
A. 1,1,0
B. 1,0,0
C. 0,1,0
D. 1,0,1
Carry =1
Overflow = 0 (In 2′𝑠 complement addition Overflow happens only when: Sign bit of two input numbers is 0,
and the result has sign bit 1 OR Sign bit of two input numbers is 1, and the result has sign bit 0.)
Sign bit = 0.

6. A CPU has 24-𝑏𝑖𝑡 instructions. A program starts at address 300 (in decimal). Which one of the following is a
legal program counter (all values in decimal)?
A. 400
B. 500
C. 600 24 bits  3 bytes instructions. So, PC will have multiples of 3 in it.
D. 700

7. The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically
A. has fewer instructions
B. has fewer addressing modes
C. has more registers
D. is easier to implement using hard-wired logic

8. Suppose a processor does not have any stack pointer registers, which of the following statements is true?
A. It cannot have subroutine call instruction
B. It cannot have nested subroutines call
C. Interrupts are not possible
D. All subroutine calls and interrupts are possible

9. The most relevant addressing mode to write position-independent codes is:

A. Direct mode
B. Indirect mode
C. Relative mode
D. Indexed mode
Relative Mode since we can just change the content of base register if we wish to relocate.
10. Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which during execution reads a
32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is
obtained by the addition of a constant 20 and the contents of register R2. Which of the following best reflects
the addressing mode implemented by this instruction for the operand in memory?
A. Immediate addressing
B. Register addressing
C. Register Indirect Scaled Addressing
D. Base Indexed Addressing
Base Index Addressing, as the content of register R2 will serve as the index, and 20 will be the Base address.
11. Which of the following addressing modes are suitable for program relocation at run time?
i. Absolute addressing
ii. Based addressing
iii. Relative addressing
iv. Indirect addressing
12. I and IV
13. I and II
14. II and III
15. I, II and IV
Register add mode : access the local variables
Immediate add mode : access the constant
Direct/Absolute add mode : access the static variables
Indirect add mode : implement pointer
indexed/ Base index : access the random array
Auto index: access the linear array
relative add mode and base register add mode : relocation at run time
base register add mode : best suit to write positions independent code

16. In the absolute addressing mode:

A. the operand is inside the instruction
B. the address of the operand in inside the instruction
C. the register containing the address of the operand is specified inside the instruction
D. the location of the operand is implicit

17. Which of the following addressing modes permits relocation without any change whatsoever in the code?
A. Indirect addressing
B. Indexed addressing
C. Base register addressing
D. PC relative addressing

18. A certain processor supports only the immediate and the direct addressing modes. Which of the following
programming language features cannot be implemented on this processor?
A. Pointers
B. Arrays
C. Records
D. Recursive procedures with local variable

19. Relative mode of addressing is most relevant to writing:

A. Co – routines
B. Position – independent code
C. Shareable code
D. Interrupt Handlers
20. Horizontal microprogramming:
A. does not require use of signal decoders
B. results in larger sized microinstructions than vertical microprogramming
C. uses one bit for each control signal
D. all of the above

21. Arrange the following configuration for CPU in decreasing order of operating speeds:
Hard wired control, Vertical microprogramming, Horizontal microprogramming.
A. Hard wired control, Vertical microprogramming, Horizontal microprogramming.
B. Hard wired control, Horizontal microprogramming, Vertical microprogramming.
C. Horizontal microprogramming, Vertical microprogramming, Hard wired control.
D. Vertical microprogramming, Horizontal microprogramming, Hard wired control.

22. A micro instruction is to be designed to specify:

a. none or one of the three micro operations of one kind and
b. none or upto six micro operations of another kind
The minimum number of bits in the micro-instruction is:
A. 9
B. 5
C. 8  log2(3) = 2 + 6  8
D. None of the above

23. A micro program control unit is required to generate a total of 25 control signals. Assume that during any
micro instruction, at most two control signals are active. Minimum number of bits required in the control word
to generate the required control signals will be:
A. 2
B. 2.5
C. 10  log225 = 5 *2  10
D. 12

24. A microprogrammed control unit

A. Is faster than a hard-wired control unit.
B. Facilitates easy implementation of new instruction.
C. Is useful when very small programs are to be run.
D. Usually refers to the control unit of a microprocessor.

25. Indirect Addressing  Passing Array as Parameter / Pointers

Indexed Addressing  Array Implementation
Base Register Addressing  Writing Relocatable Code
Immediate Addressing  Constants
Auto decrement Addressing  Loops

26. Consider the 𝐶 struct defined below: struct data {

int marks [100];
char grade;
int cnumber;
}; struct data student;
The base address of student is available in register 𝑅1. The field student.grade can be accessed efficiently using:
A. Post-increment addressing mode, (𝑅1)+
B. Pre-decrement addressing mode, −(𝑅1)
C. Register direct addressing mode, 𝑅1
D. Index addressing mode, 𝑋(𝑅1), where 𝑋 is an offset represented in 2′𝑠 complement 16-bit
representation
27. Consider a computer with a 4MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device
to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer
rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?
A. 2,56,000
B. 3,200
C. 25,60,000
D. 32,000
Cycle time=1/4MHZ=0.25us
Transfer time=ty=1 cycle=0.25 us
Cycle stealing mode (given)
% cpu block=(ty/tx)*100
1=ty/tx *100
tx=ty*100
tx=25us
In 25 us 8B data is transferred
In 25us 8*8 bits data is transferred
In 1 sec 64/25us data is transferred
So data transfer rate =64/25us =2.56*10^6

28. Which one of the following statements is FALSE?

A. In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main
memory in a stolen cycle
B. For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode
C. Programmed I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism
D. The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-
vectored interrupts
In a system using programmed I/O, the cpu polls the devices regarding the status update of the I/O event. till the event is
completed, the cpu would have wasted cycles trying to poll devices for the completion of I/O Task. In an interrupt based
mechanism the CPU keeps running uninturrupted till the device activates the interrupt line indicating to the cpu about
the completion of the I/O event. Hence there will not be any wasted cycles. Hence Interrupt based I/O mechanisms have
better CPU utilisation rate.

29. Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest
throughput?
A. DMA based I/O transfer
B. Interrupt driven I/O transfer
C. Polling based I/O transfer
D. Programmed I/O transfer

30. Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in
one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider
a 2 MHz processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is
_80,000_________ bits per second.  1/2MHz * 0.5%

31. For the daisy chain scheme of connecting I/O devices, which of the following statements is true?
A. It gives non-uniform priority to various devices
B. It gives uniform priority to all devices
C. It is only useful for connecting slow devices to a processor device
D. It requires a separate interrupt pin on the processor for each device
Daisy chaining approach tells the processor in which order the interrupt should be handled by providing priority to the
devices.
In daisy-chaining method, all the devices are connected in serial. The device with the highest priority is placed in the
first position, followed by lower priority devices. The interrupt pin is common to all.
32. An instruction format has the following structure:
Instruction Number: Opcode destination reg, source reg-1, source reg-2
Consider the following sequence of instructions to be executed in a pipelined processor:
I 1: DIV R3, R1, R2
I 2: SUB R5, R3, R4
I 3: ADD R3, R5, R6
I 4: MUL R7, R3, R8

Which of the following statements is/are TRUE?

A. There is a RAW dependency on R 3 between I 1 and I 2
B. There is a WAR dependency on R 3 between I 1 and I 3
C. There is a RAW dependency on R 3 between I 2 and I 3
D. There is a WAW dependency on R 3 between I 3 and I 4

33. Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX),
Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about
forwarding is/are CORRECT?
A. In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is
passed on to the destination stage of a later instruction
B. In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of
the next instruction
C. Forwarding cannot prevent all pipeline stalls
D. Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

34. Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first,
second, and the third stages, respectively. Assume that there is no other delay and the processor does not suffer
from any pipeline hazards. Also assume that one instruction is fetched every cycle.
The total execution time for executing 100 instructions on this processor is _____2040________

delays = 10𝑛𝑠,20𝑛𝑠,14𝑛𝑠
total instruction (n) = 100
We take pipeline delay as 𝑡𝑝=𝑚𝑎𝑥(10,20,14)=20
number of stages (𝑘) =3
So,
Total execution time =(𝑘+(𝑛–1))×𝑡𝑝
⟹(3+100−1)×20𝑛𝑠  2040 ns

35. Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero
latency.
P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns.
P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.
P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns.
P4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns.
Which processor has the highest peak clock frequency?
A. P1
B. P2
C. P3  frequency = 1/ max (time in stages)
D. P4
36. Register renaming is done in pipelined processors:
A. as an alternative to register allocation at compile time
B. for efficient access to function parameters and local variables
C. to handle certain kinds of hazards
D. as part of address translation

37. For a pipelined CPU with a single ALU, consider the following situations
I. The 𝑗+1𝑠𝑡 instruction uses the result of the 𝑗𝑡ℎ instruction as an operand
II. The execution of a conditional jump instruction
III. The 𝑗𝑡ℎ and 𝑗+1𝑠𝑡 instructions require the ALU at the same time.
Which of the above can cause a hazard
A. I and II only
B. II and III only
C. III only
D. All the three  1) Data Hazard 2) Control Hazard & 3) Structural Hazard

38. The performance of a pipelined processor suffers if:

A. the pipeline stages have different delays
B. consecutive instructions are dependent on each other
C. the pipeline stages share hardware resources
D. All of the above

39. Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-
pipelined but identical CPU, we can say that
A. T1 ≤ T2
B. T1 ≥ T2
C. T1 < T2
D. T1 and T2 plus the time taken for one instruction fetch cycle

40. The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the
memory system has 16 address lines denoted by 𝐴15 to 𝐴0. What is the range of address (in hexadecimal) of
the memory system that can get enabled by the chip select (CS) signal?

A. C800 to CFFF
B. CA00 to CAFF According to question:
C. C800 to C8FF 𝐴15=1,𝐴14=1,𝐴13=0,𝐴12=0,𝐴11=1
D. DA00 to DFFF So the possible range in binary:
(1100100000000000) to (1100111111111111)
Converting to Hexadecimal:
(𝐶800) to (𝐶𝐹𝐹𝐹)

41. How many 32𝐾×1 RAM chips are needed to provide a memory capacity of 256𝐾 bytes?
A. 8
B. 32
C. 64 Total size/ 1 RAM size  256 K bytes / 32 * 1 RAM  64
D. 128
42. DMA I/O  Disk
Cache  High speed RAM
Interrupt I/O  Printer
Condition Code Register  ALU

43. A processor takes 12 cycles to complete an instruction I. The corresponding pipelined processor uses 6 stages
with the execution times of 3,2,5,4,6 and 2 cycles respectively. What is the asymptotic speedup assuming that
a very large number of instructions are to be executed?
A. 1.83
B. 2
C. 3
D. 6
Speed Up= Time without Pipeline / Time with Pipeline
Time without Pipeline =12 cycle
Time with Pipeline = 6 cycle take maximun one
Speed up =12/6=2

44. Which of the following is not a form of memory

A. instruction cache
B. instruction register
C. instruction opcode
D. translation look-a-side buffer

45. The main memory of a computer has 2cm blocks while the cache has 2c blocks. If the cache uses the set
associative mapping scheme with 2 blocks per set, then block 𝑘 of the main memory maps to the set:
A. (𝑘mod𝑚) of the cache
B. (𝑘mod𝑐) of the cache
C. (𝑘mod2𝑐) of the cache
D. (𝑘mod2𝑐𝑚) of the cache
Cache set no=(Main memory block no.) mod (Total sets in cache)
total sets in cache=(total blocks in cache)/(total blocks in set)=(2c)/(2)=c
cache se no=(k) mod (c)=k mod c

46. The principle of locality justifies the use of:

A. Interrupts
B. DMA
C. Polling
D. Cache Memory

47. A 32-bit wide main memory unit with a capacity of 1GB is built using 256M×4-bit DRAM chips. The number
of rows of memory cells in the DRAM chip is 214. The time taken to perform one refresh operation
is 50nanoseconds. The refresh period is 2milliseconds. The percentage (rounded to the closest integer) of the
time available for performing the memory read/write operations in the main memory unit is _________.

One refresh operation takes 50ns.

Total number of rows =214

Total time to refresh all Rows =214×50ns=819200ns=0.819200ms

The Refresh Period is 2ms.

% Time spent in refresh =Total time to Refresh all Rows / Refresh period∗100
=0.8192ms / 2.0ms∗100 = 40.96%
 % Time spent in Read/Write =100 − 40.96=59.04%

=59% (Rounded to the closest Integer)

48. A cache memory that has a hit rate of 0.8 has an access latency 10ns and miss penalty 100ns. An optimization
is done on the cache to reduce the miss rate. However, the optimization results in an increase of cache access
latency to 15ns, whereas the miss penalty is not affected. The minimum hit rate (rounded off to two decimal
places) needed after the optimization such that it should not increase the average memory access time is
_______0.85________.
Initially,
Hit rate of cache=0.8
∴Miss rate=0.2
Access Latency = HitTime=10𝑛𝑠
Miss Penalty=100𝑛𝑠
∴AMAT𝑢𝑛𝑜𝑝𝑡𝑖𝑚𝑖𝑧𝑒𝑑=10+0.2(100)=30𝑛𝑠
For the optimized cache,
Access Latency = HitTime=15𝑛𝑠
∴AMAT𝑜𝑝𝑡𝑖𝑚𝑖𝑧𝑒𝑑=15+𝑥(100)
Now,
AMAT𝑢𝑛𝑜𝑝𝑡𝑖𝑚𝑖𝑧𝑒𝑑⩾AMAT𝑜𝑝𝑡𝑖𝑚𝑖𝑧𝑒𝑑
30⩾15+100𝑥
⟹15⩾100𝑥
⟹0.15⩾𝑥
⟹0.85⩽1−𝑥

49. Consider a set-associative cache of size 2KB (1KB=210 bytes) with cache block size of 64 bytes. Assume that
the cache is byte-addressable and a 32 -bit address is used for accessing the cache. If the width of the tag field
is 22 bits, the associativity of the cache is ____2_____
bit address is used for accessing the cache.
It is given that cache is Set-Associative.
The address bits get split as follows:

Block Size =64𝐵⟹ Block offset =6𝑏𝑖𝑡𝑠.

Given that Tag field width =22𝑏𝑖𝑡𝑠.
Therefore, width of Set Index field =32−22−6=4⟹24 = 16 sets in the cache.
Cache size is 2𝐾𝐵 and Block size =64𝐵 ⟹25 = 32 blocks present in the
cache.
16 sets contain 32 blocks ⟹ 2 blocks per set or associativity

50. Consider a computer system with a byte-addressable primary memory of size 232 bytes. Assume the computer
system has a direct-mapped cache of size 32 KB (1 KB = 210 bytes), and each cache block is of size 64 bytes.
The size of the tag field is ______17____ bits.

Tag bits = PASbits - log2 (Cache Size) + log2k where k is associativity

 32 – 15 +0  17 bits

51. A direct mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns
and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main
memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in
ns (round off to 1 decimal place) is___ 13.3 0r 13.5 ___.
 Block size is 256 Bytes,word size is 64 bits or 8 bytes. So Block size in words is 8 words.
Number of words per block=32
Time to fetch a word from main-memory to cache is: 20+31×5=175ns because first word takes 20ns and rest each
subsequent words take 5ns each.
So average Memory acces time is
0.94(3)+0.06(3+175)=13.5 ns

52. A certain processor uses a fully associative cache of size 16 kB, The cache block size is 16 bytes. Assume that
the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and
the Index fields respectively in the addresses generated by the processor?
A. 24 bits and 0 bits
B. 28 bits and 4 bits
C. 24 bits and 4 bits
D. 28 bits and 0 bits
Fully Associative Cache has fields: Tag, Offset.
Direct Mapped Cache has fields: Tag, Line No., Offset
Set associative cache has fields: Tag, Set No., Offset
As you can see, in fully associative cache, there's no index field. Hence index bits = 0.
Now, Offset = 4 bits.
=> Tag =32−4=28 bits.

53. Consider a two-level cache hierarchy with 𝐿1 and 𝐿2 caches. An application incurs 1.4 memory accesses per
instruction on average. For this application, the miss rate of 𝐿1 cache is 0.1; the 𝐿2 cache experiences, on
average, 7 misses per 1000 instructions. The miss rate of 𝐿2 expressed correct to two decimal places is
____0.05____.
Since , it is given in question that for 1 instruction it takes 1.4 memory access(ma)
So, for 1000 instr. it will take =1000* 1.4 ma= 1400 ma
Now , it is given for l1 cache miss rate(mr) = 0.
and since , we know mr=no. of misses/total no. of ma
so, 0.1=no. of misses/1400
thus, no. of misses of l1 =140
As , we know when there is miss in l1 , we search for data in l2
so, now for l2 cache total no. of ma=140, and it is given there is 7 miss
so , mr for l2 cache=7/140=1/20=0.05

54. Consider a machine with a byte addressable main memory of 220 bytes, block size of 16 bytes and a direct
mapped cache having 212 cache lines. Let the addresses of two consecutive bytes in main memory
be (E201F)16 and (E2020)16. What are the tag and cache line addresses (in hex) for main memory
address (E201F)16?
A. E, 201
B. F, 201
C. E, E20
D. 2, 01F
E20 is common to both hex numbers, so ignore it.
1𝐹=0001 1111=31 (𝑑𝑒𝑐𝑖𝑚𝑎𝑙)
20=0010 0000=32 (𝑑𝑒𝑐𝑖𝑚𝑎𝑙)
So, difference between two consecutive memory locations = 1 𝐵 Hence, the memory is byte addressable.
First 4 bits would be tag bits, and next 12 bits would be index bits.
So, for (𝐸201𝐹)16
Tag = 𝐸; Line = 201

Tag Line Offset

4 12 4
55. A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words.
The word length is 32 bits. The size of the physical address space is 4 GB. The number of bits for the TAG
field is _ 20 ___
Let us fist assume that system is byte addressable
So to proceed ahead convert everything in byte addressable format
Block size= 32byte
Number of blocks in main memory= 16KB/32B= 512 blocks
Number of sets = 512/4= 128 sets
Format is TAG |SET | BLOCK
Set= 7 bit,
block = 5 bit,
tag = 32-5-7=20 bits

Now let us consider word addressable system

Convert everything with respect to word
Cache size is 4K words, physical address space is 1G words
Number of blocks in cache= 4K/8=512 blocks
Number of sets = 128 sets
Format = Tag| set | word
Set = 7 bit
Word = 3 bit
Tag =30-7-3= 20 bits

56. In a 𝑘-way set associative cache, the cache is divided into 𝑣 sets, each of which consists of 𝑘 lines. The lines
of a set are placed in sequence one after another. The lines in set 𝑠 are sequenced before the lines in set (𝑠+1).
The main memory blocks are numbered 0 onwards. The main memory block numbered 𝑗 must be mapped to
any one of the cache lines from
A. (𝑗 mod 𝑣)∗𝑘 to (𝑗 mod 𝑣)∗𝑘+(𝑘−1)
B. (𝑗 mod 𝑣) to (𝑗 mod 𝑣)+(𝑘−1)
C. (𝑗 mod 𝑘) to (𝑗 mod 𝑘)+(𝑣−1)
D. (𝑗 mod 𝑘)∗𝑣 to (𝑗 mod 𝑘)∗𝑣+(𝑣−1)
Number of sets in cache =𝑣.
The question gives a sequencing for the cache lines. For set 0, the cache lines are numbered 0,1,..,𝑘−1. Now for
set 1, the cache lines are numbered 𝑘,𝑘+1,...𝑘+𝑘−1 and so on.
So, main memory block 𝑗 will be mapped to set (𝑗 mod 𝑣), which will be any one of the cache lines
from (𝑗 mod 𝑣)∗𝑘 to (𝑗 mod 𝑣)∗𝑘+(𝑘−1).
(Associativity plays no role in mapping- 𝑘-way associativity means there are 𝑘 spaces for a block and hence reduces
the chances of replacement.)

57. Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words.
The CPU generates a 20−𝑏𝑖𝑡 address of a word in main memory. The number of bits in the TAG, LINE and
WORD fields are respectively:
A. 9,6,5
B. 7,7,6
C. 7,5,8
D. 9,5,6

Number of sets =cache size / (size of a block * No. of blocks in a set)

= (128∗64) / (64∗4) (4 way set associative means 4 blocks in a set)
=32.
So, number of index (LINE) bits =5 and number of WORD bits =6 since cache block (line) size is 64.
So, number of TAG bits =20−6−5=9.
58. Consider a system with 2 level cache. Access times of Level 1 cache, Level 2 cache and main memory
are 1 𝑛𝑠, 10 𝑛𝑠, and 500 𝑛𝑠 respectively. The hit rates of Level 1 and Level 2 caches are 0.8 and 0.9,
respectively. What is the average access time of the system ignoring the search time within the cache?
A. 13.0
B. 12.8
C. 12.6
D. 12.4
By default we consider hierarchical access - because that is the common implementation and simultaneous access
cache has great practical difficulty. But here the question is a bit ambiguous -- it says to ignore search time within
the cache - usually search is applicable for an associative cache but here no such information given and so we can
assume it is the indexing time in to the cache block.
Access time for hierarchical access,
=𝑡1+(1−ℎ1)×𝑡2+(1−ℎ1)(1−ℎ2)𝑡𝑚
=1+0.2×10+0.2×0.1×500  13 ns

59. A computer system has a 4 𝐾 word cache organized in block-set-associative manner with 4 blocks per
set, 64 words per block. The number of bits in the SET and WORD fields of the main memory address format
is:
A. 15,40 Number of sets =4𝐾 / (64×4) = 16
B. 6,4 So, we need 4-bits to identify a set ⇒ SET =4 bits.
C. 7,2 64 words per block mean WORD is 6-bits.
D. 4,6

60. More than one word are put in one cache block to:
A. exploit the temporal locality of reference in a program
B. exploit the spatial locality of reference in a program
C. reduce the miss penalty
D. none of the above

61. What is the minimum size of ROM required to store the complete truth table of an 8−𝑏𝑖𝑡×8−𝑏𝑖𝑡 multiplier?
A. 32𝐾×16 bits
B. 64𝐾×16 bits Multiplying 2 8-bit digits will give result in maximum 16 bits
C. 16𝐾×32 bits Total number of multiplications possible =28×28
D. 64𝐾×32 bits Hence, space required =64𝐾×16 bits

62. The capacity of a memory unit is defined by the number of words multiplied by the number of bits/word. How
many separate address and data lines are needed for a memory of 4𝐾×16?
A. 10 address, 16 data lines
ROM memory size =2𝑚×𝑛
B. 11 address, 8 data lines 𝑚= no. of address lines 𝑛= no. of data lines
C. 12 address, 16 data lines Given, 4𝐾×16
D. 12 address, 12 data lines =22×210×16 =212×16

63. Which of the following statements is true?

A. ROM is a Read/Write memory  Read Only Memory
B. PC points to the last instruction that was executed  to the next instruction
C. Stack works on the principle of LIFO
D. All instructions affect the flags  not all instructions

64. The main memory unit with a capacity of 4 megabytes is built using 1M×1-bit DRAM chips. Each DRAM
chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation
is 100nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is
A. 100 nanoseconds
B. 100×210 nanoseconds  similar to 47 ques
 C. 100×220 nanoseconds
D. 3200×220 nanoseconds
65. A dynamic RAM has a memory cycle time of 64 nsec. It has to be refreshed 100 times per msec and each
refresh takes 100 nsec . What percentage of the memory cycle time is used for refreshing?
A. 10
B. 6.4
C. 1
D. 0.64 Time for refresh = 100ns

Number of refreshes in a memory cycle = 100 * memory cycle time/ 1ms

= 100 * 64ns/1ms = 6.4 * 10-3

So, time for refresh in a memory cycle = 100 ns * 6.4 * 10-3

= 64 * 10-2 ns

So, percentage of time spent for refresh = (64 * 10-2 / 64) *100 = 1%

66. The amount of ROM needed to implement a 4-bit multiplier is

A. 64 bits
A ROM cannot be written. So, to implement a 4-bit multiplier we must store all the possible
B. 128 bits
combinations of 24×24 inputs and their corresponding 8 output bits giving a total
C. 1 Kbits
of 24×24×8 bits =2048 bits.
D. 2 Kbits

67. Formatting for a floppy disk refers to

A. arranging the data on the disk in contiguous fashion
B. writing the directory
C. erasing the system data
D. writing identification information on all tracks and sectors

68. Using a larger block size in a fixed block size file system leads to
A. better disk throughput but poorer disk space utilization
B. better disk throughput and better disk space utilization
C. poorer disk throughput but better disk space utilization
D. poorer disk throughput and poorer disk space utilization

69. Raid configurations of the disks are used to provide

A. Fault-tolerance
B. High speed
C. High data density
D. (A) & (B)

70. The data transfer rate of a double-density floppy disk system is about:
A. 5𝐾 bits/sec
B. 50𝐾 bits/sec
C. 500𝐾 bits/sec
D. 5000𝐾 bits/sec
71. Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 bytes of data are
stored in a bit serial manner in a sector. The capacity of the disk pack and the number of bits required to
specify a particular sector in the disk are respectively:
A. 256 Mbyte, 19 bits
B. 256 Mbyte, 28 bits Disk capacity = total number of surfaces * no. of tracks per surface *
amount of data per track
C. 512 Mbyte, 20 bits
D. 64 Gbyte, 28 bits 16 surfaces (4 bit) * 128 tracks per surface (7 bit) * 256 sectors per track
(8 bit) *512 bytes of data  256MB

and to specify a particular sector we do not need sector size, so bits

required = 4+7+8 = 19