Simplified Z80 System Architecture

I/O Port Addr 8 Address 16 Memory Addr

00 0000

Chapter 5 I/O Port

IORQ MEMRQ
RD Address
program
RD Z80 CPU Decoder
Decoder WR

……
WR
Z80 Computer System Design
8 8
data
data
FF FFFF

Minimum Z80 Computer System Minimum Z80 Computer System

• Consisting of Z80CPU, Oscillator, ROM, I/O
• Additional RAM is preferred
• Total starting cost for DIY ~500 THB
• Complete and ready to use board ~1,000 THB

• Z80CPU + RAM + ROM (Socket) + I/O Controller + Oscillator

• System extension via system bus connector
 Main memory Read-Only Memory (ROM)
• Memory
• µP can read instructions from ROM quickly
– Stores programs
– Provides data to the MPU • Cannot write new data to ROM
– Accepts result from the MPU for storage
• Main memory Types • ROM stores data, even after power cycled
– ROM : read only memory. Contains program (Firmware). does not
lose its contents when power is removed (Non-volatile) • When power is turned on, the microprocessor will start
– RAM: random access memory (read/write memory) used as fetching instructions from ROM (bootstrap )
variable data, loses contents when power is removed volatile.
When power up will contain random data values

Available ROMs ROM

• Masked ROM or just ROM A0 D0
• PROM or programmable ROM (one-time programmable) A1 D1
• EPROM (Erasable/Programmable ROM) m+1 bit A2 D2 n+1 bit
Ultra Violet (UV) light is used in erasing process Address Data
Am 2m+1 × (n + 1)
• Flash Dn
m +1
– re-writable about 10,000 times Capacity : 2 ROM
PROM
– usually must write a whole block not just 1 or 2 bytes,
EEPROM
– slow writing fast reading OE : Output Enable
• EEPROM (electrically erasable ROM) connect to RD of µP
– fast writing slow reading
– can program millions of times CE (CS ) : Chip Enable
to Address decoder CE OE
– useless for storing a program
– good for save configuration information.
 ROM Read Timing 27XX EPROM
U3

10 11
9 A0 O0 12
U1 U2 A1 O1
2 8
A2 O2
13
A0-Am 8
A0 O0
9 8
A0 O0
9
7
6 A3 O3
15
16
7 10 7 10 A4 O4
6 A1 O1 11 A1 O1 5 17
A2 O2 6 11 4 A5 O5 18
5 13 5 A2 O2 13 A6 O6
4 A3 O3 14 A3 O3 3 19
A4 O4 4 14 25 A7 O7
3 15 3 A4 O4 15 A8
A5 O5
4 D0-Dn 2
A6 O6
16 2 A5 O5 16
24
21 A9
1 17 1 A6 O6 17 A10
23 A7 O7 A7 O7 23
A8 23 2 A11
22 22 A8 A12
19 A9 A9
A10 19 22
21 A10 OE
20 A11 27
OE 20 PGM
1 18
CE 20 CE
CE 18 OE/VPP
1
21 CE VPP
VPP

2716 2732 2764

3 OE 16 kbit 32 kbit 64 kbit
2 kbyte 4 kbyte 8 kbyte
OE falls to data valid
Addr valid to data valid
* PGM and VPP are used to programming
* Defined by manufacturer

27XXX EPROM RAM (Random Access Memory)

U7
• µP can read the data from RAM quickly
U6 12 13
U4 U5 A0 D0

10 11 10 11
10
A0 O0
11
11
10 A1
A2
D1
D2
14
15 • µP can write new data to RAM quickly
A0 D0 A0 D0 9 12 9 17
9 12 9 12 A1 O1 A3 D3
8
7
A1
A2
D1
D2
13
15
8
7
A1
A2
D1
D2
13
15
8
7 A2
A3
O2
O3
13
15
8
7 A4
A5
D4
D5
18
19 • RAM is unable to store data if power is turned off
A3 D3 A3 D3 6 16 6 20
6 16 6 16 A4 O4 A6 D6
5
4
A4
A5
D4
D5
17
18
5
4
A4
A5
D4
D5
17
18
5
4 A5
A6
O5
O6
17
18
5
27 A7
A8
D7
21
• Two type is available :
A6 D6 A6 D6 3 19 26
3 19 3 19 A7 O7 A9
25
24
A7
A8
D7 25
24
A7
A8
D7 25
24 A8
A9
23
25 A10
A11
– Static RAM (SRAM): FF base, fast, expensive, low
A9 A9 21 4
21
23 A10
21
23 A10 23
2
A10
A11
28
29
A12
A13 cap/vol, applied for cache , no refresh
2 A11 2 A11 A12 A14
A12 A12 26 3
26
A13
26
27 A13 27
1
A13
A14
2 A15
A16 – Dynamic RAM (DRAM): capacitor base, slow , low cost
22 A14 A15
27
20
OE
PGM
22
20 OE 22
OE/VPP
24
31 OE
PGM
high capacity/volume , applied for main memory(pc) need
CE CE 20 22
1 1 28
CE
1
CE
refresh.
VPP VPP VCC VPP

27128 27256 27512 27010

128 kbit 256 kbit 512 kbit 1024 kbit
16 kbyte 32 kbyte 64 kbyte 128 kbyte
 RAM(Static)
Static RAM
A0 D0
A1 D1
m+1 bit A2 D2 n+1 bit
Address Data
Am 2m+1 × (n + 1)
Dn
m +1
Capacity : 2 RAM Data bus is
Bidirectional
RD : Read signal
connect to MemRD of µP
WR : Write signal
connect to MemWR of µP
CS : Chip Select CS WR RD

to Address decoder

Dynamic RAM Dynamic RAM

Write : Charge bit line HIGH or LOW and set word line HIGH

Read : Bit line is precharged to a voltage halfway
between HIGH and LOW and then the word line is set HIGH.

Sense Amp Detects change

Reads are destructive (Must follow with a write)

Address Buffer
 Z80 Memory connection Memory connection (cont.)

• CPU 16 bit address bus  64 k memory(max)

If only one RAM chip with Full size (64 kb capacity)
• CPU 8 bit data bus  8 bit data width
• Generally should be connected
– Data to data
D7~D0 D7~D0
– Address to address RAM
– WR to wr 64 kb
A15~A0 A15~A0
– RD to rd
RD WR CS
– MREQ to cs Z80
CPU
RD
WR

MREQ

Memory connection (cont.) Memory connection (cont.)

If RAM capacity is 32 kb

A15 is combined with MREQ

RAM address is from 0000h to 7FFFh • Given two 32K chips, how to obtain full 64K RAM address?
• Problem: Bus Conflict. The two memory chips will provide
data at the same time when microprocessor performs a
D7~D0 D7~D0 memory read.
RAM
32 kb
• Solution: Use address line A15 as an “arbiter”. If A15
A14~A0 A14~A0
outputs a logic “1” the upper memory is enabled (and the
lower memory is disabled) and vice-versa.
RD WR CS
Z80
CPU
RD
WR

A15 MREQ
 Memory connection (cont.) Memory connection (cont.)

There are two 32K RAM

A15 applied to select one RAM chip
32K ROM and 32K RAM

Two RAM area is from 0000h to 7FFFh
ROM doesn’t have WR signal
and 8000h to FFFFh

D7~D0 D7~D0 D7~D0 D7~D0 D7~D0 D7~D0

RAM RAM ROM RAM
32 kb 32 kb 32 kb 32 kb
A14~A0 A14~A0 A14~A0 A14~A0 A14~A0 A14~A0

RD WR CS RD WR CS OE CS RD WR CS
Z80 Z80
CPU CPU
RD RD
WR WR

A15 MREQ A15 MREQ

Memory connection (cont.) Address Bit Map

There are 4 memory chip Selects chip Selects location within chips
A14 and A15 are applied to chip selection
A15 to A0 AA AA AAAA AAAA AAAA
Memory
ROM RAM #1 RAM #2 RAM #3 (HEX) 11 11 1198 7654 3210
16 kb 16 kb 16 kb 16 kb Chip
54 32 10
0000h 00 00 0000 0000 0000
D7~D0 D7~D0 D7~D0 D7~D0 D7~D0
ROM
3FFFh 00 11 1111 1111 1111
A13~A0 A13~A0 A13~A0 A13~A0 A13~A0 4000h 01 00 0000 0000 0000
RAM1
Z80 OE CS RD WR CS RD WR CS RD WR CS
7FFFh 01 11 1111 1111 1111
CPU 8000h 10 00 0000 0000 0000
RD RAM2
WR
BFFFh 10 11 1111 1111 1111
A15
A14

MREQ En C000h 11 00 0000 0000 0000

S0 RAM3
S1 FFFFh 11 11 1111 1111 1111
 Memory Map Memory Map
0000h
• Represents the memory type ROM 0000h
• Address area of each memory chip 16k
• Empty area is neither writable nor readable ROM
3FFFh • Read op. returns FFh value (usualy)
• Empty area 3FFFh
4000h • Write op. can’t store any value on it
RAM1 4000h
Empty
ROM RAM #1 RAM #2 RAM #3 16k ROM RAM #2 RAM #3
16 kb 16 kb 16 kb 16 kb
7FFFh 16 kb 16 kb 16 kb

D7~D0 D7~D0 D7~D0 D7~D0 D7~D0 D7~D0 D7~D0 D7~D0 D7~D0

7FFFh
8000h
A13~A0 A13~A0 A13~A0 A13~A0 A13~A0 RAM2 A13~A0 A13~A0 A13~A0 A13~A0
8000h
OE CS RD WR CS RD WR CS RD WR CS
16k OE CS RD WR CS RD WR CS RAM2
BFFFh
RD
WR
RD
WR BFFFh
C000h
A15
A14

A15
A14
En En
MREQ
S0 RAM3 MREQ
S0
C000h
S1 S1

16k RAM3
FFFFh
FFFFh

Memory Map Full and Partial Decoding

• Full (exhaust) Decoding
• Empty area is neither writable nor readable
0000h – All of the address lines are connected to any
• Read op. returns FFh value (usualy)
ROM memory/device to perform selection
• Write op. can’t store any value on it
– Absolute address : any memory location has one
3FFFh address
4000h
ROM
16 kb
RAM #2 Empty
16 kb

• Partial Decoding
D7~D0 D7~D0 D7~D0 7FFFh
8000h – When some of the address lines are connected the
A13~A0 A13~A0

CS
A13~A0

WR CS
RAM memory/device to perform selection
OE RD

– Using this type of decoding results into roll-over

RD BFFFh
WR
C000h addresses (fold back or shading).
A15
A14

En

– roll-over address : any memory location has more

MREQ
S0 Empty
S1

than one address

FFFFh
 Partial Decoding Partial Decoding
0000h
RAM
• A15~A12 are not connected 0FFFh
• What is the memory map?
Every memory location has more than one address
1000h
RAM,
1FFFh

For example first RAM location has addresses: 2000h
RAM,
0000h 2FFFh
3000h
1000h RAM,
3FFFh
2000h
D7~D0 D7~D0 3000h Roll-over Address
RAM …………….
F000h
…………….
4 kb RAM,
F000h FFFFh
A11~A0 A11~A0
D7~D0 D7~D0
A15~A12 X RD WR CS RAM
AAAA AAAA AAAA AAAA Memory
4 kb
A15 to A0 A11~A0 A11~A0
1111 1198 7654 3210
Z80 RD
(HEX) Chip A15~A12 X RD WR CS
5432 10
CPU WR
X000h Z80
xxxx 0000 0000 0000 RD
WR
RAM CPU
MREQ
XFFFh xxxx 1111 1111 1111 MREQ

Partial Decoding Partial Decoding

• A12 only connected to RAM

• A13 has no connection
• What is the memory map? • 8 roll-over address for ROM
• 4 roll-over address for RAM

D7~D0 D7~D0 D7~D0

ROM RAM
4 kb 8 kb
A12~A0 A11~A0 A12~A0 D7~D0 D7~D0
AAAA AAAA AAAA AAAA
D7~D0 Memor
ROM RAM 1111 1198 7654 3210 y
OE CS RD WR CS
A13 X A12~A0 A11~A0
4 kb
A12~A0
8 kb
5432 10 Chip
0xxx 0000 0000 0000
Z80 RD
Z80 A13 X OE CS RD WR CS
ROM
CPU
CPU WR RD
WR
0xxx 1111 1111 1111
X0x0 0000 0000 0000
A15
A14

RAM
A15
A14

MREQ
MREQ
X0x1 1111 1111 1111
Partial Decoding 0000h 0000h ROM
Partial Decoding 0000h 0000h
0FFFh
ROM
0FFFh
RAM, 1000h ROM,
1000h
ROM, 1FFFh 1FFFh
1FFFh 1FFFh
2000h 2000h ROM,
2000h 2000h ROM, 2FFFh
2FFFh
3000h
D7~D0 D7~D0 D7~D0 RAM, 3000h
D7~D0 D7~D0 D7~D0 ROM,
ROM RAM
ROM, ROM RAM 3FFFh 3FFFh
3FFFh 3FFFh
4 kb 8 kb 4 kb 8 kb 4000h 4000h
ROM,
A12~A0 A11~A0 A12~A0 4000h 4000h ROM, A12~A0 A11~A0 A12~A0 4FFFh
RAM,
Z80 A13 X OE CS RD WR CS Conflict ROM,
4FFFh
5000h Z80 A13 X OE CS RD WR CS
5FFFh
5000h
5FFFh
ROM,
CPU 5FFFh 5FFFh CPU 6000h 6000h
RD 6000h 6000h RD ROM,
WR ROM, WR 6FFFh
6FFFh RAM, 7000h
ROM,
A15

A15
A14

A14
7000h ROM, 7FFFh
MREQ MREQ 7FFFh
7FFFh 7FFFh
8000h F000h
8000h F000h

RAM Conflict
AAAA AAAA AAAA AAAA Memory
AAAA AAAA AAAA AAAA Memory
9FFFh
9FFFh A000h
1111 1198 7654 3210 Chip
A000h 1111 1198 7654 3210 Chip
5432 10 RAM, 5432 10
BFFFh
0xxx 0000 0000 0000 4k BFFFh
C000h
0xxx 0000 0000 0000 4k C000h

ROM ROM RAM

0xxx 1111 1111 1111 0xxx 1111 1111 1111
DFFFh
X0x0 0000 0000 0000 8k DFFFh
E000h
X1x0 0000 0000 0000 8k E000h

RAM RAM RAM,

X0x1 1111 1111 1111 X1x1 1111 1111 1111
FFFFh
FFFFh FFFFh
FFFFh

Full (exhaustive) decoding Partial decoding

AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA

Memory Memory
1111 1198 7654 3210 1111 1198 7654 3210
Chip Chip
5432 10 A12~A0 A12~A0 5432 10 A12~A0 A12~A0
0000 0000 0000 0000 D7~D0 0000 0000 0000 0000 D7~D0
ROM 2764 ROM 2764
0001 1111 1111 1111 EPROM 0001 1111 1111 1111 EPROM
0010 0000 0000 0000 8k×
×8 001x x000 0000 0000 8k×
×8
RAM OE CE RAM OE CE
0010 0111 1111 1111 001x x111 1111 1111
D7~D0 D7~D0
RD RD
A13 C 0000h-07FFh A15 C 0000h-1FFFh
Y0 Y0
A12 B Y1 0800h-0FFFh A14 B Y1 2000h-3FFFh
A11 A Y2 1000h-17FFh 7421 A13 A Y2
1800h-1FFFh
A10~A0 A10~A0 A10~A0 A10~A0
74138 Y3 D7~D0 74138 Y3 D7~D0
2000h-27FFh 6116 6116
Y4 RWM Y4 RWM
A15 G2A Y5 2k×
×8 MREQ G2A Y5 2k×
×8

A14 G2B Y6 RD WR CS GND G2B Y6 RD WR CS

MREQ G1 Y7 VCC G1 Y7

RD WR RD WR
 Z80 Timing (revisited) Z80 Timing (revisited)
Opcode Fetch

The Z80 CPU executes instructions by stepping through a precise set of
basic operations. These include:
• Memory Read or Write
• I/O Device Read or Write
• Interrupt Acknowledge

Three to six clock periods are required to complete each operations

Number of clocks used in each operation can be extended to synchronize
the CPU to the speed of external devices.

WAIT signal can be

asserted to extend
the M1 cycle

Z80 Timing (revisited) Z80 Timing (revisited)

Wait State Memory Read
• WAIT signal is sampled at the falling edge of T2 * TW isis inserted
asserted
if WAIT
• If it is asserted, wait state (Tw) is inserted until WAIT signal is
removed
 Z80 Timing (revisited)
Memory Write Adding One Wait State to an M1 Cycle
* TW isis inserted
asserted
if WAIT

Memory is a way of holding onto the things you love,

the things you are, the things you never want to lose.

~From the television show The Wonder Years