XMC Spi

1 /**
2 * @file xmc_spi.h
3 * @date 2015-06-20
4 *
5 * @cond
6
************************************************************************************
*********************************
7 * XMClib v2.0.0 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list
of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the
distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be
used to endorse or promote
22 * products derived from this software without specific prior written
permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share
modifications, enhancements or bug fixes with
33 * Infineon Technologies AG
[email protected]).
34
*************************************************************************************
********************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-02-20:
40 * - Initial
41 *
42 * 2015-05-20:
43 * - Documentation improved 
44 * - Added XMC_SPI_CH_SetSlaveSelectDelay(), XMC_SPI_CH_TriggerServiceRequest()
and
45 * XMC_SPI_CH_SelectInterruptNodePointer() 
46 * - Added XMC_SPI_CH_SetInterwordDelaySCLK() 
47 *
48 * 2015-06-20:
49 * - Removed version macros and declaration of GetDriverVersion API
50 * @endcond
51 *
52 */
53
54 #ifndef XMC_SPI_H
55 #define XMC_SPI_H
56
57 /*************************************************************************************
*********************************
58 * HEADER FILES
59
*************************************************************************************
********************************/
60 #include "xmc_usic.h"
61
62 /**
63 * @addtogroup XMClib XMC Peripheral Library
64 * @{
65 */
66
67 /**
68 * @addtogroup SPI
69 * @brief Synchronous serial channel driver for SPI-like communication.
70 *
71 * The SPI driver uses Universal Serial Interface Channel(USIC) module.
72 * The USIC module supports multiple data lines for SPI communication. \n
73 * -# Full duplex communication with 2 separate lines for transmission and reception.
74 * -# Half duplex communication with 1 common line shared for transmission and
reception.
75 * -# Dual mode communication with 2 common lines shared for transmission and
reception.
76 * -# Quad mode communication with 4 common lines shared for transmission and
reception. 
77 *
78 * SPI driver provides structures, enumerations and APIs for configuring the USIC
channel for SPI communication
79 * and also for data transaction. 
80 * SPI driver features:
81 * -# Configuration structure XMC_SPI_CH_CONFIG_t and SPI initialization function
XMC_SPI_CH_Init()
82 * -# Allows configuration of protocol word and frame length using
XMC_SPI_CH_SetWordLength(), XMC_SPI_CH_SetFrameLength()
83 * -# Allows manipulation of data frame at runtime using XMC_SPI_CH_EnableSOF(),
XMC_SPI_CH_EnableEOF(),
84 XMC_SPI_CH_EnableSlaveSelect(), XMC_SPI_CH_DisableSlaveSelect()
85 * -# Provides APIs for transmitting data and receiving data using
XMC_SPI_CH_Transmit(), XMC_SPI_CH_Receive(), XMC_SPI_CH_GetReceivedData()
86 * -# Allows configuration of shift clock using XMC_SPI_CH_ConfigureShiftClockOutput()
87 * -# Provides enumeration of SPI protocol events using @ref XMC_SPI_CH_STATUS_FLAG_t
88 * @{
89 */
90
91 /*************************************************************************************
**********************************
92 * MACROS
93
*************************************************************************************
*********************************/
94
95 #if defined(USIC0)
96 #define XMC_SPI0_CH0 XMC_USIC0_CH0 /**< SPI0 channel 0 base address */
98 #endif
99
103 #endif
104
108 #endif
109
110 /*************************************************************************************
**********************************
111 * ENUMS
112
*************************************************************************************
**********************************/
113
114 /**
115 * Defines return status of SPI driver APIs
116 */
117 typedef enum XMC_SPI_CH_STATUS
118 {
119 XMC_SPI_CH_STATUS_OK, /**< Status of the Module: OK */
120 XMC_SPI_CH_STATUS_ERROR, /**< Status of the Module: ERROR */
121 XMC_SPI_CH_STATUS_BUSY /**< The Module is busy */
122 } XMC_SPI_CH_STATUS_t;
123 /**
124 * Defines the SPI bus mode
125 */
126 typedef enum XMC_SPI_CH_BUS_MODE
127 {
128 XMC_SPI_CH_BUS_MODE_MASTER, /**< SPI Master */
129 XMC_SPI_CH_BUS_MODE_SLAVE /**< SPI Slave */
130 } XMC_SPI_CH_BUS_MODE_t;
131
132 /**
133 * Defines the Polarity of the slave select signals SELO[7:0] in relation to the
master slave select signal MSLS.
134 */
135 typedef enum XMC_SPI_CH_SLAVE_SEL_MSLS_INV
136 {
137 XMC_SPI_CH_SLAVE_SEL_SAME_AS_MSLS = 0x0UL, /**< The SELO outputs have the same
polarity as the MSLS signal
138 (active high) */
139 XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS = 0x1UL << USIC_CH_PCR_SSCMode_SELINV_Pos /**< The
SELO outputs have the inverted
140
polarity to the MSLS signal
141
(active low)*/
142 } XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t;
143
144 /**
145 * Defines the Polarity of the data inputs.
146 */
147 typedef enum XMC_SPI_CH_DATA_POLARITY
148 {
149 XMC_SPI_CH_DATA_POLARITY_DIRECT = 0x0UL, /**< The polarity of the data line is not
inverted */
150 XMC_SPI_CH_DATA_POLARITY_INVERT = 0x1UL << USIC_CH_DX2CR_DPOL_Pos /**< The polarity
of the data line is inverted */
151 } XMC_SPI_CH_DATA_POLARITY_t;
152
153 /**
154 * Defines Slave Select lines
155 */
156 typedef enum XMC_SPI_CH_SLAVE_SELECT
157 {
158 XMC_SPI_CH_SLAVE_SELECT_0 = 1UL << USIC_CH_PCR_SSCMode_SELO_Pos, /**< Slave Select
line 0 */
line 1 */
line 2 */
line 3 */
line 4 */
line 5 */
line 6 */
165 XMC_SPI_CH_SLAVE_SELECT_7 = 128UL << USIC_CH_PCR_SSCMode_SELO_Pos /**< Slave Select
line 7 */
166 } XMC_SPI_CH_SLAVE_SELECT_t;
167
168 /**
169 * Defines SPI specific events
170 */
171 typedef enum XMC_SPI_CH_EVENT
172 {
173 XMC_SPI_CH_EVENT_RECEIVE_START = (int32_t)(0x80000000U | USIC_CH_CCR_RSIEN_Msk
), /**< Receive start event */
174 XMC_SPI_CH_EVENT_DATA_LOST = (int32_t)(0x80000000U | USIC_CH_CCR_DLIEN_Msk
), /**< Data lost event */
175 XMC_SPI_CH_EVENT_TRANSMIT_SHIFT = (int32_t)(0x80000000U | USIC_CH_CCR_TSIEN_Msk
), /**< Transmit shift event */
176 XMC_SPI_CH_EVENT_TRANSMIT_BUFFER = (int32_t)(0x80000000U | USIC_CH_CCR_TBIEN_Msk
), /**< Transmit buffer event */
177 XMC_SPI_CH_EVENT_STANDARD_RECEIVE = (int32_t)(0x80000000U | USIC_CH_CCR_RIEN_Msk
), /**< Receive event */
178 XMC_SPI_CH_EVENT_ALTERNATIVE_RECEIVE = (int32_t)(0x80000000U | USIC_CH_CCR_AIEN_Msk
), /**< Alternate receive event */
179 XMC_SPI_CH_EVENT_BAUD_RATE_GENERATOR = (int32_t)(0x80000000U |
USIC_CH_CCR_BRGIEN_Msk), /**< Baudrate generator event */
180
181 XMC_SPI_CH_EVENT_PARITY_ERROR = USIC_CH_PCR_SSCMode_PARIEN_Msk, /**< Parity
error event */
182 XMC_SPI_CH_EVENT_MSLS_CHANGE = USIC_CH_PCR_SSCMode_MSLSIEN_Msk, /**< Master
slave select(MSLS) output transition event*/
183 XMC_SPI_CH_EVENT_DX2TIEN_ACTIVATED = USIC_CH_PCR_SSCMode_DX2TIEN_Msk /**< Slave
select input signal transition event*/
184 } XMC_SPI_CH_EVENT_t;
185
186 /**
187 * Defines SPI event status
188 */
189 typedef enum XMC_SPI_CH_STATUS_FLAG
190 {
191 XMC_SPI_CH_STATUS_FLAG_MSLS = USIC_CH_PSR_SSCMode_MSLS_Msk,
/**< Status of Master slave
192
select(MSLS) signal */
193 XMC_SPI_CH_STATUS_FLAG_DX2S = USIC_CH_PSR_SSCMode_DX2S_Msk,
/**< Status of slave select
194
input(DX2) signal*/
195 XMC_SPI_CH_STATUS_FLAG_MSLS_EVENT_DETECTED = USIC_CH_PSR_SSCMode_MSLSEV_Msk,
/**< Status for master slave select
196
output signal transition*/
197 XMC_SPI_CH_STATUS_FLAG_DX2T_EVENT_DETECTED = USIC_CH_PSR_SSCMode_DX2TEV_Msk,
/**< Status for slave select
198
input signal transition */
199 XMC_SPI_CH_STATUS_FLAG_PARITY_ERROR_EVENT_DETECTED = USIC_CH_PSR_SSCMode_PARERR_Msk,
/**< Indicates status of the
200
parity error */
201 XMC_SPI_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_SSCMode_RSIF_Msk,
/**< Status for receive start
202
event */
203 XMC_SPI_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_SSCMode_DLIF_Msk,
/**< Status for data lost event*/
204 XMC_SPI_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_SSCMode_TSIF_Msk,
/**< Status for transmit shift
205
event */
206 XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_SSCMode_TBIF_Msk,
/**< Status for transmit buffer
207
event */
208 XMC_SPI_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_SSCMode_RIF_Msk,
/**< Status for receive event */
209 XMC_SPI_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_SSCMode_AIF_Msk,
/**< Status for alternative
210
receive event */
211 XMC_SPI_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION =
USIC_CH_PSR_SSCMode_BRGIF_Msk/**< Status for baud rate
212
generation error event */
213 } XMC_SPI_CH_STATUS_FLAG_t;
214
215 /**
216 * Defines input frequency sources for slave select signal delay configuration.
217 */
218 typedef enum XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY
219 {
220 XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FPDIV = 0x0UL, /**< Output of PDIV
divider: FPDIV */
221 XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FPPP = 0x1UL <<
USIC_CH_PCR_SSCMode_CTQSEL1_Pos, /**< Peripheral clock: FPPP */
222 XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FSCLK = 0x2UL <<
USIC_CH_PCR_SSCMode_CTQSEL1_Pos, /**< Shift clock: FSCLK */
223 XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FMCLK = 0x3UL <<
USIC_CH_PCR_SSCMode_CTQSEL1_Pos /**< Master clock: FMCLK */
224 } XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_t;
225
226 /**
227 * Define data and clock input stages
228 */
229 typedef enum XMC_SPI_CH_INPUT
230 {
231 XMC_SPI_CH_INPUT_DIN0 = 0UL, /**< Data input stage 0 */
232 XMC_SPI_CH_INPUT_SLAVE_SCLKIN = 1UL, /**< Clock input stage */
233 XMC_SPI_CH_INPUT_SLAVE_SELIN = 2UL, /**< Slave select input stage */
236 XMC_SPI_CH_INPUT_DIN3 = 5UL /**< Data input stage 3 */
237 } XMC_SPI_CH_INPUT_t;
238
239 /**
240 * Define SPI data transfer mode
241 */
242 typedef enum XMC_SPI_CH_MODE
243 {
244 XMC_SPI_CH_MODE_STANDARD = 0UL, /**< SPI standard full duplex mode */
245 XMC_SPI_CH_MODE_STANDARD_HALFDUPLEX = 4UL, /**< SPI standard half duplex mode */
246 XMC_SPI_CH_MODE_DUAL= 6UL, /**< SPI half duplex mode with dual data
lines */
247 XMC_SPI_CH_MODE_QUAD= 7UL /**< SPI half duplex mode with quad data
lines */
248 } XMC_SPI_CH_MODE_t;
249
250
251 /**
252 * SPI Baudrate Generator shift clock passive level
253 */
254 typedef enum XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL
255 {
256 /**< Passive clock level 0, delay disabled */
257 XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED =
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED,
258 /**< Passive clock level 1, delay disabled */
259 XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED =
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED,
260 /**< Passive clock level 0, delay enabled */
261 XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED =
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED,
262 /**< Passive clock level 1, delay enabled */
263 XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED =
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED
264 } XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t;
265
266 /**
267 * SPI Baudrate Generator shift clock output
268 */
269 typedef enum XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT
270 {
271 XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK,
/**< Baudrate Generator shift clock output: SCLK*/
272 XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1
/**< Clock obtained as input from master: DX1*/
273 } XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t;
274
275 /**
276 * SPI channel interrupt node pointers
277 */
278 typedef enum XMC_SPI_CH_INTERRUPT_NODE_POINTER
279 {
280 XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT =
XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit
shift interrupt */
281 XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER =
XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit
buffer interrupt */
282 XMC_SPI_CH_INTERRUPT_NODE_POINTER_RECEIVE =
XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive
interrupt */
283 XMC_SPI_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE =
XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for
alternate receive interrupt */
284 XMC_SPI_CH_INTERRUPT_NODE_POINTER_PROTOCOL =
XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol
related interrupts */
285 } XMC_SPI_CH_INTERRUPT_NODE_POINTER_t;
286
287 /*************************************************************************************
*********************************
288 * DATA STRUCTURES
289 **************************************************************************************
********************************/
290
291 /**
292 * Structure for initializing SPI channel.
293 */
294 typedef struct XMC_SPI_CH_CONFIG
295 {
296 uint32_t baudrate; /**< Module baud rate for
communication */
297 XMC_SPI_CH_BUS_MODE_t bus_mode; /**< Bus mode: Master/Slave */
298 XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t selo_inversion; /**< Enable inversion of Slave
select signal relative to the internal
299 MSLS signal */
300 XMC_USIC_CH_PARITY_MODE_t parity_mode; /**< Enable parity check for
transmit and received data */
301 } XMC_SPI_CH_CONFIG_t;
302
303 /*************************************************************************************
*********************************
304 * API PROTOTYPES
305
*************************************************************************************
********************************/
306
307 #ifdef __cplusplus
308 extern "C" {
309 #endif
310
311 /**
312 * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel
base address.
313 * @param config pointer to constant SPI channel configuration data structure.\n
314 * Refer data structure @ref XMC_SPI_CH_CONFIG_t for detail.
315 *
316 * @return None
317 *
318 * \parDescription: 
319 * Initializes the selected SPI \a channel with the \a config structure.\n\n
320 * Enable SPI channel by calling XMC_USIC_CH_Enable() and then configures
321 * <ul>
322 * <li>Baudrate,</li>
323 * <li>Passive data level as active high,</li>
324 * <li>Shift control signal as active high,</li>
325 * <li>Frame length as 64U,</li>
326 * <li>Word length as 8U,</li>
327 * <li>Enable Hardware port control mode,</li>
328 * <li>Enable transmission of data TDV(Transmit data valid) bit is set to 1,</li>
329 * <li>Enable invalidation of data in TBUF once loaded into shift register,</li>
330 * <li>Parity mode settings</li>
331 * </ul>
332 * And if master mode is selected,
333 * <ul>
334 * <li>Enables MSLS signal generation,</li>
335 * <li>configures slave selection as normal mode,</li>
336 * <li>Set polarity for the Slave signal,</li>
337 * <li>Enable Frame end mode(MSLS signal is kept active after transmission of a
frame)</li>
338 * </ul>
339 */
340 void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const
config);
341
342 /**
base address.
344 *
345 * @return None
346 *
348 * Set the selected USIC channel to operate in SPI mode, by setting CCR.MODE bits.\n\n
349 * It should be executed after XMC_SPI_CH_Init() during initialization. By invoking
XMC_SPI_CH_Stop(), the MODE is set
350 * to IDLE state. Call XMC_SPI_CH_Start() to set the SPI mode again, as needed later
in the program.
351 *
352 * \parRelated APIs: 
353 * XMC_SPI_CH_Init(), XMC_SPI_CH_Stop()
354 */
355 __STATIC_INLINE void XMC_SPI_CH_Start(XMC_USIC_CH_t *const channel)
356 {
357 /* USIC channel in SPI mode */
358 XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_SPI);
359 }
360
361 /**
base address.
363 *
364 * @return XMC_SPI_CH_STATUS_t Status of the SPI driver after the request for
stopping is processed. \n
365 * XMC_SPI_CH_STATUS_OK- If the USIC channel is successfully put to IDLE mode.
\n
366 * XMC_SPI_CH_STATUS_BUSY- If the USIC channel is busy transmitting data.
367 *
369 * Set the selected SPI channel to IDLE mode, by clearing CCR.MODE bits.\n\n
370 * After calling XMC_SPI_CH_Stop, channel is IDLE mode. So no communication is
supported. XMC_SPI_CH_Start() has to be
371 * invoked to start the communication again.
372 *
374 * XMC_SPI_CH_Start()
375 */
376 XMC_SPI_CH_STATUS_t XMC_SPI_CH_Stop(XMC_USIC_CH_t *const channel);
377
378 /**
base address.
380 * @param rate Bus speed in bits per second
381 *
382 * @return XMC_SPI_CH_STATUS_t Status of the SPI driver after the request for setting
baudrate is processed. \n
383 * XMC_SPI_CH_STATUS_OK- If the baudrate is successfully changed. \n
384 * XMC_SPI_CH_STATUS_ERROR- If the new baudrate value is out of range.
385 *
387 * Sets the bus speed in bits per second
388 *
390 * XMC_SPI_CH_Init(), XMC_SPI_CH_Stop()
391 */
392 XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const
uint32_t rate);
393
394 /**
base address.
396 * @param slave Slave select signal.\n
397 * Refer @ref XMC_SPI_CH_SLAVE_SELECT_t for valid values.
398 *
399 * @return None
400 *
402 * Enable the selected slave signal by setting PCR.SELO bits.\n\n
403 * Each slave is connected with one slave select signal. This is not configured in
XMC_SPI_CH_Init(). Invoke
404 * XMC_SPI_CH_EnableSlaveSelect() with required \a slave to to start the
communication. After finishing the
405 * communication XMC_SPI_CH_DisableSlaveSelect() can be invoked to disable the slaves.
406 *
408 * XMC_SPI_CH_DisableSlaveSelect()
409 */
410 void XMC_SPI_CH_EnableSlaveSelect(XMC_USIC_CH_t *const channel, const
XMC_SPI_CH_SLAVE_SELECT_t slave);
411
412 /**
413 * @param channel A constant ponter to XMC_USIC_CH_t, pointing to the USIC channel
base address.
414 *
415 * @return None
416 *
418 * Disable all the slave signals by clearing PCR.SELO bits.\n\n
419 * XMC_SPI_CH_EnableSlaveSelect() has to be invoked to start the communication with
the desired slave again.
420 *
422 * XMC_SPI_CH_EnableSlaveSelect()
423 */
424 void XMC_SPI_CH_DisableSlaveSelect(XMC_USIC_CH_t *const channel);
425
426 /**
base address.
428 * @param data Data to be transmitted
429 * @param mode Communication mode of the SPI, based on this mode TCI(Transmit control
information)is updated.\n
430 * Refer @ref XMC_SPI_CH_MODE_t for valid values.
431 *
432 * @return None
433 *
435 * Puts the data into FIFO, if FIFO mode is enabled or else into standard buffer, by
setting the proper mode.\n\n
436 * In Dual and Quad modes, hardware port control(CCR.HPCEN) mode is enabled. By
enabling this the direction of the data
437 * pin is updated by hardware itself. TCI(Transmit Control Information) allows
dynamic control of both the data shift mode
438 * and pin direction during data transfers by writing to SCTR.DSM and SCTR.HPCDIR bit
fields. To support this auto
439 * update, TCSR.HPCMD(Hardware Port control) will be enabled during the
initialization using XMC_SPI_CH_Init() for all modes.
440 *
441 *
443 * XMC_SPI_CH_Receive()
444 */
445 void XMC_SPI_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const
XMC_SPI_CH_MODE_t mode);
446
447 /**
base address.
449 * @param mode Communication mode of the SPI, based on this mode TCI(Transmit control
information)is updated.\n
450 * Refer @ref XMC_SPI_CH_MODE_t for valid values.
451 *
452 * @return None
453 *
455 * Transmits a dummy data(FFFFH) to provide clock for slave and receives the data
from the slave.\n\n
456 * XMC_SPI_CH_Receive() receives the data and places it into buffer based on the FIFO
selection. After reception of data
457 * XMC_SPI_CH_GetReceivedData() can be invoked to read the data from the buffers.
458 *
460 * XMC_SPI_CH_GetReceivedDaa()
461 */
462 __STATIC_INLINE void XMC_SPI_CH_Receive(XMC_USIC_CH_t *const channel, const
XMC_SPI_CH_MODE_t mode)
463 {
464 /* Transmit dummy data */
465 XMC_SPI_CH_Transmit(channel, (uint16_t)0xffffU, (XMC_SPI_CH_MODE_t)((uint16_t)mode &
0xfffbU));
466 }
467
468 /**
base address.
470 *
471 * @return uint16_t Data read from the receive buffer.
472 *
474 * Reads data from the receive buffer based on the FIFO selection.\n\n
475 * Invocation of XMC_SPI_CH_Receive() receives the data and place it into receive
buffer. After receiving the data
476 * XMC_SPI_CH_GetReceivedData() can be used to read the data from the buffer.
477 *
479 * XMC_SPI_CH_Receive()
480 */
481 uint16_t XMC_SPI_CH_GetReceivedData(XMC_USIC_CH_t *const channel);
482
483 /**
base address.
485 *
486 * @return None
487 *
489 * Set the order of data transfer from LSB to MSB, by clearing SCTR.SDIR bit.\n\n
490 * This is typically based on the slave settings. Invoke
XMC_SPI_CH_SetBitOrderLsbFirst() to set direction as needed in
491 * the program.
492 *
494 * XMC_SPI_CH_SetBitOrderMsbFirst()
495 */
496 __STATIC_INLINE void XMC_SPI_CH_SetBitOrderLsbFirst(XMC_USIC_CH_t *const channel)
497 {
498 channel->SCTR &= (uint32_t)~USIC_CH_SCTR_SDIR_Msk;
499 }
500
501 /**
base address.
503 *
504 * @return None
505 *
507 * Set the order of data transfer from MSB to LSB, by setting SCTR.SDIR bit.\n\n
508 * This is typically based on the slave settings. This is not set during
XMC_SPI_CH_Init().
509 * Invoke XMC_SPI_CH_SetBitOrderMsbFirst() to set direction as needed in the program.
510 *
512 * XMC_SPI_CH_SetBitOrderLsbFirst()
513 */
514 __STATIC_INLINE void XMC_SPI_CH_SetBitOrderMsbFirst(XMC_USIC_CH_t *const channel)
515 {
516 channel->SCTR |= (uint32_t)USIC_CH_SCTR_SDIR_Msk;
517 }
518
519 /**
base address.
521 * @param event Protocol events which have to be enabled.
522 * Refer @ XMC_SPI_CH_EVENT_t for valid values. OR combinations
of these enum items can be used
523 * as input.
524 *
525 * @return None
526 *
528 * Enables the SPI protocol specific events, by configuring PCR register.\n\n
529 * Events can be enabled as needed using XMC_SPI_CH_EnableEvent().
530 * XMC_SPI_CH_DisableEvent() can be used to disable the events.
531 *
533 * XMC_SPI_CH_DisableEvent()
534 */
535 void XMC_SPI_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
536
537 /**
base address.
539 * @param event Protocol events which have to be disabled.
540 * Refer @ XMC_SPI_CH_EVENT_t for valid values. OR combinations
of these enum item can be used
541 * as input.
542 *
543 * @return None
544 *
546 * Disables the SPI protocol specific events, by configuring PCR register.\n\n
547 * After disabling the events, XMC_SPI_CH_EnableEvent() has to be invoked to
re-enable the events.
548 *
550 * XMC_SPI_CH_EnableEvent()
551 */
552 void XMC_SPI_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
553
554 /**
base address.
556 *
557 * @return uint32_t Status of SPI protocol events.
558 *
560 * Returns the status of the events, by reading PSR register.\n\n
561 * This indicates the status of the all the events, for SPI communication.
562 *
564 * XMC_SPI_CH_ClearStatusFlag()
565 */
566 __STATIC_INLINE uint32_t XMC_SPI_CH_GetStatusFlag(XMC_USIC_CH_t *const channel)
567 {
568 return channel->PSR_SSCMode;
569 }
570
571 /**
base address.
573 * @param flag Protocol event status to be cleared for detection of next occurence.
574 * Refer @ XMC_SPI_CH_STATUS_FLAG_t for valid values. OR
combinations of these enum item can be used
575 * as input.
576 * @return None
577 *
579 * Clears the events specified, by setting PSCR register.\n\n
580 * During communication the events occurred have to be cleared to detect their next
occurence.\n
581 * e.g: During transmission Transmit buffer event occurs to indicating data word
transfer has started. This
582 * event has to be cleared after transmission of each data word. Otherwise next
event cannot be recognized.
583 *
585 * XMC_SPI_CH_GetStatusFlag()
586 */
587 __STATIC_INLINE void XMC_SPI_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const
uint32_t flag)
588 {
589 channel->PSCR |= flag;
590 }
591
592 /**
base address.
594 *
595 * @return None
596 *
598 * Enables the generation of Master clock by setting PCR.MCLK bit.\n\n
599 * This clock can be used as a clock reference for external devices. This is not
enabled during initialization in
600 * XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_EnableMasterClock() to enable as needed in
the program, or if it is disabled by
601 * XMC_SPI_CH_DisableMasterClock().
602 *
604 * XMC_SPI_CH_DisableMasterClock()
605 */
606 __STATIC_INLINE void XMC_SPI_CH_EnableMasterClock(XMC_USIC_CH_t *const channel)
607 {
608 channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_MCLK_Msk;
609 }
610
611 /**
base address.
613 *
614 * @return None
615 *
617 * Disables the generation of Master clock by clearing PCR.MCLK bit.\n\n
618 * This clock can be enabled by invoking XMC_SPI_CH_EnableMasterClock() as needed in
the program.
619 *
621 * XMC_SPI_CH_EnableMasterClock()
622 */
623 __STATIC_INLINE void XMC_SPI_CH_DisableMasterClock(XMC_USIC_CH_t *const channel)
624 {
625 channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_MCLK_Msk;
626 }
627
628 /**
base address.
630 *
631 * @return None
632 *
634 * Enables the delay after each word, by setting PCR.TIWEN bit.\n\n
635 * The inter word delay starts at the end of last SCLK cycle of data word. During
this time no clock pulses are
636 * generated and MSLS signal stays active. If inter word delay is not enabled, last
data bit of a data word is directly
637 * followed by the first data bit of the next data word. This is not enabled in
XMC_SPI_CH_Init(). To enable
638 * XMC_SPI_CH_EnableInterwordDelay() has to be invoked as needed in the program. And
can be disabled by invoking
639 * XMC_SPI_CH_DisableInterwordDelay().
640 *
642 * XMC_SPI_CH_DisableInterwordDelay()
643 */
644 __STATIC_INLINE void XMC_SPI_CH_EnableInterwordDelay(XMC_USIC_CH_t *const channel)
645 {
646 channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_TIWEN_Msk;
647 }
648
649 /**
base address.
651 *
652 * @return None
653 *
655 * Disables the delay after after each word, by clearing PCR.TIWEN bit.\n\n
656 * So the last data bit of a data word is directly followed by the first data bit of
the next data word. If needed can
657 * be enabled by invoking XMC_SPI_CH_EnableInterwordDelay().
658 *
660 * XMC_SPI_CH_EnableInterwordDelay()
661 */
662 __STATIC_INLINE void XMC_SPI_CH_DisableInterwordDelay(XMC_USIC_CH_t *const channel)
663 {
664 channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_TIWEN_Msk;
665 }
666
667 /**
base address.
669 * @param tinterword_delay_ns delay in terms of nano seconds.
670 *
671 * @return None
672 *
674 * Configures the inter word delay by setting PCR.PCTQ1, PCR.DCTQ1 bit fields.\n\n
675 * The inter word delay is dependent on the peripheral clock. The maximum possible
value is calculated by using the
676 * below formula\n
677 * Maximum inter word delay = ((1 + PCTQ1_max)(1 + DCTQ1_max)) /
peripheral clock\n
678 * where PCTQ1_max = 3 and DCTQ1_max = 31\n
679 * After configuring the inter word delay, this has to be enabled by invoking
XMC_SPI_CH_EnableInterwordDelay().
680 *
682 * XMC_SPI_CH_EnableInterwordDelay(),XMC_SPI_CH_SetInterwordDelaySCLK()
683 */
684 void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel,uint32_t
tinterword_delay_ns);
685
686 /**
base address.
688 * @param sclk_period in terms of clk cycles.
689 *
690 * @return None
691 *
693 * Configures the inter word delay by setting PCR.DCTQ1 bit fields.\n\n
694 * This delay is dependent on the peripheral clock. The maximum possible value
supported by this API
695 * is 32 clock cycles.
696 * After configuring the inter word delay, this has to be enabled by invoking
XMC_SPI_CH_EnableInterwordDelay().
697 *
699 * XMC_SPI_CH_EnableInterwordDelay(),XMC_SPI_CH_EnableInterwordDelay()
700 */
701 __STATIC_INLINE void XMC_SPI_CH_SetInterwordDelaySCLK(XMC_USIC_CH_t *const channel,
uint32_t sclk_period)
702 {
703 channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode) & (~(
USIC_CH_PCR_SSCMode_DCTQ1_Msk |
704
USIC_CH_PCR_SSCMode_PC
TQ1_Msk |
705
USIC_CH_PCR_SSCMode_CT
QSEL1_Msk))) |
706 (((sclk_period - 1U) << USIC_CH_PCR_SSCMode_DCTQ1_Pos) |
707 (0x02U << USIC_CH_PCR_SSCMode_CTQSEL1_Pos));
708 }
709
710 /**
base address.
712 * @param sclk_period delay in terms of sclk clock cycles.
713 *
714 * @return None
715 *
717 * Configures the leading/trailing delay by setting BRG.DCTQ bit field.\n\n
718 * This delay is dependent on the peripheral clock. The maximum possible value
supported by this API
719 * is 30 clock cycles.
720 *
721 */
722 __STATIC_INLINE void XMC_SPI_CH_SetSlaveSelectDelay(XMC_USIC_CH_t *const channel,
uint32_t sclk_period)
723 {
724
725 channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk |
726 USIC_CH_BRG_PCTQ_Msk)) |
727 (((sclk_period - 1U) << USIC_CH_BRG_DCTQ_Pos) | (0x01U <<
USIC_CH_BRG_PCTQ_Pos));
728 }
729
730 /**
base address.
732 *
733 * @return None
734 *
736 *
737 * Configure to keep MSLS(Slave select signal) active even after finishing the
current data frame,
738 * by setting PCR.FEM bit.\n\n
739 * This is typically used during the transmission of multi-data word frames, where
there is possibility of delay in
740 * delivering the data. Frame end mode is enabled in XMC_SPI_CH_Init() during
initialization. To disable
741 * XMC_SPI_CH_DisableFEM() can be invoked as needed in the program.
742 *
744 * XMC_SPI_CH_DisableFEM()
745 */
746 __STATIC_INLINE void XMC_SPI_CH_EnableFEM(XMC_USIC_CH_t *const channel)
747 {
748 channel->PCR_SSCMode |= (uint32_t)USIC_CH_PCR_SSCMode_FEM_Msk;
749 }
750
751 /**
base address.
753 *
754 * @return None
755 *
757 * Configure to disable the MSLS(Slave select signal) if the current data frame is
considered as finished,
758 * by setting PCR.FEM bit.\n\n
759 *
760 * When the last bit of a data word has been sent out and the transmit buffer TBUF
does not contain new data, is
761 * considered as frame is ended and MSLS(Slave select signal) is disabled.
762 *
764 * XMC_SPI_CH_EnableFEM()
765 */
766 __STATIC_INLINE void XMC_SPI_CH_DisableFEM(XMC_USIC_CH_t *const channel)
767 {
768 channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_FEM_Msk;
769 }
770
771 /**
base address.
773 * @param passive_level polarity and delay of the selected shift clock.\n
774 * Refer @ref XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t for
valid inputs.
775 * @param clock_output shift clock source.\n
776 * Refer @ref XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t for valid
inputs.
777 *
778 * @return None
779 *
781 * Configures the shift clock source with the selected polarity and delay by setting
BRG.SCLKOSEL and BRG.SCLKCFG.\n\n
782 * In Master mode operation, shift clock is generated by the internal baud rate
generator. This SCLK is made available
783 * for external slave devices by SCLKOUT signal.\n
784 * In Slave mode, the signal is received from the external master. So the DX1(input)
stage has to be connected to input.\n
785 * The shift clock output(SCLKOUT) signal polarity can be set relative to SCLK, with
the delay of half the shift clock
786 * period. These settings are applicable only in master mode.
787 */
788 __STATIC_INLINE void XMC_SPI_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel
,
789 const
XMC_SPI_CH_BRG_SHIFT_CLOCK_P
ASSIVE_LEVEL_t passive_level
,
790 const
XMC_SPI_CH_BRG_SHIFT_CLOCK_O
UTPUT_t clock_output)
791 {
792 XMC_USIC_CH_ConfigureShiftClockOutput(channel, (
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t)passive_level,
793 (XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t)
clock_output);
794 }
795
796 /**
base address.
798 * @param word_length Number of bits to be configured for a data word. \n
799 * \b Range: 1 to 16.
800 *
801 * @return None
802 *
803 * \parDescription 
804 * Defines the data word length.\n\n
805 * Sets the number of bits to represent a data word. Frame length should be a
multiple of word length.
806 *
808 * XMC_SPI_CH_SetFrameLength()
809 */
810 __STATIC_INLINE void XMC_SPI_CH_SetWordLength(XMC_USIC_CH_t *const channel, const
uint8_t word_length)
811 {
812 XMC_USIC_CH_SetWordLength(channel, word_length);
813 }
814
815 /**
base address.
817 * @param frame_length Number of bits in a frame. \n
818 * \b Range: 1 to 64. If the value 64 is configured, then the frame
does not
819 * automatically end. User should explicitly end the frame.
820 *
821 * @return None
822 *
824 * Define the data frame length.\n\n
825 * Set the number of bits to be serially transmitted in a frame.
826 * The frame length should be multiples of word length. If the value is set to 64,
the frame does not
827 * automatically end. Use XMC_SPI_CH_DisableSlaveSelect() to end the frame after all
the data
828 * is transmitted.
829 *
831 * XMC_USIC_CH_SetWordLength(), XMC_USIC_CH_EnableFrameLengthControl(),
XMC_SPI_CH_DisableSlaveSelect()
832 */
833 __STATIC_INLINE void XMC_SPI_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const
uint8_t frame_length)
834 {
835 XMC_USIC_CH_SetFrameLength(channel, frame_length);
836 }
837
838 /**
base address.
840 *
841 * @return None
842 *
844 * Configure the handling of start of frame through software, by setting TCSR.SOF
bit.\n\n
845 * This can be used if the software handles the TBUF data without FIFO. If SOF is
set, a valid content of the TBUF is
846 * considered as first word of a new frame by finishing the currently running frame.
For software handling of SOF bit,
847 * it is recommended to configure TCSR.WLEMD as 0. This is not configured during
initialization. XMC_SPI_CH_EnableSOF()
848 * can be called as needed in the program and can be disabled by
XMC_SPI_CH_DisableSOF().
849 *
851 * XMC_SPI_CH_DisableSOF()
852 */
853 __STATIC_INLINE void XMC_SPI_CH_EnableSOF(XMC_USIC_CH_t *const channel)
854 {
855 channel->TCSR |= (uint32_t)USIC_CH_TCSR_SOF_Msk;
856 }
857
858 /**
base address.
860 *
861 * @return None
862 *
864 * Set the control of the handling start of frame through hardware, by clearing
TCSR.SOF bit.\n\n
865 * Typically this can be disabled, where the transmission control is done by the
hardware.
866 *
868 * XMC_SPI_CH_EnableSOF()
869 */
870 __STATIC_INLINE void XMC_SPI_CH_DisableSOF(XMC_USIC_CH_t *const channel)
871 {
872 channel->TCSR &= (uint32_t)~USIC_CH_TCSR_SOF_Msk;
873 }
874
875 /**
base address.
877 *
878 * @return None
879 *
881 * Configure the handling of end of frame through software, by setting TCSR.EOF
bit.\n\n
882 * This can be used if the software handles the TBUF data without FIFO. If EOF is
set, a valid content of the TBUF is
883 * considered as last word of a frame. After transfer of the last word, MSLS signal
becomes inactive. For software
884 * handling of EOF bit, it is recommended to configure TCSR.WLEMD as 0. \n
885 * \b Note: The API should be called before putting the last data word of the frame
to TBUF.
886 *
888 * XMC_SPI_CH_DisableEOF()
889 */
890 __STATIC_INLINE void XMC_SPI_CH_EnableEOF(XMC_USIC_CH_t *const channel)
891 {
892 channel->TCSR |= (uint32_t)USIC_CH_TCSR_EOF_Msk;
893 }
894
895 /**
base address.
897 *
898 * @return None
899 *
901 * Configure the handling of end of frame through hardware, by clearing TCSR.EOF
bit.\n\n
902 * Typically this can be disabled, where the transmission control is done by the
hardware.
903 *
905 * XMC_SPI_CH_EnableEOF()
906 */
907 __STATIC_INLINE void XMC_SPI_CH_DisableEOF(XMC_USIC_CH_t *const channel)
908 {
909 channel->TCSR &= (uint32_t)~USIC_CH_TCSR_EOF_Msk;
910 }
911
912 /**
base address.
914 * @param input SPI channel input stage.\n
915 * Refer @ref XMC_SPI_CH_INPUT_t for valid values
916 * @param source Input source select for the input stage.
917 * Range : [0 to 7]
918 *
919 * @return None
920 *
922 * Selects the data source for SPI input stage, by configuring DXCR.DSEL bits.\n\n
923 * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage.
The API can be used for all the
924 * input stages like DX0CR, DX1CR etc. This is not done during initialization. This
has to be configured before starting
925 * the SPI communication.
926 */
927 __STATIC_INLINE void XMC_SPI_CH_SetInputSource(XMC_USIC_CH_t *const channel,
928 const XMC_SPI_CH_INPUT_t input,
929 const uint8_t source)
930 {
931 channel->DXCR[input] = USIC_CH_DX0CR_INSW_Msk;
932 XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source);
933 }
934
935 /**
base address.
937 * @param selo_inversion Polarity of the slave select signal relative to the MSLS
signal.\n
938 * Refer @ref XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t for valid values
939 *
940 * @return None
941 *
943 * Set the polarity of the slave select signal, by configuring PCR.SELINV bit.\n\n
944 * Normally MSLS signal is active low level signal. SO based on the slave inversion
has to be applied. This is configured
945 * in XMC_SPI_CH_Init() during initialization. Invoke
XMC_SPI_CH_SetSlaveSelectPolarity() with desired settings as
946 * needed later in the program.
947 */
948 __STATIC_INLINE void XMC_SPI_CH_SetSlaveSelectPolarity(XMC_USIC_CH_t *const channel,
949 const
XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t
selo_inversion)
950 {
951 /* Configuration of Protocol Control Register */
952 channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode & (~
USIC_CH_PCR_SSCMode_SELINV_Msk)) | (uint32_t)selo_inversion);
953 }
954
955 /**
base address.
958 * Refer @ref XMC_SPI_CH_INPUT_t for valid inputs.
959 *
960 * @return None
961 *
963 * Enables the polarity inversion of input data signal, by setting DXyCR.DPOL(where y
= \a input).\n\n
964 * This is not set in XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_EnableInputInversion() as
needed later in the program. To
965 * disable the inversion XMC_SPI_CH_DisableInputInversion() can be invoked.
966 *
968 * XMC_SPI_CH_DisableInputInversion()
969 */
970 __STATIC_INLINE void XMC_SPI_CH_EnableInputInversion(XMC_USIC_CH_t *const channel,
971 const XMC_SPI_CH_INPUT_t input)
972 {
973 XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
974 }
975
976 /**
base address.
979 * Refer @ref XMC_SPI_CH_INPUT_t for valid inputs.
980 *
981 * @return None
982 *
984 * Disables the polarity inversion of input data signal, by clearing DXyCR.DPOL(where
y = \a input).\n\n
985 * Resets the input data polarity. Invoke XMC_SPI_CH_EnableInputInversion() to apply
inversion.
986 *
988 * XMC_SPI_CH_EnableInputInversion()
989 */
990 __STATIC_INLINE void XMC_SPI_CH_DisableInputInversion(XMC_USIC_CH_t *const channel,
991 const XMC_SPI_CH_INPUT_t input)
992 {
993 XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
994 }
995
996 /**
base address.
998 * @param service_request Service request number.
999 Range: [0 to 5]
1000 *
1001 * @return None
1002 *
1004 * Sets the interrupt node for SPI channel events.\n\n
1005 * For an event to generate interrupt, node pointer should be configured with service
request(SR0, SR1..SR5).
1006 * The NVIC node gets linked to the interrupt event by doing so. This is not
configured in XMC_SPI_CH_Init() during
1007 * initialization.
1008 *
1009 * \parNote:: 
1010 * 1. NVIC node should be separately enabled to generate the interrupt.
1011 *
1013 * XMC_USIC_CH_EnableEvent()
1014 */
1015 __STATIC_INLINE void XMC_SPI_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
1016 const uint8_t service_request)
1017 {
1018 XMC_USIC_CH_SetInterruptNodePointer(channel,
XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, (uint32_t)service_request);
1019 }
1020
1021
1022 /**
1023 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1024 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
1025 * @param interrupt_node Interrupt node pointer to be configured. \n
1026 * \b Range: @ref
XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
1027 * @ref
XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
1028 * @param service_request Service request number.\n
1029 * \b Range: 0 to 5.
1030 * @return None
1031 *
1033 * Sets the interrupt node for USIC channel events. \n\n
1034 * For an event to generate interrupt, node pointer should be configured with service
request(SR0, SR1..SR5).
1035 * The NVIC node gets linked to the interrupt event by doing so. 
1036 * Note: NVIC node should be separately enabled to generate the interrupt.
1037 *
1039 * XMC_SPI_CH_EnableEvent() \n\n\n
1040 */
1041 __STATIC_INLINE void XMC_SPI_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const
channel,
1042 const
XMC_SPI_CH_INTERRUPT_NODE_P
OINTER_t interrupt_node,
1043 const uint32_t
service_request)
1044 {
1045 XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)
interrupt_node,
1046 (uint32_t)service_request);
1047 }
1048
1049 /**
1050 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1051 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
1052 * @param service_request_line service request number of the event to be triggered.
\n
1053 * \b Range: 0 to 5.
1054 * @return None
1055 *
1057 * Trigger a SPI interrupt service request.\n\n
1058 * When the SPI service request is triggered, the NVIC interrupt associated with it
will be
1059 * generated if enabled.
1060 *
1062 * XMC_SPI_CH_SelectInterruptNodePointer() \n\n\n
1063 */
1064 __STATIC_INLINE void XMC_SPI_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel,
const uint32_t service_request_line)
1065 {
1066 XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line);
1067 }
1068
1069 #ifdef __cplusplus
1070 }
1071 #endif
1072
1073 /**
1074 * @}
1075 */
1076
1077 /**
1078 * @}
1079 */
1080
1081 #endif
1082

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