Multimedia Tools and Applications (2019) 78:18309–18338

https://doi.org/10.1007/s11042-019-7187-2

Novel high-speed reconfigurable FPGA architectures

for EMD-based image steganography

K. Sathish Shet 1 2 3
& A. R. Aswath & M. C. Hanumantharaju & Xiao-Zhi Gao
4

Received: 10 July 2018 / Revised: 18 December 2018 / Accepted: 6 January 2019 /

Published online: 24 January 2019
# Springer Science+Business Media, LLC, part of Springer Nature 2019

Abstract
Exploiting modification direction (EMD)-based image steganography algorithm has higher
embedding efficiency, low distortion, and best security that finds application in secure
communication, data protection, access control in digital content distribution, etc., EMD
steganography encapsulates secret digit represented in (2n + 1)-ary notational system by
increasing or decreasing one of the n cover pixels by one. New high-speed reconfigurable
architectures and field programmable gate array (FPGA) implementation of EMD based image
steganography algorithms have been proposed. Although, earlier work on FPGA implemen-
tation of steganography algorithms offer higher speed, low chip area, and better throughput it
usually operates on a fixed number of pixels. The proposed system works well for both
arbitrary numbers of pixel groups and variable image resolution. The developed system is
capable of embedding a secret message from two to eight-pixel groups with an image
resolution of 512 × 512 pixels at a real-time video rate of 549 frames/s.. The complete design
is implemented using RTL compliant Verilog code which fits into a single FPGA/ASIC chip
with a gate density of two million gates.

Keywords Algorithms . Image steganography . Exploiting modification direction (EMD) .

Reconfigurable architectures . Field programmable gate arrays (FPGA)

* K. Sathish Shet
[email protected]; [email protected]

1
Department of Electronics and Communication Engineering, JSS Academy of Technical Education,
Bengaluru, India
2
Department of Telecommunication Engineering, Dayananda Sagar College of Engineering,
Bengaluru, India
3
Department of Electronics and Communication Engineering, BMS Institute of Technology and
Management, Bengaluru, India
4
School of Computing, University of Eastern Finland, Kuopio, Finland
18310 Multimedia Tools and Applications (2019) 78:18309–18338

1 Introduction

Steganography was started as an art in earlier days and now it has become one of the
specialized areas in cybersecurity. The mobile internet technology has led the internet to grow
faster with a four-fold increase in internet users over the past few years. As it is evident from
McKinsey report 2013 [17], five billion individuals are using various mobile devices to
connect to the internet and it is expected to increase in an exponential manner in next few
years. Disruptive IoT and mobile internet technology have provided easy access to the internet
through portable/handheld devices, and hence securing user data in public networks is a major
concern. According to the identity theft resource center (ITRC) breach report (http://www.
idtheftcenter.org/images/breach/DataBreachReports_2015.pdf) published in 2015, there are
total of 780 breaches and the records exposed were 177,866,236. Therefore, the data
protection using steganography and cryptography techniques is the need of the hour.
The prominent applications of Steganography include secured communication, particularly
in banking, defense and space explorations. Cryptography deals with the practice and study of
procedures for secure communication in the presence of third parties. It means that the original
data is replaced with some other data using a key and the secret data. The cryptography
techniques are mainly used in securing any time money (ATM) cards, computer passwords,
and electronic commerce applications etc. The cryptography algorithm must be robust enough
since the message is encrypted and transmitted in the presence of third parties. However, the
steganography does not reveal the existence of the secret message. Therefore, the steganog-
raphy schemes are more widely used compared to cryptography techniques.
Steganography schemes work in both spatial and transform domains. In the spatial domain,
the secret message is embedded by direct modification of the cover data values. In the
transform domain, the cover object is converted to a transform space such as discrete Fourier
transforms (DFT), discrete wavelet transforms (DWT),discrete cosine transforms (DCT) etc.
Embedding of secrete message is done by changing the transform coefficients.
In steganography, the image steganography has created a lot of curiosity among researchers
due to its simplicity, high security and difficulty to hack. Image steganography hides confi-
dential information in an image without altering the visual details of an image. Image
steganography not only enables secret communication with encryption and decryption using
existing networks but also increases the security to manageable levels. Numerous researchers
[1, 5, 6, 24, 25] have addressed various challenges in image steganography, namely, level of
security, capacity, imperceptibility, the domain of embedding, types of images supported and
time complexity. The three prominent challenges that were not addressed by the majority of
algorithm developers are security, capacity, and time complexity. Steganography algorithms
[11, 30] coded in conventional software’s such as C, C++, Java, Matlab fail to produce real-
time results with high security and significant capacity compared to its hardware counterparts.
A reconfigurable device such as FPGAs is becoming increasingly important for digital
signal processing, image processing, and computer vision tasks [9]. In FPGAs, high degrees of
pipelining and massive parallel processing can be easily accomplished compared to central
processing units (CPUs) and digital signal processors (DSPs). These unique characteristics of
FPGAs best suit implementing image steganography algorithms and hence are responsible for
overcoming challenges of other researcher methods. The throughput of the image steganog-
raphy system based on FPGAs can be greatly enhanced compared to other implementation
schemes. Rest of the paper is organized as follows: Section 2 describes the background
concepts necessary for understating the proposed method. Prominent, hardware compatible,
Multimedia Tools and Applications (2019) 78:18309–18338 18311

and RTL compliant EMD algorithms are discussed in Section 3 Section 4 presents the
proposed reconfigurable architectures for basic and advanced EMD steganographic methods.
In Section 5, the experimental results for each of the proposed framework are shown in more
detail. Finally, a brief conclusion is presented in Section 6.

2 Existing work

Shet et al. [27] proposed reconfigurable architectures and FPGA implementation of LSB
steganography. Although designed architectures offer high-speed embedding and extraction
of secret message, hiding capacity is very low compared to other hiding schemes. Soumendu
et al. [2] proposed adaptive steganography that embeds binary payload in an edge area of the
cover image with higher embedding rate and low distortion. The area in an image is selected
using a modified median edge detector predictor that reduces the probability of detection.
Achieving high embedding capacity and detection due to a minimum number of edges
available in an image are the main constraints of this work.
Numerous researchers [2, 14, 28] have contributed their thoughts into image steganography
to protect public domain data. Edgar et al. [7] proposed reconfigurable architectures for
context-based image steganography technique that is compatible for FPGA implementation.
The context method exploits the advantage of noisy and quick gray level changes in a picture
to hide the secret information. Identification of such regions is challenging since the process is
highly repetitive and computationally intensive. The hardware architectures presented in this
work resolve the speed problem of software simulation. As it can be seen from the hardware
architectures presented, there is a still scope to improve the throughput of a system.
Zaidan et al. [37] proposed a new evaluation and benchmarking methodology for software
and hardware image steganography based on multi-criteria decision. This scheme uses two
iterations, of which the first iteration evaluates the test samples and second iteration selects the
best technique based on the results of the comparative analysis. Adaptive image steganography
based on discrete cosine transform (DCT) and a chaotic map embedding scheme proposed by
Saidi et al. [26] provides good imperceptibility and flexibility but at the cost of computational
complexity.
Ramalingam et al. [23] proposed the design of reconfigurable architectures for adaptive
image steganography algorithm based on integer wavelet transform (IWT). The system
proposed uses Haar-IWT to separate the image into its sub-bands, namely, LL, LH, HL, and
HH and hides the encrypted secret message in the LH, HL, and HH coefficient blocks
respectively. The time taken by the system to embed data into the coefficient blocks is 1.6
micro seconds with 34% of logic elements, 22% of the dedicated logic register, and 2% of
embedded multiplier resource utilization in FPGAs. The schematic approach used in this work
offers an advantage of improvising the existing system based on hardware description
languages (HDL).
Zhang et al. [38] proposed an efficient steganographic scheme using EMD for the first time.
In this scheme, a secret data is embedded in the image such that each secret digit in a (2n + 1)-
ary notational system is carried by ‘n’ cover pixels. Zhang method increments or decrements at
most one pixel by unity. The matrix-encoding scheme adopted in this work was extracted from
hamming code that yields a greater embedding efficiency far better than previous techniques.
A very few contributions can be seen in FPGA implementation of image steganography
algorithms. The main reason behind this is the design and FPGA realization. However, there is
18312 Multimedia Tools and Applications (2019) 78:18309–18338

still room left for improving the existing work or propose new algorithms. This paper presents
the design and development of new high-speed reconfigurable architectures and FPGA
implementation of EMD-based image steganography algorithms.
The related work presented offers many advantages over other researcher’s methods, like
robust against attacks, increased embedding capacity, high embedding efficiency, etc. As it is
evident from the survey of state-of-the-art methods, EMD method offers a number of
advantages to secure the secret data. More than 400 articles published in the literature have
been derived from the Zhang method which gives an opportunity for the present authors to
design the novel architectures suitable for ASIC/FPGA implementation. Therefore, in this
paper design of a robust EMD steganographic system based on Zhang method is proposed.
The new high-speed reconfigurable architectures for the proposed EMD-based steganography
system employs massive pipelining and parallel processing to each of the modules. These
throughput improvement techniques not only speed up the system but also reduce the power
consumption at the cost of increased chip area. The main reason for the increase in chip area is
due to a large number of pipelined registers employed in order to accomplish high throughput.

3 Exploiting modification direction algorithms

3.1 Basic EMD (BEMD) algorithm

Zhang and Wang [38] proposed an efficient EMD-based steganography algorithm wherein
each secret digit is represented in (2n + 1)-ary notational system encapsulated in n cover pixels
group. The extraction function for the group of n pixels in a cover image, fEMD is defined as a
weighted sum of modulo (2n + 1).


f EMD ðg1 ; g 2 ; ⋯gn Þ ¼ ∑ni¼1 ðg i :iÞ mod ð2n þ 1Þ ð1Þ

where, (g1, g2, ⋯gn) are the gray value of pixels in a group, gi is ith pixel value in the cover
image, ‘i’ is the weight, ‘n’ is the number of pixel values selected for embedding a secret data.
The pseudocode of EMD embedding algorithm with an example is illustrated in the following
section:
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Example 1 For the two cover image pixels, (g1, g2) = (20, 32) and secret data d = (1111)2, prove
 0 0 
that the stego image pixels are equivalent to g1 ; g2 ¼ ð19; 32Þ using BEMD steganography.

Solution Given cover image pixels (g1, g2) = (20, 32), secret data d = (1111)2, and n = 2, the
ary notation used here is, (2n + 1) = (2 × 2 + 1) = 5-ary notation.

Step - 1: Compute the extraction function, fEMD using Eq. (1)

f EMD ð20; 32Þ ¼ ð20  1 þ 32  2Þ mod ð2  2 þ 1Þ; since n ¼ 2

f EMD ð20; 32Þ ¼ ð20 þ 64Þ mod ð5Þ ¼ ð84Þ mod ð5Þ ¼ 4

Step - 2: Convert the secret message, d into the 5-ary notational system.

i.e., d = (1111)2 = (3)5.

Step - 3: Compute the difference value, s

s¼ð3−4Þ mod ð2  2 þ 1Þ ¼ ð−1Þ mod ð5Þ ¼ 4

Step – 4: Embedding stage

From the data computed in previous steps, it is clear that f = 4, d = (3)5, s = 4, and n = 2 satisfies
case (iii) of step BEMD-5 of the pseudocode. Since f ≠ d and s < n , then,
0    
g2nþ1−s ¼ g 2nþ1−s −1 ¼ g22þ1−4 −1 ¼ ðg1 −1Þ ¼ ð20−1Þ ¼ 19
 0 0 
Therefore, the stego pixels are g 1 ; g2 ¼ ð19; 32Þ:

Extraction Secret data is recovered from the stego pixels using EMD extraction algorithm
illustrated in the next section:
 0 0 
Given the stego pixels g 1 ; g 2 ¼ ð19; 32Þ. Extraction function, fEMD defined in (1) is used
to recover secret data.
f EMD ð19; 32Þ ¼ ð19  1 þ 32  2Þ mod ð2  2 þ 1Þ; since n ¼ 2
0
f EMD ð19; 32Þ ¼ ð19 þ 64Þ mod ð5Þ ¼ ð83Þ mod ð5Þ ¼ ð3Þ5 ¼ ð1111Þ2 ¼ d

The basic EMD algorithm discussed earlier has several advantages over other embedding
schemes. As it is evident from experimental results presented by Zhang et al. method [38] the
18314 Multimedia Tools and Applications (2019) 78:18309–18338

algorithm offers the very good visual quality of stego images. The average peak signal- to- noise
ratio (PSNR) obtained from BEMD technique is 51 dB. BEMD method provides the highest
embedding efficiency and embedding rate compared to run length and matrix encoding methods.
The data hiding bit rate is approximately equal to 1.16 bits per pixel (BPP) for n = 2 or 5-ary
notational system. However, the BEMD scheme has two shortcomings. As the number of pixels
(i.e., ‘n’) increases the embedding capacity rapidly decreases. The second drawback is that the
BEMD method has a saturation problem. This is illustrated in the following example:
For n ¼ 2; ðg1 ; g 2 Þ ¼ ð255; 255Þ; d ¼ ð0101Þ2 ¼ ð1Þ5 ; the extraction function;
f EMD ð255; 255Þ ¼ ð255  1 þ 255  2Þ mod ð2  2 þ 1Þ ¼ ð255 þ 510Þ mod ð5Þ
f EMD ð255; 255Þ ¼ ð765Þ mod ð5Þ ¼ 0;
s ¼ ð1−0Þ mod ð5Þ ¼ ð1Þ mod ð5Þ ¼ 1

From the above computation, it is clear that fEMD = 0, d = (1)5, s = 1, and n = 2 satisfies case (ii)
of step BEMD-5 of pseudocode of embedding algorithm, since f ≠ d and s < n. Therefore,
0  0 0 
g1 ¼ ðg 1 þ 1Þ¼ð255 þ 1Þ ¼ 256. The steo pixels are g 1 ; g2 ¼ ð256; 255Þ. This shows
that the basic EMD algorithm has an overflow problem.

3.2 Modulus operation based EMD

Hyun et al. [10] proposed a modulus operation based EMD (MEMD) method. The modulus
method provides high embedding capacity and better PSNR compared to other methods. Most
of the steps in the MEMD method remains similar to that of BEMD scheme, except extraction
function. The extraction function defined for MEMD is given by fMEMD:
f MEMD ¼ ðg i þ xÞ mod ð2n þ 1Þ ð2Þ

Where gi is the ith pixel value and x|≤n.

MEMD embedding and extraction procedures are illustrated in the following sections:
Multimedia Tools and Applications (2019) 78:18309–18338 18315

The examples in the following section are illustrated in different cases:

Case(i) For stego pixel range 2 ≤ gi ≤ 253, the range of x is : − (2n − 1) < x < + (2n − 1).
The embedding and extraction operations are discussed in the following example:

Example 2 For n = 2, cover image pixel, g1 = 153 and secret data, d = (2)5, compute the stego
0
image pixel g 1 ¼ 152 using MEMD embedding procedure.

Solution Given n = 2, g1 = (153)5, d = (2)5

The stego pixel is calculated using the embedding procedure. In the first step, extraction
function is used to determine possible, f values.
f ¼ ðg i þ xÞ mod ð2n þ 1Þ
2≤gi≤253; −ð2n−1Þ < x < þð2n−1Þ
f ¼ ðgi þ xÞ mod ð2n þ 1Þ; −2≤x≤ þ 2 ði:e: x ¼ 2; 1; 0; −1; −2Þ
f ¼ ð153 þ 2Þ mod ð2  2 þ 1Þ ¼ ð155Þ mod ð5Þ ¼ 0
f ¼ ð153 þ 1Þ mod ð2  2 þ 1Þ ¼ ð154Þ mod ð5Þ ¼ 4
f ¼ ð153 þ 0Þ mod ð2  2 þ 1Þ ¼ ð153Þ mod ð5Þ ¼ 3
f ¼ ð153 þ ð−1ÞÞ mod ð2  2 þ 1Þ ¼ ð152Þ mod ð5Þ ¼ 2
f ¼ ð153 þ ð−2ÞÞ mod ð2  2 þ 1Þ ¼ ð151Þ mod ð5Þ ¼ 1

f = d, when x = −1. Therefore, new stego pixel value: g’i = gi + x

g ’ i ¼ 153 þ ð−1Þ ¼ 152

0 0
The secret message is extracted using equ. d ¼ g i mod ð2n þ 1Þ
0
d ¼ 152 mod ð2  2 þ 1Þ ¼ 152 mod ð5Þ ¼ ð2Þ5

Case (ii): For stego pixel range 0 ≤ gi ≤ 1, the range of x is : 0 ≤ x < + (2n + 1). The
embedding and extraction operations are discussed in the following example:

Example 3 For n = 2, cover image pixel, g1 = 0 and secret data, d = (4)5, stego image pixels is
0
computed as g 1 ¼ 4 using MEMD embedding procedure.
18316 Multimedia Tools and Applications (2019) 78:18309–18338

Solution Given n = 2, g1 = (0)5, d = (4)5

The stego pixel is calculated using the embedding procedure. In the first step, extraction
function is used to determine possible, f values.

f ¼ ðgi þ xÞ mod ð2n þ 1Þ

0≤gi≤1; the range of x is : 0≤x < þð2n þ 1Þ
f ¼ ðgi þ xÞ mod ð2n þ 1Þ; 0≤x≤5 ði:e: x ¼ 0; 1; 2; 3; 4Þ
f ¼ ð0 þ 0Þ mod ð2  2 þ 1Þ ¼ ð0Þ mod ð5Þ ¼ 0
f ¼ ð0 þ 1Þ mod ð2  2 þ 1Þ ¼ ð1Þ mod ð5Þ ¼ 1
f ¼ ð0 þ 2Þ mod ð2  2 þ 1Þ ¼ ð2Þ mod ð5Þ ¼ 2
f ¼ ð0 þ 3Þ mod ð2  2 þ 1Þ ¼ ð3Þ mod ð5Þ ¼ 3
f ¼ ð0 þ 4Þ mod ð2  2 þ 1Þ ¼ ð4Þ mod ð5Þ ¼ 4

f = d, when x = 4, Therefore, new stego pixel value: g’i = gi + x

g’ i ¼ 0 þ 4 ¼ 4
0 0
The secret message is extracted using d ¼ gi mod ð2n þ 1Þ
0
d ¼ 4 mod ð2  2 þ 1Þ ¼ 4 mod ð5Þ ¼ ð4Þ5

Case (iii): For stego pixel range 254 ≤ gi ≤ 255, the range of x is : − (2n + 1) < x ≤ 0. The
embedding and extraction operations are discussed in the following example:

Example 4 For n = 2, cover pixel g1 = 254 and secret data d = (4)5, compute the stego image
0
pixels as g1 ¼ 254 using MEMD embedding procedure.

Solution Given n = 2, g1 = (254)5, d = (4)5

The stego pixel is calculated using the embedding procedure. In the first step, extraction
function is used to determine possible f values.

f ¼ ðgi þ xÞ mod ð2n þ 1Þ

254≤gi≤255; the range of x is : −ð2n þ 1Þ < x ≤0
f ¼ ðgi þ xÞmod ð2n þ 1Þ; −5 < x≤0ði:e:x ¼ −4; −3; −2; −1; 0Þ
f ¼ ð254 þ ð−4ÞÞ mod ð2  2 þ 1Þ ¼ ð250Þ mod ð5Þ ¼ 0
f ¼ ð254 þ ð−3ÞÞ mod ð2  2 þ 1Þ ¼ ð251Þ mod ð5Þ ¼ 1
f ¼ ð254 þ ð−2ÞÞ mod ð2  2 þ 1Þ ¼ ð252Þ mod ð5Þ ¼ 2
f ¼ ð254 þ ð−1ÞÞ mod ð2  2 þ 1Þ ¼ ð253Þ mod ð5Þ ¼ 3
f ¼ ð254 þ ð0ÞÞ mod ð2  2 þ 1Þ ¼ ð254Þ mod ð5Þ ¼ 4

f = d, when x = 0, Therefore, new stego pixel value: g’i = gi + x

g’ i ¼ 254 þ 0 ¼ 254
0 0
The secret message is extracted using d ¼ gi mod ð2n þ 1Þ
0
d ¼ 254 mod ð2  2 þ 1Þ ¼ 254 mod ð5Þ ¼ ð4Þ5
Multimedia Tools and Applications (2019) 78:18309–18338 18317

3.3 Fully EMD

Xuejing et al. [18] proposed fully EMD (FEMD) steganography. This scheme uses redundancy
space to embed data. The image quality is well preserved since the algorithm is robust. At the
same time, embedding and extraction techniques are simple to that of BEMD. Difference
histogram analysis adopted in this scheme validates the method presented. The extraction
function used in this method is given by
 
f ðg1 ; g 2 ; g 3 ::…g n Þ ¼ ∑ni¼1 gi  3i−1 mod ð3n Þ ð3Þ

Embedding and extraction procedures of FEMD method are illustrated in the following
sections:

Example 5 Illustrate the FEMD embedding and extraction algorithm for n = 3, cover
pixels(g1, g2, g3) = (31, 22, 32) , and secret digit d = (26)27
18318 Multimedia Tools and Applications (2019) 78:18309–18338

Solution Given n = 3, (g1, g2, g3) = (31, 22, 32) , d = (26)27 since n = 3, 33 = 27 hence the secret
digit is represented in 27-ary notational system

The Embedding

The extraction function, f is computed as shown below:

3    
f ðg 1 ; g2 ; g3 Þ ¼ ∑ gi  3i−1 mod 33
i¼1  
f ð31; 22; 32Þ ¼ ð31  1 þ 22  3 þ 32  9Þmod 33
f ð31; 22; 32Þ ¼ ð385Þmodð27Þ
f ð31; 22; 32Þ ¼ 727

The extraction function, f(g1, g2, g3) ≠ d. Therefore, it is required to compute the s function

s ¼ ðd− f ð31; 22; 32ÞÞ mod 33

s ¼ ð26−7Þ mod 27 ¼ 1927

For ith pixel we define a function:

2  1−1   3
3 −1
6 s− 7
6 2 7
f ðiÞ ¼ 6 7 mod ð3n Þ
4 3i−1 5

 
31−1 −1
g 1 ¼ ð31Þ; s > and f ð1Þ ¼ 0: Therefore; g 1 needs plus 1
2
  2−1 
3 −1
g 2 ¼ ð22Þ; s > and f ð2Þ ¼ 2: Therefore; g 2 is not modified
2
  3−1 
3 −1
g 3 ¼ ð32Þ; s > and f ð3Þ ¼ 2: Therefore; g 3 needs minus 1
2

Therefore, the stego pixels are: f(g′1, g′2, g′3) = (32, 22, 31)

The Extraction

Given stego pixels: f(g′1, g′2, g′3) = (32, 22, 31) the secret message can be extracted as follows:
Extraction function defined in Eq. (3) is used to recover the secret message
 
f ð32; 22; 31Þ ¼ ð32  1 þ 22  3 þ 31  9Þmod 33
f ð32; 22; 31Þ ¼ ð32 þ 66 þ 279Þmod ð27Þ
f ð32; 22; 31Þ ¼ 2627

The three versions of EMD steganography methods presented, namely, BEMD, MEMD, and
FEMD are well suited for ASIC/FPGA implementations. Design of architectures and imple-
mentation on FPGAs offer real-time throughput compared to the software realization since
these algorithms are iterative. Also, loop unrolling, parallel execution and enormous pipelining
adopted yield higher efficiency.
Multimedia Tools and Applications (2019) 78:18309–18338 18319

4 Proposed reconfigurable architectures for EMD algorithms

The designs of architectures for EMD algorithms illustrated in the earlier section are presented
in this section.

4.1 Architectures of basic EMD (BEMD) algorithm

The overall architecture depicted for the BEMD algorithm [38] is shown in Fig. 1. The
designed architecture is in compliance with the pseudocode presented in section 3. The
cover image pixels are divided into a number of groups. In each group, the number of
pixels varies from two to four. Although the proposed system is validated for, the group
with two pixels g1[7:0] and g2[7:0], but a number of pixels can be increased up to four.
A secret message consisting of alphanumeric symbols is read through the signal, d[7:0].
The input signal, n[1:0] indicates a total number of cover image pixels in the group.
The asynchronous global reset signal, reset_n is used to reset the system during power-
on conditions. The complete architecture is divided into three levels. The top-level
system starts functioning when the ‘start’ signal is asserted. The output of the top
module consists of g’1 [7:0] and g’2 [7:0]. The two pixels occupy the first and second
position of the stego pixel group. The validity of the output stego pixels is indicated by
the ‘valid’ signal.
Table 1 provides the signal description for the top module of BEMD steganography.
The top module is divided into three levels in order to ease the operation. First level shown
in Figure 2a comprises saturation avoidance (SA), multiply and accumulate (MAC), modulus,
and subtraction blocks. The second level presented in Fig. 2b encompasses comparators and
subtraction module. The third level shown in Fig. 2c includes primary blocks, namely,
increment, decrement, and a buffer.

Fig. 1 Top module of BEMD steganography

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Table 1 Signal description of the

top module of BEMD Image Signals Description
steganography
clk Global clock signal
reset_n Active low system reset
n [1: 0] Number of pixels usually varies from two to four
g1 [7: 0] The first pixel in the input cover image group
g2 [7: 0] The second pixel in the input cover image group
d [7: 0] Secret message of size 8-bits
start System start signal
g’1 [7: 0] The first pixel in the output stego image group
g’2 [7: 0] The second pixel in the output stego image group
valid Signal to indicate output pixels are valid

The SA block operates only when the pixel values are 255 or 0, or else the block
remains idle. SA block reduces the pixel 255 by one and increments zero pixels by one.
The output of the SA block provides input for the MAC unit. The MAC module computes
the cumulative sum of each input by multiplying with a suitable weight. Figure 3 presents
the detailed architecture for the MAC unit comprising of shifter and adder. Although MAC
unit demands dedicated multiplier block, the same has been eliminated by the shift left
operation.

Fig. 2 Proposed architectures for BEMD steganography

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Fig. 3 Detailed architecture for MAC unit

4.2 MEMD algorithm architectures

Design of reconfigurable architectures for MEMD [10] steganography is presented in this

section conforms to the pseudocode described in section 3.2. Figure 4 presents the top-level
architecture for MEMD embedding algorithm.
Table 2 provides a signal description for the top module of MEMD steganography.
Most of the signals described in MEMD architectures remain similar to that of the top
module presented in Fig. 1. However, the signals x1[2:0] to x5 [2:0] takes different values for

Fig. 4 Top module of MEMD steganography

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Table 2 Signal description for top

module of modulus EMD Signals Description

clk Global clock signal

reset_n Active low system reset
n[1:0] Number of pixels
g [7:0] Input pixel of the cover image
x1[2:0] to x5 [2:0] Input variable of 3-bits size
d[7:0] Secret message of size 8-bits
start System start signal
g’[7:0] Output stego pixel
valid Signal to indicate output pixel is valid

each cover image pixel. The range of ‘x’ values is computed in accordance with ‘g’ as defined
in the algorithm. The ‘x’ values are added to the cover pixel to produce input for modulus
module. The detailed architecture for MEMD steganography presented in Fig. 5 comprises
adders at the first level, followed by modulus operation, comparator, encoder, and multiplexer
in the next level.
The output of modulus operation is labeled as ‘f’ and is fed to the comparator along with
the secret digit, ‘d’. Each of the ‘f’ values is compared with the secret digit, ‘d’ in a comparator
section and generates logic ‘1’ if they are equal. Comparator outputs are fed into the 8:3
encoder module to produce the selection lines of the multiplexer. Multiplexer chooses one of
the ‘x’ values depending upon the select inputs. The ‘x’ value produced from the multiplexer is
used to generate stego pixel using adder and delay elements. Extraction operation is similar to
that of the extraction carried out for basic EMD presented in Fig. 6.

4.3 Architectures for fully EMD algorithm

Fully EMD proposed by Xuejing et al. [18] alters a group of ‘n’ pixels by incrementing or
decrementing by one. FEMD system converts the alphanumeric-based secret message into 3n -
ary notational system. The transformed secret message is embedded into a cover image as
depicted by the algorithm. FEMD simultaneously achieves greater embedding capacity and
preserves the quality of an image. However, when the size of the secret message increases, the
resolution of the cover image needs to be enlarged. Increasing the resolution of the cover
image to preserve the same visual quality increases computational complexity. Therefore,

Fig. 5 Detailed embedding architecture of MEMD steganography

Multimedia Tools and Applications (2019) 78:18309–18338 18323

Fig. 6 Architecture to extract secret message using MEMD

software schemes adopted in embedding and extraction are obsolete. The computational
complexity can be efficiently addressed by implementing the embedding and extraction
algorithms in FPGA device. The main reason to select an FPGA device in the implementation
of the FEMD algorithm is the iterative nature of the algorithm. Regularity, scalability,
portability, reconfigurability, etc. are the important properties that make FPGA, an ideal choice
for hardware implementation.
The top-level architecture proposed for the FEMD embedding algorithm is depicted in Fig. 7.
The algorithm has been designed to concurrently accept three pixels,- g1[7:0], g2[7:0], and,
g3[7:0], respectively. A secret message, d[7:0] with character length of 8-bits is applied to the
system in line with cover image pixels. The ‘start’ signal applied to the system synchronizes
cover image pixels and a secret message. The ‘start’ signal is in turn synchronized with the
system clock signal, ‘clk’. ‘reset_n’ is an active low signal that has set to high priority and
resets the system during the falling edge of a clock signal. The proposed system produces stego
pixels, g’1[7:0], g’2[7:0], and, g’3[7:0] after a latency of eight clock cycles. The validity of
stego pixels is indicated by an output signal, ‘valid’.
Table 3 provides a signal description for the top module of the FEMD embedding
algorithm.

Fig. 7 Top module of fully EMD steganography

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Table 3 Signal description for top

module of fully EMD Signals Description

clk Global clock signal

reset_n Active low system reset
n[1:0] Number of pixels
g1[7:0] The first pixel in the group selected in a cover image
g2[7:0] The second pixel in the group selected in a cover image
g3[7:0] A third pixel in the group selected in a cover image
d[7:0] Secret message of size 8-bits
start System start signal
g’1[7:0] First stego pixel
g’2[7:0] Second stego pixel
g’3[7:0] Third stego pixel
valid Signal to indicate output pixel is valid

Detailed architecture developed for the FEMD algorithm is presented in Fig. 8. Saturation
avoidance shown in Fig. 8a receives three cover image pixels that eliminate the system getting
into saturation. The saturation free signals are fed into MAC unit. The MAC unit multiplies
g1[7:0], g2[7:0], and, g3[7:0] with the position weights of one, three and nine, respectively and
then finally sums up. The result is sent to the modulus unit to compute the modulus operation
with 3n, where, ‘n’ is the total number of pixels in the selected group. In a nutshell, Fig. 8a
presents the modules to compute extraction function as defined in Eq. (3). Figure 8b calculates

Fig. 8 Proposed architectures for FEMD

Multimedia Tools and Applications (2019) 78:18309–18338 18325

‘s’ function which is highly essential in embedding. These modules exploit subtraction and
modulus units to generate ‘s’ output. Figure 8c presents control, increment, decrement and,
buffer modules. The control unit works in accordance with the function ‘s ‘s’ and ‘f’. This
module decides whether to increment, decrement, or buffer the cover image pixels.
The architectures to extract secret message from stego image pixels are similar to that of the
BEMD extraction. However, there exists a change in the position weights. Each stego pixels
g’1[7:0], g’2[7:0], and, g’3[7:0] are multiplied with one, three and nine, respectively in order
recover the secret message.
Numerous EMD algorithms [16, 31, 35, 39] are available in literature but BEMD algorithm
offers very good visual quality of stego images. It’s embedding rate and efficiency are found to
be better than matrix and run-length encoding schemes. Maximum data hiding rate of BEMD
method is 1 bpp. However, the BEMD algorithm experiences saturation problem. Although,
MEMD algorithm overcomes saturation problem encountered in BEMD technique, the
scheme has lower embedding efficiency [21]. The embedding rate and efficiency have
improved to higher levels in the FEMD algorithm. Therefore, the FEMD method is superior
compared to other EMD schemes [4, 8, 12, 19, 29].

5 Experimental results

In the previous sections, development of algorithms and design of architectures for various
functional modules such as saturation avoidance, MAC, modulus, addition, subtraction,
increment, decrement, buffer, encoder, multiplexer, etc. of BEMD, MEMD, and FEMD
steganography algorithms were presented in more detail. Embedding algorithm [13, 15, 32]
receives a secret message and cover image pixels as input and embeds a secret message in the
cover image pixels. The stego output produced by embedding algorithm is provided as input
for the extraction module. The extraction module reconstructs the secret message without
altering the cover image. As it can be seen from the architectures presented in the earlier
section the secret message extraction function remains the same for all the methods. But, there
is a change in position weights.
The EMD architectures [22] proposed in this paper have been coded in Matlab (Ver. 2017b)
and have been tested first in order to ensure the correct working of the algorithm developed.
The test conducted has produced satisfactory results. Subsequently, the complete architectures
have been coded in Verilog (a hardware description language) so that it may be implemented
on an FPGA or as an ASIC. Verilog coding adopted in this work conforms to RTL standard
which is widely used in industry.
A Matlab function was written to capture a standard picture in .tif format and convert
into an equivalent text version. The text file generated by the Matlab function is in raster

Fig. 9 Matlab and modelsim processing of an image

18326 Multimedia Tools and Applications (2019) 78:18309–18338

Fig. 10 The waveform for top module of EMD steganography: validity of cover image and secret data input at 40 ns

scan order and can be easily used by ModelSim (Ver. SE 10.5) for simulation. The top-
level module invokes other sub-modules developed in the form of a tree structure. The test
bench developed passes the stimulus for the top design which is useful in the analysis of
output results. The Verilog design of top module was run in ModelSim, to get the
processed picture in .txt format. This obtained .txt file converted back into .tif image
format using another Matlab function. This function automatically displays both the
original image as well as the stego image. The Matlab and ModelSim simulation procedure
is depicted in Fig. 9.
The simulation waveforms were analyzed and checked for formal language verification.
The sample waveforms presented in the following sections depicts the working of the idea
proposed.

Fig. 11 Output waveforms for top module of EMD steganography: secret message reconstruction at 26,980 ns
Multimedia Tools and Applications (2019) 78:18309–18338 18327

Fig. 12 Project summary of synthesis and implementation

5.1 Simulation waveform analysis of top module of BEMD algorithms

The simulation results waveform for the top module of BEMD embedding and extraction
algorithms [3, 33, 34, 36, 40], are presented in Fig. 10 indicating the validity of cover image
and secret message data. As it is evident from the simulation waveforms of BEMD method, the
input cover image and secret message data arrives at-40 ns for the top module. The ‘clk’ is the
system clock and ‘reset_n’ is the global reset signal in order to reset the system during power-
on conditions. Final stego output arrives at 26,980 ns which is shown in Fig. 11. It is clear from
the simulation waveform that the system takes 26,940 ns to embed the secret message into the
cover image. The initial latency of the system is 26,940 ns is obtained by subtracting reset time
of 40 ns which is very small and hence may be negligible.

Fig. 13 RTL schematic view of the EMD steganography system

18328 Multimedia Tools and Applications (2019) 78:18309–18338

Fig. 14 Place and routed design on Xilinx FPGA XC7a75tcsg324–1

5.2 Logic synthesis of top module of BEMD system

The Modelsim (Ver. SE 10.5) verified RTL code is synthesized and implemented using Xilinx
Vivado (Ver. 2017.1). Although Vivado tool offers a platform to conduct language verification,
this paper uses ModelSim, since it is widely used in industry. The design is placed on to the
target FPGA device and routed to various configurable logic blocks. The bit file equivalent of
the design produced by the Vivado tool is downloaded into a real FPGA device using a joint
test action group (JTAG) cable. Figure 12 shows the snapshot of the complete project summary
starting from synthesis to final FPGA implementation.
Detailed RTL schematic of the top module of EMD algorithm is presented in Fig. 13. The
schematic diagram and the signals captured from the tool match with the designed architec-
tures are shown in section 4. Since each of the small modules are integrated into the top
module, henceforth the blocks become visible in the resultant RTL schematic.
Further, the design is placed & routed onto the Xilinx FPGA device, XC7A75TCSG324–1.
Manual and automated routing options are explored to validate the design. It is found that the
manual routing gives the best throughput compared to automated routing method. The routed
design is presented in Fig. 14.

Fig. 15 Summary of device utilization

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Fig. 16 Snapshot for power analysis from implemented netlist

The summary of post-implementation device utilized in the targeted FPGA is shown in

Fig. 15. It can be seen from the figure that input/output (IO), BUFG, FF, and LUT in target
FPGA are 10%, 3%, 2%, and 1% respectively. The maximum frequency of operation of
the design is 144 MHz. Therefore, the design works in real-time producing a frame rate of
549 fps. Another constraint in the hardware design of the EMD algorithm is power
estimation.
Figure 16 shows the snapshot of power analysis for the implemented netlist.
Detailed power analysis showing power consumed for each module is shown in
Fig. 17.
The FPGA implementation of BEMD, MEMD and FEMD algorithms are validated
using a standard database. Although, the proposed method is tested using over dozens of
images a few sample results are shown in this paper. Figures 18, 19, and 20 present original
and stego images of the selected EMD algorithms. The images chosen have a resolution of
512 × 512 pixels and are in .tiff format. Three popular metrics, namely, Mean Structural
Similarity Index Measurement (MSSIM) [20], Peak Signal-To-Noise Ratio (PSNR), and
Mean Squared Error (MSE) are used for qualitative evaluation of the stego images with
reference to original images. Figures 21, 22, and 23 show the visual performance metrics of
the stego images. It is clear that MSSIM for the FEMD method is closer to the BEMD. This
shows that the FEMD method offers higher capacity at the cost of small change in image
visual quality.

Fig. 17 Detailed power analysis for each modules

18330 Multimedia Tools and Applications (2019) 78:18309–18338

Fig. 18 Simulation results of BEMD algorithm. Note: Original Images are shown in Figs. a, b, c, d, e, and f. The
stego images are presented in Figs. a’, b’, c’, d’, e’, and f’

5.3 Analysis of pipelining operation in BEMD algorithm

The pipelining operation of various modules of the BBEMD algorithm^ is presented in

the form of a timing diagram shown in Fig. 24. The timing details are presented for
gray image BTemple.jpg^ of size 512 × 512 pixels as an example. As shown in the
timing diagram, the EMD embedding process starts at 40 ns, after applying the start
signal. The test clock runs at 20 ns which is equivalent to 50 MHz. The first pixel is
Multimedia Tools and Applications (2019) 78:18309–18338 18331

Fig. 19 Simulation results of MEMD algorithm. Note: Original Images are shown in Figs. a, b, c, d, e, and f. The
stego images are presented in Figs. a’, b’, c’, d’, e’, and f’

fed into the system at 40 ns and one pixel is processed in each clock cycle. Secret
message and pixels to avoid saturation are fed at the same time as the cover image
pixel. Since the MAC block receives the input from saturation avoidance block, the
MAC is activated at 60 ns. The MAC block has multiplier and adder and hence it has a
18332 Multimedia Tools and Applications (2019) 78:18309–18338

Fig. 20 Simulation results of FEMD algorithm. Note: Original Images are shown in Figs. a, b, c, d, e and f. The
stego images are presented in Figs. a’, b’, c’, d’, e’, and f’

latency of 40 ns. The output of the MAC block actuates the modulus unit. Henceforth,
it is triggered at 100 ns. The modulus block has a delay of 60 ns due to the division
and subtraction unit embedded in it. The last pixel arrives at 52,42,900 ns. First stego
pixel arrives at 520 ns. This implies that the total delay for the BEMD processor is
480 ns. This is obtained by subtracting the initial 40 ns latency. The frame rate of 549
fps is achieved in the proposed method. Therefore, the proposed architectures are well
suited for real-time operation.
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Fig. 21 Mean structural similarity index measurement (MSSIM)

6 Conclusions

Design of high-speed architectures and FPGA implementation of EMD algorithms, namely,

BEMD, MEMD, and FEMD for image steganography have been presented. The implemen-
tation can also be used to embed secret information in audio and video sequence. Verilog RTL
modelling style hardware description conforms to industry standard and offers high through-
put. The proposed method works for ASIC as well with more throughputs as compared to
FPGA implementation. New performance enhancement techniques such as pipelining and
parallel processing are exploited to each of the modules to increase the speed of operation. The
entire design is implemented on Xilinx FPGA device, XC7A75TCSG324–1 with single chip
density of two million gates. Simulation, Synthesis, and FPGA realization are carried out using

Fig. 22 Peak signal to noise ratio (PSNR)

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Fig. 23 Mean squared error (MSE)

ModelSim, Matlab, Synplify, and Xilinx Vivado tools respectively. It is found that the
proposed framework is capable of achieving 549 fps which are suited for real-time operation.
Qualitative metrics such as MSSIM, MSE, and PSNR are used in order to test the quality of
stego images. The detailed experimental result presented shows that the proposed methods
outperform the other existing methods. Work has been initiated to implement Syndrome trellis
code (STC) and double STC to improve the security of the system on FPGA/ASICS. Use of
dual Ram to store the pixels for parallel processing is considered for the high-speed operation.

Fig. 24 Timing diagram for illustrating the pipeline operation of BEMD steganography. Note: Acronyms used in
the timing diagram are as follows: P: Pixels, SM: Secret Message, SA: Saturation Avoidance, MAC: Multiply
and Accumulate, MOD: Modulus Operator, SUB: Subtractor, CMP: Comparator
Multimedia Tools and Applications (2019) 78:18309–18338 18335

Publisher’s Note Springer Nature remains neutral with regard to jurisdictional claims in published maps and
institutional affiliations.

References

1. Biswapati J, Debasis G, Kumar MS (2017) Dual-image based reversible data hiding scheme through pixel
value differencing with exploiting modification direction. In: Proceedings of the first international confer-
ence on intelligent computing and communication. Springer, Singapore
2. Chakraborty S, Jalal AS, Bhatnagar C (2017) LSB based non-blind predictive edge adaptive image
steganography. Multimed Tools Appl 76(6):7973–7987
3. Denemark T, Fridrich J (2017) Steganography with multiple JPEG images of the same scene. IEEE
Transactions on Information Forensics and Security 12(10):2308–2319
4. De-Sheng F, Jing Z-J, Zhao S-G, Fan J (2014) Reversible data hiding based on prediction-error histogram
shifting and EMD mechanism. AEU Int J Electron Commun 68:933–943
5. Dhawale CA, Jambhekar ND (2017) Digital image steganography. Advanced Image Processing Techniques
and Applications
6. Fridrich J, Pevny T, Kodovsky J (2007) Statistically undetectable JPEG steganography: dead ends, challenges,
and opportunities. In: Proceeding 9th workshop on multimedia and security. ACM, New York, pp 3–14
7. Gómez-Hernández E, Feregrino-Uribe C, Cumplido R (2008) FPGA Hardware Architecture of the
Steganographic Context Technique. IEEE 18th International Conference on Electronics, Communications
and Computers, p 123–128
8. Hong W, Chen T-S (2012) A novel data embedding method using adaptive pixel pair matching. IEEE
Transactions on Information Forensics and Security 7(1)
9. W. James MacLean (2005) An Evaluation of the Suitability of FPGAs for Embedded Vision Systems. In: IEEE
Computer Society Conference, Computer Vision and Pattern Recognition (CVPR) Workshops, p 131–131
10. Jung K-H, Yoo K-Y (2009) Improved exploiting modification direction method by Modulus operation.
International Journal of Signal Processing, Image Processing, and Pattern 2(1)
11. Kasana G, Singh K, Bhatia SS (2017) EMD-based steganography techniques for JPEG-2000 encoded
images. Int J Wavelets Multiresolution Inf Process 15(3):1750020
12. Kieu TD, Chang C-C (2011) A steganographic scheme by fully exploiting modification directions. Expert
Syst Appl 38:10648–10657
13. Kim HJ, Kim C, Choi Y, Wang S, Zhang X (2010) Improved modification direction methods. Journal of
Computers & Mathematics with Applications 60(2):319–325
14. Kumar V, Kumar D (2017) A modified DWT-based image steganography technique. Multimed Tools Appl:1–30
15. Lee C-F, Wang Y-R, Chang C-C (2007) A steganographic method with high embedding capacity by
improving exploiting modification direction. IEEE Proceedings on Intelligent Information Hiding and
Multimedia Signal Processing 1
16. Li J-J, Wu Y-H, Lee C-F, Chang C-C (2018) Generalized PVO-K embedding technique for reversible data
hiding. International Journal of Network Security 20(1):65–77
17. Manyika J, Chui M, Bughin J, Dobbs R, Bisson P, Marrs A (2013) Disruptive technologies: advances that
will transform life, business, and the global economy. McKinsey Global Institute, San Francisco
18. Niu X, Ma M, Tang R, Yin Z (2015) Image steganography via fully exploiting modification direction.
International Journal of Security and its Applications 9(5):243–254
19. Omoomi M, Samavi S, Dumitrescu S (2011) An efficient high payload ±1 data embedding scheme. J
Multimed Tools Appl 54:201–218
20. Pradhan A, Sahu AK, Swain G, Sekhar KR (2016) Performance evaluation parameters of image steganog-
raphy techniques. Research Advances in Integrated Navigation Systems (RAINS), IEEE, p 1–8
21. Rabie T, Kamel I (2017) Toward optimal embedding capacity for transform domain steganography: a quad-
tree adaptive-region approach. J Multimed Tools Appl 76(6):8627–8650
22. Rajagopalan S, Amirtharajan R, Upadhyay HN, Rayappan JBB (2012) Survey and analysis of hardware
cryptographic and steganographic systems on FPGA. J Appl Sci 12:201–210
23. Ramalingam B, Amirtharajan R, Rayappan JBB (2014) Stego on FPGA: an IWT approach. Sci World J
2014:192512, 9 pages. https://doi.org/10.1155/2014/192512
24. Roy R, Changder S, Sarkar A, Debnath NC (2013) Evaluating Image Steganography Techniques: Future
Research Challenges. International Conference on Computing, Management and Telecommunications
(ComManTel 2013) [IEEE], pp. 309–314, January 21–24, 2013
25. Safaa Younus Alsaffawi Z (2017) Image steganography by using exploiting modification direction and
knight tour algorithm. Journal of Al-Qadisiyah for Computer Science and Mathematics 8(1):1–11
18336 Multimedia Tools and Applications (2019) 78:18309–18338

26. Saidi M, Hermassi H, Rhouma R, Belghith S (2016) A new adaptive image steganography scheme based on
DCT and chaotic map. Multimed Tools Appl 76:1–18
27. Shet KS, Aswath AR, Hanumantharaju MC, Gao X-Z (July 2016) Design and development of new reconfigurable
architectures for LSB/multi-bit image steganography system. Multimed Tools Appl 76(11):13197–13219
28. Sharma VK, Srivastava DK (2017) Comprehensive data hiding technique for discrete wavelet transform-
based image steganography using advanced encryption standard. Computing and Network Sustainability,
Springer, Singapore 12:353–360
29. Shen S-Y, Huang L-H (2015) A data hiding scheme using pixel value differencing and improving exploiting
modification directions. J Comput Secur 48:131–141
30. Shih FY (2017) Multimedia security: watermarking, steganography, and forensics. CRC Press, Boca Raton
31. Vallathan G, Balachandran K, Jayanthi K (2017) Enhanced data security and integrity using Contourlet
transform for medical images. Indian J Sci Technol 10(8)
32. Wang Z-H, Kieu TD, Chang CC, Li MC (2010) A novel information concealing method based on exploiting
modification direction. Journal of Information Hiding and Multimedia Signal Processing 1(1):1–9
33. Wang C-C, Kuo W-C, Huang Y-C, Wuu L-C (2017a) A high capacity data hiding scheme based on re-
adjusted GEMD. J Multimed Tools Appl, ISSN: 1380–7501, p 1–15
34. Wang Z, Yin Z, Zhang X (2017b) Distortion function for JPEG steganography based on image texture and
correlation in DCT domain. IETE Technical Review, p 1–8
35. Xu J, Zhang W, Jiang R, Hu X, Yu N (2017) Optimal structural similarity constraint for reversible data
hiding. J Multimed Tools Appl 76(14):15491–15511
36. Yao H, Qin C, Tang Z, Tiana Y (2017) Improved dual-image reversible data hiding method using the
selection strategy of shiftable pixels' coordinates with minimum distortion. Signal Process 135:26–35
37. Zaidan BB, Zaidan AA (2017) Software and hardware FPGA-based digital watermarking and steganogra-
phy approaches: toward new methodology for evaluation and benchmarking using multi-criteria decision-
making techniques. Journal of Circuits, Systems, and Computers 26(7):1750116
38. Zhang X, Wang S (Nov. 2006) Efficient Steganographic embedding by exploiting modification direction.
IEEE Commun Lett 10(11):781–783
39. Zhou H, Chen K, Zhang W, Yu N (2017a) Comments on steganography using reversible texture synthesis.
IEEE Trans Image Process 26(4):1623–1625
40. Zhou W, Zhang W, Yu N (2017b) A new rule for cost reassignment in adaptive steganography. IEEE
Transactions on Information Forensics and Security 12(11):2654–2667

K. Sathish Shet received his B. E degree in Electronics and Communication Engineering, M. Tech degree in
VLSI Design and Embedded Systems and Ph. D from Visvesvaraya Technological University, Belgaum, India in
2000, 2006, and 2019 respectively. He is currently an Assistant Professor in the Department of Electronics and
Communication Engineering (ECE) at JSS Academy of Technical Education. He has published six technical
articles in peer-reviewed journals and proceedings such as Springer, IEEE, etc. His research interests include
VLSI and Image processing.
Multimedia Tools and Applications (2019) 78:18309–18338 18337

A. R. Aswath received his B. E, M. Tech, and Ph. D degrees in Low power VLSI Design from MGR University,
Tamilnadu, India in 1991, 1994, and 2006, respectively. He is currently a Professor and Head of the Department
of Telecommunication Engineering of Dayananda Sagar College of Engineering, Bengaluru, India. He has
published 25 technical articles and proceedings in IEEE, Springer, Elsevier, etc. His area of interests includes
Low power VLSI design and Embedded systems.

M. C. Hanumantharaju received his B. E, M. Tech, and Ph. D degrees in VLSI Signal and Image Processing
from Visvesvaraya Technological University, Belgaum, Karnataka, India in 2001, 2004 and 2014, respectively.
He is currently a Professor and Head of the Department of ECE at BMS Institute of Technology and
Management, Bengaluru, India. He has published two books and 50 technical articles in refereed journals and
proceedings such as IEEE, Intelligent Systems, Particle Swarm Optimization, etc. His research interests include
Design of Hardware Architectures for Signal and Image Processing Algorithms, RTL Verilog Coding, FPGA/
ASIC Design.
18338 Multimedia Tools and Applications (2019) 78:18309–18338

Xiao-Zhi Gao received his, D. Sc. degree in Electrical Engineering from Helsinki University of Technology,
Finland in 1999. He is currently a Professor in the School of Computing, University of Eastern Finland, Finland.
He has published more than 350 technical articles in refereed journals and conference proceedings. His research
interests include nature-inspired computing methods with applications in optimization, prediction, data mining,
signal processing, and control.