Digital Signal Processing 134 (2023) 103889

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Digital Signal Processing

journal homepage: www.elsevier.com/locate/dsp

FPGA image encryption-steganography using a novel chaotic system

with line equilibria
Sun Jing-yu a , Cai Hong a , Wang Gang b , Gao Zi-bo b , Zhang Hao b,∗
a
College of Software, Taiyuan University of Technology, Jinzhong 030600, China
b
College of Information and Computer, Taiyuan University of Technology, Jinzhong 030600, China

a r t i c l e i n f o a b s t r a c t

Article history: The wide dissemination of images makes its protection problems urgent. Chaos theory is widely applied
Available online 23 December 2022 since it provides better solutions to image protection. This paper introduces a novel chaotic system
that has line equilibrium points. Chaotic signals generated by chaotic systems are used in encryption
Keywords:
and steganography to enhance security. Besides, the scrambling-diffusion encryption system is combined
Chaotic system
Line equilibria
with the least significant bit (LSB)-pixel value differencing (PVD) steganography algorithm. The proposed
Digital circuit algorithm process is reversible and the extracted image is lossless. And the whole system is designed and
Encryption-steganography implemented on a field programmable gate array (FPGA), which improves the embedding efficiency and
achieves high throughput while ensuring good image quality.
© 2022 Elsevier Inc. All rights reserved.

1. Introduction

Since J. Fridrich first combined chaotic systems with image encryption in the 1990s [1], chaotic systems have been widely used in
cryptography because of their ergodicity, pseudo-randomness, and initial value sensitivity. Scholars have been deepening their research on
chaotic systems to pursue better adaptation of chaotic systems to cryptography. Solving and analyzing the equilibrium point of chaotic
systems is an important content of qualitative analysis of chaotic systems. Many scholars have used the properties and types of equilibria
to construct new chaotic systems [2,3]. Among them, chaotic systems without equilibrium and infinite equilibria have hidden attractors,
which are very important in theoretical problems and applications. Dong et al. [4] presented a novel four-dimensional hyperchaotic
system, complex dynamical behaviors and coexisting attractors of the system are investigated and discussed. Wang et al. [5] proposed
a new memristive chaotic system that has a plane of equilibria and two other lines of equilibria via exhaustive computer searching.
Jahanshahi et al. [7] studied a chaotic system without equilibrium, and the chaotic behavior of the system is studied by designing and
implementing analog circuits. Compared with software-simulated chaotic systems, hardware-implemented chaotic systems can easily and
stably observe chaotic signals using various measuring instruments. However, the design of the analog circuit to produce chaotic signals
is very easy to be affected by the outside world due to analog elements’ nature. Using modern digital signal processing technology can
make the continuous chaotic signal stable and reliable. Thus, FPGA has become more of a choice in modern digital signal processing by
its large capacity, high density, and reliability.
With the wide spread of images on multimedia platforms, the emerging stealing of image information has led to the increasing demand
for secret image communication. Encryption is widely used as a universal method of information protection. Research on the combination
of encryption and the chaotic system has also been promoted in recent years [23–25]. However, the encrypted images transmitted in a
public channel are easy to attract the attention of attackers. To solve this problem, researchers introduce Image steganography which hides
the secret image information in the cover image. Image steganography uses the spatial domain method to embed secret information into
pixel values [26,27] or converts images to frequency domain before embedding [28,29]. In addition, because of the achievements of neural
networks in the image field, image steganography based on the neural network has also been further explored [30,31].
Steganalysis technology is also evolving [32,33], and using steganography alone is inadequate to protect images. The combination of
steganography and encryption can protect the image information from different aspects [8]. Therefore, research on image encryption

* Corresponding author.
E-mail address: [email protected] (H. Zhang).

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S. Jing-yu, C. Hong, W. Gang et al. Digital Signal Processing 134 (2023) 103889

Fig. 1. Transformation process of the proposed system.

steganography double-layer image security systems has been studied in recent years. Maji et al. [9] proposed a spatial domain image
steganography method that uses XOR operation to encrypt the data and higher-order pixel bits to embed the data. However, only diffu-
sion is performed during the encryption process and the location information of the image is not changed, the security of the algorithm
is insufficient. Jaradat et al. [10] proposed a steganography method using particle swarm optimization and chaos theory and the re-
sults showed that the steganographic images have high quality. However, the chaotic system used in this work is low-dimensional and its
chaotic behavior is relatively simple. Khandelwal et al. [11] proposed an image scrambling method. In this article, discrete wavelet transfor-
mation (DWT) and singular value decomposition (SVD) were used to embed the secret information into the cover image. Although a high
embedding capacity is achieved in this work, the extracted image is lossy and the quality of the secret image is difficult to be guaranteed.
In addition, due to the limitation of the software, the efficiency and real-time performance of steganography also need to be strengthened.
This work studied the hardware implementation of an encryption-steganographic security system based on chaos theory. The main
contribution of this paper can be concluded as follows: (1) A novel 4-dimensional chaotic system with line equilibria is proposed and
analyzed. The system is further verified by FPGA digital circuit. (2) The proposed algorithm is a lossless reversible data-hiding scheme. The
secret image is encrypted and dynamically embedded by the combination of PVD and LSB. (3) The algorithm is realized on FPGA, which
highly improves the embedding efficiency. The high throughput and low power dissipation indicate the good performance of the design.
The rest of this paper is organized as follows: chapter 2 gives the chaotic system model and its relevant analysis. Chapter 3 introduces
the encryption method and steganographic process. The oscilloscope verification of the chaotic system and FPGA implementation of the
steganographic algorithm are illustrated in chapter 4. Chapter 5 presents the experimental results. Finally, the conclusion is drawn in
chapter 6.

2. Chaotic system model and analysis

The proposed chaotic system is derived from Sprott B-type chaotic flow by adding a linear term [6]. The ordinary differential equation
(ODE) described in Fig. 1(1) is the original model of the Sprott B-type chaotic system. Switch the state variables x and y and introduce
parameters a, b and c, the ODE becomes Fig. 1(2). A linear item with a parameter d is added as the state variable w to make the
constructed chaotic system has line equilibriums. The final equation in Fig. 1(3) is the proposed chaotic system.
Consider the mathematical model in Fig. 1(3):
⎧
⎪
⎪ ẋ = a( y − x)
⎨
ẏ = bxz
. (1)
⎪
⎪ ż = c w − xy
⎩
ẇ = dy
The equilibrium points can be obtained by solving ẋ = 0, ẏ = 0, ż = 0 and ẇ = 0.
⎧
⎪
⎪ a( y − x) = 0
⎨
bxz = 0
. (2)
⎪
⎪ c w − xy = 0
⎩
dy = 0
Obviously, for non-zero parameters, (0, 0, z, 0) is the equilibrium point of the system. Therefore, the system is a four-dimensional
chaotic system with line equilibriums (4DLECS). From a computational point of view, these attractors are hidden, and knowledge about
equilibria does not help in their localization [6]. When parameters of system (1) are set as a = 2, b = 6, c = 2 and d = 0.1, while initial
values are [1, 1, 1, 1], the state diagram of 4DLECS can be obtained (cf. Fig. 2)
Lyapunov exponent is an essential quantitative index to measure the dynamic characteristics of the system. The existence of dynamic
chaos in the system can be intuitively judged by whether the maximum Lyapunov exponent (MLE) is greater than zero. The Lyapunov
exponents of 4DLECS are presented in Fig. 3(a). The calculated results are λ1 = 0.3405, λ2 = 0.0033, λ3 = −0.0169 and λ4 = −2.3269. Since
the MLE is greater than zero, the system is in a chaotic state. Table 1 compares a series of chaotic systems with infinite equilibriums. It
can be seen from the table that the MLE of 4DLECS is larger, which indicates that it has better unpredictability.
The Poincare part of the continuous system can represent the topological properties of the phasing orbit of the system. The periodic,
quasi-periodic, and chaotic motions of the system are represented by isolated points or finite isolated points distributed in a certain region,
closed curves, and uncountable sets respectively. When the system response is chaotic motion, the Poincare part may appear as a scatter
plot of discrete accumulation. The Poincare map of the section z = 0 is shown in Fig. 3(b). Where xn indicates the Poincare map of n
iterations and yn the periodic solutions of the differential equation. The flaky cutoff shows two swifts flying in shape, which also indicates
that the system is in a chaotic state.
The random detection typically uses probability statistics to check whether the sequence under test satisfies certain random character-
istics. The randomness of 4DLECS is evaluated by the NIST SP800-22 test, which provides 15 tests to check the randomness of the binary
sequences used in the cryptographic system. Tests are performed using binary sequences of length 106 , and each test has a significance
level α = 0.01. The probability value (P-value) is obtained after the statistical tests. A P-value greater than 0.01 indicates that the test
sequence is random. Conversely, if the P-value is less than 0.01, the sequence is not random. The test results in Table 2 are all greater
than 0.01, indicating that the sequences generated by 4DLECs have good pseudo-randomness and can be applied to encryption.

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S. Jing-yu, C. Hong, W. Gang et al. Digital Signal Processing 134 (2023) 103889

Fig. 2. Hidden attractors of 4DLECS (a) x-y plane, (b) x-z plane, (c) y-z plane, (d) x-y-z 3D view, (e) x-y-w 3D view.

Fig. 3. Chaotic characteristics of the 4DLECS (a) Lyapunov exponents, (b) Poincare section. (For interpretation of the colors in the figure(s), the reader is referred to the web
version of this article.)

Table 1
Comparison of MLEs.

Ref. [7] Ref. [12] Ref. [13] 4DLECS

MLE 0.185 0.15405 0.0553 0.3405

3. Encryption and steganography method

The encryption-steganography algorithm presented is reversible and lossless. The key is required when the receiver needs to extract
the secret image from the steganography image. The key consists of two parts of information: the initial values of the chaotic system and
the size of the secret image. The original cover image is not required. The secret image is shuffled before being converted into binary
information. For the diffusion of the encryption system, an XOR operation is performed between the chaotic sequence and the binary
secret data. The pseudo-code description of the encryption scheme is presented in Algorithm 1.

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Table 2
NIST SP800-22 test results using 4DLECS.

Sub-tests P-value Result

The Frequency Test 0.2593 Pass
Frequency Test within a Block 0.2156 Pass
The Runs Test 0.5705 Pass
Test for the Longest-Run-of-Ones in a Block 0.6570 Pass
The Binary Matrix Rank Test 0.0130 Pass
The Discrete Fourier Transform Test 0.0394 Pass
The Non-overlapping Template Matching Test 0.5497 Pass
The Overlapping Template Matching Test 0.5271 Pass
Maurer’s “Universal Statistical” Test 0.5049 Pass
The Linear Complexity Test 0.5721 Pass
The Serial Test (P-value 1) 0.3501 Pass
The Serial Test (P-value 2) 0.5337 Pass
The Approximate Entropy Test 0.6840 Pass
The Cumulative Sums Test (Forward) 1.0000 Pass
The Cumulative Sums Test (Reverse) 0.9998 Pass
The Random Excursions Test(m) 0.0505 Pass
The Random Excursions Variant Test(m) 0.4643 Pass

Algorithm 1 Secret image encryption.

Input: secret image P , chaotic sequence X , Y , Z
Output: encrypted data enData
1: function Encryption ( P , X , Y , Z)
2: [height, width] = size( P );
3: for i = 1: height
4: shuffle_row(:,i) = circshift( P (:,i), X (i));
5: end
6: for i = 1: width
7: shuffle_col(i,:) = circshift(shuffle_row(i,:),Y (i));
8: end
9: enData = bitxor(shuffle_col, Z);
10: end function

Table 3
Pixel difference range division.

[Low, High] Method Embedding bits

[0,15] LSB Chaotic_seq(i)
[16,31] 4
[32,63] 5
PVD
[64,127] 6
[128,255] 7

In Algorithm 1, the chaotic sequences X and Y are within the range of the image height and width, respectively. Z is a sequence in
the range of 8-bit pixel values. The function circshift performs the cyclic shift process of the image pixels. The output enData is the secret
information to be embedded.
The principle of the PVD concept is that human vision has a greater tolerance for edge regions than for smooth regions [14]. As a spatial
steganography method, PVD has shown high load, good visual quality, and resistance to steganography attacks. The LSB steganography
method is widely used in steganography due to its simple principle and high applicability. Using the LSB method in the smooth area of
the image, while the PVD method in the edge area of the image can effectively increase the embedding capacity while ensuring image
quality.
Divide the cover image into two-pixel non-overlapping pixel pairs. Calculate the absolute difference value of each pair. Since the pixel
value is between [0, 255], the absolute value of the difference also ranges to [0, 255]. Steganographic methods and bits are divided
according to the ranges of differences, as shown in Table 3.
Consider a pixel pair ( P i , P i +1 ), denote its difference value as di f f = | P i − P i +1 |. The embedding method is determined according to
the corresponding scope of the diff.
The number of embedded bits of the LSB is determined by the pseudo-random integer produced by the chaotic sequence. Read 2 × k
bits secret image information, where k = Chaotic_seq(i), Chaotic_seq[i ] ∈ [1, 2, 3]. The read secret information is embedded in the lower
k bits of the front and rear pixels, respectively. In order to ensure that the difference value range does not change after embedding, the
difference value of the new pixel pair needs to be obtained. If it exceeds 15, the following adjustments need to be made:

( P  i − 2k , P  i +1 + 2k ), P  i ≥ P  i +1
( P  i , P  i +1 ) . (3)
( P  i + 2k , P  i +1 − 2k ) P  i < P  i +1
The extraction process needs to extract the least-significant data according to the value of the chaotic sequence.
The number of PVD embedding bits depends on the corresponding range, which is t = log2 Low. The embedding process of PVD is as
follows:
Step 1: Read the t-bit secret information that needs to be embedded and convert it to a decimal value dec.
Step 2: Obtain the new difference value by ne wdi f f = Low + dec.

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S. Jing-yu, C. Hong, W. Gang et al. Digital Signal Processing 134 (2023) 103889

Fig. 4. The flowchart of the proposed algorithm.

Step 3: Get the modified value by V = |ne wdi f f − di f f |. Modify the pixel value according to the following formula to get stegano-
graphic pixel value pairs.
⎧
⎪
⎪ ( P +  V /2 , P i +1 −  V /2 ), P i ≥ P i +1 and ne wdi f f > di f f
⎨ i
  ( P i −  V /2 , P i +1 +  V /2), P i < P i +1 and ne wdi f f > di f f
( P i , P i +1 ) = . (4)
⎪
⎪ ( P i −  V /2 , P i +1 +  V /2 ), P i ≥ P i +1 and ne wdi f f ≤ di f f
⎩
( P i +  V /2 , P i +1 −  V /2), P i < P i +1 and ne wdi f f ≤ di f f
The extraction process is to first get the difference value between the pixel pairs, then subtract the lower boundary of the corresponding
range, and convert it into binary information of the corresponding number of bits.
The overall algorithm is composed of a complete scrambling-diffusion encryption system and a PVD-LSB steganography system. In
addition, dynamic embedding is also carried out by chaotic sequence in steganography. As the advantage of the encryption-steganography
double-layer security system, the steganography image is the final manifestation of the secret image. The embedding rules of the steganog-
raphy algorithm are necessary for the extraction of secret images. From this point of view, attacks against cryptography are ineffective. The
flowchart is shown in Fig. 4. The chaotic sequences generated by the chaotic system are used in the secret image encryption as well as in
the dynamic LSB embedding process of steganography. And the encrypted secret information is selected for the embedding method based
on the difference of the cover image pixel pairs. Finally, the steganographic image with little difference from the original cover image is
obtained.

4. FPGA implementation

As a kind of semi-custom circuit in the ASIC field, FPGA not only solves the shortage of custom circuits but also overcomes the
disadvantage of the gate number limitation of the original programmable devices. Currently, circuit designs with hardware description
language (Verilog or VHDL) can be quickly tested on FPGA development boards through simple synthesis and layout, which has become
the mainstream technology for modern IC design verification.

4.1. Chaotic oscillator of 4DLECS

Continuous systems must be discretized to be output on FPGAs. The commonly used discretization methods are the Euler method, the
Runge-Kutta method, and the Heun method. In order to save resources and ensure the accuracy of data, this paper uses the Euler method
to discretize 4DLECS. Consider τ as the integration step, the mathematical model of the 4DLECS Euler discretization algorithm can be
expressed as:
⎧
⎪
⎪ x(k + 1) = x(k) + τ · a( y (k) − x(k))
⎨
y (k + 1) = y (k) + τ · bx(k) z(k)
. (5)
⎪
⎪ z (k + 1) = z(k) + τ · (c w (k) − x(k) y (k))
⎩
w (k + 1) = w (k) + τ · dy (k)
As shown in the model, the value x(k + 1) is computed by using the value x(k) and y (k) in an iterative manner. The physical time of the
system at the end of each iteration can be denoted as t (k) = τ k. The digital circuit of 4DLECS is designed and implemented using FPGA.
The circuit diagram of 4DLECS can be seen in Fig. 5. The circuit is composed of Adder, Multiplier, and D Flip-Flop. The D Flip-Flops store
the state value x(k), y (k), z(k), and w (k) in the current iteration, and output these values as the initial conditions of the next iteration.
The combinational logic path composed of Adder and Multiplier computes the next state x(k + 1), y (k + 1), z(k + 1) and w (k + 1) given in

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S. Jing-yu, C. Hong, W. Gang et al. Digital Signal Processing 134 (2023) 103889

Fig. 5. Circuit of 4DLECS chaotic oscillator.

Fig. 6. Modelsim simulation waveform results.

Table 4
Resource occupancy of FPGA with the 4DLECS.

Resource Available Used Utilization

Total logic elements 10320 944 9%
Total combinational functions 10320 886 9%
Dedicated logic registers 10320 467 5%
Total pins 180 41 23%
Embedded Multiplier 9-bit elements 46 16 35%
Total PLLs 2 0 0%

Eq. (5). Then, the computed values are fed back to the input of D Flip-Flops. Whenever the rising edge of the clock is triggered, the state
variables are updated and their values are output to 32-bit ports ( X_o, Y _o, Z _o, and W _o).
The initial conditions x(0), y (0), z(0) and w (0) are assigned by setting the synchronous load ports of D Flip-Flops connected to 32-bit
input ports ( X_i, Y _i, Z _i, and W _i) when the system resets.
The Adder and Multiplier are designed in a hardware-friendly manner: fixed-point operation is used and constant coefficient multi-
plication is realized by shift and addition operation, which reduces the computational intensity. In addition, the embedded DSP slice is
utilized to optimize the area, frequency, and power consumption of the arithmetic units. The 4DLECS circuit was simulated using ModelSim
before implementation. The results of the chaotic oscillator are shown in Fig. 6.
The digital circuit is translated into FPGA bitstream, and the logic synthesis and place & route flow were performed on Quartus (Quartus
Prime 18.0 Standard Edition). The resource occupancy of FPGA is presented in Table 4. Note that the experiment is performed on Altera
Cyclone IV EP4CE10F17C8 FPGA, which integrated an analog-to-digital converter for output to an oscilloscope. The results show that only
9% of the total logic units are used in the chaotic oscillator, which leaves sufficient resources for the steganography process.

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S. Jing-yu, C. Hong, W. Gang et al. Digital Signal Processing 134 (2023) 103889

Fig. 7. Oscilloscope verification (a) Experimental devices, (b) X_o, Y _o plane, (c) Y _o, Z _o plane.

Fig. 8. Block diagram of the encryption subsystem.

The digital-to-analog converter chip DAC904E (14-bit) is used to convert the calculation result of FPGA into an analog output, which
is connected to the digital storage oscilloscope (DSO) UPO3203CS in order to observe the output waveform. Two output signals are
transferred to chip AD9767 for digital-to-analog conversion. The oscilloscope results are presented in Fig. 7.
The oscilloscope results in Fig. 6 are consistent with the corresponding plan view in Fig. 2, which illustrates the correctness of the
FPGA simulation.

4.2. Encryption and steganographic subsystems

The key to using FPGA for image processing lies in the storage of image data. If the traditional shift operation is used to implement the
scrambling part of the encryption process, it is necessary to wait for the completion of the transmission of the secret image data before
the subsequent operations can be performed, which ignores the advantage of the parallelism of the FPGA. Therefore, block random access
memory (BRAM) is used to store data, and the address change of each pixel shift is calculated and stored in another BRAM. The BRAM
can be generated by instantiating the IP core inside the FPGA and controlled through Verilog HDL code.
Consider a pixel located in (i, j), where 0 ≤ i < Row, 0 ≤ j < Col. According to the pseudo-random number generated by the chaotic
sequence, the shift number of row i is X [i], and the shift number of column j is Y [ j]. After cyclic shift by row, the new coordinate of
the pixel is:

(i , ( j + x[i ])%Col) . (6)

After cyclic shift by row, the new coordinate of the pixel is:

((i + y [ j ]) %Row , j ) . (7)

Therefore, the coordinate of pixel (i, j) after the scrambling is:

((i + y [( j + x[i ])%Col]) %Row , ( j + x[i ])%Col) . (8)

Fig. 8 describes the block diagram of the encryption subsystem. Block ShiftVector_X and ShiftVector_Y receive the chaotic signal and
produce the cyclic shift vector of pixels. The CircShift module calculates the according address of a pixel and performs an XOR operation
with chaotic signal z_o before transmitting to BRAM_2.
In order to enhance the stability and efficiency of embedding, the encrypted secret information will be embedded in the form of first-
in-first-out (FIFO), processing one pair of pixel values at one time. Its data address is automatically incremented by the internal read/write
pointer.
The block diagram of the steganographic section is presented in Fig. 9. Bram_3 stores the data of the cover image. BRAM_2 acts as a
temporary buffer that stores the binary information of the secret image. The bitstream_buffer obtains the secret data bits of the current
pixel pair according to the range and the chaotic signal w_o. A multiplexing selector determines whether the value of the new pixel pair
is from the PVD or LSB method.
In order to obtain more resources and better performance, the Xilinx Kintex7 xc7k325tfbv676-3 FPGA is used to experiment. The
verified RTL code is synthesized and implemented on Xilinx Vivado (version 2019.2). A bit file equivalent to the design generated by the
Vivado tool is downloaded to the FPGA device using the Joint Test Action Group (JTAG) cable. Moreover, by instantiating the virtual JTAG

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S. Jing-yu, C. Hong, W. Gang et al. Digital Signal Processing 134 (2023) 103889

Fig. 9. Block diagram of the steganography subsystem.

Fig. 10. The overall hardware design.

Fig. 11. Cover image examples (a) “Airplane”, (b) “Pepper”, (c) “Boat”, (d) “Baboon”.

module, the CPU or logic in FPGA can be debugged through the JTAG pins of FPGA devices. The Tool Command Language (TCL) control
interface is used to realize data read and write operations. The overall system design is shown in Fig. 10.

5. Experimental results and analysis

In this paper, the performance analysis of steganography results is divided into two parts according to the actual situation, software
analysis, and hardware analysis. The software analysis part will use MATLAB 2016b to analyze and compare the quality of steganographic
images and the embedding capacity of algorithms. Hardware analysis considers the resource occupancy, power consumption, and through-
put of FPGA design. The tested images are derived from USC-SIPI standard image dataset, the secret image is embedded in several cover
images. Fig. 11 presents some cover image examples, namely “Airplane”, Pepper”, “Boat” and “Baboon”.
Cover images with size 512 × 512 and secret images with size 256 × 256 are selected to experiment. The image data is transmitted in
hexadecimal format and the resulting steganographic data needs to be converted into an image. The experimental results are presented
in Fig. 12. It can be observed that there is little visual difference between the steganographic image and the cover image, and the secret
image is visually identical to the extracted image.
The histogram directly reflects the pixel distribution of the image, which is of great significance to grasp the image features. According
to the histogram of the cover image and the steganographic image given in Fig. 13, the change in pixel distribution before and after
steganography is subtle, which also demonstrates the algorithm’s good invisibility.

5.1. Imperceptibility and capacity analysis

Imperceptible means that the difference between the steganography image and the cover image should not be too large, which is an
important criterion to measure the steganography algorithm. Common indicators used to analyze image imperceptibility include mean

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Fig. 12. Experimental results (a) cover image ‘Lena’, (b) secret image ‘Man’, (c) steganographic image, (d) extracted image.

Fig. 13. Histogram analysis (a) ‘Airplane’, (b) ‘Pepper’, (c) ‘Boat’, (d) ‘Baboon’, (e)-(h) steganographic image of (a)-(d).

square error (MSE), peak signal noise ratio (PSNR), structural similarity (SSIM), universal image quality index (UIQI), and Pearson correla-
tion coefficient (PCC) [10,26].
Both PSNR and MSE measure image quality by the global size of pixel error between images. MSE represents the overall difference
between two images, and the larger the MSE, the more obvious the difference. The larger the PSNR value is, the smaller the distortion
degree between test images is. SSIM and UIQI can measure the degree of distortion and similarity of two images. PCC measures the degree
of linear correlation between two variables. Their ideal values are 1, and the closer to the ideal value, the more similar the images are.
The calculation formula for these indicators is as follows:

1 
W 
H
MSE = ( p i , j − p  i , j )2 , (9)
W ×H
i =1 j =1

2552
P S N R = 10 log , (10)
MSE
(2M c M s + C 1)(2σcs + C 2)
SSIM = , (11)
( M c2 + M s2 + C 1)(σc2 + σs2 + C 2)
4σcs M c M s
UIQ I = , (12)
(σc2 + σs2 )( M c2 + M s2 )
σcs
ρc,s = . (13)
σc σs
In the above equations, the p i , j , p  i , j represent the pixel value located in (i , j), while M c and M s represent the mean pixel value of
the cover image and steganographic image respectively. σc and σs indicates the standard deviation and σcs is the covariance of the cover
image and steganographic image, C 1 and C 2 are constants.

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Table 5
Imperceptibility and capacity test results.

Cover image MSE PSNR SSIM UIQI PCC Capacity BPP

Lena 6.8856 39.7514 0.9637 0.9985 0.9985 528686 2.02
Airplane 7.8115 39.2035 0.9622 0.9982 0.9982 530407 2.02
Boat 9.7886 38.2236 0.9706 0.9978 0.9977 533163 2.03
Pepper 7.1615 39.5807 0.9651 0.9988 0.9987 528621 2.02
Baboon 14.4271 36.5390 0.9826 0.9960 0.9960 544148 2.08
Average 9.2149 38.6596 0.9688 0.9979 0.9978 533005 2.03

Table 6
Comparison of steganographic metrics.

Images Lena Baboon Pepper Boat

Proposed PSNR 39.7514 36.5390 39.5807 38.2236
SSIM 0.9637 0.9826 0.9651 0.9706
Capacity 528686 544148 528621 533163
BPP 2.02 2.08 2.02 2.03
3-LSB method PSNR 35.70 35.70 35.69 35.70
Capacity 786432 786432 786432 786432
BPP 3.00 3.00 3.00 3.00
Ref. [14] PSNR 41.18 37.00 40.86 39.56
Capacity 409807 457087 407479 421965
BPP 1.56 1.74 1.55 1.61
On software

Ref. [15] PSNR 51.14 44.18 51.14 51.14

Capacity 262144 262144 262144 262144
BPP 1.00 1.00 1.00 1.00
Ref. [16] PSNR 46.96 43.11 46.10 45.34
Capacity 409807 457105 407643 422194
BPP 1.56 1.74 1.56 1.61
Ref. [17] PSNR 33.21 31.74 33.55 32.84
Capacity 1049742 1054327 1050571 1051124
Ref. [18] PSNR 35.28 - 35.83 -
SSIM 0.98 - 0.98 -
Capacity 799801 - 799957 -
BPP 3.00 - 3.00 -
Ref. [19] PSNR - 33.11 - -
SSIM - 0.9305 - -
On FPGA

Capacity - 262144 - -
Ref. [22] PSNR 38.4670 38.0517 - -
SSIM 0.8901 0.9269 - -
Capacity 1048576 1048576 - -

The hidden capacity of steganography algorithms can be calculated using bit per pixel (BPP) [27]. BPP represents the number of secret
image bits hidden in each pixel value of the cover image. The value of BPP must be high to ensure the high embedding capacity of
steganography algorithms. The value of BPP is calculated:

bits
BP P = . (14)
H×W
In Eq. (14), ‘bits’ stands for the total bits of the embedded secret image, while H and W represent the height and width of the cover
image respectively.
The secret image ‘Man’ is tested and embedded in different cover images. Based on the size of the secret image, the value of BPP can
be obtained as 2. Since the embedded bits of LSB are dynamically determined by 4DLECS, the chaotic sequence generated is also related
to the calculation of capacity, so as to obtain the final BPP value. The analysis results are presented in Table 5.
The average PSNR is 38.6956, which can maintain a good visual effect. The values of SSIM, UIQI, and PCC are very close to their ideal
values. The average capacity and BPP value are 533005 bits and 2.03, respectively. The test results reveal that the proposed algorithm has
a relatively high capacity while satisfying visual requirements.
Moreover, the results given by relevant literature are compared with software methods and hardware methods, as shown in Table 6.
The data from Table 6 are all based on 512 × 512 test cover images.
The three-LSB substitute method has a fixed capacity for the size of 512 × 512 images, but the PSNR value is relatively low. Wu et al.
proposed the PVD method in Ref. [14], which has a better PSNR value and smaller capacity. Ref. [15] described an algorithm using LSB
matching. Its PSNR value is higher but dwarfed in capacity. Wang et al. proposed a method using PVD and modulus function in Ref. [16].
The PSNR value is promoted compared to Ref. [14], but the capacity did not improve. Jung et al. used PVD and LSB on the bit plane in
Ref. [17]. This scheme has a higher embedding capacity but a lower PSNR value. And same for the algorithm which is also based on PVD-
LSB in Ref. [18], the capacity and BPP value is higher. Conversely, the PSNR and SSIM values are lower than the proposed scheme. From
the comparison of the effects of FPGA hardware steganography, the proposed steganography scheme has a better SSIM value and PSNR
value, which proves that the algorithm has a better visual effect. In addition, Ref. [19] and Ref. [22] are researches based on hardware

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S. Jing-yu, C. Hong, W. Gang et al. Digital Signal Processing 134 (2023) 103889

Table 7
System resource usage.

Proposed Ref. [19] Ref. [20]

FPGA Xilinx Kintex 7 Xilinx Virtex 7 Xilinx Virtex 6
Resource Utilization Available Utilization (%) Utilization Available Utilization (%) Utilization (%)
LUT 5565 203800 2.73 38729 303600 12.8 18
LUTRAM 587 64000 0.92 - - - -
FF 7438 407600 1.82 16865 607200 2.8 6
BRAM 263.5 445 59.21 2 130800 0.002 -
DSP 12 840 1.43 33 2800 1.2 30
IO 5 400 1.25 - - - -
BUFG 3 32 9.38 - - - -
MMCM 1 10 10 - - - -

Fig. 14. On-chip power dissipation.

Table 8
Power dissipation comparison.

Proposed Ref. [21] Ref. [22]-method 1 Ref. [22]-method 2

FPGA Xilinx Kintex 7 Xilinx Artix 7 Xilinx Virtex 7
Total 0.443 W 3.807 W 1.14 W 1.238 W

image steganography. As can be seen from the data, the proposed algorithm is also better than Ref. [19] in terms of capacity and Ref. [22]
in terms of SSIM.

5.2. Hardware performance analysis

The resource usage of the overall system is presented in Table 7. Since the design uses BRAM to accomplish image scrambling, the
utilization rate of BRAM is 59.21%. However, it can still be seen from the table that the overall design takes up less than 3% of LUT
resources, and the occupancy rates of other resources also remained low. Compared with the design in Ref. [19], this design only occupies
1/7 of LUT resources. Although Ref. [20] only provides the proportion data, it can also be found that the proportion of LUT is only 1/6 of
the given data.
Power analysis is an essential part of FPGA design. The total power consumption of the whole FPGA design consists of static power
consumption and dynamic power consumption. FPGA dynamic power consumption is mainly reflected in memory, internal logic, clock,
and I/O consumption power consumption. The power consumption of the design is presented specifically in Fig. 14.
Table 8 compares the total power with relevant literature. The proposed design has a total power of 0.443 W, which is lower than
other steganographic hardware designs in Ref. [21] and Ref. [22]. The comparison results indicate that the proposed design has better
performance in power dissipation.
The maximum frequency of the design is 109.15 MHz. And 147,468 clock cycles are obtained for processing 256*256 cover images and
128*128 secret image. The system throughput can be calculated as:

processed bits (256 × 256 + 128 × 128) × 8

throughput = = 1
≈ 485.07 Mbps. (15)
time
109.15 MHz
× 147468
The throughput comparison is shown in Table 9. It’s undisputed that the proposed design has a high throughput which is more than
100 times of both methods in Ref. [22]. The computed result and comparison of throughput demonstrate that the proposed design is
capable of processing massive data and meeting the requirements of real-time communication.

6. Conclusion

A new four-dimensional chaotic system with line equilibrium points is proposed in this paper. The chaotic signal generated by the
chaotic system is then used to enhance the security of secret image information. The encryption system and the PVD-LSB steganography is
implemented using FPGA technology. The PSNR between the cover image and the steganographic image can reach 38.6596, and the average

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S. Jing-yu, C. Hong, W. Gang et al. Digital Signal Processing 134 (2023) 103889

Table 9
Throughput comparison.

Proposed Ref. [22]-method 1 Ref. [22]-method 2

FPGA Xilinx Kintex 7 Xilinx Virtex 7
throughput 485.07 Mbps 3.5 Mbps 4.09 Mbps

embedding capacity is 533005 bits. On the premise of maintaining a good visual effect, the proposed algorithm has a high embedding
capacity. Moreover, the system only consumes less than 3% LUT resources and its throughput is about 485.07 Mbps. These experimental
results show that the proposed technology can improve steganography efficiency while meeting the image quality requirements and
ensuring the embedding capacity. In addition, the proposed algorithm can be applied to color images. The work in this paper has enriched
the research of nonlinear systems and provided a direction for the research of real-time cryptography-steganography security systems.

CRediT authorship contribution statement

Sun Jing-yu: Data curation, Methodology.

Cai Hong: Methodology, Writing-Original draft preparation, Writing-Reviewing and Editing.
Wang Gang: Supervision, Validation.
Gao Zi-bo: Hardware, Validation.
Zhang Hao: Supervision.

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to
influence the work reported in this paper.

Data availability

No data was used for the research described in the article.

Acknowledgment

This research is supported by the National Natural Science Foundation of China (Nos: 61702356), Project 1331 of Shanxi Province (Nos:
SC9100026), Natural Science Foundation of Shanxi Province (Nos: 20210302124050).

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Jing-yu Sun received his PHD degree from Taiyuan University of Technology, China, in 2010. He is currently working with the
College of Software Engineering, Taiyuan University of Technology, China. His research interests include recommendation system, big
data and artificial intelligence.

Hong Cai received the bachelor’s degree from Hainan University, China, in 2020. She is now studying for a master’s degree in the
College of Software Engineering, Taiyuan University of Technology, China. Her research interests cover image processing, cryptography.

Gang Wang received his PHD degree from Beihang University, China, in 2014. He is currently working with the College of Infor-
mation and Computer, Taiyuan University of Technology, China. His research interests include neural network, image processing and
artificial intelligence.

Zi-bo Gao is currently studying for bachelor’s degree in College of Information and Computer, Taiyuan University of Technology,
China.

Hao Zhang received the PHD degree in computer software and theory from Dalian University of Technology, China, in 2016. He
is currently working with the College of Information and Computer, Taiyuan University of Technology, China. His research interests
include systems biology, complex networks and image processing.

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