Crystal growth and Wafer preparation

Si vs. Ge
• Ge was unstable in certain applications due to narrow gap of 0.66
eV at 300 K, whereas Si has band gap of 1.11 ev at 300 K.

• Si becomes an obvious choice as the devices operate till 150 0C vs

100 0C for Ge.

• SiO2 is suitable for device applications.

• Electronic grade Ge is more costly.

Crystal growth and Wafer preparation
Si Crystal Growth

Starting SiO2
material
Distillation and
reduction
Polycrystalline
semiconductor
Crystal growth
Single
crystal
Grind, saw and
polish
Wafer

Process flow from starting material to polish wafer

Starting material is quartzite.

Preparation of MGS

Firstly, metallurgical grade Si (MGS) is produced in an arc

furnace.

2C (solid) +SiO2 ( solid) = Si(L)+2CO (g)

Finally, 98 % pure MGS is solidified.

Formation of SiHCl3 (Trichlorosilane)

The silicon is pulverized and treated with hydrogen chloride (HCl) at 300°C to
form trichiorosilane (SiHCl3 ).

Reaction at 300 0C

Si (s)+3HCl(g) = SiHCl3 (g)+H2 (g)+ heat

SiHCl3 is a liquid at room temperature (b.p = 32 C)

Fractional distillation of SiHCl3 for removing the unwanted chlorides.

EGS (Electronic grade semiconductor)

EGS (Electronic grade semiconductor) : Polycrstalline Si is the raw material

for the preparation of single crystal Si. EGS is prepared from the purified SiHCl 3
through a CVD process.

SiHCl3 + 2H2 = 2Si (s)+6HCl (g)

What is chemical vapor deposition

A chemical process to produce high purity materials.

Any wafer/substrate is exposed to volatile precursors, which

react/decompose on the substrate surface to form desirable material.
chemical vapor deposition
This diagram shows the nomenclature for the different phase transitions
 H2
+

A resistance heated rod of Si serves as a nucleation point for Si deposition. Finally,

EGS rods are formed. Si is deposited on Si to avoid foreign contamination.
Single Crystal Growth Techniques

Once we have Electronic Grade Silicon, Next step it is to obtain a single crystal.

Crystal growth can be broadly classified as:

1. Bridgman technique.

2. Czochralski technique.

3. Float Zone Technique.

Silicon that is available today are grown by Czochralski technique and sometimes
further purified.
 Bridgman technique
 A quartz tube. The mouth of
the tube is sealed. It is
evacuated and sealed.

 Inside tube, we have a quartz

boat.

 In the boat, a seed crystal and

charge are placed.

 Charge is heated to its melting

point, but make sure that the
seed crystal is not molten.

 Therefore, the temperature

profile of the furnace has to be
Bridgman system of crystal growth
something as shown in the
figure.
 Seed is kept at a lower temperature, while the charge is at high
temperature.

 The solidification is taking place at the seed and the surface of

the boat is going to act as a confining barrier.

 It creates a lot of stress on the crystal.

 Due to stress, dislocations will be formed.

 Therefore, Bridgman growth single crystals have a lot of

dislocations in them.

 Silicon expand when solidified ( density of solid is less than

density of silicon in melt and thus volume occupy will be more.
3
Density (near r.oom. Temp.) 2.3290 g/cm
3
when liquid (at melting .point) 2.57 g/cm
Czochralski growth Technique

 Czochralski system of crystal growth

is actually a much more complicated
system, compared to a Bridgman
system.

 But we can grow single crystals with

much less defects.

 Large size single crystal

 Dopant can be introduced easily.

 Contains many small amount of

impurities like carbon, oxygen, Iron
etc.
Czochralski System

Four main parts of the Czochralski crystal growth system.

1. Furnace.

2. Crystal Pulling mechanism

3. Ambient Control

4. Control systems
Crystal pulling mechanism:

We have a pull rod which is passed through a opening at the top and at
the end of the pull rod, a small seed crystal is fixed in a chuck.

Ambient control:

 We have a graphite susceptor and graphite heaters.

 Therefore, there must not be any oxygen inside the system.
 Evacuate the quartz chamber.
 Fill it up with an inert ambient - argon or nitrogen,
 Maintain atmospheric pressure or sometimes even reduced pressure.

Control Systems:

Temperature control and microcontroller based rod pulling system.

• Si used for crystal growth is purified from SiO2 (sand) through refining,
fractional distillation and CVD.

• The raw material contains < 1 ppb impurities. Pulled crystals contain O
(≈ 1018 cm-3) and C (≈ 1016 cm-3), plus any added dopants placed in the melt.

• Essentially all Si wafers used for ICs

today come from Czochralski grown
crystals.

• Polysilicon material is melted, held

at close to 1417 ˚C, and a single crystal
seed is used to start the growth.

• Pull rate, melt temperature are all

important control parameters.
(More information on crystal growth at
http://www.memc.com/co-as-description-crystal-growth.asp
Also, see animations of http://www.memc.com/co-as-process-animation.asp) (Photo courtesy of Ruth Carranza.))
Modeling Crystal Growth

We wish to find a relationship between pull rate and crystal diameter

Heat balance:

latent heat of fusion heat heat

(i.e. crystallization) conducted radiated
+ = =
through the away
heat conducted from crystal (C).
melt to crystal (B)

(A)
 L  latent heat of fusion
Freezing occurs between isotherms X1
dm
and X2.  amount of freezing per unit time
dt
dm dT dT
(1) L  kL A1  k S A2 k L  thermal conductivity of liquid
dt dx 1 dx 2 dT
 thermal gradient at isotherm x1
dx 1
(A) (B) k S  thermal conductivity of solid
 A1,2 = Cross-sectional area
dT
 thermal gradient at x 2
dx 2

The rate of heat change is given above dm

 vP AN
• The rate of growth of the crystal is  dt (2)

where vP is the pull rate ( cm/hr) and N is the density ( gm/cm3) .

As, density = mass/volume.

 k S dT (3)
• Neglecting the middle term in Eqn. (1) we have: v PMAX 
LN dx 2

• In order to replace dT/dx2, we need to consider the heat transfer processes again in
solid phase.

• Heat radiation from the crystal (C)
is given by the Stefan-Boltzmann law


dQ  2rdx  T4  (4)

Surface area of cylinder

• Heat conduction up the crystal is given

by:

 dT
Q  k S r 2
dx
(5)
 2 2
• Differentiating (5), we have dQ
dx
 k S r  
2 d T

dx 2
 r
dx
 
2 dT dk S
dx
 k S r  
2 d T

dx 2
(6)

d2 T 2 4
• Substituting (6) into (4), we have  T 0 (7)
 dx 2 k Sr

• kS varies roughly as 1/T, so if kM is the TM

kS  kM (8)
thermal conductivity at the melting point,
 T

d2 T 2
 2
 T5  0 (9)
dx k M rTM



 5
1 2k M TM
v PMAX  (10)
LN 3r


Dopant incorporation during crystal growth
• Dopants are added to the melt to provide a controlled N or P doping level in the
wafers.
• However, the dopant incorporation process is complicated by dopant segregation.
• Generally, impurities “prefer to stay in the liquid” as opposed to being incorporated
into the solid.
• This process is known as segregation. The degree of segregation is characterized
by the segregation coefficient, ko, for the impurity.
• Segregation occurs due to the different solubilities of impurity atoms in two
phases.
C
kO  S
CL
CS and CL are the impurity
concentration just on the either
side of the solid/liquid interface.

Dopant behavior during crystal growth

CS
kO 
CL



Most k0 values are <1 which means the impurity prefers to stay in the liquid.
Thus as the crystal is pulled, dopant concentration will increase.
In other words, the distribution of dopant along the ingot will be graded.
Distribution coefficient: example
 cs 1016 atoms/cm 3
kd =  cL   2.86x1016 atoms/cm 3
cL .35
Patoms  2.86x1016 atoms / cm3 (2145.0cm3 )  6.135x1019
 6.135x1019 atomsx31g / mole 3
Zp =31g
23
 3.159x10  3.16mg
6.023x10 atoms / mole
Dopant incorporation during crystal growth with rapid stirring

VO = initial volume of the melt

IO = number of impurities atoms

C0 = initial impurity concentration in the

melt

C0 = I0/V0

CL = impurity concentration in the melt

during growth
CS = impurity concentration in the solid
IL = number of impurities in the melt during
Vs = volume of impurities in the solid
growth.
CL and CO are the concentration in the
melt, where melt means silicon and VL = volume of the melt during growth.
impurity atoms both Or we can say in
*Liquid terms is for the melt near the interface
solution of silicon and impurity atoms. *Melt is for the liquid inside the container
If during growth, an additional volume dV freezes, the impurities
incorporated into dV are given by:

IL Due to small change in I from Io

dI=-k 0 c L dv=-k 0 dv to IL small amount of freezing is
V0 -VS
done from 0 to Vs
IL Vs dI = Cs dv and Cs = ko CL
dI dv
 =-k 0 
I0
IL 0
V0 -VS Minus is there as it extracted
from the melt. CL = IL / VL

VS k 0
 I L =I 0 (1- )
V0
 k0
I0  
V
 1- S
V0  I 1-f 
k0

CL =
IL
=   = 0 =C 0 1-f 
k 0 -1

VL V0 -VS V0 1-f

The impurity level in the crystal (Cs)

 CS =CO ko 1-f 
k 0 -1
Doping concentration versus position along the
grown CZ crystal for common dopants in silicon

Note the relatively flat profile produced by boron with a ko close to 1.

Dopants with ko << 1 produce much more doping variation along the crystal.
Dopant incorporation during crystal growth under partial stirring condition

Impurities concentration will be higher at the interface than at the melt in case of
partial stirring.

 As a result of it, crystal doping concentration of impurities will also exceed than that
obtained in case of full stirring.
Figure : Partial Stirring Condition
 Thickness of stagnant layer:

D1/3 v1/6
δ= -1/2
cm
(2Πn)

Where v is the viscosity of the melt, n is the rotational rate and D is the diffusivity of
the impurity in the melt. As a result of this boundary layer the concentration of the
melt at the interface exceeds the equilibrium concentration.
Now, Effective segregation coefficient is define as :

Ke = Cs/ CL , Under partial stirring condition, where CL is the equilibrium

concentration in the melt

The effective segregation coefficient is larger than k (distribution coefficient)

k (distribution coefficient) = CS/CL’ , where CL’ is the concentration at the

interface.
 R= growth velocity (pull-rate) for crystal (i.e., rate of movement of the
liquid-solid interface.
D=diffusivity for solute atoms in liquid (m 2/s).

The equation governing the diffusion of solute atoms in the layer

may now be written. Noting that the amount of solute rejected from
the solid is equal to that gained by the liquid, distribution is given by

d 2c dc
D 2
+R =0
dx dx

Dd2C /dx2 = is a factor which will decide the rate of concentration of impurity
atoms in the stagnant layer or dC/dt due to diffusion of impurity atoms
RdC/dx = will decide the rate of dC/dt due to the rejection of impurity atoms at
interface. For stationary distribution, both should be equal and opposite.
 This the solution of equation given in the previous slide

-Rx/D
c=Ae +B
If we differentiate the above equation , we will get

dc AR -Rx/D
=- e
dx D

Where A and B are constants of integration

How to find the value of constants.

 Use boundary conditions. (a). C = CL’ at x = 0

(b)

As sum of impurity flux at boundary must be zero.

Flux means number of impurity atom diffusing unit area per unit time.

Unit = No of atoms/ area-time.

and noting that C = CL at x =

 We can obtain the following relation:

C L -CS
=e -Rδ/D
C L '-CS

Substituting k and Ke value in the above equation we get:

k
ke =
k+(1-k)e -Rδ/D
Where k = Cs / CL , and CL is the concentration of impurity atoms which is
uniform through out the melt.

Ke = Cs / CL , where CL’ is the concentration at the boundary or interface and

CL is the concentration in the melt. CL and CL’ are different.
 Means that under full stirring case, we have only segregation coefficient
But under partial stirring case, we have both segregation coefficient and effective
segregation coefficient.
k
ke =
k+(1-k)e -Rδ/D

Ke can ne made equal to 1, if R and are tending to infinite or very high.

i.e., with high pull rate and low spin rate or partial stirring ( high ), whereas k is
not dependent on any such parameters ( as under rapid stirring case ke = k and
and tends to 0.
Finally, the crystal growth for partial stirring may be derived from the
results for complete stirring by substituting ke in place of k because all
parameters are define wrt to the melt.
The impurity level in the crystal (Cs)

 CS  CO kO 1  f 
k O 1

f = Vs/Vo is the fraction frozen.

ko= Segregation Coefficient

ke= Effective Segregation Coefficient

Recap
dm
 vP AN Pull rate has inverse relation with
dt diameter of a ingot.

 CS =CO ko 1-f 
k 0 -1
The impurity level in the crystal

CS Segregation coefficient or distribution

kO  coefficient is always define at the
CL
interface of liquid and solid.
ke = CS/CL
Effective segregation coefficient.


The effective segregation coefficient

k depends on pull rate and thickness of
ke =
k+(1-k)e -Rδ/D stagnant layer. The value of R and
should be very high to make Ke = 1.
 Float-zone crystal growth Technique
Why FZ ?

For CZ-grown Si, impurities (O and C) can be introduced from the

melt contacting the SiO2 crucible and from graphite susceptor.

This limits the resistivity to 20Ωcm, while intrinsic Si is 230 kΩcm.

Through FZ, resistivity of the order of 1 kΩcm to 2 kΩcm is possible.

These crystals are more expensive and have very low oxygen and
carbon.

It is far less common, and is reserved for situations where oxygen
and carbon impurities cannot be tolerated.
It is good for power electronic devices (thyristors and rectifiers) that use
the entire volume of the wafer not just a thin surface layer, etc.

Problems with FZ technique

Float-zone does not allow as large Si wafers as CZ does (200 mm and 300
mm) .

 Cost
 Float-zone crystal growth process
Polycrystalline silicon is converted into single-crystal by zone heating (zone
melting).

The entire poly-Si rod from the EGS process is extracted as a whole

The rod is clamped at each end, with one end in contact with a single crystal
seed.

RF heater is used for melting the silicon.

The "floating" melt zone is about 2 cm wide.

The seed crystal touches the melt zone.

Limited to about a 4” wafer, as the melt zone will collapse - it is only held
together by surface tension.
 Ingot from CZ can be further processed through FZ technique to
alleviate the impurity problems.

Doping in FZ growth
 Pill doping: Drill a small hole in the top of the EGS rod, and insert the
dopant. If the dopant has a small segregation coefficient, most of it will
be carried with the melt as it passes the length of the boule. Resulting
in only a small non-uniformity. Ga and In doping work well this way.
 FZ

Zone Refining Zone Levelling

Float-zone: zone refining
Melt is not held in a container, it is “float”, thus the name “float zone”.

 Dopants/impurities prefer to stay in

the liquid than in the solid.

 Thus, the impurities generally stay in

the melt zone, and don't solidify in
the boule.
 That is, segregation of impurities in
the melt zone help in purify the Si
further.
 One can "purify" FZ wafers further by
successively passing the coil along
the boule. The impurities then Direction of motion
segregate towards the end of the
boule
Ref: S.k. Ghandhi : VLSI Fabrication Principles
Float Zone Crystal Growth

Initial concentration of impurity is the same throughout the ingot of polysilicon.

Ref: Plummer Silicon VLSI Technology

Zone refining

Zone length = L
The rod has initial uniform impurity concentration = C0

Io = number of impurities in the zone when it is first formed at the

bottom ( which is there in molten state).

I = number of impurities in the liquid

CL = I / L , Io = C0 L

If the molten zone moves upwards by dx, the

number of impurities in the liquid will change since
some will be added to it C0dx portion and some
will be lost to the freezing solid on the bottom
(=CSdx=k0CLdx).

Ref: Plummer Silicon VLSI Technology

dI  (C0 -k0C L )dx, but C L  I / L Co dx = amount of molt in dx length.
(i.e. in liquid phase)
x I dI
0 dx  I 0 k I Ko CL = CS dx = small amount of
C0  0 molt, which is solidified.
L
C0 L  C0 L  k 0 x L dI = change in number of impurity
I     I 0 e atom.
k0  k0 
I = Io + dI
I
C S  k 0 C L  k 0 ; I 0  C0 L
L Co dx is shown in the previous
slide ( amount of impurity atoms)
 k0 x

C S  C0 1  1  k 0 e

L
 Now, due to small shift ( delta x) in
  molten length L, Cs dx amount of
atoms will be solidified.
Floating zone crystal growth – zone refining

Impurity during float-zone growth or

Zone refining with multiple
zone refining. One pass of the molten
passes, k0=0.1. L is the
zone through the solid. L is the length
length of the molten zone.
of the molten zone (2 cm)
Ref: Plummer Silicon VLSI Technology
FZ vs. CZ in terms of impurities distribution

We can not do multiple pass in CZ

Float-zone: zone levelling
Model for doping by zone levelling

Cs = Ko C1 e-kox/L

In this method, we drill a small hole in the top of the EGS

rod, and insert the dopant.
Zone levelling

 k is very less than 1 will results in uniform distribution of dopant atoms.

Dopant Concentration Nomenclature

Concentration (Atoms/cm3)
14
Dopant
Material < 10 1014 to 1016 1016 to 1018 >1020
Type (Very Lightly Doped) (Lightly Doped) (Doped) (Heavily Doped)

-- - +
Pentavalent n n n n n
-- - +
Trivalent p p p p p

Ref: Plummer Silicon VLSI Technology

Ref: S.k. Ghandhi : VLSI Fabrication Principles
Oxygen in silicon
Oxygen has a segregation coefficient greater than 1. That is oxygen will
come preferentially into the crystal.

Source of oxygen during crystal growth:

Furnace ( atmosphere)
Crucible

What are the effects of oxygen in the single crystal silicon?

The amount of oxygen will vary from

in a Czochralski grown crystal
95% of it, will be in the interstitial sites, 95% will stay in the interstitial sites.
Improve the mechanical strength of Silicon.

The rest 5%, it can form a complex

This complex is electronically active and affect the resistivity of the grown crystal and the
formation temperature of these complexes are around 450 C to 500 C.

Their formation is reduced at the wafer level.

Heat the wafers to temperature above 600 C. The complexes are dissolved.

When you cool it down, see, a wafer is going to cool much faster than the entire
ingot. It has got a much smaller thermal mass. It is going to cool much faster.

The complexes have less time to form again.

Steps for wafer preparation

Crystal Growth Etching

Shaping Polishing

Wafer Slicing Cleaning

Wafer Lapping and Edge Grind Inspection

Packaging
 Ingot Diameter Grind

Preparing crystal ingot for grinding

Diameter
grind

Flat grind

J. D. Plummer, M. D. Deal and P. B. Griffin, Chapter-3: Lecture notes on silicon crystal structures
and growth,
90° angle between flats indicates it is a p type <100> silicon wafer
180° angle between flats indicates it is a n type <100> silicon wafer
Absence of secondary flat indicates it is a p type <111> silicon wafer
45° angle between flats indicates it is a n type <111> silicon wafer

Ref: S.M. Sze VLSI Technology

J. D. Plummer, M. D. Deal and P. B. Griffin, Chapter-3: Lecture notes on silicon crystal structures
and growth,
Internal Diameter Saw

Internal
diameter wafer
saw

www.physics.muni.cz/~jancely
Wafer Dimensions

Diameter Thickness Area

(mm) (m) (cm2)
150 675  20 176.71

200 725  20 314.16

300 775  20 706.86

400 825  20 1256.64

6’’, 8”, 12”, 16”, 4”

www.physics.muni.cz/~jancely/t
Increase in Number of Chips on Larger Wafer Diameters

www.physics.muni.cz/~jancely/t
Wafer Lapping and Edge Grind

Lapping is done in order to achieve the flatness. It also removes the saw damage

https://waferfabrication.wikispaces.com/Wafer+Preparation
Chemical Etch of Wafer Surface to Remove Sawing Damage

www.physics.muni.cz/~jancely/t
Backside Processing

In most of the cases the back of the wafer is left unpolished.

This is because normally only the front part of the wafer will be used for making
ICs.
However, in some cases (uncommon), the backside of the wafer may be used
as well.
Wafer Polishing

Ref: Plummer Silicon VLSI Technology

Double-Sided Wafer Polish

Upper polishing pad

Wafer

Slurry

Lower polishing pad

Ref: Plummer Silicon VLSI Technology