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Von Neumann Architecture

The document discusses the Von Neumann architecture and its components. It describes the main units including the memory unit, control unit, and ALU. It also explains the functions of registers like the program counter and memory address register. The roles of the address, data, and control buses are defined. The fetch-decode-execute cycle is outlined.

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Nicki G
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12 views3 pages

Von Neumann Architecture

The document discusses the Von Neumann architecture and its components. It describes the main units including the memory unit, control unit, and ALU. It also explains the functions of registers like the program counter and memory address register. The roles of the address, data, and control buses are defined. The fetch-decode-execute cycle is outlined.

Uploaded by

Nicki G
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Von Neumann Architecture/Computer Architecture/Stored Program Concept/Stored Program Computer:

Main Idea: “The processor can directly access memory”

All the Components involved with Computer Architecture:

1) Units
2) Registers
3) Buses

Units:
1) Memory Unit
2) Control Unit
3) ALU [Arithmetic & Logic Unit]

Registers:
1) Program Counter [PC]
2) Memory Address Register [MAR]
3) Memory Data Register/Memory Buffer Register [MDR/MBR]
4) Current Instruction Register[CIR]
5) Accumulator [Acc]
6) Index Register [IX]

Buses:
1) Address Bus
2) Data Bus
3) Control Bus

Units:
Memory Unit:
Holds addresses and contents (data or instructions.)
Control Unit:
Manages the flow of data.
Sync in between different components of the computer system.
Sends and receives signals related to co-ordination and control.
ALU:
Processes the calculations using arithmetic operators such as +,-,*,/.
Makes decisions using logical operators such as AND, OR, NOT.

NOTE:
AND-both the conditions to be satisfied.
OR-either one of the conditions to be satisfied.
NOT-exclude a condition.
Registers:

1) PC: Holds address of the NEXT instruction.


2) MAR: Holds address of the CURRENT instruction
3) MDR: Holds data of CURRENT address.
4) CIR: Decodes and executes.

Buses: (Pathways to transmit data)


Address Bus:
Carries signals related to addresses between CPU and the memory.
It is a uni-directional bus.
Data Bus:
Carries data in between CPU, memory unit and input and output devices.
It is bi-directional.
Control Bus:
Carries signals related to co-ordination and control, transmits timing signals to control the processes.
It is bi-directional.

Inter-Link:
1) Memory Unit: [MAR & MDR, address bus & data bus]
2) Control Unit: [PC & CIR, control bus]
3) ALU: [Acc, control bus, data bus]

KEY DIFFERENCES:

ALU ACC
This is unit that will process the calculations. This is a register that will hold the calculations
processed by ALU.

Buses Control Unit


Pathways to transmit data. A unit to handle data flow.

Registers IAS [Immediate Access Store]


Holds data or instructions which is being Holds data or instructions to be processed.
processed.
BEING PROCESSED TO BE PROCESSED
FETCH – DECODE – EXECUTE CYCLE:
6 Marks 7 Marks 8 Marks 9 Marks 10 Marks
Holds the address of the PC PC IAS RAM RAM
next instruction.
The address is placed in MAR MAR PC IAS IAS
MAR via address bus.
The data of the address MDR MDR MAR PC PC
is placed in MDR via
data bus.
All the instructions are CIR CIR MDR MAR MAR
transferred to CIR.
PC is incremented by 1. PC+1 PC+1 CIR MDR MDR

Decoded & Executed D&E BACK TO PC+1 CIR CIR


MAR
D&E BACK TO PC+1 PC+1
MAR
D&E BACK TO BACK TO
MAR MAR
D&E Interrupt
D&E

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